Image sensor device and method for manufacturing the same

Abstract

The present disclosure relates to image sensor devices and methods for manufacturing the same. A method includes: forming a first photoresist layer on the front side of a device substrate and having first grooves spaced apart from each other. Performing a first implantation process using the first photoresist layer as a mask to form a first isolation region in the device substrate. A second photoresist layer is formed on the front side and has a second groove. Performing a second implantation process using the second photoresist layer as a mask to form a second isolation region in the device substrate and intersecting with the first isolation region. A third photoresist layer is formed on the front side and has third grooves spaced apart from each other. Performing a third implantation process using the third photoresist layer as a mask to form a third isolation region in the device substrate and intersecting with the first isolation region but spaced apart from the second isolation region.

Description

Technical Field

[0001] The present disclosure relates to image sensor devices and methods of manufacturing the same. Background Art

[0002] Image sensor devices are widely used in various imaging applications and products, for example, digital still cameras or mobile phone camera applications. These devices utilize an array of sensor elements (pixels) in a substrate. The pixels may be photodiodes or other photosensitive elements adapted to absorb light projected toward the substrate and convert the sensed light into an electrical signal. In order to obtain higher resolution, it is advantageous to increase the number of pixels in an image sensor device.

[0003] The ever-shrinking geometry creates challenges for the manufacturing of image sensor devices. For example, the manufacturing process may require a photoresist mask with a high aspect ratio to produce pixels with micron or sub-micron dimensions. However, photoresist masks with a high aspect ratio are more susceptible to capillary forces. These effects are exacerbated as the aspect ratio of the mask increases and / or the spacing decreases. As a result, the photoresist mask may collapse, for example, due to the pull of capillary forces between adjacent photoresist masks. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing an image sensor device is provided, comprising: forming a first photoresist layer on the front side of a device substrate, wherein the first photoresist layer has first grooves spaced apart from each other; performing a first injection process using the first photoresist layer as a mask to form a first isolation region in the device substrate; forming a second photoresist layer on the front side of the device substrate, wherein the second photoresist layer has second grooves spaced apart from each other; performing a second injection process using the second photoresist layer as a mask to form a second isolation region in the device substrate and intersecting with the first isolation region; forming a third photoresist layer on the front side of the device substrate, wherein the third photoresist layer has third grooves spaced apart from each other; performing a third injection process using the third photoresist layer as a mask to form a third isolation region in the device substrate and intersecting with the first isolation region but spaced apart from the second isolation region.

[0005] According to another embodiment of the present disclosure, a method for manufacturing an image sensor device is provided, comprising: performing a first photolithography process using a first pattern of a first photomask to form a first photoresist pattern on the front side of a device substrate, wherein the first pattern comprises parallel lines having a first spacing and arranged along a first direction; performing a first injection process using the first pattern as a mask to form a first isolation region in the device substrate; performing a second photolithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being offset from the first pattern in the first direction by a distance less than the first spacing; performing a second injection process using the second photoresist pattern as a mask to form a second isolation region in the device substrate and spaced apart from the first isolation region; and forming pixels between the first isolation region and the second isolation region.

[0006] According to another embodiment of the present disclosure, there is provided an image sensor device, comprising: a device substrate; an isolation region located in the device substrate and defining a pixel region in the device substrate; and pixels located in the pixel regions, respectively, wherein each of the pixels has a length and a width, the width is less than 1 micron, and a doping concentration of some portions of the isolation region is greater than a doping concentration of another portion of the isolation region, the some portions are located at four corners of at least one of the pixels, and the other portion is located on a side wall of the at least one pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read together with the accompanying drawings, various aspects of the present disclosure can be better understood according to the following detailed description. It is worth noting that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0008] Figures 1A to 18B A method for manufacturing an image sensor device at various stages according to some embodiments of the present disclosure is shown.

[0009] Fig.19A and Fig.19B is a flow chart illustrating an exemplary method for manufacturing an image sensor device according to various embodiments of the present disclosure.

[0010] Fig. 20A and Fig. 20B Simplified cross-sectional views of a method for fabricating an image sensor device at various stages are shown in accordance with some embodiments.

[0011] Fig.21ASimplified top view diagrams for manufacturing an image sensor device at various stages are shown in accordance with some embodiments.

[0012] Fig. 21B It is along Fig.21A A cross-sectional view taken along line BB in FIG.

[0013] Fig.22A and Fig. 22B A simplified cross-sectional view of an image sensor device is shown in accordance with some embodiments.

[0014] Fig.23A Simplified top view diagrams for manufacturing an image sensor device at various stages are shown in accordance with some embodiments.

[0015] Fig. 23B It is along Fig.23A A cross-sectional view taken along line BB in FIG.

[0016] Fig.24A and Fig. 24B A simplified cross-sectional view of an image sensor device is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing different features of the subject matter provided. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat the figure marks and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or (or multiple) feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0019] As used herein, "roughly," "about," "approximately," or "substantially" shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. The values ​​given herein are approximate, meaning that if not explicitly stated, the term "roughly," "about," "approximately," or "substantially" can be inferred.

[0020] Embodiments of the present disclosure provide a method for forming sub-micron isolation regions for image sensor devices using multiple photolithography processes and optional shrinking materials applied to photoresist pillars provided by the photolithography processes. The photoresist pillars are formed to have low aspect ratios and ultra-high aspect ratio trenches between the photoresist pillars without collapsing the photoresist pillars.

[0021] Figures 1A to 18B 1 shows a method for manufacturing an image sensor device 100 at various stages according to some embodiments of the present disclosure. Figure 1A and Figure 1B . Figure 1A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 1B It is along Figure 1A BB in FIG. The image sensor device 100 can be used in various electronic devices (e.g., cameras, cellular phones, personal digital assistants, computers, etc.) for capturing images. Examples of such image sensor devices may include complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices, charge coupled devices (CCDs), active pixel sensor (APS) devices, or passive pixel sensor devices. In some embodiments, the image sensor device 100 is a backside illumination (BSI) image sensor device. Although the present disclosure is described for backside illumination image sensor devices, embodiments of the present disclosure may also be applied to frontside illumination (FSI) image sensor devices. The image sensor device 100 may be a CIS and include a device substrate 110. The device substrate 110 is, for example, a bulk silicon substrate, an epitaxial layer above a silicon substrate, a semiconductor wafer, a silicon germanium substrate, or a silicon on insulator (SOI) substrate. In some embodiments, other semiconductor materials including group III, group IV, and group V elements may be used. In some embodiments, the device substrate 110 may be undoped. In some other embodiments, the device substrate 110 is doped with a p-type dopant such as boron (i.e., a p-type substrate), or is doped with an n-type dopant such as phosphorus or arsenic (i.e., an n-type substrate). The device substrate 110 may optionally include a compound semiconductor and / or an alloy semiconductor. In some embodiments, the device substrate 110 may include an epitaxial layer, which may be strained to improve performance.

[0022] The device substrate 110 has a front side (also referred to as a front surface) 112 and a back side (also referred to as a back surface) 114 opposite the front side 112. For a BSI image sensor device (e.g., image sensor device 100), light or radiation is incident on the back side 114 (after the substrate thinning process) and passes through the back side 114 into the remaining device substrate 110. The front side 112 is an active surface on which circuit designs (e.g., transistors, contacts, and interconnect features) will be formed to provide external communication with pixels in the pixel area. It is understood that in order to better understand the inventive concepts of the present disclosure, Figures 1A to 18B and FIG. 20A to FIG. 23B have been simplified and therefore may not be drawn to scale.

[0023] A first photoresist layer 120 is formed over the front side 112 of the device substrate 110. The first photoresist layer 120 may be formed by depositing (e.g., spin coating) a photoresist film over the front side 112 of the device substrate, and then patterning the photoresist film in a first photolithography process, which may involve one or more processes, such as exposure, post-exposure baking, development, etc. The first photolithography process may pattern the first photoresist layer 120 using a photolithography apparatus. The photolithography apparatus may include: a radiation source for providing radiation energy; a lens system for projecting radiation energy for photolithography patterning; and a mask stage having a scanning function. The radiation source may be a suitable light source, such as an ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) source. For example, the radiation source may include, but is not limited to: a krypton fluoride (KrF) excimer laser with a wavelength of 248 nm; an argon fluoride (ArF) excimer laser with a wavelength of 193 nm; a fluoride (F2) excimer laser with a wavelength of 157 nm; a mercury lamp with a wavelength of 436 nm or 365 nm; or other light sources with a wavelength below about 100 nm. The lens system may include one or more illumination modules designed to direct a radiation beam from the radiation source onto a photomask. The mask stage is operable to fix the photomask and manipulate the photomask in a transition and / or rotation mode. The lithography apparatus also includes a substrate stage for holding a substrate to be patterned during a first lithography process and manipulating the substrate to be patterned in a transition and / or rotation mode. It will be appreciated that the manipulation of the substrate is considered relative to the photomask so that one or both of the mask stage and the substrate stage can be moved to achieve the desired manipulation. An alignment device may be used to align the photomask and the substrate.

[0024] Figure 1C The method according to some embodiments is shown to transfer an image to Figure 1A Schematic diagram of a first photolithography process on a first photoresist layer 120 on a device substrate 110. For simplicity, Figure 1CThe portion of the first photoresist layer 120 that receives the image is shown. During the first photolithography process, a photomask (e.g., having Figure 1C A first photomask 210 (shown as a first pattern 212) is loaded onto a mask stage, and a device substrate 110 is loaded onto the substrate stage. Depending on the features to be formed in the first photoresist layer 120, the first pattern 212 may have various features, for example, lines, holes, grids, or any desired shape such as polygons. In some embodiments, the pattern of the first pattern 212 is substantially parallel lines arranged in a first direction D1. The pattern of substantially parallel lines may be composed of repeating features, for example, a plurality of substantially parallel lines. The radiation beam may be scanned over the first photomask 210. The features of the first pattern 212 allow the radiation beam to pass through and expose a field 214 on the device substrate 110. The field 214 may define at least one edge of a die (or chip). In some embodiments, the field 214 includes one or more pixel array regions defined in the device substrate 110. In this way, the first pattern 212 is transferred to the first photoresist layer 120 at the exposure field 214. The lithography apparatus steps the device substrate 110 to the next field (e.g., a scan field) to expose another field. The step-and-scan process is performed until the pixel array area of ​​the device substrate 110 is exposed by the first pattern 212. The radiation beam contacts and changes the chemical composition of the first photoresist layer 120 so that the developer can subsequently remove the exposed portion of the first photoresist layer 120.

[0025] The pattern of substantially parallel lines has a constant mask pitch of submicron level or above. In some embodiments, the pattern of substantially parallel lines has a mask pitch P1 greater than about 1 micron, for example, about 1.15 microns to about 3 microns, for example, about 1.2 microns to about 1.9 microns. In some embodiments, the pattern of substantially parallel lines has a mask pitch P1 of about 1.8 microns. The term "mask pitch" described herein refers to the width of a feature (e.g., a line) plus the distance to the next adjacent feature. It should be understood that the mask pitch P1 of the first pattern 212 can vary according to the critical dimension (CD) of the pattern (one or more) to be formed in the first photoresist layer 120.

[0026] refer to Figure 2A and Figure 2B . Figure 2A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 2B It is along Figure 2A A cross-sectional view taken along line BB in FIG. Figure 2A and Figure 2BIt is shown that the first pattern 210 according to some embodiments has been transferred to the first photoresist layer 120 to form first photoresist columns 122a-122c on the front side 112 of the device substrate 110. It should be understood that the three (3) first photoresist columns 122a-122c shown herein are for illustration purposes only. Depending on the first pattern 212 for the application, the first photoresist layer 120 may include any number of first photoresist columns. For simplicity, three photoresist columns 122a-122c of the first photoresist layer 120 will be discussed herein.

[0027] The photoresist columns 122a-122c define the pixel area of ​​the image sensor device 100. For example, each of the photoresist columns 122a, 122b and 122c defines a pixel area 116a, 116b and 116c in the device substrate 110, respectively. The pixel areas 116a, 116b and 116c are areas where one or more pixels are to be formed. The pixel areas 116a, 116b and 116c may be collectively referred to as a pixel array area 116. A logic area (not shown) may be disposed outside the pixel array area 116. The resist pitch P2 of the photoresist columns 122a, 122b and 122c substantially corresponds to the mask pitch P1 of the first pattern 212. The term "resist pitch" refers to the center-to-center distance between two adjacent photoresist columns. The pixel area spacing of pixel areas 116a, 116b and 116c can correspond to the resist spacing P2 of first photoresist pillars 122a, 122b and 122c. The term "pixel area spacing" described herein refers to the center-to-center distance between two adjacent pixel areas. In the case of using the pattern of substantially parallel lines discussed above, the pixel area spacing of pixel areas 116a, 116b and 116c is greater than 1 micron, such as about 1.15 microns to about 2 microns, such as about 1.2 microns to about 1.9 microns.

[0028] Each of the first photoresist columns 122a, 122b, and 122c has a height H1 (i.e., a vertical dimension) and a width W1 (i.e., a lateral dimension). The aspect ratio of the first photoresist columns 122a, 122b, and 122c can be defined as the ratio of the height H1 to the width W1. For a pixel size of about 1 micron, each of the first photoresist columns 122a, 122b, and 122c can have an aspect ratio of about 3:1 to 1:1, for example, about 2:1. In some embodiments, the first photoresist columns 122a, 122b, and 122c each have an aspect ratio of about 1:1. The first photoresist columns 122a, 122b, and 122c are separated by gaps or grooves 123. The grooves 123 have a height equal to the height H1 of the first photoresist columns 122a, 122b, and 122c, and a width W2. The aspect ratio of the groove 123 can be defined as the ratio of the height H1 to the width W2. The groove 123 has an aspect ratio of 10:1 or higher, for example, about 12:1 to about 30:1, for example, about 13:1 to about 25:1. Therefore, the aspect ratio of the first photoresist pillars 122a, 122b, and 122c is lower than the aspect ratio of the groove 123. In some embodiments, the groove 123 has an aspect ratio of 15:1 to 20:1. In various embodiments, the ratio of the width W1 of each of the first photoresist pillars 122a, 122b, and 122c to the width W2 of the groove 123 can be about 4:1 to about 30:1, for example, about 6:1 to about 20:1, for example, about 8:1 to about 10:1.

[0029] Although the trench 123 has an ultra-high aspect ratio of 10:1 or higher (e.g., 13:1, 15:1 or higher), the lower aspect ratio of the first photoresist pillars 122a, 122b, and 122c provides sufficient strength to the first photoresist pillars 122a, 122b, and 122c to withstand the capillary force inside the trench 123 without collapsing. Specifically, the ultra-high aspect ratio trench 123 and the lower aspect ratio of the first photoresist pillars 122a, 122b, and 122c produce an increased width W1 of each of the first photoresist pillars 122a, 122b, and 122c, which achieves good adhesion of the first photoresist pillars 122a, 122b, and 122c to the front side 112 of the device substrate 110. Thus, the likelihood of collapse of the first photoresist pillars 122a, 122b, and 122c is reduced compared to those high aspect ratio photoresist layers having high aspect ratio photoresist pillars and trench aspect ratios of 10:1 or greater. As a result, the first photoresist pillars 122a, 122b, and 122c can be formed taller and / or closer together (i.e., with higher aspect ratio trenches between the first photoresist pillars 122a, 122b, and 122c) without the risk of collapse of the first photoresist pillars 122a, 122b, and 122c. The combination of lower aspect ratios (e.g., approximately 3:1 or lower) of the first photoresist pillars 122a, 122b, and 122c and ultra-high aspect ratio trenches (e.g., 13:1 or higher) is advantageous when performing subsequent manufacturing processes (e.g., forming isolation regions by ion implantation), which will be discussed below. Figure 3A and Figure 3B Discussed in more detail in .

[0030] In some embodiments, the possibility of collapse of the first photoresist pillars 122a, 122b, and 122c can be further reduced by applying a shrink material to the exposed surfaces of the first photoresist pillars 122a, 122b, and 122c, which will Fig. 20A and Fig. 20B Discussed in more detail in .

[0031] refer to Figure 3A and Figure 3B . Figure 3A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 3B It is along Figure 3ABB in FIG. 1 is a cross-sectional view taken along line BB in FIG. After the first photolithography process, the device substrate 110 is subjected to a first ion implantation process 130 to form a first isolation region 102 in the device substrate 110. The first ion implantation process 130 is performed using the first photoresist columns 122a, 122b, and 122c as a mask to implant ions into regions of the device substrate 110 that are not protected by the first photoresist columns 122a, 122b, and 122c. The first isolation region 102 separates the pixel regions 116a, 116b, and 116c from each other. The first isolation region 102 prevents carriers at a specific pixel region from leaking to adjacent pixel regions (also referred to as crosstalk). In some embodiments, the first isolation region 102 may exceed the depth of each pixel to be formed in the pixel regions 116a, 116b, and 116c. In some embodiments, the first isolation region 102 can extend from the front side 112 of the device substrate 110 to the back side 114 to provide good isolation between the pixel regions 116a, 116b, and 116c. Because the first photoresist pillars 122a, 122b, and 122c are formed with ultra-high aspect ratio trenches between the first photoresist pillars 122a, 122b, and 122c, deeper isolation regions can be achieved with limited implant damage to the image sensor device (e.g., the isolation region can be formed with minimal lateral diffusion), even with high implant energy. As a result, ions can be implanted deeper to provide effective pixel-to-pixel isolation for the image sensor device 100.

[0032] The first isolation region 102 may be formed of a p-type or n-type material. The first isolation region 102 may be formed of a material having the same doping polarity as the device substrate 110. In some embodiments, the first isolation region 102 is a p-type region formed by injecting a p-type dopant (e.g., boron, boron fluoride (BF2), diborane (B2H6), etc.) into the device substrate 110. The doping concentration of the first isolation region 102 may be about 1×10 12 Ions / cm 3 About 1×10 20 Ions / cm 3 In the range of, for example, about 1×10 18 Ions / cm 3 In some embodiments, the doping concentration of the first isolation region 102 may be about 5×10 11 Ions / cm 3 To about 5×10 17 Ions / cm 3 In the range of, for example, about 5×10 15 Ions / cm 3 .

[0033] Each first isolation region 102 has a height H2 (vertical dimension) and a width W3 (lateral dimension). The aspect ratio of the first isolation region 102 can be defined as the ratio of the height H2 to the width W3. In some embodiments, the first isolation region 102 has an aspect ratio of 10:1 or higher, for example, about 12:1 to about 15:1.

[0034] refer to Figure 4A and Figure 4B . Figure 4A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 4B It is along Figure 4A After the first isolation region 102 has been formed, Figure 3A and Figure 3B The first photoresist pillars 122a, 122b, and 122c (ie, the first photoresist layer 120) are removed, for example, using a photoresist ashing or stripping process.

[0035] refer to Figure 5A and Figure 5B . Figure 5A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 5B It is along Figure 5A A cross-sectional view taken along line BB in FIG. Figure 3A and Figure 3B After the first photoresist layer 120 in the device substrate 110 is formed, a second photoresist layer 140 is formed over the front side 112 of the device substrate 110. The second photoresist layer 140 can be formed by depositing (e.g., spin coating) a photoresist film over the front side 112 of the device substrate 110, and then Figures 1C to 4B The photoresist film is patterned by a second photolithography process in the same manner as discussed. The second photolithography process for patterning the second photoresist layer 140 is similar to the first photolithography process for the first photoresist layer 120, except that the second photolithography process uses a second photomask to pattern the second photoresist layer 140, and the pattern of the second photomask is offset from the first pattern 212 of the first photomask 210 by about half a mask pitch.

[0036] Figure 5C A simplified top view of a second photomask 220 having a second pattern 222 is shown in accordance with some embodiments. The second photomask 220 is substantially identical to the first photomask 210, except that the second pattern 222 is laterally offset from the first pattern 212 (along the first direction D1) by substantially half a mask pitch. The first isolation region 102 is depicted in dashed lines for illustration purposes only. Similar to Figure 1C The first pattern 212 in the device substrate 110 and the second pattern 222 can be a pattern of substantially parallel lines with a constant mask pitch P1' greater than about 1 micron, such as about 1.15 microns to about 3 microns, such as about 1.2 microns to about 1.9 microns. In some embodiments, the pattern of substantially parallel lines has a mask pitch P1' of about 1.8 microns. The lateral offset of the second pattern 222 allows pixel regions to be formed in a parallel line arrangement in the device substrate 110. In some embodiments, the mask pitch P1 (see Figure 1C ) and P1' can be substantially the same.

[0037] Although the lateral offset of the second pattern 222 is discussed, the second pattern 222 can be offset from the first pattern 212 by half the mask pitch in any desired direction (e.g., in a lateral manner) to double the density of the isolation regions in the device substrate 110, as will be discussed in more detail below. In addition, it should be understood that the second pattern 222 is not limited to the pattern of substantially parallel lines shown. The second pattern 222 can be any other arrangement of patterns and can be used with the first pattern 212 so that the second photoresist layer 220 is patterned to provide a second photoresist column having a resist pitch greater than 1 micron (e.g., about 1.2 microns to about 1.9 microns).

[0038] During the second photolithography process, the mask stage is operable to fix the second photomask 220 and manipulate the photomask in a transition and / or rotation mode. The substrate stage holding the device substrate 110 can also be manipulated in a transition and / or rotation mode. An alignment device is used to align the photomask and the device substrate 110 so that the radiation beam exposes a field 224 on the device substrate 110. The radiation beam (e.g., a krypton fluoride (KrF) excimer laser with a wavelength of 248nm, or an argon fluoride (ArF) excimer laser with a wavelength of 193nm) can be scanned over the second photomask 220 to expose the field 224 on the device substrate 110. In this way, the second pattern 222 is transferred to the second photoresist layer 140 at the exposure field 224. The photolithography apparatus steps the device substrate 110 to the next field (e.g., a scan field) to expose another field. The step-and-scan process may be performed in the same manner as the first photolithography process until the pixel array region of the device substrate 110 is exposed by the second pattern 222 .

[0039] Although the first photoresist layer 120 and the second photoresist layer 140 are patterned respectively using two different photomasks (i.e., the first photomask 210 and the second photomask 220), it is expected that the first photolithography process and the second photolithography process can use the same photomask to pattern the first photoresist layer 120 and the second photoresist layer 140 by moving the mask stage or the substrate stage to achieve a half-mask pitch offset movement.

[0040] refer to Fig. 6A and Figure 6B . Fig. 6A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 6B It is along Fig. 6A BB in FIG. 1. It can be seen that the second pattern 222 has been transferred to the second photoresist layer 140 to form second photoresist pillars 142a and 142b on the front side 112 of the device substrate 110. Although not shown, it should be understood that the patterned photoresist layer 140 has the same Figure 2A and Figure 2B The first photoresist pillars 122a, 122b, and 122c are shown arranged in a similar pattern of substantially parallel lines, except that the second photoresist pillars 142a and 142b are laterally offset from the first photoresist pillars 122a, 122b, and 122c by half a pitch.

[0041] The second photoresist columns 142a and 142b are separated by the groove 143. The groove 143 has a height H3 (vertical dimension) equal to the height of the second photoresist columns 142a and 142b, and a width W4 (lateral dimension). The groove 143 has a height-to-width ratio substantially the same as the groove 123. For example, the groove 143 may have a height-to-width ratio of 10:1 or higher, such as about 12:1 to about 30:1, such as about 13:1 to about 25:1. In some embodiments, the groove 143 has a height-to-width ratio of 15:1 to 20:1. Similarly, for a pixel size of about 1 micron, each of the second photoresist columns 142a and 142b may have a height-to-width ratio of about 1:1 to about 3:1 or less, such as about 2:1. In some embodiments, each of the second photoresist columns 142a and 142b has a height-to-width ratio of about 1:1. Therefore, the aspect ratio of the second photoresist pillars 142a and 142b is lower than the aspect ratio of the trench 143. In various embodiments, the ratio of the width W5 of each of the second photoresist pillars 142a and 142b to the width W4 of the trench 143 may be about 4:1 to about 30:1, such as about 6:1 to about 20:1, such as about 8:1 to about 10:1.

[0042] Similarly, although the trench 143 has an ultra-high aspect ratio of 10:1 or higher (e.g., 13:1, 15:1 or higher), due to the lower aspect ratio of the second photoresist pillars 142a and 142b, the second photoresist pillars 142a and 142b have sufficient strength to withstand the capillary force inside the trench 143 without collapsing. Specifically, the ultra-high aspect ratio trench and the lower aspect ratio of the second photoresist pillars 142a and 142b produce an increased width W5 of each of the second photoresist pillars 142a and 142b, which achieves good adhesion of the second photoresist pillars 142a and 142b to the front side 112 of the device substrate 110. Therefore, compared with those high aspect ratio photoresist layers having a trench aspect ratio of 10:1 or higher, the possibility of the second photoresist pillars 142a and 142b collapsing is reduced. This means that the second photoresist pillars 142a and 142b can be formed taller or closer together (i.e., with a higher aspect ratio trench between the second photoresist pillars 142a and 142b) without the risk of the second photoresist pillars 142a and 142b collapsing. The combination of the lower aspect ratio (e.g., about 3:1 or lower) of the second photoresist pillars 142a and 142b and the ultra-high aspect ratio trench (e.g., 13:1 or higher) is advantageous when performing subsequent manufacturing processes (e.g., forming a second isolation region by ion implantation).

[0043] In some embodiments, the possibility of collapse of the second photoresist pillars 142a and 142b can be further reduced by applying a shrink material to the exposed surfaces of the second photoresist pillars 142a and 142b, which will Fig. 20A and Fig. 20B Discussed in more detail in .

[0044] refer to Fig. 7A and Figure 7B . Fig. 7A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 7B It is along Fig. 7ABB in FIG. 1 is a cross-sectional view taken by line BB in FIG. After the second photolithography process, the device substrate 110 is subjected to a second ion implantation process 150 to form a second isolation region 104 in the device substrate 110. The second ion implantation process 150 is performed using the second photoresist columns 142a and 142b as a mask to implant ions into the device substrate 110 in an area that is not protected by the second photoresist columns 142a and 142b. Because the second photoresist columns 142a and 142b are offset by half a pitch from the first photoresist columns 122a, 122b, and 122c, the resulting second isolation region 104 divides each of the pixel regions 116a, 116b, and 116c into half, and the divided pixel regions are spaced apart from each other. The second isolation region 104 prevents carriers at a specific pixel region from leaking to an adjacent pixel region. The second isolation region 104 may exceed the depth of each pixel to be formed in the divided pixel region. In some embodiments, the second isolation region 104 can extend from the front side 112 of the device substrate 110 to the back side 114 to provide good isolation between the divided pixel regions. Because the second photoresist pillars 142a and 142b are formed with ultra-high aspect ratio trenches between the second photoresist pillars 142a and 142b, deeper isolation regions can be achieved with limited implant damage to the image sensor device (e.g., the isolation region can be formed with minimal lateral diffusion), even with high implant energy. As a result, ions can be implanted deeper to provide effective pixel-to-pixel isolation for the image sensor device 100.

[0045] Each second isolation region 104 has a height H4 (vertical dimension) and a width W6 (lateral dimension). The aspect ratio of the second isolation region 104 can be defined as the ratio of the height H4 to the width W6. In some embodiments, the second isolation region 104 has an aspect ratio of 10:1 or higher, for example, about 12:1 to about 15:1. Because the first isolation region 102 and the second isolation region 104 are formed separately, the height H4 of the second isolation region 104 can be the same as the height H2 of the first isolation region 102 (see Figure 3B Alternatively, the height H4 of the second isolation region 104 may be substantially the same as the height H2 of the first isolation region 102.

[0046] Similar to the first isolation region 102, the second isolation region 104 may be formed of a p-type or n-type material and include the same doping polarity as the device substrate 110 and / or the first isolation region 102. For example, the second isolation region 104 may be a p-type region formed by implanting a p-type dopant (e.g., boron, boron fluoride (BF2), diborane (B2H6), etc.) into the device substrate 110. Similar to the first isolation region 102, the doping concentration of the second isolation region 104 may be approximately 1×1012 Ions / cm 3 , and the maximum is about 5×10 17 Ions / cm 3 The aspect ratio of each second isolation region 104 may be 10:1 or higher, for example, about 12:1 to about 15:1.

[0047] exist Figure 5C In the case where the second pattern 222 in FIG. 1 uses a pattern of substantially parallel lines having a mask pitch of about 1.8 microns, the second photolithography process and the second ion implantation process 150 will form the second isolation region 104 and the first isolation region 102 at a constant pitch P2′ of about 0.9 microns (which is sub-micron level). By performing two photolithography processes (i.e., two mask patterning processes), the pixel region (e.g., Fig. 7A and Figure 7B The density of the pixel regions 117a-117f shown is increased by more than two times. Specifically, the photolithography process is performed using photoresist pillars with ultra-high aspect ratio trenches (eg, greater than 13:1) without the risk of photoresist pattern collapse.

[0048] refer to Fig. 8A and Figure 8B . Fig. 8A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Figure 8B It is along Fig. 8A BB in FIG. After the second isolation region 104 has been formed, the second photoresist pillars 142a, 142b and 142c are removed, for example using a photoresist ashing or stripping process. It is contemplated that the above process may be repeated to obtain a high density of isolation regions at a sub-micron pitch or even lower pitch.

[0049] refer to Fig. 9A and Fig. 9B . Fig. 9A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 9B It is along Fig. 9A A cross-sectional view taken along the line B'-B' in FIG. Fig. 7A and Figure 7B After the second photoresist layer 140 in the device substrate 110 is formed, a third photoresist layer 160 is formed over the front side 112 of the device substrate 110. The third photoresist layer 160 can be formed by depositing (e.g., spin coating) a photoresist film over the front side 112 of the device substrate 110, and then Figures 1C to 4BThe photoresist film is patterned by a third photolithography process in the same manner as discussed. The third photolithography process for patterning the third photoresist layer 160 is similar to the first photolithography process for the first photoresist layer 120, except that the third photolithography process uses a third photomask to pattern the third photoresist layer 160, and the pattern of the third photomask is substantially perpendicular to the first pattern 212 of the first photomask 210.

[0050] Fig. 9C A simplified top view of a third photomask 230 having a third pattern 232 is shown in accordance with some embodiments. The third photomask 230 is substantially identical to the first photomask 210, except that the third pattern 232 is substantially perpendicular to the first pattern 212 (i.e., rotated approximately 90 degrees from the first pattern 212). The first isolation region and the second isolation region are depicted in dashed lines for illustration purposes only. Similar to Figure 1C The first pattern 212 in the device substrate 110, the third pattern 232 can be a pattern of substantially parallel lines arranged in the second direction D2 and having a constant mask pitch P3 greater than about 1 micron, such as about 1.15 microns to about 3 microns, for example, about 1.2 microns to about 1.9 microns. In some embodiments, the pattern of substantially parallel lines has a mask pitch P3 of about 1.8 microns. The third pattern 232 allows pixel regions to be formed in a parallel line arrangement in the device substrate 110. In some embodiments, the mask pitch P1 (see Figure 1C ) and P3 may be substantially the same or different. It should be understood that the mask pitch P3 of the third pattern 232 may vary depending on the critical dimension (CD) of the pattern(s) to be formed in the third photoresist layer 160. The radiation beam may be scanned over the third photomask 230. The features of the third pattern 232 allow the radiation beam to pass through and expose a field 234 on the device substrate 110. The field 234 may define at least one edge of a die (or chip).

[0051] refer to Fig. 10A and Fig. 10B . Fig. 10A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 10B It is along Fig. 10A A cross-sectional view taken along line B'-B' in FIG. Fig. 10A and Fig. 10BIt is shown that the third pattern 230 according to some embodiments has been transferred to the third photoresist layer 160 to form third photoresist pillars 162a-162c on the front side 112 of the device substrate 110. It should be understood that the three (3) third photoresist pillars 162a-162c shown herein are for illustration purposes only. Depending on the third pattern 232 for the application, the third photoresist layer 160 may include any number of third photoresist pillars. For simplicity, three photoresist pillars 162a-162c of the third photoresist layer 160 will be discussed herein.

[0052] The photoresist columns 162a-162c define pixel regions of the image sensor device 100. For example, each of the photoresist columns 162a, 162b, and 162c defines a pixel region 118a, 118b, and 118c, respectively, in the device substrate 110. The pixel regions 118a, 118b, and 118c are regions where one or more pixels are to be formed. The pixel regions 118a, 118b, and 118c may be collectively referred to as the pixel array region 118 (or Figure 2B 16). The resist pitch P4 of the photoresist columns 162a, 162b and 162c substantially corresponds to the mask pitch P3 of the third pattern 232. The term "resist pitch" refers to the center-to-center distance between two adjacent photoresist columns. The pixel area spacing of pixel regions 118a, 118b and 118c may correspond to the resist pitch P4 of the third photoresist columns 162a, 162b and 162c. The term "pixel area spacing" described herein refers to the center-to-center distance between two adjacent pixel areas. In the case of using the pattern of substantially parallel lines discussed above, the pixel area spacing of pixel regions 118a, 118b and 118c is greater than 1 micron, such as about 1.15 microns to about 2 microns, such as about 1.2 microns to about 1.9 microns.

[0053] Each of the third photoresist columns 162a, 162b and 162c has a height H5 (i.e., vertical dimension) and a width W7 (i.e., lateral dimension). The aspect ratio of the third photoresist columns 162a, 162b and 162c can be defined as the ratio of the height H5 to the width W7. For a pixel size of about 1 micron, each of the third photoresist columns 162a, 162b and 162c can have an aspect ratio of about 3:1 to 1:1, for example, about 2:1. In some embodiments, the third photoresist columns 162a, 162b and 162c each have an aspect ratio of about 1:1. The third photoresist columns 162a, 162b and 162c are separated by gaps or grooves 163. The grooves 163 have a height equal to the height H5 of the third photoresist columns 162a, 162b and 162c, and a width W8. The aspect ratio of the groove 163 can be defined as the ratio of the height H5 to the width W8. The groove 163 has an aspect ratio of 10:1 or higher, for example, about 12:1 to about 30:1, for example, about 13:1 to about 25:1. Therefore, the aspect ratio of the third photoresist pillars 162a, 162b and 162c is lower than the aspect ratio of the groove 163. In some embodiments, the groove 163 has an aspect ratio of 15:1 to 20:1. In various embodiments, the ratio of the width W7 of each of the third photoresist pillars 162a, 162b and 162c to the width W8 of the groove 163 can be about 4:1 to about 30:1, for example, about 6:1 to about 20:1, for example, about 8:1 to about 10:1.

[0054] Although the trench 163 has an ultra-high aspect ratio of 10:1 or higher (e.g., 13:1, 15:1 or higher), the lower aspect ratio of the third photoresist pillars 162a, 162b, and 162c provides sufficient strength to the third photoresist pillars 162a, 162b, and 162c to withstand the capillary force inside the trench 163 without collapsing. Therefore, the possibility of the third photoresist pillars 162a, 162b, and 162c collapsing is reduced compared to those high aspect ratio photoresist layers having high aspect ratio photoresist pillars and trench aspect ratios of 10:1 or higher. As a result, the third photoresist pillars 162a, 162b and 162c can be formed taller and / or closer together (i.e., with higher aspect ratio trenches between the third photoresist pillars 162a, 162b and 162c) without the risk of the third photoresist pillars 162a, 162b and 162c collapsing.

[0055] In some embodiments, the possibility of collapse of the third photoresist pillars 162a, 162b, and 162c can be further reduced by applying a shrink material to the exposed surfaces of the third photoresist pillars 162a, 162b, and 162c, which will Fig. 20A and Fig. 20B Discussed in more detail in .

[0056] refer to Fig.11A and Fig. 11B . Fig.11A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 11B It is along Fig.11A . A cross-sectional view taken along line B'-B' in FIG. After the third photolithography process, a third ion implantation process 170 is performed on the device substrate 110 to form a third isolation region 106 in the device substrate 110. The third photoresist columns 162a, 162b, and 162c are used as a mask to perform the third ion implantation process 170 to implant ions into the device substrate 110 that is not protected by the third photoresist columns 162a, 162b, and 162c. The third isolation region 106 separates the pixel regions 118a, 118b, and 118c from each other. The third isolation region 106 prevents carriers at a specific pixel region from leaking to adjacent pixel regions (also referred to as crosstalk). In some embodiments, the third isolation region 106 may exceed the depth of each pixel to be formed in the pixel regions 118a, 118b, and 118c. In some embodiments, the third isolation region 106 can extend from the front side 112 of the device substrate 110 to the back side 114 to provide good isolation between the pixel regions 118a, 118b, and 118c. Because the third photoresist pillars 162a, 162b, and 162c are formed with ultra-high aspect ratio trenches between the third photoresist pillars 162a, 162b, and 162c, deeper isolation regions can be achieved with limited implant damage to the image sensor device (e.g., the isolation region can be formed with minimal lateral diffusion), even with high implant energy. As a result, ions can be implanted deeper to provide effective pixel-to-pixel isolation for the image sensor device 100.

[0057] The third isolation region 106 may be formed of a p-type or n-type material. The third isolation region 106 may be formed of a material having the same doping polarity as the device substrate 110 and / or the first isolation region 102 and the second isolation region 104. In some embodiments, the third isolation region 106 is a p-type region formed by injecting a p-type dopant (e.g., boron, boron fluoride (BF2), diborane (B2H6), etc.) into the device substrate 110. The doping concentration of the third isolation region 106 may be about 1×10 12 Ions / cm 3 About 1×10 20 Ions / cm 3 In the range of, for example, about 1×10 18 Ions / cm 3In some embodiments, the doping concentration of the first isolation region 102 may be about 5×10 11 Ions / cm 3 To about 5×10 17 Ions / cm 3 In the range of, for example, about 5×10 15 Ions / cm 3 In addition, the third isolation region 106 intersects the first isolation region 102 and the second isolation region 104, and the doping concentration of the intersecting portion thereof is greater than the doping concentration of the first isolation region 102, the second isolation region 104, and / or the third isolation region 106. For example, the doping concentration of the intersecting portion is substantially twice the doping concentration of the single first isolation region 102, the second isolation region 104, and / or the third isolation region 106.

[0058] Each third isolation region 106 has a height H6 (vertical dimension) and a width W9 (lateral dimension). The aspect ratio of the third isolation region 106 can be defined as the ratio of the height H6 to the width W9. In some embodiments, the third isolation region 106 has an aspect ratio of 10:1 or higher, such as about 12:1 to about 15:1. In some embodiments, the height H6 can be the same as the height H2 of the first isolation region 102 (see Figure 3B ) and / or the height H4 of the second isolation region 104 (see Figure 7B Alternatively, the height H6 of the third isolation region 106 may be substantially the same as the height H2 of the first isolation region 102 and / or the height H4 of the second isolation region 104.

[0059] refer to Fig. 12A and Fig. 12B . Fig. 12A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 12B It is along Fig. 12A After the third isolation region 106 has been formed, Fig.11A and Fig. 11B The third photoresist pillars 162a, 162b, and 162c in FIG. 1 (ie, the first photoresist layer 160) are removed, for example, using a photoresist ashing or stripping process.

[0060] refer to Fig.13A and Fig. 13B . Fig.13A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 13B It is along Fig.13A A cross-sectional view taken along the line B'-B' in FIG. Fig.11Aand Fig. 11B After the third photoresist layer 160 in the device substrate 110 is formed, a fourth photoresist layer 180 is formed over the front side 112 of the device substrate 110. The fourth photoresist layer 180 can be formed by depositing (e.g., spin coating) a photoresist film over the front side 112 of the device substrate 110, and then Figures 1C to 4B The photoresist film is patterned by a fourth photolithography process in the same manner as discussed. The fourth photolithography process for patterning the fourth photoresist layer 180 is similar to the third photolithography process for the third photoresist layer 160, except that the fourth photolithography process uses a fourth photomask to pattern the fourth photoresist layer 180, and the pattern of the fourth photomask is offset from the third pattern 232 of the third photomask 230 by about half a mask pitch.

[0061] Fig. 13C A simplified top view of a fourth photomask 240 having a fourth pattern 242 is shown in accordance with some embodiments. The fourth photomask 240 is substantially identical to the third photomask 230, except that the fourth pattern 242 is laterally offset from the third pattern 232 (in the second direction D2) by substantially half a mask pitch. The first isolation region, the second isolation region, and the third isolation region are depicted in dashed lines for illustration purposes only. Similar to Fig. 9C The third pattern 232 in the fourth pattern 242 can be a pattern of substantially parallel lines with a constant mask pitch P3' greater than about 1 micron, such as about 1.15 microns to about 3 microns, such as about 1.2 microns to about 1.9 microns. In some embodiments, the pattern of substantially parallel lines has a mask pitch P3' of about 1.8 microns. The lateral offset of the fourth pattern 242 allows pixel regions to be formed in a parallel line arrangement in the device substrate 110. In some embodiments, the mask pitch P3 (see Fig. 9C ) and P3' can be substantially the same.

[0062] Although the lateral offset of the fourth pattern 242 is discussed, the fourth pattern 242 can be offset from the third pattern 232 by half a mask pitch in any desired direction (e.g., in a lateral manner) to double the density of the isolation regions in the device substrate 110, as will be discussed in more detail below. In addition, it should be understood that the fourth pattern 242 is not limited to the pattern of substantially parallel lines shown. The fourth pattern 242 can be any other arrangement of patterns and can be used with the third pattern 232 so that the fourth photoresist layer 240 is patterned to provide two photoresist pillars having a resist pitch greater than 1 micron (e.g., about 1.2 microns to about 1.9 microns).

[0063] During the second photolithography process, the mask stage is operable to fix the fourth photomask 240 and manipulate the photomask in a transition and / or rotation mode. The substrate stage holding the device substrate 110 can also be manipulated in a transition and / or rotation mode. An alignment device is used to align the photomask and the device substrate 110 so that the radiation beam exposes a field 244 on the device substrate 110. The radiation beam (e.g., a krypton fluoride (KrF) excimer laser with a wavelength of 248nm, or an argon fluoride (ArF) excimer laser with a wavelength of 193nm) can be scanned over the second photomask 220 to expose the field 244 on the device substrate 110. In this way, the fourth pattern 242 is transferred to the fourth photoresist layer 180 at the exposure field 244. The photolithography apparatus steps the device substrate 110 to the next field (e.g., a scan field) to expose another field. The step-and-scan process may be performed in the same manner as the third photolithography process until the pixel array region of the device substrate 110 is exposed by the fourth pattern 242 .

[0064] Although the third photoresist layer 160 and the fourth photoresist layer 180 are patterned respectively using two different photomasks (i.e., the third photomask 230 and the fourth photomask 240), it is expected that the third photolithography process and the fourth photolithography process can use the same photomask to pattern the third photoresist layer 160 and the fourth photoresist layer 180 by moving the mask stage or the substrate stage to achieve a half-mask pitch offset movement.

[0065] refer to Fig.14A and Fig. 14B . Fig.14A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 14B It is along Fig.14A . It can be seen that the fourth pattern 242 has been transferred to the fourth photoresist layer 180 to form fourth photoresist columns 182a and 182b on the front side 112 of the device substrate 110. Although not shown, it should be understood that the patterned photoresist layer 180 has the same Fig. 10A and 10B The third photoresist pillars 162a, 162b, and 162c are shown arranged in a similar pattern of substantially parallel lines, except that the fourth photoresist pillars 182a and 182b are laterally offset from the third photoresist pillars 162a, 162b, and 162c by half a pitch.

[0066] The fourth photoresist columns 182a and 182b are separated by grooves 183. Groove 183 has a height H7 (vertical dimension) equal to the height of the fourth photoresist columns 182a and 182b, and a width W10 (lateral dimension). Groove 183 has a height-to-width ratio substantially the same as groove 163. For example, groove 183 may have a height-to-width ratio of 10:1 or higher, such as about 12:1 to about 30:1, such as about 13:1 to about 25:1. In some embodiments, groove 183 has a height-to-width ratio of 15:1 to 20:1. Similarly, for a pixel size of about 1 micron, each of the second photoresist columns 182a and 182b may have a height-to-width ratio of about 1:1 to about 3:1 or less, such as about 2:1. In some embodiments, each of the fourth photoresist columns 182a and 182b has a height-to-width ratio of about 1:1. Therefore, the aspect ratio of the fourth photoresist pillars 182a and 182b is lower than the aspect ratio of the trench 183. In various embodiments, a ratio of a width W11 of each of the fourth photoresist pillars 182a and 182b to a width W10 of the trench 183 may be about 4:1 to about 30:1, for example, about 6:1 to about 20:1, for example, about 8:1 to about 10:1.

[0067] Similarly, although the trench 183 has an ultra-high aspect ratio of 10:1 or higher (e.g., 13:1, 15:1 or higher), due to the lower aspect ratio of the fourth photoresist pillars 182a and 182b, the fourth photoresist pillars 182a and 182b have sufficient strength to withstand the capillary force inside the trench 183 without collapsing. Specifically, the ultra-high aspect ratio trench and the lower aspect ratio of the fourth photoresist pillars 182a and 182b produce an increased width W11 of each of the fourth photoresist pillars 182a and 182b, which achieves good adhesion of the fourth photoresist pillars 182a and 182b to the front side 112 of the device substrate 110. Therefore, compared with those high aspect ratio photoresist layers having a trench aspect ratio of 10:1 or higher, the possibility of the fourth photoresist pillars 182a and 182b collapsing is reduced. This means that the fourth photoresist pillars 182a and 182b can be formed taller or closer together (i.e., with a higher aspect ratio trench between the fourth photoresist pillars 182a and 182b) without the risk of the fourth photoresist pillars 182a and 182b collapsing. The combination of the lower aspect ratio (e.g., about 3:1 or lower) of the fourth photoresist pillars 182a and 182b and the ultra-high aspect ratio trench (e.g., 13:1 or higher) is advantageous when performing subsequent manufacturing processes (e.g., forming a fourth isolation region by ion implantation).

[0068] In some embodiments, the possibility of collapse of the fourth photoresist pillars 182a and 182b can be further reduced by applying a shrink material to the exposed surfaces of the fourth photoresist pillars 182a and 182b, which will Fig. 20A and Fig. 20B Discussed in more detail in .

[0069] refer to Fig.15A and Fig. 15B . Fig.15A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 15B It is along Fig.15A . A cross-sectional view taken along line B'-B' in FIG. After the fourth photolithography process, a fourth ion implantation process 190 is performed on the device substrate 110 to form a fourth isolation region 108 in the device substrate 110. The fourth ion implantation process 190 is performed using the fourth photoresist columns 182a and 182b as a mask to implant ions into the device substrate 110 in an area that is not protected by the fourth photoresist columns 182a and 182b. Because the fourth photoresist columns 182a and 182b are offset by half a pitch from the third photoresist columns 162a, 162b, and 162c, the resulting fourth isolation region 108 divides each of the pixel regions 119a, 119b, and 119c into halves, and the divided pixel regions are spaced apart from each other. The fourth isolation region 108 prevents carriers at a specific pixel region from leaking to an adjacent pixel region. The fourth isolation region 108 may exceed the depth of each pixel to be formed in the divided pixel region. In some embodiments, the fourth isolation region 108 can extend from the front side 112 of the device substrate 110 to the back side 114 to provide good isolation between the divided pixel regions. Because the fourth photoresist pillars 182a and 182b are formed with ultra-high aspect ratio trenches between the fourth photoresist pillars 182a and 182b, deeper isolation regions can be achieved with limited implant damage to the image sensor device (e.g., the isolation region can be formed with minimal lateral diffusion), even with high implant energy. As a result, ions can be implanted deeper to provide effective pixel-to-pixel isolation for the image sensor device 100.

[0070] Each fourth isolation region 108 has a height H8 (vertical dimension) and a width W12 (lateral dimension). The aspect ratio of the fourth isolation region 108 can be defined as the ratio of the height H8 to the width W12. In some embodiments, the fourth isolation region 108 has an aspect ratio of 10:1 or higher, for example, about 12:1 to about 15:1. Because the first isolation region 102, the second isolation region 104, the third isolation region 106, and the fourth isolation region 108 are formed separately, the height H8 of the fourth isolation region 108 can be the same as the height H2 of the first isolation region 102 (see Figure 3B ), the height H4 of the second isolation region 104 (see Figure 7B ), and / or the height H6 of the third isolation region 106 (see Fig. 11B Alternatively, the height H8 of the fourth isolation region 108 may be substantially the same as the height H2 of the first isolation region 102 , the height H4 of the second isolation region 104 , and / or the height H6 of the third isolation region 106 .

[0071] Similar to the third isolation region 106, the fourth isolation region 108 may be formed of a p-type or n-type material and include the same doping polarity as the device substrate 110 and / or the first isolation region 102, the second isolation region 104, and the third isolation region 106. For example, the fourth isolation region 108 may be a p-type region formed by implanting a p-type dopant (e.g., boron, boron fluoride (BF2), diborane (B2H6), etc.) into the device substrate 110. Similar to the third isolation region 106, the doping concentration of the fourth isolation region 108 may be approximately 1×10 12 Ions / cm 3 , and the maximum is about 5×10 17 Ions / cm 3 . The aspect ratio of each fourth isolation region 108 may be 10:1 or higher, for example, about 12:1 to about 15:1. In addition, the fourth isolation region 108 intersects the first isolation region 102 and the second isolation region 104, and the doping concentration of the intersecting portion thereof is greater than the doping concentration of the first isolation region 102, the second isolation region 104, and / or the third isolation region 106. For example, the doping concentration of the intersecting portion is substantially twice the doping concentration of the single first isolation region 102, the second isolation region 104, and the fourth isolation region 108. In addition, the third isolation region 106 and the fourth isolation region 108 are spaced apart from each other.

[0072] exist Fig. 13CIn the case where the fourth pattern 242 in FIG. 1 uses a pattern of substantially parallel lines having a mask pitch of about 1.8 microns, the fourth photolithography process and the fourth ion implantation process 190 will form the fourth isolation region 108 and the third isolation region 106 at a constant pitch P4′ of about 0.9 microns (which is sub-micron level). By performing two photolithography processes (i.e., two mask patterning processes), the pixel region (e.g., Fig.15A and Fig. 15B The density of the pixel regions 119a-119f shown is increased by more than a factor of two. Specifically, the photolithography process is performed using photoresist pillars with ultra-high aspect ratio trenches (eg, greater than 13:1) without the risk of photoresist pattern collapse.

[0073] refer to Fig.16A and Fig. 16B . Fig.16A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 16B It is along Fig.16A . After the fourth isolation region 108 has been formed, the fourth photoresist pillars 182a, 182b and 182c are removed, for example using a photoresist ashing or stripping process. It is contemplated that the above process may be repeated to obtain a high density of isolation regions at a sub-micron pitch or even lower pitch.

[0074] refer to Fig.17A and Fig. 17B . Fig.17A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 17B It is along Fig.17A After the fourth photoresist pillars 182a and 182b have been removed, the pixel regions 119a-119f (see Fig. 16B ) to form a plurality of pixels 310, such as Fig.17A and Fig. 17BAs shown. Pixel 310 may also be referred to as a radiation detection device or a light sensor. Pixel 310 includes a radiation sensing region. These radiation sensing regions may be formed by one or more ion implantation processes and have a doping polarity opposite to the device substrate 110 and / or the first isolation region 102, the second isolation region 104, the third isolation region 106, and the fourth isolation region 108. In the case where the device substrate 110 is a p-type substrate, the pixel 310 includes an n-type doped region. For a BSI image sensor device (e.g., image sensor device 100), the pixel 310 is operable to detect radiation projected from the back side 114 to the device substrate 110. In some embodiments, each pixel 310 includes a photodiode. In some embodiments, a deep implantation region may be formed below each photodiode. In some other embodiments, the pixels 310 may each include a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, and a transfer transistor.

[0075] exist Fig.17A , each pixel 310 has a length L1 and a width W13. The length L1 is defined by the adjacent first isolation region 102 and the second isolation region 104, and the width W13 is defined by the adjacent third isolation region 106 and the fourth isolation region 108. The length L1 and the width W13 are at a sub-micron level. For example, the length L1 and the width W13 are about 0.75 microns to about 0.95 microns. In some embodiments, the length L1 is substantially the same as the width W13. Alternatively, the length L1 is greater than or less than the width W13.

[0076] The intersection portions 109 of the first isolation region 102, the second isolation region 104, the third isolation region 106, and the fourth isolation region 108 are respectively located at the corners of the pixel 310. As described above, the doping concentration of the intersection portion 109 is greater than the doping concentration of the single first isolation region 102, the second isolation region 104, the third isolation region 106, and the fourth isolation region 108 (e.g., the portion 101 on the sidewall of the pixel 310). The doping concentration of the intersection portion 109 may be about twice the doping concentration of the portion 101.

[0077] An additive manufacturing process may be performed to complete the manufacture of the image sensor device 100. For example, Fig.18A and Fig.18B A cross-sectional view of an image sensor device 100 is shown in accordance with some embodiments. Fig.18A The cross-sectional position and Figure 8B The same, and Fig.18B The cross-sectional position and Fig. 17B Same. Fig.18A and Fig.18B1 , an interconnect structure 320 is formed over the front side 112 of the device substrate 110. The interconnect structure 320 may include a plurality of patterned dielectric layers and conductive layers that provide interconnections between various doping features, circuits, and input / outputs of the image sensor device 100. The interconnect structure 320 may include an interlayer dielectric (ILD) and a multilayer interconnect (MLI) structure. The MLI structure includes contacts, vias, and metal lines. For illustration purposes, Fig.18A and Fig.18B 3. A plurality of conductive lines 322 and vias / contacts 324 are shown. It should be understood that the conductive lines 322 and vias / contacts 324 shown are exemplary only, as the actual positioning and configuration of the lines / vias / contacts may vary depending on design needs and manufacturing requirements.

[0078] A buffer layer 330 may be formed on the interconnect structure 320. The buffer layer 330 may include a dielectric material, such as silicon oxide or silicon nitride. Thereafter, a carrier substrate 340 may be bonded to the device substrate 110 via the buffer layer 330 so that processing of the back side 114 of the device substrate 110 may be performed. The carrier substrate 340 may include a silicon substrate, a glass substrate, or any suitable substrate. The buffer layer 330 provides electrical isolation between the device substrate 110 and the carrier substrate 340. The carrier substrate 340 provides support and mechanical strength for processing of the back side 114 of the device substrate 110.

[0079] After the carrier substrate 340 is bonded, a thinning process is then performed to thin the device substrate 110 from the back side 114. The thinning process may include a mechanical grinding process and a chemical thinning process. After the thinning process, a color filter layer 350 may be formed on the back side 114' of the device substrate 110. The color filter layer 350 may include a plurality of color filters that may be positioned so that the incident radiation is directed thereon and passes through it. The color filter may include a dye-based (or pigment-based) polymer or resin for filtering incident radiation of a specific wavelength band that corresponds to a color spectrum (e.g., red, green, and blue). Thereafter, a microlens layer 360 including a plurality of microlenses 370 is formed over the color filter layer 350. The microlenses direct and focus the incident radiation to a specific radiation sensing area in the device substrate 102, such as a pixel 310. Depending on the refractive index of the material used for the microlenses and the distance from the sensor surface, the microlenses may be placed in various arrangements and have various shapes. It should be understood that the order of the above-described manufacturing processes is not intended to be limiting. In other embodiments different from those shown herein, some layers or devices may be formed according to a different processing order. Although the above discussion relates to BSI image sensor devices, it is contemplated that various aspects of the present disclosure may also be applied to front side illumination (FSI) image sensor devices.

[0080] Fig.19A and Fig.19B is a flow chart illustrating an exemplary method M for manufacturing an image sensor device according to various embodiments of the present disclosure. Although method M is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown, and / or the actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0081] At block S12 , a first photolithography process is performed using a first pattern of a first photomask to form first photoresist pillars on the front side of the device substrate. Figures 1A to 2B Top views and cross-sectional views of some embodiments corresponding to the actions in block S12 are shown. At block S14, a first ion implantation process is performed using the first photoresist pillars as a mask to implant first isolation regions in the device substrate. FIG. 3A to FIG. 4B Top views and cross-sectional views of some embodiments corresponding to the actions in block S14 are shown. At block S16, a second photolithography process is performed using a second pattern of a second photomask to form a second photoresist pillar on the front side of the device substrate. FIG. 5A to FIG. 6B Top views and cross-sectional views of some embodiments corresponding to the actions in block S16 are shown. At block S18, a second ion implantation process is performed using the second photoresist pillar as a mask to implant a second isolation region in the device substrate, wherein the first isolation region and the second isolation region are spaced apart from each other. 7A to 8B A top view and a cross-sectional view of some embodiments corresponding to the actions in block S18 are shown.

[0082] At block S20 , a third photolithography process is performed using a third pattern of a third photomask to form a third photoresist pillar on the front side of the device substrate. 9A to 10B Top views and cross-sectional views of some embodiments corresponding to the actions in block S20 are shown. At block S22, a third ion implantation process is performed using the third photoresist pillar as a mask to implant a third isolation region in the device substrate, wherein the third isolation region intersects the first isolation region and the second isolation region. FIG. 11A to FIG. 12B Top views and cross-sectional views of some embodiments corresponding to the actions in block S22 are shown. At block S24, a fourth photolithography process is performed using a fourth pattern of a fourth photomask to form fourth photoresist pillars on the front side of the device substrate. FIG. 13A to FIG. 14BA top view and a cross-sectional view of some embodiments corresponding to the actions in block S24 are shown. At block S26, a fourth ion implantation process is performed using the fourth photoresist pillar as a mask to implant a fourth isolation region in the device substrate, wherein the fourth isolation region intersects the first isolation region and the second isolation region and is spaced apart from the third isolation region. FIG. 15A to FIG. 16B Top and cross-sectional views of some embodiments corresponding to the actions in block S26 are shown. The first, second, third, and fourth isolation regions define pixel regions having a pixel region pitch at a sub-micron level (eg, about 0.75 microns to about 0.95 microns).

[0083] At block S28 , pixels are formed in pixel regions of the device substrate, respectively. FIG. 17A to FIG. 17B A top view and a cross-sectional view of some embodiments corresponding to the actions in block S28 are shown. At block S30, an interconnect structure, a buffer layer, and a carrier substrate are then formed on the front side of the device substrate. At block S32, a color filter layer and a microlens layer are then formed on the back side of the device substrate. FIG. 18A to FIG. 18B A cross-sectional view of some embodiments corresponding to the actions in blocks S30 and S32 is shown.

[0084] In some embodiments, a shrink material may optionally be applied to Figure 2B , Figure 6B , Fig. 10B and Fig. 14B The first photoresist columns 122a-122c, the second photoresist columns 142a-142b, the third photoresist columns 162a-162c, and / or the fourth photoresist columns 182a-182b are respectively shown in the figure to further prevent the collapse of the photoresist columns due to capillary forces. For simplicity, the description herein will use the first photoresist columns 122a-122c as an example.

[0085] Fig. 20A and Fig. 20BSimplified cross-sectional views of various stages for manufacturing an image sensor device 100 according to some embodiments are shown. After the first photoresist columns 122a-122c have been formed, the first photoresist columns 122a-122c are exposed to a shrink material using a suitable technique such as a spin coating process. The shrink material can be produced by uniformly mixing surfactant particles in a chemical material. The surfactant particles include compounds or molecules that reduce the surface tension between liquids or between a liquid and a solid. For example, the surfactant particles include molecules that are water-soluble at one end and oil-soluble at the other end. The surfactant molecules can aggregate to form micelles. In some embodiments, each surfactant particle includes a fluorine-containing compound. In some other embodiments, the surfactant particles include hydrocarbon compounds.

[0086] In some embodiments, the chemical material includes a "resolution enhanced lithography assisted by chemical shrinkage" material (or RELACS). RELACS materials include water-soluble materials (e.g., polymers) with thermal cross-linking properties. In some other embodiments, the chemical material includes a "shrinkage-assisted film for enhanced resolution" material (or SAFIER) developed by Tokyo Ohka Kogyo Co. The SAFIER material includes an aqueous solution that includes a thermally responsive polymer that helps the photoresist flow during the baking process. The SAFIER material may or may not chemically react with the photoresist, but provides mechanical support to the sidewalls of the photoresist as it flows. The mechanical support provided by the SAFIER material can minimize the degradation of the photoresist column profile. The SAFIER material can be removed in the development process after baking.

[0087] In some exemplary embodiments, the shrink material including the RELACS material discussed above is applied to the first photoresist pillars 122a-122c. A portion of the RELACS material applied to the first photoresist pillars 122a-122c may become cross-linked with the photoresist pillars 122a-122c and form a cross-linked film 410 on the exposed surfaces of the photoresist pillars 122a-122c during the baking process, as shown in FIG. Fig. 20A When the photoresist pillars 122a-122c are used as a mask in a subsequent ion implantation process, the cross-linked film 410 can be considered as a portion of the enlarged photoresist pillars 122a-122c. After baking, the remaining unreacted (eg, uncross-linked) RELACS material is removed in a development process. Figure 2BCompared with the previous groove 123 shown, the reduced groove 123' has an increased height (vertical dimension) H9 and a reduced width (lateral dimension) W14. The reduced width W14 allows a thinner isolation region to be formed in the device substrate. For example, the first photoresist column 122a-122c can be used as an ion implantation mask to form a thinner isolation region (and thus a wider pixel region) for an image sensor device. In addition, the surfactant particles 420 of the shrinkage material disposed on or near the sidewall 412 of the cross-linked film 410 reduce the surface tension of the sidewall surface. Capillary force is related to (or varies with) surface tension. Because the surface tension on the sidewall 412 is reduced due to the presence of the surfactant particles 420, the capillary force inside the groove 123' is reduced, which reduces the risk of the first photoresist column 122a-122c collapsing.

[0088] In some other exemplary embodiments, the shrink material including the SAFIER material discussed above is applied to the first photoresist pillars 122a-122c. The SAFIER material includes a thermoresponsive polymer that helps the first photoresist pillars 122a-122c flow during the baking process. In other words, the first photoresist pillars 122a-122c flow laterally outward and are reshaped into photoresist pillars 430, respectively. Fig. 20B As shown, the sidewalls of the photoresist pillars 430 are shown herein as dashed lines before the flow occurs. It can be seen that the sidewalls 432 of the reshaped photoresist pillars 430 are therefore brought closer to each other, thereby reducing the distance between the reshaped photoresist pillars 430. Due to the lateral expansion, the height H10 of the reshaped photoresist pillars 430 is also reduced. The shrink material (i.e., the SAFIER material) also provides some mechanical support to the sidewalls 432 of the reshaped photoresist pillars 430 during the photoresist flow, thereby allowing the sidewalls 432 to maintain their shape. Figure 2B Compared to the previous trench 123 shown, the reduced trench 123" has a reduced height (vertical dimension) H10 and a reduced width (lateral dimension) W15. The reduced width W15 allows a thinner isolation region to be formed in the device substrate. For example, the reshaped photoresist pillar 430 can be used as an ion implantation mask to form a thinner isolation region (and therefore a wider pixel region) for an image sensor device.

[0089] At least some of the surfactant particles 440 of the SAFIER disposed on (or near) the sidewall 432 reduce the surface tension of the sidewall 432. As described above, capillary force is related to (or varies with) surface tension. Because the surface tension on the sidewall 432 is reduced due to the presence of the surfactant particles 440, the capillary force that produces collapse is also reduced, which reduces the risk of the first photoresist column 122a-122c collapsing.

[0090] Fig.21A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 21B It is along Fig.21A A cross-sectional view taken along line BB in FIG. In some embodiments, the actions of frames S16 and S18 are omitted. That is, a second isolation region is not formed in the device substrate 110. Therefore, each pixel 310 has a rectangular shape in a top view. Specifically, each pixel 310 has a length L2 and a width W16. The length L2 is defined by two adjacent first isolation regions 102, and the width W16 is defined by adjacent third isolation regions 106 and fourth isolation regions 108. The length L2 is greater than the width W16 and is above the submicron level. For example, the length L2 is greater than about 1 micron, such as about 1.15 microns to about 3 microns, such as about 1.2 microns to about 1.9 microns. The width W16 is at the submicron level. For example, the width W16 is about 0.75 microns to about 0.95 microns. After forming the pixel 310, an additive manufacturing process may be performed to complete the manufacture of the image sensor device 100, such as Fig.22A and Fig. 22B As shown, Fig.22A With Fig. 21B same cross-sectional location, and Fig. 22B With Fig.18B Same cross-sectional location. Fig.22A and Fig. 22B Other relevant structural details of the image sensor device in are similar to Fig.18A and Fig.18B The image sensor device in the embodiment of the present invention is described below, and therefore the related description will not be repeated.

[0091] Fig.23A shows a simplified top view of a method for manufacturing an image sensor device 100 at various stages in accordance with some embodiments, and Fig. 23B It is along Fig.23AA cross-sectional view taken along line BB in FIG. 1 is a cross-sectional view taken along line BB in FIG. 1 . In some embodiments, the actions of frames S24 and S24 are omitted. That is, a fourth isolation region is not formed in the device substrate 110. Therefore, each pixel 310 has a rectangular shape in a top view. Specifically, each pixel 310 has a length L3 and a width W17. The width W17 is defined by the adjacent first isolation region 102 and the second isolation region 104, and the length L3 is defined by the adjacent two third isolation regions 106. The length L3 is greater than the width W17 and is above the submicron level. For example, the length L3 is greater than about 1 micron, such as about 1.15 microns to about 3 microns, such as about 1.2 microns to about 1.9 microns. The width W17 is at the submicron level. For example, the width W17 is about 0.75 microns to about 0.95 microns. After forming the pixel 310, an additive manufacturing process may be performed to complete the manufacture of the image sensor device 100, such as Fig.24A and Fig. 24B As shown, Fig.24A With Fig. 22B The same cross-sectional location, and Fig. 24B With Fig. 23B Same cross-sectional location. Fig.24A and Fig. 24B Other relevant structural details of the image sensor device in are similar to Fig.18A and Fig.18B The image sensor device in FIG. 1 is a schematic diagram of an image sensor device in the embodiment of the present invention, and therefore the related description will not be repeated.

[0092] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages in this article, and specific advantages are not required for all embodiments. One advantage is that the photoresist column is formed to have a low aspect ratio and an ultra-high aspect ratio groove between the photoresist columns without collapsing the photoresist column. In addition, because the photoresist column is formed to have an ultra-high aspect ratio groove between the photoresist columns, a deeper isolation region can be achieved with limited injection damage to the image sensor device (for example, the isolation region can be formed with minimal lateral diffusion), even if a high injection energy is used. As a result, ions can be implanted deeper to provide effective pixel-to-pixel isolation for the image sensor device. In addition, because the photoresist columns are substantially parallel lines spaced apart from each other, the formed pixels avoid the problem of corner rounding.

[0093] According to some embodiments, a method for manufacturing an image sensor device includes: forming a first photoresist layer on the front side of a device substrate. The first photoresist layer has first grooves spaced apart from each other. Performing a first implantation process using the first photoresist layer as a mask to form a first isolation region in the device substrate. Forming a second photoresist layer on the front side of the device substrate. The second photoresist layer has second grooves spaced apart from each other. Performing a second implantation process using the second photoresist layer as a mask to form a second isolation region in the device substrate and intersecting with the first isolation region. Forming a third photoresist layer on the front side of the device substrate. The third photoresist layer has third grooves spaced apart from each other. Performing a third implantation process using the third photoresist layer as a mask to form a third isolation region in the device substrate and intersecting with the first isolation region but spaced apart from the second isolation region.

[0094] According to some embodiments, a method for manufacturing an image sensor device includes: performing a first photolithography process using a first pattern of a first photomask to form a first photoresist pattern on a front side of a device substrate. The first pattern includes substantially parallel lines having a first pitch and arranged along a first direction. Performing a first implantation process using the first pattern as a mask to form a first isolation region in the device substrate. Performing a second photolithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate. The second pattern is offset from the first pattern in the first direction by a distance less than the first pitch. Performing a second implantation process using the second photoresist pattern as a mask to form a second isolation region in the device substrate and spaced apart from the first isolation region. Pixels are formed between the first isolation region and the second isolation region.

[0095] According to some embodiments, an image sensor device includes: a device substrate; an isolation region; and pixels. The isolation region is located in the device substrate and defines a pixel region in the device substrate. The pixels are respectively located in the pixel region. Each pixel has a length and a width. The width is less than about 1 micron. The doping concentration of some portions of the isolation region is greater than the doping concentration of another portion of the isolation region, the some portions are located at four corners of at least one pixel, and the other portion is located on a sidewall of at least one pixel.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0097] Example 1. A method for manufacturing an image sensor device, comprising: forming a first photoresist layer on the front side of a device substrate, wherein the first photoresist layer has first grooves spaced apart from each other; performing a first injection process using the first photoresist layer as a mask to form a first isolation region in the device substrate; forming a second photoresist layer on the front side of the device substrate, wherein the second photoresist layer has second grooves spaced apart from each other; performing a second injection process using the second photoresist layer as a mask to form a second isolation region in the device substrate and intersecting with the first isolation region; forming a third photoresist layer on the front side of the device substrate, wherein the third photoresist layer has third grooves spaced apart from each other; performing a third injection process using the third photoresist layer as a mask to form a third isolation region in the device substrate and intersecting with the first isolation region but spaced apart from the second isolation region.

[0098] Example 2. The method of Example 1, wherein the second trenches of the second photoresist layer have a first pitch, and the third trenches of the third photoresist layer have a second pitch that is the same as the first pitch.

[0099] Example 3. The method of Example 2, wherein the first spacing is greater than 1 micron.

[0100] Example 4. The method of Example 2, wherein the first grooves of the first photoresist layer have a third pitch greater than 1 micron.

[0101] Example 5. The method of Example 1, wherein the second isolation regions and the third isolation regions are arranged alternately.

[0102] Example 6. The method of Example 5, wherein a spacing between adjacent second isolation regions and third isolation regions is less than 1 micron.

[0103] Example 7. The method of Example 1, wherein each of the first grooves is formed with an aspect ratio of 10:1 or greater.

[0104] Example 8. The method of Example 1, wherein the second isolation region is perpendicular to the first isolation region.

[0105] Example 9. The method according to Example 1, wherein the first isolation region, the second isolation region, and the third isolation region define a plurality of pixel regions, and the method further comprises: forming pixels in the pixel regions, respectively.

[0106] Example 10. A method for manufacturing an image sensor device, comprising: performing a first photolithography process using a first pattern of a first photomask to form a first photoresist pattern on the front side of a device substrate, wherein the first pattern includes parallel lines having a first spacing and arranged along a first direction; performing a first injection process using the first pattern as a mask to form a first isolation region in the device substrate; performing a second photolithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being offset from the first pattern in the first direction by a distance less than the first spacing; performing a second injection process using the second photoresist pattern as a mask to form a second isolation region in the device substrate and spaced apart from the first isolation region; and forming a pixel between the first isolation region and the second isolation region.

[0107] Example 11. The method of Example 10, wherein the distance is half of the first spacing.

[0108] Example 12. The method of Example 10, wherein the first pattern and the second pattern are the same.

[0109] Example 13. The method of Example 10, wherein the first isolation region and the second isolation region have the same doping polarity.

[0110] Example 14. The method of Example 10, wherein the pixel and the first isolation region have different doping polarities.

[0111] Example 15. The method according to Example 10 further includes: performing a third photolithography process using a third pattern of a third photomask to form a third photoresist pattern on the front side of the device substrate, wherein the third pattern is rotated 90 degrees from the first pattern; and performing a third injection process using the third photoresist pattern as a mask to form a third isolation region in the device substrate and intersecting with the first isolation region and the second isolation region.

[0112] Example 16. The method according to Example 15 further includes: performing a fourth photolithography process using a fourth pattern of a fourth photomask to form a fourth photoresist pattern on the front side of the device substrate, wherein the fourth pattern is offset from the third pattern by a distance less than a second spacing of the third pattern; performing a fourth injection process using the fourth photoresist pattern as a mask to form a fourth isolation region in the device substrate, separated from the third isolation region but intersecting the first isolation region and the second isolation region.

[0113] Example 17. The method of Example 16, wherein the second pitch of the third pattern is the same as the first pitch of the first pattern.

[0114] Example 18. An image sensor device, comprising: a device substrate; an isolation region located in the device substrate and defining a pixel region in the device substrate; and pixels located in the pixel region, respectively, wherein each of the pixels has a length and a width, the width is less than 1 micron, and the doping concentration of some parts of the isolation region is greater than the doping concentration of another part of the isolation region, the some parts are located at the four corners of at least one of the pixels, and the other part is located on the side wall of the at least one pixel.

[0115] Example 19. An image sensor device according to Example 18, wherein the length of each of the pixels is greater than 1 micron.

[0116] Example 20. An image sensor device according to Example 18, wherein the length of each of the pixels is less than 1 micron.

Claims

1. A method for manufacturing an image sensor device, comprising: forming a first photoresist layer on the front side of the device substrate, wherein the first photoresist layer has first grooves spaced apart from each other; performing a first implantation process using the first photoresist layer as a mask to form a first isolation region in the device substrate; forming a second photoresist layer on the front side of the device substrate, wherein the second photoresist layer has second grooves spaced apart from each other; performing a second implantation process using the second photoresist layer as a mask to form a second isolation region in the device substrate and intersecting the first isolation region; forming a third photoresist layer on the front side of the device substrate, wherein the third photoresist layer has third trenches separated from each other; A third implantation process is performed using the third photoresist layer as a mask to form a third isolation region in the device substrate and intersecting the first isolation region but spaced apart from the second isolation region.

2. The method according to claim 1, wherein: The second trenches of the second photoresist layer have a first pitch, and the third trenches of the third photoresist layer have a second pitch that is the same as the first pitch.

3. The method according to claim 2, wherein: The first spacing is greater than 1 micron.

4. The method according to claim 2, wherein: The first trenches of the first photoresist layer have a third pitch greater than 1 micrometer.

5. The method according to claim 1, wherein: The second isolation regions and the third isolation regions are alternately arranged.

6. The method according to claim 5, wherein: The distance between adjacent second isolation regions and third isolation regions is less than 1 micrometer.

7. The method according to claim 1, wherein: Each of the first trenches is formed with an aspect ratio of 10:1 or more.

8. The method according to claim 1, wherein: The second isolation region is perpendicular to the first isolation region.

9. The method according to claim 1, wherein: The first isolation region, the second isolation region, and the third isolation region define a plurality of pixel regions, and the method further comprises: Pixels are formed in the pixel regions, respectively.

10. A method for manufacturing an image sensor device, comprising: Performing a first photolithography process using a first pattern of a first photomask to form a first photoresist pattern on the front side of the device substrate, wherein the first pattern includes parallel lines having a first pitch and arranged along a first direction; performing a first implantation process using the first pattern as a mask to form a first isolation region in the device substrate; performing a second photolithography process using a second pattern of a second photomask to form a second photoresist pattern on the front side of the device substrate, the second pattern being offset from the first pattern in the first direction by a distance less than the first pitch; performing a second implantation process using the second photoresist pattern as a mask to form a second isolation region in the device substrate and spaced apart from the first isolation region; performing a third photolithography process using a third pattern of a third photomask to form a third photoresist pattern on the front side of the device substrate, the third pattern being rotated 90 degrees from the first pattern; and performing a third implantation process using the third photoresist pattern as a mask to form a third isolation region in the device substrate and intersecting the first isolation region and the second isolation region; A pixel is formed between the first isolation region and the second isolation region.

11. The method according to claim 10, wherein: The distance is half of the first spacing.

12. The method according to claim 10, wherein: The first pattern and the second pattern are identical.

13. The method according to claim 10, wherein: The first isolation region and the second isolation region have the same doping polarity.

14. The method according to claim 10, wherein: The pixel and the first isolation region have different doping polarities.

15. The method according to claim 10, further comprising: performing a fourth photolithography process using a fourth pattern of a fourth photomask to form a fourth photoresist pattern on the front side of the device substrate, the fourth pattern being offset from the third pattern by a distance less than a second pitch of the third pattern; A fourth implantation process is performed using the fourth photoresist pattern as a mask to form a fourth isolation region in the device substrate and spaced apart from the third isolation region but crossing the first isolation region and the second isolation region.

16. The method according to claim 15, wherein: The second pitch of the third pattern is the same as the first pitch of the first pattern.

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