Common-mode interference suppression circuit and secondary instrument applicable to electromagnetic water meter

Abstract

The present invention discloses a common-mode interference suppression circuit and a secondary instrument applicable to an electromagnetic water meter. The circuit includes: a voltage division circuit module, a differential amplification circuit module, and a signal gating module. The signal gating module is configured such that: when receiving an excitation period not-started signal output from the excitation signal output terminal, the signal gating module controls to gate between the first non-inverting input terminal and the first voltage division output terminal, and to gate between the second non-inverting input terminal and the second voltage division output terminal; when receiving an excitation period started signal output from the excitation signal output terminal, the signal gating module controls to disconnect between the first non-inverting input terminal and the first voltage division output terminal, and to disconnect between the second non-inverting input terminal and the second voltage division output terminal. It can be seen that the present invention can deeply suppress the common-mode component in the voltage signal output by the instrument amplification circuit in the electromagnetic water meter, so as to further expand the adaptability of the electromagnetic water meter to various working conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a common-mode interference suppression circuit and a secondary instrument applicable to an electromagnetic water meter. Background Art

[0002] In existing electromagnetic water meters, there is generally a problem that the output signal has a high common-mode component signal, which requires a higher common-mode rejection ability of the pre-stage signal processing module in the secondary instrument. Usually, a high common-mode rejection ratio instrumentation amplifier is generally used as the pre-stage amplification circuit and a metal pipe or a grounding ring is used to meet the requirements of most working conditions. However, in the case where it is difficult to ground the instrument or the grounding is not good, the performance of the pre-stage instrumentation amplifier circuit in the secondary instrument will be affected. In the prior art, this influence is not taken into account, so that there is still a problem that the common-mode component in the final output signal of the electromagnetic water meter is not fully suppressed.

[0003] Obviously, it is necessary to provide a common-mode interference suppression technology applicable to an electromagnetic water meter to solve this problem. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a common-mode interference suppression circuit and a secondary instrument applicable to an electromagnetic water meter, which can deeply suppress the common-mode component in the voltage signal output by the instrumentation amplifier circuit in the electromagnetic water meter, so as to further expand the adaptability of the electromagnetic water meter to various working conditions.

[0005] To solve the above technical problem, in a first aspect of the present invention, a common-mode interference suppression circuit applicable to an electromagnetic water meter is disclosed. The circuit includes:

[0006] A voltage division circuit module, which has a voltage division input end, a first voltage division output end and a second voltage division output end; the voltage division input end is connected to the signal output end; the signal output end outputs the output signal of the primary instrument amplified by the instrumentation amplifier circuit;

[0007] A differential amplification circuit module, which has a first inverting input end, a second inverting input end, a first non-inverting input end, a second non-inverting input end, a first output end and a second output end; the first inverting input end is connected to the signal output end, and the second inverting input end is grounded; the first output end and the second output end are used to output the output signal processed by the present common-mode interference suppression circuit;

[0008] A signal gating module, the signal input end of the signal gating module is simultaneously connected to the first non-inverting input end, the first voltage-dividing output end, the second non-inverting input end, the second voltage-dividing output end, and the excitation signal output end of the signal sampling controller. Wherein the first non-inverting input end is also grounded through a first capacitor, and the second non-inverting input end is also grounded through a second capacitor; the signal gating module is configured as:

[0009] When receiving the excitation cycle not started signal output from the excitation signal output end, the signal gating module controls: gating between the first non-inverting input end and the first voltage-dividing output end, and gating between the second non-inverting input end and the second voltage-dividing output end;

[0010] When receiving the excitation cycle started signal output from the excitation signal output end, the signal gating module controls: disconnecting between the first non-inverting input end and the first voltage-dividing output end, and disconnecting between the second non-inverting input end and the second voltage-dividing output end.

[0011] As an optional implementation manner, in the first aspect of the present invention, the circuit further includes a first resistor, and the first resistor is disposed between the signal output end and the first inverting input end.

[0012] As an optional implementation manner, in the first aspect of the present invention, the signal gating module is a two-way single-pole double-throw switch.

[0013] As an optional implementation manner, in the first aspect of the present invention, the signal gating module has a first signal end, a second signal end, a third signal end, a fourth signal end, a fifth signal end, a sixth signal end, and a gating signal end; the first signal end and the fourth signal end are floating; the second signal end is connected to the first non-inverting input end; the third signal end is connected to the first voltage-dividing output end; the fifth signal end is connected to the second non-inverting input end; the sixth signal end is connected to the second voltage-dividing output end; the gating signal end is connected to the excitation signal output end of the signal sampling controller; the signal gating module is configured as:

[0014] When the gating signal end receives the excitation cycle not started signal output from the excitation signal output end, gating between the second signal end and the third signal end, and gating between the fifth signal end and the sixth signal end;

[0015] When the gating signal end receives the excitation cycle started signal output from the excitation signal output end, gating between the first signal end and the second signal end, and gating between the fourth signal end and the fifth signal end.

[0016] As an alternative implementation, in the first aspect of the present invention, the voltage dividing circuit module includes a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

[0017] The first end of the second resistor is connected to the signal output end, the second end of the second resistor is connected to the first end of the third resistor and the third signal end, the second end of the third resistor is connected to the voltage dividing power supply and the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor and the sixth signal end, and the second end of the fifth resistor is grounded.

[0018] As an alternative implementation, in the first aspect of the present invention, the differential amplification circuit module includes a first operational amplifier, a second operational amplifier, a sixth resistor, a seventh resistor, and an eighth resistor;

[0019] The inverting input terminal of the first operational amplifier is the first inverting input terminal, the non-inverting input terminal of the first operational amplifier is the first non-inverting input terminal, and the output terminal of the first operational amplifier is the first output terminal; the eighth resistor is disposed between the first inverting input terminal and the first output terminal;

[0020] The inverting input terminal of the second operational amplifier is the second inverting input terminal, the non-inverting input terminal of the second operational amplifier is the second non-inverting input terminal, and the output terminal of the second operational amplifier is the second output terminal; the seventh resistor is disposed between the second inverting input terminal and the second output terminal; the second inverting input terminal is grounded through the sixth resistor.

[0021] As an alternative implementation, in the first aspect of the present invention, the resistance values of the first resistor, the second resistor, the fourth resistor, the fifth resistor, and the sixth resistor are 10 KΩ.

[0022] As an alternative implementation, in the first aspect of the present invention, the resistance values of the third resistor and the eighth resistor are 200 KΩ, and the resistance values of the fourth resistor and the seventh resistor are 15 KΩ.

[0023] As an alternative implementation, in the first aspect of the present invention, the capacitance values of the first capacitor and the second capacitor are 1 μF.

[0024] The second aspect of the present invention discloses a secondary instrument, including an instrument amplification circuit, an AD conversion circuit, and a common-mode interference suppression circuit; wherein the output signal of the common-mode interference suppression circuit is connected to the AD conversion circuit; the common-mode interference suppression circuit includes:

[0025] A voltage dividing circuit module, the voltage dividing circuit module having a voltage dividing input terminal, a first voltage dividing output terminal, and a second voltage dividing output terminal; the voltage dividing input terminal is connected to the signal output terminal; the signal output terminal outputs the output signal of the primary instrument after being amplified by the instrumentation amplifier circuit.

[0026] A differential amplification circuit module, the differential amplification circuit module having a first inverting input terminal, a second inverting input terminal, a first non-inverting input terminal, a second non-inverting input terminal, a first output terminal, and a second output terminal; the first inverting input terminal is connected to the signal output terminal, and the second inverting input terminal is grounded; the first output terminal and the second output terminal are used to output the output signal processed by the common-mode interference suppression circuit of the present invention.

[0027] A signal gating module, the signal input terminal of the signal gating module is simultaneously connected to the first non-inverting input terminal, the first voltage dividing output terminal, the second non-inverting input terminal, the second voltage dividing output terminal, and the excitation signal output terminal of the signal sampling controller, wherein the first non-inverting input terminal is also grounded through a first capacitor, and the second non-inverting input terminal is also grounded through a second capacitor; the signal gating module is configured to:

[0028] When receiving the excitation period not started signal output by the excitation signal output terminal, the signal gating module controls: a connection is established between the first non-inverting input terminal and the first voltage dividing output terminal, and a connection is established between the second non-inverting input terminal and the second voltage dividing output terminal;

[0029] When receiving the excitation period started signal output by the excitation signal output terminal, the signal gating module controls: the connection between the first non-inverting input terminal and the first voltage dividing output terminal is disconnected, and the connection between the second non-inverting input terminal and the second voltage dividing output terminal is disconnected.

[0030] As an optional implementation manner, in the second aspect of the present invention, the circuit further includes a first resistor, and the first resistor is disposed between the signal output terminal and the first inverting input terminal.

[0031] As an optional implementation manner, in the second aspect of the present invention, the signal gating module is a two-way single-pole double-throw switch.

[0032] As an alternative embodiment, in the second aspect of the present invention, the signal gating module has a first signal terminal, a second signal terminal, a third signal terminal, a fourth signal terminal, a fifth signal terminal, a sixth signal terminal, and a gating signal terminal; the first signal terminal and the fourth signal terminal are floating; the second signal terminal is connected to the first non-inverting input terminal; the third signal terminal is connected to the first voltage-dividing output terminal; the fifth signal terminal is connected to the second non-inverting input terminal; the sixth signal terminal is connected to the second voltage-dividing output terminal; the gating signal terminal is connected to the excitation signal output terminal of the signal sampling controller; the signal gating module is configured as follows:

[0033] When the gating signal terminal receives the excitation period not started signal output from the excitation signal output terminal, the second signal terminal and the third signal terminal are gated, and the fifth signal terminal and the sixth signal terminal are gated;

[0034] When the gating signal terminal receives the excitation period started signal output from the excitation signal output terminal, the first signal terminal and the second signal terminal are gated, and the fourth signal terminal and the fifth signal terminal are gated.

[0035] As an alternative embodiment, in the second aspect of the present invention, the voltage-dividing circuit module includes a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

[0036] The first end of the second resistor is connected to the signal output terminal, the second end of the second resistor is connected to the first end of the third resistor and the third signal terminal, the second end of the third resistor is connected to the voltage-dividing power supply and the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor and the sixth signal terminal, and the second end of the fifth resistor is grounded.

[0037] As an alternative embodiment, in the second aspect of the present invention, the differential amplifier circuit module includes a first operational amplifier, a second operational amplifier, a sixth resistor, a seventh resistor, and an eighth resistor;

[0038] The inverting input terminal of the first operational amplifier is the first inverting input terminal, the non-inverting input terminal of the first operational amplifier is the first non-inverting input terminal, and the output terminal of the first operational amplifier is the first output terminal; the eighth resistor is disposed between the first inverting input terminal and the first output terminal;

[0039] The inverting input terminal of the second operational amplifier is the second inverting input terminal, the non-inverting input terminal of the second operational amplifier is the second non-inverting input terminal, and the output terminal of the second operational amplifier is the second output terminal; the seventh resistor is disposed between the second inverting input terminal and the second output terminal; the second inverting input terminal is grounded through the sixth resistor.

[0040] As an optional implementation manner, in the second aspect of the present invention, the resistance values of the first resistor, the second resistor, the fourth resistor, the fifth resistor, and the sixth resistor are 10 KΩ.

[0041] As an optional implementation manner, in the second aspect of the present invention, the resistance values of the third resistor and the eighth resistor are 200 KΩ, and the resistance values of the fourth resistor and the seventh resistor are 15 KΩ.

[0042] As an optional implementation manner, in the second aspect of the present invention, the capacitance values of the first capacitor and the second capacitor are 1 μF.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The embodiment of the present invention discloses a common-mode interference suppression circuit applicable to an electromagnetic water meter, which can deeply suppress the common-mode component in the voltage signal output by the meter amplifier circuit in the electromagnetic water meter, so as to further expand the adaptability of the electromagnetic water meter to various working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings without creative efforts based on these drawings.

[0046] Figure 1 is a schematic diagram of the functional modules of a common-mode interference suppression circuit applicable to an electromagnetic water meter disclosed in the embodiment of the present invention;

[0047] Figure 2 is a schematic circuit design diagram of a common-mode interference suppression circuit applicable to an electromagnetic water meter disclosed in the embodiment of the present invention;

[0048] Figure 3 is an equivalent circuit diagram of an existing electromagnetic water meter disclosed in the embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of the functional modules of a secondary instrument applicable to an electromagnetic water meter disclosed in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0050] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0051] The terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or terminal comprising a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or terminals.

[0052] Referring to "embodiments" herein means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0053] Before describing the embodiments of the present invention, the prior art addressed by the present invention will be described first. Refer to Figure 3 , Figure 3 is the equivalent circuit diagram of the sensor of the electromagnetic water meter in the prior art, where RJ is the insulation resistance of the sensor coil to the electrode; C0 is the distributed capacitance between the sensor coil and the electrode; Rs is the internal resistance of the sensor induction signal. In fact, Rs is the sum of the capacitive reactances formed by the two measurement electrodes of the sensor to the measurement liquid respectively. The bulk resistance of the measurement liquid is approximately regarded as zero, and the measured liquid is used as the grounding reference point. Therefore, Figure 3The signal internal resistance of the electromagnetic water meter in [it] is divided into two equal parts (except when the electrodes are contaminated); Rd is the sensor ground resistance; ES is the induced flow velocity signal, which is divided by the signal internal resistance into differential signals +Es / 2 and -Es / 2 that are equal in magnitude and opposite in direction. Generally, the sensor insulation resistance RJ to the ground is above 50 MΩ; the value of the distributed capacitance C0 may be dozens of μF. When the sensor is assembled, the method of shielding the counter electrode or the excitation coil can reduce the effect of the distributed capacitance to a very small level. In practical applications, the sensor ground resistance Rd can be several ohms, and its value directly determines the common-mode component voltage level in the flow signal. The larger Rd is, the higher the common-mode voltage is, and the higher the requirement for the common-mode rejection ability of the pre-stage signal processing module in the secondary instrument is. Generally, an instrumentation amplifier with a high common-mode rejection ratio is usually used as the pre-stage amplifier circuit and a metal pipe or a grounding ring is used to meet the requirements of most working conditions. However, in the case where it is difficult to ground the instrument or the grounding is not good, the instrumentation amplifier cannot achieve a good common-mode component rejection effect. Therefore, the present invention proposes the technical solutions described in the following embodiments to solve this problem.

[0054] Embodiment 1

[0055] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the functional modules of a common-mode interference suppression circuit applicable to an electromagnetic water meter disclosed in an embodiment of the present invention. As Figure 1 shown, the common-mode interference suppression circuit applicable to an electromagnetic water meter includes:

[0056] A voltage division circuit module 101, having a voltage division input terminal, a first voltage division output terminal, and a second voltage division output terminal; the voltage division input terminal is connected to the signal output terminal; the signal output terminal outputs the output signal of the primary instrument amplified by the instrumentation amplifier circuit;

[0057] A differential amplification circuit module 102, having a first inverting input terminal, a second inverting input terminal, a first non-inverting input terminal, a second non-inverting input terminal, a first output terminal, and a second output terminal; the first inverting input terminal is connected to the signal output terminal, and the second inverting input terminal is grounded; the first output terminal and the second output terminal are used to output the output signal processed by this common-mode interference suppression circuit;

[0058] A signal selection module 103, the signal input terminal of the signal selection module 103 is simultaneously connected to the first non-inverting input terminal, the first voltage division output terminal, the second non-inverting input terminal, the second voltage division output terminal, and the excitation signal output terminal of the signal sampling controller, wherein the first non-inverting input terminal is also grounded through a first capacitor, and the second non-inverting input terminal is also grounded through a second capacitor; the signal selection module 103 is configured as:

[0059] When receiving the excitation cycle not - started signal output from the excitation signal output terminal, the signal selection module 103 controls: to select - connect between the first non - inverting input terminal and the first voltage - dividing output terminal, and to select - connect between the second non - inverting input terminal and the second voltage - dividing output terminal;

[0060] When receiving the excitation cycle started signal output from the excitation signal output terminal, the signal selection module 103 controls: to disconnect between the first non - inverting input terminal and the first voltage - dividing output terminal, and to disconnect between the second non - inverting input terminal and the second voltage - dividing output terminal.

[0061] As an alternative implementation, in the embodiment of the present invention, the circuit further includes a first resistor, and the first resistor is disposed between the signal output terminal and the first inverting input terminal.

[0062] As an alternative implementation, in the embodiment of the present invention, the signal selection module 103 is a two - way single - pole double - throw switch.

[0063] As an alternative implementation, in the embodiment of the present invention, the signal selection module 103 has a first signal terminal, a second signal terminal, a third signal terminal, a fourth signal terminal, a fifth signal terminal, a sixth signal terminal, and a selection signal terminal; the first signal terminal and the fourth signal terminal are floating; the second signal terminal is connected to the first non - inverting input terminal; the third signal terminal is connected to the first voltage - dividing output terminal; the fifth signal terminal is connected to the second non - inverting input terminal; the sixth signal terminal is connected to the second voltage - dividing output terminal; the selection signal terminal is connected to the excitation signal output terminal of the signal sampling controller; the signal selection module 103 is configured as:

[0064] When the selection signal terminal receives the excitation cycle not - started signal output from the excitation signal output terminal, a connection is made between the second signal terminal and the third signal terminal, and a connection is made between the fifth signal terminal and the sixth signal terminal;

[0065] When the selection signal terminal receives the excitation cycle started signal output from the excitation signal output terminal, a connection is made between the first signal terminal and the second signal terminal, and a connection is made between the fourth signal terminal and the fifth signal terminal.

[0066] As an alternative implementation, in the embodiment of the present invention, the voltage - dividing circuit module 101 includes a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

[0067] The first end of the second resistor is connected to the signal output terminal, the second end of the second resistor is connected to the first end of the third resistor and the third signal terminal, the second end of the third resistor is connected to the voltage - dividing power supply and the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor and the sixth signal terminal, and the second end of the fifth resistor is grounded.

[0068] As an alternative embodiment, in the embodiment of the present invention, the differential amplifier circuit module 102 includes a first operational amplifier, a second operational amplifier, a sixth resistor, a seventh resistor, and an eighth resistor;

[0069] The inverting input terminal of the first operational amplifier is the first inverting input terminal, the non-inverting input terminal of the first operational amplifier is the first non-inverting input terminal, and the output terminal of the first operational amplifier is the first output terminal; the eighth resistor is disposed between the first inverting input terminal and the first output terminal;

[0070] The inverting input terminal of the second operational amplifier is the second inverting input terminal, the non-inverting input terminal of the second operational amplifier is the second non-inverting input terminal, and the output terminal of the second operational amplifier is the second output terminal; the seventh resistor is disposed between the second inverting input terminal and the second output terminal; the second inverting input terminal is grounded through the sixth resistor.

[0071] As an alternative embodiment, in the embodiment of the present invention, the resistance values of the first resistor, the second resistor, the fourth resistor, the fifth resistor, and the sixth resistor are 10 KΩ.

[0072] As an alternative embodiment, in the embodiment of the present invention, the resistance values of the third resistor and the eighth resistor are 200 KΩ, and the resistance values of the fourth resistor and the seventh resistor are 15 KΩ.

[0073] As an alternative embodiment, in the embodiment of the present invention, the capacitance values of the first capacitor and the second capacitor are 1 μF.

[0074] Regarding the common-mode interference suppression circuit disclosed in the embodiment of the present invention, the circuit design schematic diagram can be referred to Figure 2 , specifically, the working principle of this circuit design is described below:

[0075] Figure 2 In, FmV is the above-mentioned signal output terminal, which is the single-ended output signal after the voltage signal output by the primary instrument electrode pair of the electromagnetic water meter is processed by the pre-stage instrument amplifier. Its amplitude contains both the common-mode component caused by reasons such as the primary instrument ground resistance and the real flow component. U1 is the above-mentioned two-way single-pole double-throw switch, and its main function is sampling and holding. Among them, PIN1 and PIN14 are the strobe pins, that is, the above-mentioned strobe signal terminals, connected to P3.0, and the conduction direction of the two switches is controlled by P3.0. Specifically, P3.0 is the I / O port control level signal of the MCU. At the moment when the excitation period starts, the I / O port of the MCU controls P3.0 to change from a low level to a high level. C1 and C2 are two identical 1Uf large capacitors, that is, the above-mentioned first capacitor and second capacitor, and their temperature characteristics show a linear change trend, which are the core components of the present invention.

[0076] Specifically, the control logic truth table of U1 is shown as follows:

[0077]

[0078] According to the characteristics of the electromagnetic water meter, its excitation and flow signal sampling are carried out synchronously. The flow signal "FmV" can be sampled only after the magnetic field of the primary instrument coil reaches a steady state; otherwise, the accuracy of the measurement result cannot be guaranteed. Therefore, the timing of the flow signal sampling must be strictly controlled to achieve the flow measurement function of the instrument. And the stability state of the magnetic field of the primary instrument coil can be accurately judged by the magnetizing current. The detailed process is as follows:

[0079] Step 1: Before the start of the excitation period, both the A0 and A1 pins are "0", and "S1A, S2A" are conducting. At this time, PIN6 is connected to PIN4, and PIN9 is connected to PIN11, that is, the selection is made between the second signal terminal and the third signal terminal above, and the selection is made between the fifth signal terminal and the sixth signal terminal. The common-mode component caused by the grounding resistance or differential interference, etc., becomes "FmV" after being processed by the front-stage instrumentation amplifier, and is set as "FmV0" at this time. "FmV0" passes through the voltage division circuit module, that is, it is divided by R2 and R3 (that is, the second resistor and the third resistor above) with the "+1.2V" voltage (that is, the voltage division power supply above) and then transmitted to PIN4, and finally charges C1 through PIN6 all the time, and the voltage value is . At the same time, the "+1.2V" voltage is divided by R4 and R5 (that is, the fourth resistor and the fifth resistor) and then transmitted to PIN11, and finally charges C2 through PIN9 all the time, and its voltage value is .

[0080] Step 2: At the moment when the excitation period starts, the A0 and A1 pins instantly become "1" at the same time, and "S1B, S2B" are conducting. At this time, PIN6 is connected to PIN5, and PIN9 is connected to PIN10, that is, the selection is made between the first signal terminal and the second signal terminal above, and the selection is made between the fourth signal terminal and the fifth signal terminal. Capacitors C1 and C2 are in a floating state. Since the sampling time is very short, it can be considered that the voltages on capacitors C1 and C2 remain unchanged during the entire sampling period. As the excitation current rises, the voltage on "FmV" also rises continuously until the magnetic field steady state is established and the AD converter is ready to sample. At this time, FmV can be set as "FmV1", where "FmV1" contains both the common-mode component "FmV0" and the real flow signal component "(FmV1 - FmV0)".

[0081] Step 3: After "FmV" passes through the differential amplifier circuit composed of U1A and U2B (that is, the first operational amplifier and the second operational amplifier in the differential amplifier circuit module above), it becomes a pair of differential signals , where S_+ and S_- are the first output terminal and the second output terminal above, and the transfer function is , with a gain of -20 times.

[0082] From the above analysis, it can be obtained that the present invention can eliminate the common-mode component "FmV0" in the "FmV" output by the pre-stage instrumentation amplifier caused by reasons such as ground resistance or differential interference, and only amplify the " " that reflects the true flow signal with a gain of -20, so that the entire pre-stage signal processing module is in a normal working state and the design purpose is achieved.

[0083] Embodiment 2

[0084] See Figure 4 , the embodiment of the present invention discloses a secondary instrument, including an instrumentation amplifier circuit, an AD conversion circuit, and a common-mode interference suppression circuit; wherein the output signal of the common-mode interference suppression circuit is connected to the AD conversion circuit. As Figure 1 shown, the common-mode interference suppression circuit includes:

[0085] A voltage division circuit module 101, having a voltage division input terminal, a first voltage division output terminal, and a second voltage division output terminal; the voltage division input terminal is connected to the signal output terminal; the signal output terminal outputs the output signal of the primary instrument amplified by the instrumentation amplifier circuit;

[0086] A differential amplifier circuit module 102, having a first inverting input terminal, a second inverting input terminal, a first non-inverting input terminal, a second non-inverting input terminal, a first output terminal, and a second output terminal; the first inverting input terminal is connected to the signal output terminal, and the second inverting input terminal is grounded; the first output terminal and the second output terminal are used to output the output signal processed by the present common-mode interference suppression circuit;

[0087] A signal selection module 103, the signal input terminal of the signal selection module 103 is simultaneously connected to the first non-inverting input terminal, the first voltage division output terminal, the second non-inverting input terminal, the second voltage division output terminal, and the excitation signal output terminal of the signal sampling controller, wherein the first non-inverting input terminal is also grounded through a first capacitor, and the second non-inverting input terminal is also grounded through a second capacitor; the signal selection module 103 is configured as:

[0088] When receiving the excitation period not started signal output by the excitation signal output terminal, the signal selection module 103 controls: a connection is selected between the first non-inverting input terminal and the first voltage division output terminal, and a connection is selected between the second non-inverting input terminal and the second voltage division output terminal;

[0089] When receiving the excitation period started signal output by the excitation signal output terminal, the signal selection module 103 controls: the connection between the first non-inverting input terminal and the first voltage division output terminal is disconnected, and the connection between the second non-inverting input terminal and the second voltage division output terminal is disconnected.

[0090] As an alternative embodiment, in the embodiment of the present invention, the circuit further includes a first resistor, and the first resistor is disposed between the signal output terminal and the first inverting input terminal.

[0091] As an alternative embodiment, in the embodiment of the present invention, the signal gating module 103 is a two-way single-pole double-throw switch.

[0092] As an alternative embodiment, in the embodiment of the present invention, the signal gating module 103 has a first signal terminal, a second signal terminal, a third signal terminal, a fourth signal terminal, a fifth signal terminal, a sixth signal terminal, and a gating signal terminal; the first signal terminal and the fourth signal terminal are floating; the second signal terminal is connected to the first non-inverting input terminal; the third signal terminal is connected to the first voltage-dividing output terminal; the fifth signal terminal is connected to the second non-inverting input terminal; the sixth signal terminal is connected to the second voltage-dividing output terminal; the gating signal terminal is connected to the excitation signal output terminal of the signal sampling controller; the signal gating module 103 is configured as follows:

[0093] When the gating signal terminal receives the excitation period not started signal output from the excitation signal output terminal, the second signal terminal and the third signal terminal are gated, and the fifth signal terminal and the sixth signal terminal are gated;

[0094] When the gating signal terminal receives the excitation period started signal output from the excitation signal output terminal, the first signal terminal and the second signal terminal are gated, and the fourth signal terminal and the fifth signal terminal are gated.

[0095] As an alternative embodiment, in the embodiment of the present invention, the voltage-dividing circuit module 101 includes a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

[0096] The first end of the second resistor is connected to the signal output terminal, the second end of the second resistor is connected to the first end of the third resistor and the third signal terminal, the second end of the third resistor is connected to the voltage-dividing power supply and the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor and the sixth signal terminal, and the second end of the fifth resistor is grounded.

[0097] As an alternative embodiment, in the embodiment of the present invention, the differential amplifier circuit module 102 includes a first operational amplifier, a second operational amplifier, a sixth resistor, a seventh resistor, and an eighth resistor;

[0098] The inverting input terminal of the first operational amplifier is the first inverting input terminal, the non-inverting input terminal of the first operational amplifier is the first non-inverting input terminal, and the output terminal of the first operational amplifier is the first output terminal; the eighth resistor is disposed between the first inverting input terminal and the first output terminal;

[0099] The inverting input terminal of the second operational amplifier is the second inverting input terminal, the non-inverting input terminal of the second operational amplifier is the second non-inverting input terminal, and the output terminal of the second operational amplifier is the second output terminal; the seventh resistor is disposed between the second inverting input terminal and the second output terminal; the second inverting input terminal is grounded through the sixth resistor.

[0100] As an alternative embodiment, in the embodiment of the present invention, a second current limiting resistor is further disposed between the base of the trigger operational amplifier unit and the control signal output terminal of the single-chip microcomputer, and / or a current limiting resistor unit is further disposed between the collector of the trigger triode unit and the trigger terminal of the thyristor unit.

[0101] As an alternative embodiment, in the embodiment of the present invention, the resistance values of the first resistor, the second resistor, the fourth resistor, the fifth resistor, and the sixth resistor are 10 KΩ.

[0102] As an alternative embodiment, in the embodiment of the present invention, the resistance values of the third resistor and the eighth resistor are 200 KΩ, and the resistance values of the fourth resistor and the seventh resistor are 15 KΩ.

[0103] As an alternative embodiment, in the embodiment of the present invention, the capacitance values of the first capacitor and the second capacitor are 1 μF.

[0104] The device embodiments described above are merely illustrative, where the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0105] Finally, it should be noted that: the common-mode interference suppression circuit and the secondary instrument applicable to the electromagnetic water meter disclosed in the embodiments of the present invention only disclose the preferred embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A common-mode interference suppression circuit applicable to an electromagnetic water meter, characterized in that, The circuit includes: A voltage division circuit module, which has a voltage division input terminal, a first voltage division output terminal, and a second voltage division output terminal; the voltage division input terminal is connected to the signal output terminal; the signal output terminal outputs the output signal of the primary instrument after being amplified by the instrumentation amplifier circuit; A differential amplifier circuit module, which has a first inverting input terminal, a second inverting input terminal, a first non-inverting input terminal, a second non-inverting input terminal, a first output terminal, and a second output terminal; the first inverting input terminal is connected to the signal output terminal, and the second inverting input terminal is grounded; the first output terminal and the second output terminal are used to output the output signal after being processed by this common-mode interference suppression circuit; A signal selection module, the signal input terminal of the signal selection module is simultaneously connected to the first non-inverting input terminal, the first voltage division output terminal, the second non-inverting input terminal, the second voltage division output terminal, and the excitation signal output terminal of the signal sampling controller, wherein the first non-inverting input terminal is also grounded through a first capacitor, and the second non-inverting input terminal is also grounded through a second capacitor; the signal selection module is configured as: When receiving the excitation period not started signal output by the excitation signal output terminal, the signal selection module controls: a connection is established between the first non-inverting input terminal and the first voltage division output terminal, and a connection is established between the second non-inverting input terminal and the second voltage division output terminal; When receiving the excitation period started signal output by the excitation signal output terminal, the signal selection module controls: the connection between the first non-inverting input terminal and the first voltage division output terminal is disconnected, and the connection between the second non-inverting input terminal and the second voltage division output terminal is disconnected.

2. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 1, wherein The circuit further includes a first resistor, and the first resistor is arranged between the signal output terminal and the first inverting input terminal.

3. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 2, characterized in that, The signal selection module is a two-way single-pole double-throw switch.

4. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 3, characterized in that, The signal selection module has a first signal terminal, a second signal terminal, a third signal terminal, a fourth signal terminal, a fifth signal terminal, a sixth signal terminal, and a selection signal terminal; the first signal terminal and the fourth signal terminal are floating; the second signal terminal is connected to the first non-inverting input terminal; the third signal terminal is connected to the first voltage division output terminal; the fifth signal terminal is connected to the second non-inverting input terminal; the sixth signal terminal is connected to the second voltage division output terminal; the selection signal terminal is connected to the excitation signal output terminal; the signal selection module is configured as: When the selection signal terminal receives the excitation period not started signal output by the excitation signal output terminal, a connection is established between the second signal terminal and the third signal terminal, and a connection is established between the fifth signal terminal and the sixth signal terminal; When the selection signal terminal receives the excitation period started signal output by the excitation signal output terminal, a connection is established between the first signal terminal and the second signal terminal, and a connection is established between the fourth signal terminal and the fifth signal terminal.

5. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 4, characterized in that, The voltage division circuit module includes a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The first end of the second resistor is connected to the signal output terminal, the second end of the second resistor is connected to the first end of the third resistor and the third signal terminal, the second end of the third resistor is connected to the voltage-dividing power supply and the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the fifth resistor and the sixth signal terminal, and the second end of the fifth resistor is grounded.

6. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 5, characterized in that, The differential amplifier circuit module includes a first operational amplifier, a second operational amplifier, a sixth resistor, a seventh resistor, and an eighth resistor; The inverting input terminal of the first operational amplifier is the first inverting input terminal, the non-inverting input terminal of the first operational amplifier is the first non-inverting input terminal, and the output terminal of the first operational amplifier is the first output terminal; the eighth resistor is disposed between the first inverting input terminal and the first output terminal; The inverting input terminal of the second operational amplifier is the second inverting input terminal, the non-inverting input terminal of the second operational amplifier is the second non-inverting input terminal, and the output terminal of the second operational amplifier is the second output terminal; the seventh resistor is disposed between the second inverting input terminal and the second output terminal; the second inverting input terminal is grounded through the sixth resistor.

7. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 6, characterized in that, The resistance values of the first resistor, the second resistor, the fourth resistor, the fifth resistor, and the sixth resistor are 10 KΩ.

8. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 7, wherein The resistance values of the third resistor and the eighth resistor are 200 KΩ, and the resistance values of the fourth resistor and the seventh resistor are 15 KΩ.

9. The common-mode interference suppression circuit applicable to an electromagnetic water meter according to claim 1, wherein The capacitance values of the first capacitor and the second capacitor are 1 μF.

10. A secondary instrument, characterized in that, It includes an instrumentation amplifier circuit, an AD conversion circuit, and a common-mode interference suppression circuit for an electromagnetic water meter as described in any one of claims 1 to 9; wherein the output signal of the common-mode interference suppression circuit is connected to the AD conversion circuit.

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