Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods for manufacturing the same. In a gate replacement process, a dummy gate and adjacent structures are formed; in a gate replacement process, a dummy gate and adjacent structures, such as source / drain regions, are formed. A directional etch is used to at least partially remove the dummy gate to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate is retained and protects adjacent structures. A gate electrode can then be formed in the trench. A two-step process can be used, first using an isotropic etch and then a directional etch.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the manufacture of semiconductor devices such as FinFETs or other transistors, a "gate last" process is often employed in which a dummy gate structure is first formed and subsequently replaced with a metal gate. During the etching process used to remove the dummy structure, surrounding structures, such as source / drain regions, may be damaged. Therefore, there is a need for improved etching processes and resulting structures. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a dummy gate and an adjacent structure; using directional etching to remove some but not all of the dummy gate to form a trench, wherein a portion of the dummy gate is retained and protects the adjacent structure; and forming a gate electrode in the trench.

[0004] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a fin extending from a semiconductor substrate; depositing a dummy gate material over the fin; patterning the dummy gate material to form a dummy gate over the top of the fin and extending along the sidewall of the fin; depositing a spacer material on the dummy gate, and patterning the spacer material to form a spacer on the corresponding sidewall of the dummy gate; etching a portion of the fin to form a fin groove using the dummy gate and the spacer as a mask; filling each fin groove with a source / drain region; depositing a dielectric layer to surround the dummy gate, the source / drain region and the fin; isotropically etching the dummy gate to remove a top portion of the dummy gate and leaving a bottom portion of the dummy gate; anisotropically etching the bottom portion of the dummy gate to partially remove the bottom portion of the dummy gate and leaving a residual portion of the dummy gate; and forming a metal gate electrode on the residual portion of the dummy gate.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin extending upward from a substrate; an isolation material formed on the fin; a gate within a trench in the isolation material and comprising a gate dielectric, the gate extending over the top and sidewalls of the fin; and a polysilicon material extending along a bottom portion of the trench, the polysilicon material being located between the gate dielectric and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 , Figure 2 , Figure 3A-3B , Figure 4 , Figure 5A-5B , Figures 6A-6D , Figure 7A-7B , Figures 8A-8D and Figures 9A-9B Intermediate steps in an exemplary method of forming a device (eg, a transistor) using a two-step removal process to remove a dummy gate stack and the resulting device are shown.

[0008] Fig.10 is a flow chart showing relevant steps in an exemplary method as disclosed herein. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for realizing the different features of the subject matter provided by the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0011] According to various exemplary embodiments, transistors formed using a replacement gate process and methods for forming the same are provided. According to some embodiments, intermediate stages of forming a transistor are shown. Some variations of some embodiments are discussed. Throughout the various views and exemplary embodiments, the same reference numerals are used to represent the same elements. In the exemplary embodiments shown, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Other multi-gate transistors, gate all around (gate all around, GAA) transistors, and in some cases planar transistors may also employ embodiments of the present disclosure.

[0012] Figures 1 to 9B Cross-sectional, perspective, and plan views are shown of intermediate stages in forming a semiconductor device such as a FinFET transistor according to some embodiments of the present disclosure. Figures 1 to 9B The steps shown are also schematically reflected in Fig.10 In the process flow 200 shown.

[0013] Figure 1 A perspective view of an initial structure is shown. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. An isolation region 22 such as a shallow trench isolation (STI) region may be formed to extend from the top surface of the substrate 20 into the substrate 20. The portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some exemplary embodiments, the top surface of the semiconductor strip 24 and the top surface of the STI region 22 may be substantially flush with each other. According to some embodiments of the present disclosure, the semiconductor strip 24 is a portion of the original substrate 20, and therefore, the material of the semiconductor strip 24 is the same as that of the substrate 20. According to an alternative embodiment of the present disclosure, the semiconductor strip 24 is a replacement strip formed by etching the portion of the substrate 20 between the STI regions 22 to form a groove, and performing epitaxy to grow another semiconductor material in the groove. Therefore, the semiconductor strips 24 are formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some exemplary embodiments, the semiconductor strips 24 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material. Although only two semiconductor strips 24 are shown, in an embodiment, many, even thousands or more semiconductor strips 24 are formed on the substrate 20. In addition, it is worth noting that the drawings are not drawn to scale. Instead, some features are shown as exaggerated in size, thickness, depth, etc. to allow for easier understanding of the disclosed features.

[0014] STI regions 22 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 22 may also include a dielectric material over the liner oxide, which may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0015] refer to Figure 2 , the STI region 22 is recessed so that the top portion of the semiconductor strip 24 protrudes higher than the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding steps are as follows Fig.10 This is shown as step 202 in the illustrated process flow 200. The etching may be performed using a dry etching process in which HF3 and NH3 are used as etching gases. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of the STI region 22. The etching chemistry may include, for example, a HF solution.

[0016] In the above exemplary embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with a spacing that is, for example, smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0017] The material of the protruding fin 24' can also be replaced with a material different from that of the substrate 20. For example, the protruding fin 24' can be formed of the following: Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge or III-V compound semiconductors (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs), etc. It should be noted that not all fins on the substrate need to have the same size, shape or material. As an example, it is conceivable that some fins will be used to make p-type transistors (or capacitors, diodes, etc. using p-type transistor structures), while other fins will be used to make n-type transistors (or capacitors, diodes, etc. using n-type transistor structures). Therefore, for example, the so-called p-type fins on the substrate can all have the same material, but can have different materials (or at least partially different materials) relative to the so-called n-type fins. As another example, some fins on the substrate, whether n-type or p-type, may differ from other fins in fin length or even fin width. After understanding the present disclosure, as will be apparent to those skilled in the art, the difference in fin width can result in differences in the channel length of the resulting transistors formed on each fin.

[0018] refer to Figure 3A , a dummy gate stack 30 is formed on the top surface and sidewalls of the (protruding) fin 24'. The corresponding steps are as follows Fig.10 The process flow 200 shown is shown as step 204. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on the dummy gate dielectric 32. For example, polysilicon may be used to form the dummy gate electrode 34, and other materials may also be used. Each of the dummy gate stacks 30 may also include one (or more) hard mask layers 36 on the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 30 may span a single or multiple protruding fins 24' and / or STI regions 22. The longitudinal direction of the dummy gate stack 30 is also perpendicular to the longitudinal direction of the protruding fin 24'. Those skilled in the art will recognize that the dummy gate stack may be formed by blanket depositing one or more layers of material from which the dummy gate stack is formed, and then patterning these layers individually or collectively using photolithography and etching or other patterning techniques to form separate dummy gate stacks. In the illustrated embodiment, two dummy gate stacks each extend over two adjacent fins, respectively. In practice, it will be apparent to those skilled in the art through routine experimentation after understanding the present disclosure that, although the specific number and arrangement of fins and gate stacks and the relationship between them are essentially a matter of design choice, in some embodiments, it is possible that many gate stacks will extend over many fins.

[0019] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbon nitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. Although only a single gate spacer is shown for simplicity, two or more gate spacers may be used when forming a FinFET or a similar type of transistor within the intended scope of the present disclosure. The gate spacer can be used to self-align the removal of portions of the fin, as described below. For example, the gate spacer can also be used to self-align to form a lightly doped drain (LDD) region, a pocket implant, a halo implant, and the like.

[0020] exist Figure 3B It is shown in Figure 3A The cross-sectional view of the structure shown. The cross-sectional view is from the Figure 3A The vertical plane of line AA is obtained. Figure 3B As shown, one of the dummy gate stacks 30 is shown. Due to process reasons such as etching effects in the patterning of the dummy gate stack 30, the bottom portion of the dummy gate stack 30 is wider than the corresponding upper portion. In addition, the dummy gate stack 30 may include an upper portion with straight and vertical sidewalls, and a lower portion with inclined or tapered sidewalls. The inclined sidewalls may also be straight, or may be substantially straight with a slight curvature. The widening of the bottom portion of the dummy gate stack 30 is called the footing effect, and the widened portion is called the footing area (or portion), as shown in portion 30'. This footing phenomenon is particularly evident at the intersection or "corner" between the dummy gate stack and the STI layer (adjacent to the sidewalls of the fin, on which the dummy gate stack is formed), and is more evident at the intersection or "corner" between the dummy gate stack, the fin and the STI layer. The footing portion 30' overlaps with a portion of the gate spacer 38. According to some embodiments of the present disclosure, the difference between the bottom width W1 and the width W2 of the top portion (having the vertical edge) of the gate stack 30 is greater than about 4 nm and may be in a range between about 4 nm and about 12 nm. The gate spacer 38 may follow the contour of the sidewall of the dummy gate stack 30 and thus also have a footing portion.

[0021] According to some embodiments of the present disclosure, an etching step (hereinafter referred to as source / drain recess) is performed to etch the portion of the protruding fin 24' not covered by the dummy gate stack 30 and the gate spacer 38, thereby obtaining Figure 4The structure shown. The recess may be anisotropic, and thus the portion of the fin 24' directly below the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 may be lower than the top surface 22A of the STI region 22. Thus, a groove 40 is formed between the STI regions 22. The groove 40 is located on the opposite side of the dummy gate stack 30.

[0022] Next, an epitaxial region (source / drain region) 42 is formed by selectively growing a semiconductor material in the groove 40, thereby obtaining Figure 5A The corresponding steps are as follows Fig.10 In the process flow 200 shown, it is shown as step 206. According to some exemplary embodiments, the epitaxial region 42 includes silicon germanium, silicon or silicon carbon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to alternative embodiments of the present disclosure, the epitaxial region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or multiple layers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 42 begins to expand horizontally, and a facet can be formed. In some embodiments, a series of epitaxial growth and etching processes may be performed to remove, alter, or otherwise change the shape of the facet profile. In some embodiments (not shown), adjacent epitaxial regions 42 on adjacent fins 24' may grow horizontally until they fuse together.

[0023] After the epitaxy step, p-type or n-type impurities may be further implanted into the epitaxy region 42 to form source and drain regions, which are also indicated by reference numeral 42. According to an alternative embodiment of the present disclosure, when the epitaxy region 42 is in-situ doped with p-type or n-type impurities during epitaxy to form source / drain regions, the implantation step is skipped. The epitaxy source / drain region 42 includes a lower portion formed in the STI region 22 and an upper portion formed above the top surface of the STI region 22.

[0024] Figure 5BFIG. 3 shows the formation of cladding source / drain regions 42 according to alternative embodiments of the present disclosure. According to these embodiments, the protruding fin 24' as shown in FIG. 3 is not recessed, and the epitaxial region 41 is grown on the protruding fin 24'. Depending on whether the resulting FinFET is a p-type or n-type FinFET, the material of the epitaxial region 41 can be similar to Figure 5A The material of the epitaxial semiconductor material 42 shown. For example, the epitaxial region 41 may include silicon germanium, silicon, or carbon silicon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, etc. may be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. may be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 41 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or multiple layers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 41 begins to expand horizontally, and a facet may be formed. In some embodiments, a series of epitaxial growth and etching processes may be to remove, change the facet profile, or otherwise change the shape of the facet profile. In some embodiments (not shown), adjacent epitaxial regions 41 on adjacent fins 24' may grow horizontally until they merge together. Thus, source / drain 42 includes protruding fin 24' and epitaxial regions 41. Implantation may (or may not) be performed to implant n-type impurities or p-type impurities.

[0025] Fig. 6A 4 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. The corresponding steps are shown in FIG. Fig.10 The CESL 46 may be formed of silicon nitride, silicon carbonitride, or the like. For example, a conformal deposition method such as ALD or CVD may be used to form the CESL 46. Although a single CESL layer is shown, it is within the contemplated scope of the present disclosure to deposit or otherwise form two or more CESL layers having the same or different respective thicknesses and having the same or different respective materials, in lieu of one CESL layer. Fig. 6AA single CESL layer 46 is shown. ILD 48 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 48 may also be made of an oxygen-containing dielectric material, which may be based on silicon oxide, such as tetraethyl orthosilicate (TEOS) oxide, plasma enhanced CVD (PECVD) oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. Similarly, like CESL 45, ILD 48 may be embodied as two or more sub-layers that together form an ILD layer, which sub-layers may have the same or different respective thicknesses, be formed of the same or different materials, and be formed using the same or different deposition techniques, processes, and / or parameters. A planarization step such as chemical mechanical polishing (CMP) or mechanical grinding is performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 flush with each other.

[0026] exist Figure 6B It is shown in Fig. 6A The cross-sectional view of the structure shown. The cross-sectional view is from the Fig. 6A The vertical plane of line AA is obtained. Figure 6B As shown, similar to the spacer 38 , the CESL 46 also follows the contour of the dummy gate stack 30 including the footing region 30 ′, and thus the CESL 46 also has a portion that widens outwardly, like the dummy stack 30 .

[0027] In some embodiments, hard mask 36 is not used, or if used, it is removed before forming CESL 46 and ILD 48. Such embodiments are Figure 6C and Fig.6D As shown in the figure, in such an embodiment, after CMP or other planarization steps, the dummy gate electrode 34 is coplanar or at least substantially coplanar with the top surface of the ILD 48. Based on the disclosure, those skilled in the art will recognize that Fig. 6A and Figure 6C The footing area 30' is not specifically shown in the other perspective views, but Figure 6B and Fig.6D , and other cross-sectional views still exist.

[0028] Next, the dummy gate stack 30 including the hard mask layer 36 , the dummy gate electrode 34 , and the dummy gate dielectric 32 is removed and subsequently replaced with a replacement gate stack including a metal gate and a replacement gate dielectric, as described below.

[0029] In conventional processes for removing the dummy gate stack 30, an isotropic etch, such as a wet etch, a remote plasma etch, etc., is used to completely remove the dummy gate stack including the hard mask 36 (if present) and the dummy gate electrode 34. In some instances, the dummy gate dielectric 32 may also be removed (etched) during the dummy gate stack removal process, while in other instances, some or all of the dummy gate dielectric may remain after the dummy gate stack 30 is removed. However, the inventors of the present disclosure have recognized that the dummy gate stack removal (etching) process may cause damage to adjacent structures such as the source / drain regions 42. Although the mechanism underlying this phenomenon is not fully understood, the inventors believe that the footing region of the dummy gate stack described above causes the spacers 38 and CESL 46 to be damaged or compromised during the etching process. Such damage or compromise may allow the etchant / etching process to erode adjacent structures such as the source / drain regions 42 and possibly the fins 24'. It has been observed that in some cases, damage (eg, partial removal, pitting, etc.) may occur to the source / drain regions and / or the fin regions, while in extreme cases, these structures may be completely or nearly completely removed.

[0030] 7A to 9B Steps in a preferred embodiment are shown that minimize or eliminate damage to adjacent structures during the dummy gate stack removal process. Fig. 7A and Figure 7B The result of the first partial etching of the dummy gate stack 30 is shown, including the hard mask 36 (if used) and the upper portion of the dummy gate electrode 34. In the illustrated embodiment, the first partial etching of the dummy gate stack 30 is an isotropic etching, i.e., an etching that is not directional in effect. The corresponding steps are shown in FIG. Fig.10 The process flow 200 is shown as step 210. In an embodiment, the dummy gate stack is exposed to an appropriate wet or dry etch recipe, such as NF3 / H2 / Ar / He, or NF3 / H2 / Ar / He, NF3 / CH4 / H2 / N2 / Ar / He, or NF3 / H2 / Ar / CH4 or NF3 / H2 / Ar / CH3F, etc. Once known from this disclosure, other recipes and variations of the disclosed recipes will be apparent to those skilled in the art. Typical process parameters for isotropic etching include a temperature of from about 10°C to about 120°C at atmospheric pressure and a time period of from about 20 seconds to about 300 seconds.

[0031] It is contemplated that the first partial etch is a timed etch, timed to allow the first partial etch process to proceed such that the top of the dummy gate stack 30 is etched down to a level approximately flush with the top of the fin 24'. This is a convenient reference point and may in fact allow for endpoint detection rather than a timed etch, but is not required for the described embodiments. In fact, in other embodiments, the first etch process may stop when the top of the dummy gate stack 30 is above the level of the fin 24' or below the level of the fin 24'. Regardless of the relationship to the top of the fin 24', preferably, the first partial etch / isotropic etch stops before reaching the level of the footing region 30'.

[0032] Next, a second etching process is used to further remove the dummy gate stack 30. The corresponding steps are as follows. Fig.10 The second partial etching process is shown as step 212 in the process flow 200 shown. The second partial etching process is an anisotropic etching process, sometimes also referred to herein as a directional etching process, such as an ion bombarded plasma etching. Advantageously, the directional etching removes the dummy gate stack material in the vertical direction much faster than in the horizontal direction. As a result, remnants of the dummy gate stack material remain, particularly in the footing regions 30', which tend to extend horizontally outward relative to the upper portion of the dummy gate stack 30. These remnants are Figure 8B . Although directional etching provides favorable results, as described herein, performing only directional etching to remove the entire dummy gate stack 30 may cause other disadvantages. For example, directional etching typically involves ion bombardment and polymer formation for sidewall passivation protection. The physical forces of ion bombardment may cause undesirable gate height loss or corner loss. Similarly, polymer formation can result in incomplete polysilicon removal. Therefore, it is advantageous to have two etching processes, where the isotropic etching removes a portion of the dummy gate stack, and the anisotropic etching removes (most or all of) the remainder.

[0033] like Figure 8B As shown, the remnant portion of the dummy gate stack material (typically polysilicon) that remains after the second partial etch can be substantially coextensive with the footing region 30' of the dummy gate stack 30. However, this is not required, and depending on the etching chemistry and etching conditions, the remaining remnant portion of polysilicon (or other dummy gate stack material) may be larger or smaller than the footing region 30'. Figure 8C and Fig.8D Best shown, they are Figure 8B A plan view (also called a top view) of the structure shown (in other words, Figure 8C and Fig.8D Only one fin 24' is shown).

[0034] exist Figure 8C In the embodiment shown, the second partial etch continues until substantially all of the dummy gate stack material is removed, with only residual material 31 remaining in the corner region where the dummy gate stack 30 has expanded laterally beyond the lateral dimensions of the gate stack due to the footing effect. Because the second partial etch is a directional etch, these residual portions will remain after the majority of the dummy gate stack material, particularly the dummy gate electrode 34, has been removed. In contrast, in Fig.8D In the embodiment, more residual material 31 remains in the groove 33, especially at the bottom of the groove 33. This is because, for example Fig.8D The second etching process of the embodiment is performed without Figure 8C The etching process shown is not that long even though the same etching process parameters (except for the duration) may be used in both embodiments. Fig.8D In the illustrated embodiment, residual dummy gate stack material, such as polysilicon or the like, extends across the bottom of trench 33 from one sidewall of trench 33 to the opposite sidewall of trench 33. In some embodiments, the residual material may not extend all the way across the entire trench, or at least may not extend in a continuous layer.

[0035] Although the mechanism is not fully understood, the inventors believe that the residual material 31 serves to protect adjacent structures (e.g., source / drain regions 42 and fins 24') from being attacked or damaged by the etchant chemistry during the dummy gate removal process. In this way, device performance and reliability are improved.

[0036] In an exemplary embodiment, the directional or anisotropic etch is a plasma etch in which ion bombardment is used due to a substrate self-bias voltage of about 200 V or less. x F y The etchant gas is preferably an etchant gas such as O2, CO2, SO2, HBr, SiCl4, CH4, CH3F, etc., and a passivation gas such as O2, CO2, SO2, HBr, SiCl4, CH4, CH3F, etc., and a diluent gas or carrier gas such as an inert gas (Ar, He, N2, etc.). As an example, a gas chemistry of NF3 is used at a flow rate from about 5 sccm to about 100 sccm and a temperature in a range from about 10°C to about 120°C, at a pressure of about 20 mTorr to about 2 Torr, and for a time period in a range from about 10 seconds to 300 seconds.

[0037] In the embodiment shown above, the dummy gate stack dielectric 32 is retained after the rest of the dummy gate stack 30 has been removed (except for the residual portion 31). In other embodiments, the dummy gate stack dielectric can be removed during the dummy gate stack removal process, or in other embodiments, the dummy gate stack dielectric 32 can be removed in a subsequent etching process after the dummy gate electrode 34 has been substantially removed (again except for the residual portion 31 that remains after the two-step removal process). In other embodiments, the dummy gate dielectric layer 32 can be retained and incorporated into a final device (e.g., a transistor) alone or in combination with a subsequently formed high-k, or other gate dielectric layer compatible with a metal gate, etc.

[0038] Next, refer to Fig. 9A and Fig. 9B , forming a (replacement) gate stack 60, the (replacement) gate stack 60 including a gate dielectric layer 54 and a gate electrode 56. The corresponding steps are as follows Fig.10 In the process flow 200 shown, it is shown as step 214. In this embodiment, the dummy gate dielectric layer 32 has been removed before forming the gate stack 60. The formation of the gate stack 60 includes forming / depositing multiple layers, and then performing a planarization process such as a CMP process or a mechanical grinding process. The gate dielectric layer 54 extends into the trench 33 left by the removed dummy gate stack. According to some embodiments of the present disclosure, the gate dielectric layer 54 may include an interfacial layer (IL) as its lower portion. IL 50 is formed on the exposed surface of the protruding fin 24'. IL 50 may include an oxide layer such as a silicon oxide layer, which is formed by thermal oxidation, a chemical oxidation process, or a deposition process of the protruding fin 24'. The gate dielectric layer 54 may also include a high-k dielectric layer 52 ( Figure 8B and Figure 8C The high-k dielectric layer 52 includes a high-k dielectric material, such as HfO2, ZrO2, HfZrO x 、HfSiO x 、HfSiON、ZrSiO x 、HfZrSiO x 、Al2O3、HfAlO x 、HfAlN、ZrAlO x , La2O3, TiO2, Yb2O3, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is preferably higher than 3.9, and may be higher than about 7.0. The high-k dielectric layer 52 is formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the sidewalls of the gate spacer 38. According to some embodiments of the present disclosure, the high-k dielectric layer 52 is formed using ALD or CVD.

[0039] Reference again Fig. 9A and Fig. 9B , a gate electrode 56 is formed on the gate dielectric layer 54 and fills the remaining portion of the trench 33 left by the removed dummy gate stack. Fig. 9A , but in reality, these sub-layers can be distinguished from each other due to different compositions. The deposition of at least the lower sub-layer can be performed using a conformal deposition method such as ALD or CVD, so that the thickness of the vertical portion and the thickness of the horizontal portion of the gate electrode 56 (and each sub-layer) are substantially equal to each other.

[0040] The gate electrode 56 may include multiple layers, including but not limited to titanium silicon nitride (TSN) layers, tantalum nitride (TiN) layers, titanium nitride (TiN) layers, titanium aluminum (TiAl) layers, additional TiN and / or TaN layers, and fill metals. Some of these layers define the work function of the corresponding FinFET. In addition, the metal layer of the p-type FinFET and the metal layer of the n-type FinFET may be different from each other so that the work function of the metal layer is suitable for the corresponding p-type or n-type FinFET. The fill metal may include aluminum, copper, or cobalt.

[0041] Fig. 9B A cross-sectional view of an exemplary metal gate stack 60 is shown. The cross-sectional view is taken from a perspective including Fig. 9A 2 is obtained from a vertical plane of AA shown. Since the cross-sectional view is obtained from a plane intersecting the STI region 22 rather than the protruding fin 24', the above-mentioned IL does not exist in the cross-sectional view. Instead, the high-k dielectric layer 52 contacts the top surface of the STI region 22. According to some exemplary embodiments, the gate electrode 56 includes a TSN layer 56-1, a TaN layer 56-2, a TiN layer 56-3, a TiAl layer 56-4, a TiN layer 56-5 and a filling metal 56-6. It will be understood that this layer stack is an example and that metal stacks with different structures may be employed. The gate stack 60 also includes a footing portion 60', which is due to the presence of the footing region 30' ( Figure 6B ). The footing portion 60' is shown to include the high-k dielectric layer 52 and possibly some metal layers, such as TSN, TaN and / or TiN layers. The footing portion 60' is located directly below and overlaps some portions of the gate spacer 38. Similarly, the remaining portion 31 of the original dummy gate stack 30 is Fig. 9B , but it is recognized that portions of remnant portion 31 may be removed or otherwise altered during the step of forming replacement gate 60 .

[0042] Further processing will be apparent to those skilled in the art after having an understanding of this disclosure, and may include forming one or more contact structures (contacting gate 60) and source / drain regions 42, forming one or more layers of electrical interconnects over the transistor, and the like.

[0043] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0044] A general aspect of the embodiments disclosed herein includes a method of forming a dummy gate and adjacent structures. The method also includes removing some but not all of the dummy gate using directional etching to form a trench, wherein a portion of the dummy gate remains and protects the adjacent structures. The method also includes forming a gate electrode in the trench.

[0045] Another general aspect of the embodiments disclosed herein includes a method, the method including forming a fin extending from a semiconductor substrate. The method also includes depositing a dummy gate material on the fin. The method also includes patterning the dummy gate material to form a dummy gate extending above the top of the fin and along the sidewall of the fin. The method also includes depositing a spacer material on the dummy gate, and patterning the spacer material to form a spacer on the corresponding sidewall of the dummy gate. The method also includes etching a portion of the fin to form a fin groove using the dummy gate and the spacer as a mask. The method also includes filling each fin groove with a source / drain region. The method also includes depositing a dielectric layer to surround the dummy gate, the source / drain region, and the fin. The method also includes isotropically etching the dummy gate to remove the top portion of the dummy gate and leaving the bottom portion of the dummy gate. The method also includes anisotropically etching the bottom portion of the dummy gate to partially remove the bottom portion of the dummy gate and leaving a residual portion of the dummy gate. The method also includes forming a metal gate electrode on the residual portion of the dummy gate.

[0046] Another general aspect of the embodiments disclosed herein includes a device including a fin extending upward from a substrate. The device also includes an isolation material formed over the fin. The device also includes a gate including a gate dielectric within a trench in the isolation material, the gate extending over a top and sidewalls of the fin. The device also includes a polysilicon material extending along a bottom portion of the trench, the polysilicon material being between the gate dielectric and the substrate.

[0047] Example 1. A method for manufacturing a semiconductor device, comprising: forming a dummy gate and adjacent structures; using directional etching to remove some but not all of the dummy gate to form a trench, wherein a portion of the dummy gate is retained and protects the adjacent structure; and forming a gate electrode in the trench.

[0048] Example 2. The method of Example 1 further comprises: before the step of using directional etching, using isotropic etching to remove a top portion of the dummy gate.

[0049] Example 3. The method of Example 1, wherein the step of forming a dummy gate results in the dummy gate having a footing region that widens outward from a nominal edge of the dummy gate.

[0050] Example 4. The method of Example 3, wherein the step of removing some but not all of the dummy gate includes leaving only the footing region of the dummy gate.

[0051] Example 5. The method of Example 3, wherein the step of removing some but not all of the dummy gate includes leaving a portion of the dummy gate extending from a first sidewall of the trench to a second sidewall of the trench.

[0052] Example 6. The method of Example 1, wherein the dummy gate extends over a fin, and the method further comprises: etching a portion of the fin adjacent to the dummy gate to form a fin recess; and epitaxially growing the adjacent structure in the fin recess.

[0053] Example 7. A method according to Example 2, wherein the dummy gate extends above the fin, and further wherein: the step of removing the top portion of the dummy gate using isotropic etching includes: etching back the dummy gate to the level of the topmost surface of the fin; and the step of removing some but not all of the dummy gate using directional etching includes: etching back the dummy gate along the sidewalls of the fin.

[0054] Example 8. The method of Example 1, wherein the directional etching is plasma etching performed using ion bombardment.

[0055] Example 9. The method of Example 8, wherein the directional etching is performed using an etching gas selected from the group consisting of chlorine, fluorine, C x F y , and a group consisting of the foregoing combinations; and a passivating gas selected from the group consisting of oxygen-based gases and HBr, and a combination of the foregoing; and an inert carrier gas.

[0056] Example 10. A method for manufacturing a semiconductor device, comprising: forming a fin extending from a semiconductor substrate; depositing a dummy gate material over the fin; patterning the dummy gate material to form a dummy gate over the top of the fin and extending along the sidewall of the fin; depositing a spacer material on the dummy gate, and patterning the spacer material to form a spacer on the corresponding sidewall of the dummy gate; using the dummy gate and the spacer as a mask, etching a portion of the fin to form a fin groove; filling each fin groove with a source / drain region; depositing a dielectric layer to surround the dummy gate, the source / drain region and the fin; isotropically etching the dummy gate to remove the top portion of the dummy gate and leave a bottom portion of the dummy gate; anisotropically etching the bottom portion of the dummy gate to partially remove the bottom portion of the dummy gate and leave a residual portion of the dummy gate; and forming a metal gate electrode on the residual portion of the dummy gate.

[0057] Example 11. The method of Example 10, wherein the step of isotropically etching the dummy gate comprises: performing wet etching or remote plasma etching.

[0058] Example 12. The method of Example 11, wherein the step of anisotropically etching the bottom portion of the dummy gate comprises: performing plasma etching using ion bombardment to remove some but not all of the bottom portion while leaving a residual portion of the dummy gate.

[0059] Example 13. A method according to Example 12, wherein the step of isotropically etching the dummy gate and the step of anisotropically etching the bottom portion of the dummy gate form a trench in the dielectric layer, and further wherein a residual portion of the dummy gate remains at a bottom corner of the trench.

[0060] Example 14. The method of Example 13, wherein a remaining portion of the dummy gate extends from a first sidewall of the trench to a second sidewall of the trench.

[0061] Example 15. The method of Example 10, wherein the step of forming a metal gate electrode on the remaining portion of the dummy gate comprises: forming a gate dielectric directly on the remaining portion of the dummy gate.

[0062] Example 16. The method of Example 10, wherein the step of filling each fin recess with a source / drain region comprises: epitaxially growing a semiconductor material in each fin recess.

[0063] Example 17. The method of Example 10, wherein the step of isotropically etching the dummy gate to remove a top portion of the dummy gate includes timing the isotropic etching to remove the dummy gate material to a level coplanar with a top surface of the fin.

[0064] Example 18. A semiconductor device comprising: a fin extending upward from a substrate; an isolation material formed above the fin; a gate within a trench in the isolation material and comprising a gate dielectric, the gate extending over the top and sidewalls of the fin; and a polysilicon material extending along a bottom portion of the trench, the polysilicon material being located between the gate dielectric and the substrate.

[0065] Example 19. The semiconductor device of Example 18, wherein the substrate includes a dielectric layer top surface.

[0066] Example 20. The semiconductor device of Example 18, wherein the polysilicon material is between a gate and a source / drain region of the device.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a dummy gate and adjacent structures, the dummy gate including an upper portion having a vertical sidewall and a footing portion having a sidewall widened outwardly; removing some but not all of the dummy gate using a directional etch to form a trench, wherein the footing portion of the dummy gate remains and protects the adjacent structure; as well as A gate electrode is formed in the trench.

2. The method according to claim 1, further comprising: Prior to the step of using a directional etch, an isotropic etch is used to remove a top portion of the dummy gate.

3. The method according to claim 1, wherein: The step of forming a dummy gate results in the dummy gate having a footing region that widens outwardly from a nominal edge of the dummy gate.

4. The method according to claim 3, wherein: The step of removing some but not all of the dummy gate includes leaving only the footing region of the dummy gate.

5. The method according to claim 3, wherein: The step of removing some but not all of the dummy gate includes leaving a portion of the dummy gate extending from a first sidewall of the trench to a second sidewall of the trench.

6. The method according to claim 1, wherein: The dummy gate extends over the fin, and the method further comprises: etching a portion of the fin adjacent to the dummy gate to form a fin recess; and The adjacent structure is epitaxially grown in the fin recess.

7. The method according to claim 2, wherein: The dummy gate extends over the fin, and further wherein: The step of removing the top portion of the dummy gate using an isotropic etch comprises: etching the dummy gate back to the level of the topmost surface of the fin; and The step of removing some but not all of the dummy gate using directional etching includes etching back the dummy gate along the sidewalls of the fin.

8. The method according to claim 1, wherein: The directional etching is plasma etching performed using ion bombardment.

9. The method according to claim 8, wherein: The directional etching is performed using: Etching gas selected from chlorine, fluorine, C x F y , and a combination of the foregoing; and a passivating gas selected from the group consisting of oxygen-based gases and HBr, and combinations of the foregoing; and Inert carrier gas.

10. A method for manufacturing a semiconductor device, comprising: forming a fin extending from a semiconductor substrate; depositing a dummy gate material over the fin; patterning the dummy gate material to form a dummy gate over a top of the fin and extending along a sidewall of the fin; depositing a spacer material on the dummy gate and patterning the spacer material to form spacers on corresponding sidewalls of the dummy gate; etching a portion of the fin to form a fin recess using the dummy gate and the spacer as a mask; filling each fin recess with a source / drain region; depositing a dielectric layer to surround the dummy gate, the source / drain regions, and the fin; isotropically etching the dummy gate to remove a top portion of the dummy gate and leave a bottom portion of the dummy gate; anisotropically etching a bottom portion of the dummy gate to partially remove the bottom portion of the dummy gate and leave a residual portion of the dummy gate; as well as A metal gate electrode is formed on a remaining portion of the dummy gate.

11. The method according to claim 10, wherein: The step of isotropically etching the dummy gate includes performing wet etching or remote plasma etching.

12. The method according to claim 11, wherein: The step of anisotropically etching the bottom portion of the dummy gate includes performing a plasma etch using ion bombardment to remove some but not all of the bottom portion while leaving a residual portion of the dummy gate.

13. The method according to claim 12, wherein: The steps of isotropically etching the dummy gate and anisotropically etching a bottom portion of the dummy gate form a trench in the dielectric layer, and further wherein a remnant portion of the dummy gate remains at a bottom corner of the trench.

14. The method according to claim 13, wherein: A remaining portion of the dummy gate extends from a first sidewall of the trench to a second sidewall of the trench.

15. The method according to claim 10, wherein: The step of forming a metal gate electrode on the remaining portion of the dummy gate includes: forming a gate dielectric directly on the remaining portion of the dummy gate.

16. The method according to claim 10, wherein: The step of filling each fin recess with the source / drain region includes: epitaxially growing a semiconductor material in each fin recess.

17. The method according to claim 10, wherein: The step of isotropically etching the dummy gate to remove a top portion of the dummy gate includes timing the isotropic etch to remove dummy gate material to a level coplanar with a top surface of the fin.

18. A semiconductor device comprising: a fin extending upward from the substrate; an isolation material formed on the fin; a gate within a trench in the isolation material and including a gate dielectric, the gate extending over a top and sidewalls of the fin; as well as A polysilicon material extends along a bottom portion of the trench, the polysilicon material being located between the gate dielectric and the substrate in a direction perpendicular to the major surface of the substrate.

19. The semiconductor device according to claim 18, wherein: The substrate includes a dielectric layer top surface.

20. The semiconductor device according to claim 18, wherein The polysilicon material is between the gate and source / drain regions of the device.

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