Shift register unit and driving method thereof, scanning driving circuit, and display device

Abstract

The present application provides a shift register unit and a driving method thereof, a scanning driving circuit, and a display device. The shift register unit includes: a first input unit, configured to write the first constant voltage signal to the first node when the first clock signal is at an effective level; a second input unit, configured to write the trigger signal to the second node when the first clock signal is at an effective level; a first control unit, configured to write the second clock signal to the third node when the second node is at an effective level; a first output unit, configured to output the second constant voltage signal when the first node is at an effective level; wherein the second constant voltage signal is opposite to the level of the first constant voltage signal; and a second output unit, configured to output the first constant voltage signal when the third node is at an effective level. The shift register unit directly outputs a constant voltage signal through the control of a clock signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a scan driving circuit, and a display device. Background Art

[0002] In the existing Organic Light-Emitting Diode (OLED) display panel, since the pixel circuit has a threshold voltage (Vth) compensation function, the pixel circuit requires an Emission (light emission) control signal, a Gate (data writing) control signal, and a Reset (reset) control signal to perform timing control on the pixel circuit in order to work normally.

[0003] The low temperature polysilicon (LTPS) shift register circuit usually integrated on the display panel can generally realize the following functions, such as using the Emission signal shift register to realize the shift output of the high level pulse signal, and using the Reset signal shift register to realize the shift output of the low level pulse signal. The high level pulse signal output by the high level shift register is usually used as the Emission (light emission) control signal. The low level pulse signal output by the low level shift register is usually used as the Gate and Reset (data writing and resetting) control signals.

[0004] Existing OLED display panels generally use Emission signal shift registers and Gate / Reset shift registers to control the output of Emission and Gate / Reset signals respectively. In addition, in the operation of existing OLED panels, Gate and Reset signals are output through the shift of clock signals. However, under the influence of the load (voltage drop) of the peripheral circuit, the switching of the high and low levels of the clock signal takes time, which directly affects the Tr (rising edge time) and Tf (falling edge time) of the Gate and Reset signals, and ultimately leads to poor display. Summary of the invention

[0005] In view of the above problems, the present application provides a shift register unit and a driving method thereof, a scan drive circuit, and a display device, which solve the technical problem in the prior art of outputting Gate and Reset signals by shifting a clock signal, resulting in poor display.

[0006] In a first aspect, the present application provides a shift register unit, comprising:

[0007] A first input unit, whose input end is connected to a first constant voltage signal, whose control end is connected to a first clock signal, whose output end is connected to a first node, and is configured to write the first constant voltage signal into the first node when the first clock signal is at a valid level;

[0008] A second input unit, whose input end is connected to the trigger signal, whose control end is connected to the first clock signal, whose output end is connected to the second node, and is configured to write the trigger signal into the second node when the first clock signal is at a valid level;

[0009] A first control unit, whose input terminal is connected to the second clock signal, whose control terminal is connected to the second node, whose output terminal is connected to the third node, and is configured to write the second clock signal into the third node when the second node is at a valid level;

[0010] a first output unit, whose input terminal is connected to the second constant voltage signal, whose control terminal is connected to the first node, and configured to output the second constant voltage signal when the first node is at a valid level; wherein the second constant voltage signal is opposite to the level of the first constant voltage signal;

[0011] The second output unit has an input terminal connected to the first constant voltage signal and a control terminal connected to the third node, and is configured to output the first constant voltage signal when the third node is at a valid level.

[0012] In some embodiments, in the above-mentioned shift register unit, the first input unit includes a first transistor; wherein the source of the first transistor is the input end of the first input unit, the drain of the first transistor is the output end of the first input unit, and the gate of the first transistor is the control end of the first input unit.

[0013] In some embodiments, in the above-mentioned shift register unit, the second input unit includes a second transistor; wherein the source of the second transistor is the input end of the second input unit, the drain of the second transistor is the output end of the second input unit, and the gate of the second transistor is the control end of the second input unit.

[0014] In some embodiments, in the above-mentioned shift register unit, the first control unit includes a third transistor; wherein the source of the third transistor is the input end of the first control unit, the drain of the third transistor is the output end of the first control unit, and the gate of the third transistor is the control end of the first control unit.

[0015] In some embodiments, in the above-mentioned shift register unit, the first control unit further includes a first capacitor; wherein a first end of the first capacitor is connected to the gate of the third transistor, and a second end of the first capacitor is connected to the drain of the third transistor.

[0016] In some embodiments, in the above-mentioned shift register unit, the first output unit includes a fourth transistor; wherein the source of the fourth transistor is the input end of the first output unit, the drain of the fourth transistor is the output end of the first output unit, and the gate of the fourth transistor is the control end of the first output unit.

[0017] In some embodiments, in the above-mentioned shift register unit, the first output unit further includes a second capacitor; wherein a first end of the second capacitor is connected to the gate of the fourth transistor, and a second end of the second capacitor is connected to the source of the fourth transistor.

[0018] In some embodiments, in the above-mentioned shift register unit, the second output unit includes a fifth transistor; wherein the source of the fifth transistor is the input end of the second output unit, the drain of the fifth transistor is the output end of the second output unit, and the gate of the fifth transistor is the control end of the second output unit.

[0019] In some embodiments, the above shift register unit further includes:

[0020] a second control unit, whose input end is connected to the first clock signal, whose control end is connected to the second node, whose output end is connected to the first node, and configured to write the first clock signal into the first node when the second node is at a valid level;

[0021] A third control unit, whose input end is connected to the second constant voltage signal, whose first control end is connected to the first node, whose second control end is connected to the second clock signal, whose output end is connected to the third node, and is configured to write the second constant voltage signal into the third node when the first node and the second clock signal are both at a valid level.

[0022] In some embodiments, in the above-mentioned shift register unit, the second control unit includes a sixth transistor; wherein the source of the sixth transistor is the input end of the second control unit, the drain of the sixth transistor is the output end of the second control unit, and the gate of the sixth transistor is the control end of the second control unit.

[0023] In some embodiments, in the above shift register unit, the third control unit includes a seventh transistor and an eighth transistor;

[0024] Among them, the source of the seventh transistor is the input end of the third control unit, the gate of the seventh transistor is the first control end of the third control unit, the drain of the seventh transistor is connected to the source of the eighth transistor, the gate of the eighth transistor is the second control end of the third control unit, and the drain of the eighth transistor is the output end of the third control unit.

[0025] In a second aspect, the present application provides a driving method of a shift register unit as described in any one of the first aspects, comprising:

[0026] In a first stage when the trigger signal is at a valid level, the first clock signal is set to a valid level, and the second clock signal is set to an invalid level, so that the first output unit outputs the second constant voltage signal;

[0027] In a second stage after the first stage when the trigger signal is at an invalid level, the first clock signal is set to an invalid level, and the second clock signal is set to a valid level, so that the second output unit outputs the first constant voltage signal;

[0028] In each stage after the second stage in which the trigger signal is at an invalid level, the first clock signal is set to a level opposite to that of the first clock signal in the previous stage, and the second clock signal is set to a level opposite to that of the second clock signal in the previous stage, so that the first output unit continues to output the second constant voltage signal.

[0029] In a third aspect, the present application provides a scan driving circuit, comprising a plurality of cascaded shift register units as described in any one of the first aspects.

[0030] In a fourth aspect, the present application provides a display substrate, characterized in that it includes a scan drive circuit as described in the third aspect.

[0031] In a fifth aspect, the present application provides a display device, characterized in that it includes a display substrate as described in the fourth aspect.

[0032] By adopting the above technical solution, at least the following technical effects can be achieved:

[0033] The present application provides a shift register unit and a driving method thereof, a scan driving circuit, and a display device. The shift register unit includes: a first input unit, configured to write the first constant voltage signal to the first node when the first clock signal is at a valid level; a second input unit, configured to write the trigger signal to the second node when the first clock signal is at a valid level; a first control unit, configured to write the second clock signal to the third node when the second node is at a valid level; a first output unit, configured to output the second constant voltage signal when the first node is at a valid level; wherein the second constant voltage signal is opposite in level to the first constant voltage signal; and a second output unit, configured to output the first constant voltage signal when the third node is at a valid level. The shift register unit directly outputs the second constant voltage signal or the first constant voltage signal through the control of the clock signal to realize the output of the Gate and Reset signals. Since the constant voltage signal itself does not have high and low level switching, the load (voltage drop) of the peripheral circuit has little effect on the high and low level switching of the Gate and Reset signals, which can greatly reduce the Tr (rising edge time) and Tf (falling edge time) of the Gate and Reset signals, effectively improving poor display. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0035] Figure 1 is a circuit diagram of a shift register unit;

[0036] Figure 2 is a circuit schematic diagram of a pixel compensation circuit;

[0037] Figure 3 It is a timing state diagram of each signal in a shift register unit;

[0038] Figure 4 is a connection frame diagram of a shift register unit shown in an exemplary embodiment of the present application;

[0039] Figure 5 is a circuit diagram of a shift register unit shown in an exemplary embodiment of the present application;

[0040] Figure 6 is a timing state diagram of each signal in a shift register unit shown in an exemplary embodiment of the present application;

[0041] Figure 7 is a connection frame diagram of another shift register unit shown in an exemplary embodiment of the present application;

[0042] Figure 8 is a circuit diagram of another shift register unit shown in an exemplary embodiment of the present application;

[0043] Fig. 9 is a simulation verification schematic diagram of another shift register unit shown in an exemplary embodiment of the present application;

[0044] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0045] The following will describe the implementation methods of the present application in detail in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present application applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present application. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0046] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] In order to thoroughly understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0049] A circuit diagram of a shift register unit, such as Figure 1 As shown, it is an 8T2C circuit structure, including the first transistor T1 to the eighth transistor T8, and the first capacitor C1 and the second capacitor C2. The first transistor T1 to the eighth transistor T8 are all LTPS thin film transistors (Thin Film Transistor, TFT), that is, P-type TFT, the threshold voltage Vth is negative, when the voltage difference Vgs between the gate and the source of the TFT is less than Vth, the TFT is turned on. The shift register unit is used to output the drive such as Figure 2 The pixel circuit shown in the figure requires Gate and Reset signals. The 7T1C pixel circuit requires the input of Emission (light emission) control signal, Gate (data writing) control signal, and Reset (reset) control signal for the pixel to work properly. The EM signal (i.e., Emission control signal) can be output through other shift register units. The Data signal, VDD signal, and VSS signal are directly input by the IC.

[0050] The source of the first transistor T1 is connected to the constant low-level signal VGL, the gate is connected to the first clock signal CK, and the drain is connected to the node N1; the source of the second transistor T2 is connected to the trigger signal GSTV, the gate is connected to the first clock signal CK, and the drain is connected to the node N2; the source of the third transistor T3 is connected to the node N2, the gate is connected to the constant low-level signal VGL, and the drain is connected to the node N3; the source of the fourth transistor T4 is connected to the constant high-level signal VGH, the gate is connected to the node N1, and the drain is the first output terminal GOUT of the shift register unit; the source of the fifth transistor T5 is connected to the trigger signal GSTV, the gate is connected to the first clock signal CK, and the drain is connected to the node N2; The sixth transistor T6 has a source connected to the first clock signal CK, a gate connected to the node N2, and a drain connected to the drain of the first transistor T1; the seventh transistor T7 has a source connected to the constant high level signal VGH, a gate connected to the node N1, and a drain connected to the node N4; the eighth transistor T8 has a source connected to the node N4, a gate connected to the second clock signal CB, and a drain connected to the node N2; the two ends of the first capacitor C1 are respectively connected to the gate and source of the fourth transistor T4; the two ends of the second capacitor C2 are respectively connected to the gate and drain of the fifth transistor T5.

[0051] The timing state diagram of each signal in the shift register unit is as follows: Figure 3 As shown, its driving principle is:

[0052] Phase A: the first clock signal CK and the trigger signal GSTV are both low level (valid level), the second clock signal CB is high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and a low level signal is written to the node N2, the third transistor T3 is turned on under the control of the constant low level signal VGL, the low level signal written to the node N2 continues to be written to the node N3, so that the fifth transistor T5 is turned on, the second clock signal CB (high level) is derived through the drain of the fifth transistor T5, and at this time the second output terminal GOUT of the shift register unit outputs a high level signal; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is written to the node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4, and at this time the first output terminal GOUT of the shift register unit outputs a high level signal.

[0053] Phase B: the first clock signal CK and the trigger signal GSTV are both high level (invalid level), and the second clock signal CB is low level (valid level). Because the node N3 (may be under the action of the second capacitor C2) maintains the low level of phase A, the fifth transistor remains turned on. After the second clock signal CB switches, the second output terminal GOUT of the shift register unit outputs a low level signal at this time; at the same time, because the node N2 (may be under the action of the first capacitor C1) maintains the low level of phase A, the sixth transistor T6 is turned on, and the first clock signal CK is derived through the drain of the sixth transistor T6 and written into the node N1, pulling up the voltage of the node N1, so that the fourth transistor T4 and the seventh transistor T7 are turned off.

[0054] Phase C: the first clock signal CK is at a low level (valid level), the trigger signal GSTV and the second clock signal CB are both at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and high-level signals are written to the nodes N2 and N3 in turn, and the fifth transistor T5 is turned off; at the same time, the constant low-level signal VGL is derived through the drain of the first transistor T1, and a low-level signal is written to the node N1, so that the fourth transistor T4 is turned on, and the constant high-level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output terminal GOUT of the shift register unit outputs a high-level signal.

[0055] Phase D: The first clock signal CK and the trigger signal GSTV are both high level (invalid level), and the second clock signal CB is low level (valid level). Because the nodes N2 and N3 both maintain the high level of the C phase (the effect of the second capacitor C2), the fifth transistor T5 and the sixth transistor T6 are both turned off, and the node N1 maintains the low level of the C phase (the effect of the first capacitor C1). The fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output terminal GOUT of the shift register unit outputs a high level signal.

[0056] Phase E: the first clock signal CK is at a low level (valid level), the trigger signal GSTV and the second clock signal CB are both at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and high-level signals are written to the nodes N2 and N3 in turn, and the fifth transistor T5 is turned off; at the same time, the constant low-level signal VGL is derived through the drain of the first transistor T1, and a low-level signal is input to the node N1, so that the fourth transistor T4 is turned on, and the constant high-level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output terminal GOUT of the shift register unit outputs a high-level signal.

[0057] In the time period when a low level output is not required, the trigger signal GSTV is at a high level, and the first clock signal CK turns on the first transistor T1 every half cycle. The low level is written into the capacitor C1 through the first transistor T1, thereby keeping the fourth transistor T4 and the seventh transistor T7 in a normally open state.

[0058] In the above shift register unit, although the A, C, D, and E stages are mainly achieved by turning on the fourth transistor T4 so that the constant high-level signal VGH is directly derived through the drain of the fourth transistor T4, in the C stage, GOUT is switched from a low level to a high level. In the C stage, it is only necessary to control the fourth transistor T4 to turn on so as to output a high level (constant high-level signal VGH), that is, the rising edge time Tr is very small.

[0059] However, in the B phase, the second output terminal of the shift register unit outputs a low-level signal, which is the second clock signal CB switched from a high level to a low level. However, under the influence of the load (voltage drop) of the peripheral circuit, the high and low level switching of the second clock signal CB requires time, that is, the time for GOUT to switch from a high level to a low level is longer, that is, the falling edge time Tf is longer. This results in differences in Tr (rising edge time) and Tf (falling edge time) of the Gate and Reset signals, causing poor display.

[0060] The present application embodiment provides a shift register unit, see Figure 4The shift register unit includes a first input unit 110 , a second input unit 120 , a first control unit 130 , a first output unit 140 and a second output unit 150 .

[0061] The first input unit 110 has an input terminal connected to the first constant voltage signal, a control terminal G connected to the first clock signal CK, an output terminal connected to the first node N1, and is configured to write the first constant voltage signal to the first node N1 when the first clock signal CK is at a valid level;

[0062] A second input unit 120, whose input terminal is connected to the trigger signal GSTV, whose control terminal G is connected to the first clock signal CK, whose output terminal is connected to the second node N2, and is configured to write the trigger signal GSTV into the second node N2 when the first clock signal CK is at a valid level;

[0063] A first control unit 130, whose input terminal is connected to the second clock signal CB, whose control terminal G is connected to the second node N2, whose output terminal is connected to the third node N3, and is configured to write the second clock signal CB into the third node N3 when the second node N2 is at a valid level;

[0064] The first output unit 140 has an input terminal connected to the second constant voltage signal, a control terminal G connected to the first node N1, and is configured to output the second constant voltage signal when the first node N1 is at a valid level; wherein the second constant voltage signal is opposite to the level of the first constant voltage signal;

[0065] The second output unit 150 has an input terminal connected to the first constant voltage signal and a control terminal G connected to the third node N3, and is configured to output the first constant voltage signal when the third node N3 is at a valid level.

[0066] like Figure 5 As shown, in some embodiments, the first input unit 110 includes a first transistor T1; wherein the source of the first transistor T1 is the input end of the first input unit 110, the drain of the first transistor T1 is the output end of the first input unit 110, and the gate of the first transistor T1 is the control end G of the first input unit 110.

[0067] In some embodiments, the second input unit 120 includes a second transistor T2; wherein the source of the second transistor T2 is the input end of the second input unit 120, the drain of the second transistor T2 is the output end of the second input unit 120, and the gate of the second transistor T2 is the control end G of the second input unit 120.

[0068] In some embodiments, the first control unit 130 includes a third transistor T3; wherein the source of the third transistor T3 is the input end of the first control unit 130, the drain of the third transistor T3 is the output end of the first control unit 130, and the gate of the third transistor T3 is the control end G of the first control unit 130.

[0069] In some embodiments, the first control unit 130 further includes a first capacitor C1; wherein the first end of the first capacitor C1 is connected to the gate of the third transistor T3, and the second end of the first capacitor C1 is connected to the drain of the third transistor T3. In the case where there is no voltage input to the gate (second node N2) and the drain (third node N3) of the third transistor T3 (in a floating state), the first capacitor C1 can further maintain the voltage of the gate and the drain of the third transistor T3 (i.e., the voltage of the second node N2 and the third node N3) unchanged; and the first capacitor C1 also has the function of voltage jump. In the case where there is no voltage input to the gate (second node N2) of the third transistor T3, the voltage change of the third node N3 will cause the voltage of the node N2 to change in the same direction, and vice versa.

[0070] In some embodiments, the first output unit 140 includes a fourth transistor T4; wherein the source of the fourth transistor T4 is the input end of the first output unit 140, the drain of the fourth transistor T4 is the output end of the first output unit 140, and the gate of the fourth transistor T4 is the control end G of the first output unit 140.

[0071] In some embodiments, the first output unit 140 further includes a second capacitor C2; wherein a first end of the second capacitor C2 is connected to the gate of the fourth transistor T4, and a second end of the second capacitor C2 is connected to the source of the fourth transistor T4. When there is no voltage input to the gate (first node N1) of the fourth transistor T4, the second capacitor C2 can further maintain the gate voltage of the fourth transistor T4 (i.e., the voltage of the first node N1) unchanged.

[0072] In some embodiments, the second output unit 150 includes a fifth transistor T5; wherein the source of the fifth transistor T5 is the input end of the second output unit 150, the drain of the fifth transistor T5 is the output end of the second output unit 150, and the gate of the fifth transistor T5 is the control end G of the second output unit 150.

[0073] The timing state diagram of each signal in the above shift register unit is as follows: Figure 6 As shown, the driving principle (method) is:

[0074] In the first phase (phase A) when the trigger signal GSTV is at the effective level, the first clock signal CK is set to the effective level, and the second clock signal CB is set to the ineffective level, so that the first output unit 140 outputs the second constant voltage signal;

[0075] In the second phase (phase B) after the first phase when the trigger signal GSTV is at an invalid level, the first clock signal CK is set to an invalid level, and the second clock signal CB is set to a valid level, so that the second output unit 150 outputs the first constant voltage signal;

[0076] In each stage (stages C, D, and E) in which the trigger signal GSTV is at an invalid level after the second stage, the first clock signal CK is set to a level opposite to that of the first clock signal CK of the previous stage, and the second clock signal CB is set to a level opposite to that of the second clock signal CB of the previous stage, so that the first output unit 140 continues to output the second constant voltage signal.

[0077] In some embodiments, the first constant voltage signal is a constant low level signal VGL, the second constant voltage signal is a constant high level signal VGH, and the first transistor T1 to the eighth transistor T5 are all P-type TFTs, the low level is the effective level, and the high level is the ineffective level.

[0078] Correspondingly, in stage A: the first clock signal CK and the trigger signal GSTV are both low level (valid level), the second clock signal CB is high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and a low level signal is written to the second node N2, so that the third transistor T3 is turned on, the second clock signal CB is derived through the drain of the third transistor T3, and a high level signal is written to the third node N3, and the fifth transistor T5 is turned off; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is written to the first node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT is a high level).

[0079] Phase B: the first clock signal CK and the trigger signal GSTV are both high level (invalid level), and the second clock signal CB is low level (valid level). Because the second node N2 (can be under the action of the first capacitor C1) maintains the low level of phase A, the third transistor T3 is turned on, and the second clock signal CB is derived through the drain of the third transistor T3, and a low level signal is written to the third node N3. The fifth transistor T5 is turned on, and the constant low level signal VGL is directly derived through the drain of the fifth transistor T5. At this time, the second output unit 150 outputs a low level signal (GOUT is a low level); at the same time, the constant high level signal VGH at the source of the fourth transistor T4 can pull up the voltage of the first node N1 under the voltage jump of the second capacitor C2, and the fourth transistor T4 is turned off.

[0080] Among them, the second clock signal CB is written into the third node N3 to lower its voltage. Under the action of the voltage jump of the first capacitor C1, the voltage of the second node N2 can be further lowered to maintain the low voltage of the second node N2, so that the duration of the second output unit 150 outputting a low level signal (GOUT is a low level) increases.

[0081] Phase C: the first clock signal CK is at a low level (valid level), the trigger signal GSTV and the second clock signal CB are both at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and a high level signal is written to the second node N2, the third transistor T3 is turned off, the third node N3 is in a floating state, and the voltage of the second node N2 is pulled up, and the voltage of the third node N3 can be pulled up under the voltage jump of the first capacitor C1, and the fifth transistor T5 is turned off; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is written to the first node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT is a high level).

[0082] Phase D: the first clock signal CK and the trigger signal GSTV are both high level (invalid level), and the second clock signal CB is low level (valid level). Because the second node N2 and the third node N3 (which can be the effect of the first capacitor C1) maintain the high level of the C phase, the third transistor T3 and the fifth transistor T5 are turned off; at the same time, the first node N1 (which can be the effect of the second capacitor C2) maintains the low level of the C phase, the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT is a high level).

[0083] Phase E: the first clock signal CK is at a low level (valid level), the trigger signal GSTV and the second clock signal CB are both at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, a high level signal is written to the second node N2, and the third transistor T3 is turned off; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is written to the first node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT is a high level).

[0084] In addition, the levels of the signals in the above-mentioned stage E can be the same as those in the above-mentioned stage A, and the first output unit 140 can also output a high-level signal.

[0085] It can be seen that the shift register unit directly outputs the second constant voltage signal (A, C, D, E stages) or the first constant voltage signal (B stage) through the control of the clock signal to realize the output of the Gate and Reset signals. Since the constant voltage signal itself does not have high and low level switching, whether it is stage B (GOUT switches from high level to low level, falling edge) or stage C (GOUT switches from low level to high level, rising edge), it is less affected by the load (voltage drop) of the peripheral circuit, and the level switching time is very short. The difference in Tr (rising edge time) and Tf (falling edge time) of the Gate and Reset signals is small, which can be greatly reduced, effectively improving the display defect.

[0086] See also Figure 7 In some embodiments, the shift register unit further includes: a second control unit 160 and a third control unit 170 .

[0087] The second control unit 160 has its input terminal connected to the first clock signal CK, its control terminal G connected to the second node N2, and its output terminal connected to the first node N1, and is configured to write the first clock signal CK into the first node N1 when the second node N2 is at a valid level.

[0088] The third control unit 170 has its input terminal connected to the second constant voltage signal, its first control terminal G connected to the first node N1, its second control terminal G connected to the second clock signal CB, and its output terminal connected to the third node N3, and is configured to write the second constant voltage signal to the third node N3 when the first node N1 and the second clock signal CB are both at valid levels.

[0089] like Figure 8As shown, in some embodiments, the second control unit 160 includes a sixth transistor T6; wherein the source of the sixth transistor T6 is the input end of the second control unit 160, the drain of the sixth transistor T6 is the output end of the second control unit 160, and the gate of the sixth transistor T6 is the control end G of the second control unit 160.

[0090] In some embodiments, the third control unit 170 includes a seventh transistor T7 and an eighth transistor T8; wherein the source of the seventh transistor T7 is the input terminal of the third control unit 170, the gate of the seventh transistor T7 is the first control terminal G of the third control unit 170, the drain of the seventh transistor T7 is connected to the source of the eighth transistor T8, the gate of the eighth transistor T8 is the second control terminal G of the third control unit 170, and the drain of the eighth transistor T8 is the output terminal of the third control unit 170.

[0091] In some embodiments, the first constant voltage signal is a constant low level signal VGL, the second constant voltage signal is a constant high level signal VGH, and the first transistor T1 to the eighth transistor T8 are all P-type TFTs, the low level is the effective level, and the high level is the ineffective level.

[0092] Correspondingly, in phase A: the first clock signal CK and the trigger signal GSTV are both at a low level (valid level), the second clock signal CB is at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and a low level signal is written to the second node N2, so that the third transistor T3 and the sixth transistor T6 are turned on (the seventh transistor T7 is turned on but the eighth transistor T8 is turned off, and the third control unit 170 is not turned on), the second clock signal CB is derived through the drain of the third transistor T3, and a high level signal is written to the third node N3, and the fifth transistor T5 is turned off; and the sixth transistor T6 is turned on, the first clock signal CK is derived through the sixth transistor T6, and a low level signal is written to the first node N1; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is also written to the first node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4, and at this time the first output unit 140 outputs a high level signal (GOUT is a high level).

[0093] Phase B: the first clock signal CK and the trigger signal GSTV are both high level (invalid level), and the second clock signal CB is low level (valid level). Because the second node N2 (can be under the action of the first capacitor C1) maintains the low level of phase A, the third transistor T3 and the sixth transistor T6 are turned on; the third transistor T3 is turned on, the second clock signal CB is derived through the drain of the third transistor T3, and a low level signal is written to the third node N3, the fifth transistor T5 is turned on, and the constant low level signal VGL is directly derived through the drain of the fifth transistor T5. At this time, the second output unit 150 outputs a low level signal (GOUT is a low level); the sixth transistor T6 is turned on, the first control signal is derived through the sixth transistor T6, and a high level signal is written to the first node N1, so that the fourth transistor T4 and the seventh transistor T7 are turned off.

[0094] Among them, the second clock signal CB is written into the third node N3 to lower its voltage. Under the action of the voltage jump of the first capacitor C1, the voltage of the second node N2 can be further lowered to maintain the low voltage of the second node N2, so that the duration of the second output unit 150 outputting a low level signal (GOUT is a low level) increases.

[0095] Phase C: the first clock signal CK is at a low level (valid level), the trigger signal GSTV and the second clock signal CB are both at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, and a high level signal is written to the second node N2, the third transistor T3 and the sixth transistor T6 are turned off, the third node N3 is in a floating state, the voltage of the second node N2 is pulled up, and the voltage of the third node N3 can be pulled up under the voltage jump of the first capacitor C1, and the fifth transistor T5 is turned off; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is written to the first node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT is a high level).

[0096] Phase D: The first clock signal CK and the trigger signal GSTV are both high level (invalid level), the second clock signal CB is low level (valid level), because the second node N2 (which can be the function of the first capacitor C1) maintains the high level of the C phase, so the third transistor T3 and the sixth transistor T6 are turned off, the first node N1 (which can be the function of the second capacitor C2) maintains the low level of the C phase, the fourth transistor T4 and the seventh transistor T7 are turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT); and the second clock signal CB is low level, the eighth transistor T8 is turned on, the constant high level signal VGH is derived through the seventh transistor T7 and the eighth transistor T8, and a high level signal is written to the third node N3, and the fifth transistor T5 is turned off. It can be seen that the seventh transistor T7 and the eighth transistor T8 (the third control unit 170) can make the third node N3 more effectively maintain a high level.

[0097] Phase E: the first clock signal CK is at a low level (valid level), the trigger signal GSTV and the second clock signal CB are both at a high level (invalid level), the first transistor T1 and the second transistor T2 are turned on under the control of the first clock signal CK, the trigger signal GSTV is derived through the drain of the second transistor T2, a high level signal is written to the second node N2, the third transistor T3 and the sixth transistor T6 are turned off, the third node N3 is in a floating state, the voltage of the second node N2 is pulled up, and the voltage of the third node N3 can be pulled up under the voltage jump of the first capacitor C1, and the fifth transistor T5 is turned off; at the same time, the constant low level signal VGL is derived through the drain of the first transistor T1, and a low level signal is written to the first node N1, so that the fourth transistor T4 is turned on, and the constant high level signal VGH is derived through the drain of the fourth transistor T4. At this time, the first output unit 140 outputs a high level signal (GOUT is a high level).

[0098] In addition, the levels of the signals in the above-mentioned stage E can be the same as those in the above-mentioned stage A, and the first output unit 140 can also output a high-level signal.

[0099] It can be seen that the shift register unit directly outputs the second constant voltage signal (A, C, D, E stages) or the first constant voltage signal (B stage) through the control of the clock signal to realize the output of the Gate and Reset signals. Since the constant voltage signal itself does not have high and low level switching, whether it is stage B (GOUT switches from high level to low level, falling edge) or stage C (GOUT switches from low level to high level, rising edge), it is less affected by the load (voltage drop) of the peripheral circuit, and the level switching time is very short. The difference in Tr (rising edge time) and Tf (falling edge time) of the Gate and Reset signals is small, which can be greatly reduced, effectively improving the display defect.

[0100] Fig. 9 The simulation verification schematic diagram of the above shift register unit is shown. Fig. 9 The simulation results show that the results are consistent with Figure 6 The timing diagrams are basically consistent, and the Tr (rising edge time) and Tf (falling edge time) of GOUT are relatively small, and the difference between the two is small.

[0101] An embodiment of the present application also provides a scan drive circuit, which includes a plurality of cascaded shift register units as in any of the above embodiments. The scan drive circuit can be a gate scan drive circuit, i.e., a Gate on Array (GOA) circuit, for outputting Gate and Reset signals.

[0102] The embodiment of the present application further provides a display substrate, which includes the above-mentioned scan drive circuit. The display substrate includes a display area and a non-display area arranged outside the display area, and the above-mentioned scan drive circuit is located in the non-display area of ​​the display substrate.

[0103] An embodiment of the present application further provides a display device, which includes the above-mentioned display substrate.

[0104] In some embodiments, the display device is a display panel, and the display panel includes the above-mentioned display substrate and a glass cover.

[0105] In some embodiments, the display device may include a display panel and a housing, wherein the display panel is connected to the housing, for example, the display panel is embedded in the housing. The display device may be, for example, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, or any other device having a display function.

[0106] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. Although the implementation methods disclosed in the present application are as above, the content is only an implementation method adopted to facilitate the understanding of the present application and is not intended to limit the present application. Any technician in the technical field to which the present application belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application, but the protection scope of the present application shall still be subject to the scope defined by the attached claims.

Claims

1. A shift register unit, characterized in that: include: A first input unit, whose input end is connected to a first constant voltage signal, whose control end is connected to a first clock signal, whose output end is connected to a first node, and is configured to write the first constant voltage signal into the first node when the first clock signal is at a valid level; A second input unit, whose input end is connected to the trigger signal, whose control end is connected to the first clock signal, whose output end is connected to the second node, and is configured to write the trigger signal into the second node when the first clock signal is at a valid level; A first control unit, whose input terminal is connected to the second clock signal, whose control terminal is connected to the second node, and whose output terminal is connected to the third node, and is configured to maintain the level signal at the second node when the second input unit does not input a voltage to the second node, and is further configured to write the second clock signal to the third node when the second node is at an effective level, and the voltage change of the third node causes the voltage of the second node to change in the same direction to maintain the effective level at the second node; a first output unit, whose input terminal is connected to the second constant voltage signal, whose control terminal is connected to the first node, and configured to output the second constant voltage signal when the first node is at a valid level; wherein the second constant voltage signal is opposite to the level of the first constant voltage signal; The second output unit has an input terminal connected to the first constant voltage signal and a control terminal connected to the third node, and is configured to output the first constant voltage signal when the third node is at a valid level.

2. The shift register unit according to claim 1, characterized in that: The first input unit includes a first transistor, wherein a source of the first transistor is an input terminal of the first input unit, a drain of the first transistor is an output terminal of the first input unit, and a gate of the first transistor is a control terminal of the first input unit.

3. The shift register unit according to claim 1, characterized in that: The second input unit includes a second transistor, wherein the source of the second transistor is the input terminal of the second input unit, the drain of the second transistor is the output terminal of the second input unit, and the gate of the second transistor is the control terminal of the second input unit.

4. The shift register unit according to claim 1, characterized in that: The first control unit includes a third transistor; wherein the source of the third transistor is the input end of the first control unit, the drain of the third transistor is the output end of the first control unit, and the gate of the third transistor is the control end of the first control unit.

5. The shift register unit according to claim 4, characterized in that: The first control unit also includes a first capacitor; wherein a first end of the first capacitor is connected to the gate of the third transistor, and a second end of the first capacitor is connected to the drain of the third transistor.

6. The shift register unit according to claim 1, characterized in that: The first output unit includes a fourth transistor; wherein the source of the fourth transistor is the input end of the first output unit, the drain of the fourth transistor is the output end of the first output unit, and the gate of the fourth transistor is the control end of the first output unit.

7. The shift register unit according to claim 6, characterized in that: The first output unit further includes a second capacitor; wherein a first end of the second capacitor is connected to the gate of the fourth transistor, and a second end of the second capacitor is connected to the source of the fourth transistor.

8. The shift register unit according to claim 1, characterized in that: The second output unit includes a fifth transistor; wherein the source of the fifth transistor is the input end of the second output unit, the drain of the fifth transistor is the output end of the second output unit, and the gate of the fifth transistor is the control end of the second output unit.

9. The shift register unit according to claim 1, characterized in that: Also includes: a second control unit, whose input end is connected to the first clock signal, whose control end is connected to the second node, whose output end is connected to the first node, and configured to write the first clock signal into the first node when the second node is at a valid level; A third control unit, whose input end is connected to the second constant voltage signal, whose first control end is connected to the first node, whose second control end is connected to the second clock signal, whose output end is connected to the third node, and is configured to write the second constant voltage signal into the third node when the first node and the second clock signal are both at a valid level.

10. The shift register unit according to claim 9, characterized in that: The second control unit includes a sixth transistor; wherein the source of the sixth transistor is the input end of the second control unit, the drain of the sixth transistor is the output end of the second control unit, and the gate of the sixth transistor is the control end of the second control unit.

11. The shift register unit according to claim 9, characterized in that: The third control unit includes a seventh transistor and an eighth transistor; Among them, the source of the seventh transistor is the input end of the third control unit, the gate of the seventh transistor is the first control end of the third control unit, the drain of the seventh transistor is connected to the source of the eighth transistor, the gate of the eighth transistor is the second control end of the third control unit, and the drain of the eighth transistor is the output end of the third control unit.

12. A driving method of a shift register unit according to any one of claims 1 to 11, characterized in that: include: In a first stage when the trigger signal is at a valid level, the first clock signal is set to a valid level, and the second clock signal is set to an invalid level, so that the first output unit outputs the second constant voltage signal; In a second stage after the first stage when the trigger signal is at an invalid level, the first clock signal is set to an invalid level, and the second clock signal is set to a valid level, so that the second output unit outputs the first constant voltage signal; In each stage after the second stage in which the trigger signal is at an invalid level, the first clock signal is set to a level opposite to that of the first clock signal in the previous stage, and the second clock signal is set to a level opposite to that of the second clock signal in the previous stage, so that the first output unit continues to output the second constant voltage signal.

13. A scan driving circuit, comprising a plurality of cascaded shift register units according to any one of claims 1 to 11.

14. A display substrate, characterized in that: Comprising the scan driving circuit as claimed in claim 13.

15. A display device, characterized in that: Comprising the display substrate as claimed in claim 14.

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