Method for improving the image resolution capability of planar fully depleted silicon-on-insulator devices

Abstract

The present application relates to the field of integrated circuit design, and specifically to a method for improving the graphic resolution capability of a planar fully depleted silicon-on-insulator device, comprising the following steps: obtaining data of a main graphic on an integrated circuit; inserting a virtual graphic according to the data; screening out graphics that are prone to rounded corners according to a predetermined rule; inserting scattering strips at at least part of the corners of the screened graphics; inserting scattering strips according to the data; and performing the step of correcting the optical proximity effect. By inserting scattering strips at the corners of graphics that are prone to rounded corners, the rounding of the graphics is greatly reduced, thereby improving the resolution of the main graphics and the graphic resolution capability, and improving the yield of the product.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a method for improving the graphic analysis capability of a planar fully depleted silicon-on-insulator device. Background Art

[0002] With the booming development of integrated circuits today, chip miniaturization and integration are inevitable trends and important topics that are actively developed by all sectors. In the manufacturing process of integrated circuits, the photolithography step is an important key to determine the performance of components. With the gradual increase in integration, the chip size gradually decreases, and the distance between chips must also be reduced, which causes deviations in pattern transfer during the photolithography step. For example, when a mask pattern is transferred to a wafer using photolithography, the right angle part is rounded, the tail end of the pattern shrinks, and the line width is reduced or increased. This is the so-called optical proximity effect (OPE). These deviations will not have too much negative effect when the chip size is large or the integration is low. However, in highly integrated integrated circuits, they seriously affect the performance of the chip. Therefore, in order to solve the problem, the mask can be subjected to optical proximity correction (OPC). The OPC method is to pre-process the photolithography mask before lithography and make advance modifications so that the amount of modification compensation can just compensate for the optical proximity effect caused by the exposure system.

[0003] In order to improve the resolution of the graphics during the OPC process, scattering bars (sbars) of different sizes are usually inserted according to the line width and spacing of the main graphics on the mask. However, it should be noted that although the insertion of scattering bars can improve the resolution of the graphics, when the line spacing of the graphics is too small and lower than the limit value of the OPC correction, the problem of rounded right angles cannot be properly corrected, which in turn causes a decrease in product yield. Summary of the invention

[0004] The present application solves the above technical problems in the related art at least to some extent. To this end, the present application proposes a method for improving the image resolution capability of a planar fully depleted silicon-on-insulator device to solve at least one of the above technical problems.

[0005] In order to achieve the above-mentioned object, the first aspect of the present application provides a method for improving the image resolution capability of a planar fully depleted silicon-on-insulator device, comprising the following steps:

[0006] Acquire data of a main pattern on an integrated circuit;

[0007] inserting a virtual graphic according to the data;

[0008] Screen out graphics that are prone to rounded corners according to predetermined rules;

[0009] inserting scattering strips at at least some of the corners of the screening pattern;

[0010] inserting scatter bars based on the data;

[0011] The step of performing optical proximity effect correction.

[0012] Compared with the prior art, by inserting scattering strips at the corners where rounded corners are easily generated, the rounding of the graphics is greatly reduced, thereby improving the resolution of the main graphics and the graphics analysis capability, and improving the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0014] Figure 1 A flow chart of a lifting method in an embodiment of the present invention is shown;

[0015] Figure 2 A schematic diagram is shown before the scattering strips are inserted in the embodiment of the present invention;

[0016] Figure 3 Shown in Figure 2 Schematic diagram after inserting scattering bars;

[0017] Figure 4 Shown in Figure 3 Schematic diagram after inserting scattering bars. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0019] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0020] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0021] Please refer to Figures 1 to 4 The present invention provides a method for improving the image resolution capability of a planar fully depleted silicon-on-insulator device (FDSOI for short), which specifically includes the following steps:

[0022] like Figure 1 As shown, firstly, the data of the main pattern on the integrated circuit is obtained; specifically, all the original design data of the hierarchical layout and the specific location of the main pattern in the initial GDS (Graphic Data Stream, referred to as the graphic data stream) file are read in. It should be noted that this embodiment is described by taking the main pattern in the GDS format as an example, but this embodiment is not limited to this, and the main pattern can also be a CAD format file.

[0023] EDA software is usually used, such as Mentor's layout processing tool Calibre; specifically, it can automatically identify data at each process level and the identification of specific devices (such as SRAM, Flash, I / O and other devices) as required, calculate the length, width, area and other information of a specific area, and complete the designation of the center position and transition area of ​​a specific area, and the specific area can be an area marked by the customer.

[0024] The above-mentioned GDS file is a data stream file that stores the layout of the integrated circuit in binary form. The GDS file includes a hierarchical structure, which includes top-level units and non-top-level units. The top-level units and non-top-level units also include graphic layers and labels, wherein the graphic layer can be an active area, silicon gate, metal layer, through hole, etc. in a semiconductor device, and the label is a text data that identifies the port name through the label. A port is the metal used by a unit to connect to other units.

[0025] Next, a dummy pattern is inserted according to the data; specifically, the smallest design unit is determined according to the position information of the main pattern, thereby obtaining the size and position of the dummy pattern to be inserted. The inserted dummy pattern is mainly used to ensure that the edge area and the center position of the main pattern area and the transition area have different light intensities, and the dummy pattern does not form an effective pattern on the chip, and ultimately can have a higher pattern consistency on the chip without affecting the design performance of the circuit itself.

[0026] Next, continue to refer to Figure 3 , according to predetermined rules, the graphics that are easy to generate rounded corners are screened out; specifically, the graphics with specific line width and line distance are obtained by using EDA software, the graphics that are easy to generate rounded corners are determined according to the line width and line distance of the graphics 10, and the position information of the graphics generating rounded corners is obtained.

[0027] Next, continue to refer to Figure 4 , scattering strips 11 are inserted at some corners according to the position information of the rounded corners generated by the screening pattern.

[0028] Next, the scattering strips are inserted according to the data of the main graphic; specifically, the smallest design unit is determined according to the position information of the main graphic, thereby obtaining the size and position of the scattering strips to be inserted.

[0029] Next, the step of optical proximity effect correction is performed. Specifically, the OPC calculation correction is performed using the existing OPC model. It is worth mentioning that the step of optical proximity effect correction used in this embodiment is the same as that in the prior art, so it will not be repeated here.

[0030] It is worth mentioning that before inserting the scattering strips 11, it is necessary to ensure that the inserted scattering strips 11 will not expose redundant patterns on the device. Specifically, the scattering strips 11 that produce redundant patterns can be determined based on the line width and length of the scattering strips 11, and then the scattering strips that produce redundant patterns can be removed, and finally the qualified scattering strips 11 that remain can be inserted into the pattern.

[0031] Compared with the prior art, by inserting scattering strips at the corners where rounded corners are easily generated, the rounding of the graphics is greatly reduced, thereby improving the resolution of the main graphics and the graphics analysis capability, and improving the yield of the product.

[0032] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0033] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for improving the image resolution capability of a planar fully depleted silicon-on-insulator device, characterized in that: The following steps are involved: Acquire data of a main pattern on an integrated circuit; inserting a virtual graphic according to the data; Screen out graphics that are prone to rounded corners according to predetermined rules; The predetermined rule includes: obtaining a graphic with a specific line width and line distance, determining a graphic that is prone to rounded corners according to the line width and line distance of the graphic, and obtaining position information of the graphic where the rounded corners are generated; inserting scattering strips at at least a portion of the corners of the screening pattern according to the position information of the rounded corners generated by the screening pattern; Continue to insert scattering strips according to the data, determine the smallest design unit according to the position information of the main graphic, and obtain the size and position of the scattering strips to be inserted; Before inserting the scattering strips, determine the scattering strips that generate redundant patterns according to the line width and length of the scattering strips, remove the scattering strips that generate redundant patterns, and insert the remaining qualified scattering strips into the pattern; The step of performing optical proximity effect correction.

2. The lifting method according to claim 1, characterized in that: The length and width of each scattering strip are the same.

3. The lifting method according to claim 1, characterized in that: The data of the main graphics is in CAD format or GDS format.

4. The lifting method according to claim 1, characterized in that: Use EDA software to screen out graphics that are prone to rounded corners and insert scattering bars.

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