A circuit and method for evaluating equivalent load of signal interconnection lines in multi-chip packaging

Abstract

The present invention relates to the technical field of multi-chip packaging, and specifically to an evaluation circuit and method for the equivalent load of a signal interconnection line in a multi-chip package. The circuit comprises: a first analog circuit, comprising a target signal interconnection line in a multi-chip package, for obtaining a target analog signal amount of the target signal interconnection line; a second analog circuit, comprising an adjustable capacitor, for obtaining a capacitance analog signal amount of the adjustable capacitor at different capacitance values; a signal comparison module, for obtaining a comparison result between the target analog signal amount and the capacitance analog signal amount. The present invention constructs a first analog circuit, and constructs a second analog circuit based on the adjustable capacitor, and then uses a signal comparison module to compare the difference between the capacitance analog signal amount and the target analog signal amount, and finally the current capacitance value of the adjustable capacitor can be equivalent to the load of the target signal interconnection line, thereby accurately evaluating the signal interconnection load in the multi-chip package.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip packaging, and in particular to an evaluation circuit and method for equivalent load of signal interconnection lines in a multi-chip packaging. Background Art

[0002] Multi-chip package is a package that can integrate multiple chips of different sizes, different manufacturing processes, and different materials into one package shell, including 2D, 2.5D, 3D and other chip stacking methods, and is used in advanced mobile communications / computing, high-bandwidth memory and other systems.

[0003] Figure 1 It is a typical microsystem diagram composed of 3D multi-chip packaging, which includes two chips dieA and dieB for realizing different functions. Signal interconnection connectors (such as through silicon vias TSV, hybrid bonding wires, etc.) can realize the electrical connection between dieA and dieB, and signal interconnection bonding wires (such as ordinary bonding wires, solder bumps, etc.) realize the electrical connection between chips and between chips and the outside world through metal routing in the package base substrate.

[0004] Figure 2 yes Figure 1 In the schematic diagram of the microsystem, dieA is composed of the core circuit dieA_core and the input-output circuit IOA, which realizes functions such as control and calculation; dieB is composed of the core circuit dieB_core and the input-output circuit IOB, which realizes functions such as storage, digital / analog conversion, and data exchange); the signal interconnection line realizes the physical electrical connection of the input and output signals IO_1~IO_n.

[0005] It can be seen that the signal interconnection line serves as a bridge between the input and output circuits of each chip. The size of its equivalent load directly affects the signal integrity of the input and output signals (especially high-speed signals) and the power integrity of the chip, so it is particularly important to accurately evaluate the signal interconnection load.

[0006] At present, the equivalent load value of the signal interconnection line is generally provided by the packaging factory, and after modeling through the EDA tool, an approximate value range is provided to the user. Since the accurate equivalent load value of the signal interconnection line cannot be known, multi-chip packaging cannot be applied to some application scenarios with high precision requirements.

[0007] Therefore, how to accurately evaluate the signal interconnection load in multi-chip packaging is a technical problem that needs to be solved urgently. Summary of the invention

[0008] The object of the present invention is to provide a circuit and method for evaluating the equivalent load of signal interconnection lines in a multi-chip package, so as to accurately evaluate the signal interconnection load in the multi-chip package.

[0009] To achieve the above objectives, the embodiments of the present invention provide the following solutions:

[0010] In a first aspect, an embodiment of the present invention provides an evaluation circuit for equivalent load of a signal interconnect line in a multi-chip package, comprising:

[0011] A first analog circuit, comprising a target signal interconnection line in a multi-chip package, for obtaining a target analog signal amount of the target signal interconnection line;

[0012] A second analog circuit includes an adjustable capacitor, and is used to obtain a capacitance analog signal quantity of the adjustable capacitor at different capacitance values;

[0013] The signal comparison module is used to obtain the comparison result between the target analog signal quantity and the capacitance analog signal quantity, so as to equate the capacitance value of the current adjustable capacitor to the load of the target signal interconnection line when the difference between the capacitance analog signal quantity and the target analog signal quantity is less than a set threshold.

[0014] In a possible embodiment, the target signal interconnection line includes a signal interconnection line between any two chips in the multi-chip package and / or a signal interconnection line between any one chip and a package base.

[0015] In a possible embodiment, the first analog circuit is a first oscillation circuit; wherein the target signal interconnection line is a capacitor of the first oscillation circuit;

[0016] The second analog circuit is a second oscillation circuit; wherein the adjustable capacitor is the capacitor of the second oscillation circuit.

[0017] In a possible embodiment, the first analog circuit is a first ring oscillator; and the second analog circuit is a second ring oscillator.

[0018] In a possible embodiment, the target signal interconnection line includes at least one group of signal interconnection line combinations; wherein each group of signal interconnection line combinations includes two signal interconnection lines connected in series;

[0019] The first ring oscillator and the second ring oscillator are arranged in a common ring oscillator;

[0020] The common ring oscillator comprises a delay module and a NAND gate logic circuit; the output end of the NAND gate logic circuit is connected to the input end of the delay module; the output end of the delay module is connected to the input end of the NAND gate logic circuit;

[0021] The delay module includes at least one delay unit; wherein each group of signal interconnection line combinations corresponds to a delay unit;

[0022] The delay unit includes an input buffer, a first selector, a second selector and an output buffer;

[0023] The output end of the output buffer is connected to the input end of the first selector; the first output end of the first selector is connected to the first input end of the second selector through the signal interconnection line combination corresponding to the delay unit; the second output end of the first selector and the second input end of the second selector are both grounded through the adjustable capacitor; the output end of the second selector is connected to the input end of the output buffer;

[0024] The common ring oscillator further includes: a first buffer and a frequency divider;

[0025] The output end of the NAND gate logic circuit is connected to the input end of the frequency divider through the first buffer.

[0026] In a possible embodiment, the first analog circuit is a first charge-discharge circuit; wherein the target signal interconnection line is a charge-discharge capacitor of the first charge-discharge circuit;

[0027] The second analog circuit is a second charge-discharge circuit; wherein the adjustable capacitor is a charge-discharge capacitor of the charge-discharge circuit.

[0028] In a possible embodiment, the first charge-discharge circuit includes a first current source, a first MOS transistor, a second MOS transistor and a first capacitor; the second charge-discharge circuit includes a second current source, a third MOS transistor, a fourth MOS transistor and a second capacitor;

[0029] The first current source is grounded via the first MOS transistor, the target signal interconnection line and the first capacitor; the target signal interconnection line is also grounded via the second MOS transistor;

[0030] The second current source is grounded via the third MOS tube and the adjustable capacitor; the fourth MOS tube and the second capacitor are both connected in parallel with the adjustable capacitor;

[0031] The gate of the first MOS tube is respectively connected to the gate of the second MOS tube, the gate of the third MOS tube and the gate of the fourth MOS tube;

[0032] The channel types of the first MOS tube and the second MOS tube are different; the channel types of the third MOS tube and the fourth MOS tube are different; and the channel types of the first MOS tube and the third MOS tube are the same.

[0033] In a possible embodiment, the signal comparison module includes a comparator and a D flip-flop;

[0034] The first input end of the comparator is connected to the drain of the first MOS tube; the second input end of the comparator is connected to the drain of the third MOS tube; the output end of the comparator is connected to the D end of the D flip-flop; the gate of the first MOS tube is connected to the CP end of the D flip-flop through an inverter.

[0035] In a second aspect, an embodiment of the present invention provides a method for acquiring a load of a signal interconnect line based on any evaluation circuit described in the first aspect, characterized in that the method comprises:

[0036] Acquire a target analog signal quantity of a target signal interconnection line in a multi-chip package; wherein the target analog signal quantity includes a target frequency signal quantity, a target voltage signal quantity, or a target current signal quantity;

[0037] Adjusting the capacitance value of the adjustable capacitor so that the difference between the current analog signal amount of the adjustable capacitor and the target analog signal amount is less than a set threshold, and obtaining the current capacitance value of the adjustable capacitor;

[0038] The current capacitance value is equivalent to the load of the target signal interconnection line.

[0039] In a possible embodiment, after the current capacitance value is equivalent to the load of the target signal interconnection line, the method further includes:

[0040] According to the load of the target signal interconnection line, the driving capability of the chip corresponding to the target signal interconnection line is adjusted.

[0041] In a third aspect, an embodiment of the present invention provides a device for acquiring a load of a signal interconnection line based on the evaluation circuit as described in any one of the first aspects, characterized in that the device comprises:

[0042] A first acquisition module is used to acquire a target analog signal quantity of a target signal interconnection line in a multi-chip package; wherein the target analog signal quantity includes a target frequency signal quantity, a target voltage signal quantity or a target current signal quantity;

[0043] A second acquisition module is used to adjust the capacitance value of the adjustable capacitor so that the difference between the current analog signal amount of the adjustable capacitor and the target analog signal amount is less than a set threshold value, and acquire the current capacitance value of the adjustable capacitor;

[0044] The third acquisition module is used to equate the current capacitance value to the load of the target signal interconnection line.

[0045] In a possible embodiment, the device further includes:

[0046] The driving capability adjustment module is used to adjust the driving capability of the chip corresponding to the target signal interconnection line according to the load of the target signal interconnection line.

[0047] In a fourth aspect, an embodiment of the present invention provides a multi-chip packaged microsystem, comprising: an evaluation circuit as described in any one of the first aspects; wherein the evaluation circuit is arranged in any chip in the multi-chip packaged microsystem.

[0048] In a fifth aspect, an embodiment of the present invention provides a computer system, comprising a multi-chip packaged microsystem, wherein the multi-chip packaged microsystem executes the steps of any one of the methods described in the second aspect.

[0049] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0050] The present invention converts the actual load of the signal interconnection line into equivalent capacitance according to the actual size of the signal interconnection line. Since the equivalent capacitance is small and difficult to measure directly, the present invention constructs a first analog circuit based on the target signal interconnection line to obtain the target analog signal amount of the target signal interconnection line, and constructs a second analog circuit based on the adjustable capacitor to obtain the capacitance analog signal amount of the adjustable capacitor at different capacitance values. Then, a signal comparison module is used to compare the difference between the capacitance analog signal amount and the target analog signal amount. Finally, the capacitance value of the adjustable capacitor when the difference between the capacitance analog signal amount and the target analog signal amount is less than a set threshold value can be equivalent to the load of the target signal interconnection line, thereby accurately evaluating the signal interconnection load in the multi-chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 It is a typical schematic diagram of a microsystem composed of 3D multi-chip packaging;

[0053] Figure 2 yes Figure 1 Schematic diagram of the microsystem;

[0054] Figure 3 It is a connection diagram of an evaluation circuit for equivalent load of a signal interconnection line in a multi-chip package provided by an embodiment of the present invention;

[0055] Figure 4 yes Figure 3Schematic diagram of working principle;

[0056] Figure 5 is a connection diagram of a common ring oscillator provided by an embodiment of the present invention;

[0057] Figure 6 is a connection diagram of a delay unit provided by an embodiment of the present invention;

[0058] Figure 7 yes Figure 5 The waveform diagram of the working process of the common ring oscillator shown;

[0059] Figure 8 It is a connection diagram of an evaluation circuit for equivalent load of a signal interconnection line in a multi-chip package provided by an embodiment of the present invention;

[0060] Fig. 9 yes Figure 8 The waveform diagram of the working process of the evaluation circuit of the equivalent load of the signal interconnection line in the multi-chip package shown;

[0061] Fig.10 A flow chart of a method for acquiring a load of a signal interconnection line provided by an embodiment of the present invention;

[0062] Fig.11 A schematic diagram of the structure of a device for acquiring a load of a signal interconnection line provided by an embodiment of the present invention;

[0063] Fig.12 A schematic diagram of the principle of a multi-chip packaged microsystem provided by an embodiment of the present invention.

[0064] Explanation of the accompanying drawings: 110 is a first analog circuit, 111 is a target signal interconnection line, 112 is a signal interconnection line combination, 120 is a second analog circuit, 121 is an adjustable capacitor, 130 is a signal comparison module, 210 is a delay module, 220 is an NAND gate logic circuit, 230 is a first buffer, 240 is a divider, 310 is a delay unit, 311 is an input buffer, 312 is a first selector, 313 is a second selector, 314 is an output buffer, It is a first current source, Ir is a second current source, M1 is a first MOS tube, M2 is a second MOS tube, M3 is a third MOS tube, M4 is a fourth MOS tube, Ctb is a first capacitor, Crb is a second capacitor, 411 is a comparator, and 412 is a D trigger. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention belong to the scope of protection of the embodiments of the present invention.

[0066] See also Figure 3 , Figure 3 A connection diagram of a circuit for evaluating an equivalent load of a signal interconnect line in a multi-chip package provided by an embodiment of the present invention, the circuit comprising: a first analog circuit 110 , a second analog circuit 120 and a signal comparison module 130 .

[0067] The first analog circuit 110 includes a target signal interconnection line 111 in a multi-chip package and is used to obtain a target analog signal quantity of the target signal interconnection line 111 .

[0068] Specifically, the signal interconnection line in the multi-chip package can be a connection line between multiple chips, or a connection line between a chip and a package shell. Here, the chip can be a packaged chip, or a bare chip (i.e., a chip that has not been packaged after the wafer is produced, cut, and tested in a processing plant). The target signal interconnection line can be one or more signal interconnection lines in the multi-chip package that need to detect the load.

[0069] Here, since the actual size of the signal interconnection line is in the nanometer to micrometer level, its equivalent resistance and equivalent inductance are very small, so the equivalent load of the signal interconnection line can be regarded as an equivalent capacitance. In this embodiment, the first analog circuit 110 is constructed based on the equivalent capacitance to obtain an analog signal quantity representing the size of the equivalent capacitance.

[0070] Specifically, the target analog signal quantity can be in the form of analog quantities such as current, voltage or frequency. Correspondingly, the first analog circuit 110 can use an RC oscillation circuit to obtain the oscillation signal of the equivalent capacitance corresponding to the signal interconnection line, or a capacitor charging and discharging circuit to obtain the charging voltage or discharge voltage of the equivalent capacitance corresponding to the signal interconnection line. A ring oscillator can also be used to obtain the oscillation signal frequency corresponding to the equivalent capacitance corresponding to the signal interconnection line. Of course, other capacitor-based analog circuits can also be used to construct the first analog circuit 110 in this embodiment to achieve the purpose of obtaining the target analog signal quantity of the target signal interconnection line 111. The specific implementation method is not limited here.

[0071] The second analog circuit 120 includes an adjustable capacitor 121 and is used to obtain capacitance analog signal quantities of the adjustable capacitor 121 at different capacitance values.

[0072] Specifically, the adjustable capacitor 121 is provided with a control terminal. When the adjustable capacitor 121 receives an instruction to adjust the capacitance value, the adjustable capacitor 121 can adjust the capacitance value according to the instruction.

[0073] The capacitance analog signal can be in the form of analog quantities such as current, voltage or frequency. Correspondingly, the second analog circuit 120 can use a capacitance charging and discharging circuit to obtain the charging voltage or discharging voltage of the adjustable capacitor 121, and can also use a ring oscillator to obtain the oscillation signal frequency corresponding to the adjustable capacitor 121. Of course, other capacitance-based analog circuits can also be used to construct the second analog circuit 120 in this embodiment to achieve the purpose of obtaining the capacitance analog signal of the adjustable capacitor 121 at different capacitance values. The specific implementation method is not limited here.

[0074] The signal comparison module 130 is used to obtain a comparison result between the target analog signal quantity and the capacitance analog signal quantity, so that when the difference between the capacitance analog signal quantity and the target analog signal quantity is less than a set threshold, the capacitance value of the current adjustable capacitor is equivalent to the load of the target signal interconnect line 111.

[0075] In practical applications, the signal comparison module 130 can be set according to the type of analog signal quantity obtained by the first analog circuit 110 and the second analog circuit 120. If the analog signal quantity type is in the form of voltage, the signal comparison module 130 can be implemented by using the comparator 411 circuit; if the analog signal quantity type is in the form of frequency, the frequency value can be directly obtained to realize the function of the signal comparison module 130; of course, the analog signal quantity obtained by the first analog circuit 110 and the second analog circuit 120 can also be directly output to the oscilloscope, so as to use the oscilloscope to obtain the comparison result of the target analog signal quantity and the capacitance analog signal quantity, and the specific implementation method of the signal comparison module 130 is not limited here.

[0076] When the capacitance value of the adjustable capacitor 121 is adjusted appropriately and the difference between the capacitance analog signal and the target analog signal is smaller than the set threshold, the load corresponding to the current adjustable capacitor 121 is equivalent to the equivalent load of the target signal interconnection line 111 .

[0077] Here, the difference between the capacitance analog signal and the target analog signal may be in the form of a ratio or in the form of a difference in analog signal quantities, and the corresponding set threshold may be flexibly selected according to actual conditions.

[0078] The working principle of this embodiment:

[0079] like Figure 4 Shown Figure 3The schematic diagram of the working principle shows that the first analog circuit 110 can obtain the target analog signal amount of the target signal interconnection line 111, the second analog circuit 120 can obtain the capacitance analog signal amount of the adjustable capacitor 121 at different capacitance values, and the signal comparison module 130 can obtain the comparison result between the target analog signal amount and the capacitance analog signal amount, so that the controller (for example, a chip in a multi-chip package, or a host computer outside the multi-chip package, etc.) can issue a capacitance adjustment instruction according to the comparison result to adjust the capacitance value of the adjustable capacitor 121 until the difference between the capacitance analog signal amount and the target analog signal amount is less than the set threshold.

[0080] In this embodiment, the target analog signal quantity of the target signal interconnect line 111 is characterized as the equivalent load of the target signal interconnect line 111. When the difference between the capacitance analog signal quantity of the adjustable capacitor 121 and the target analog signal quantity characterization of the target signal interconnect line 111 is small, the equivalent load of the target signal interconnect line 111 can be characterized by the current adjustable capacitor 121, thereby achieving accurate evaluation of the equivalent load of the target signal interconnect line 111 in a multi-chip package.

[0081] In a multi-chip package, the target signal interconnection line 111 may be a signal interconnection line between any two chips in the multi-chip package, or a signal interconnection line between any chip in the multi-chip package and a package base, which is not limited here.

[0082] In practical applications, the first analog circuit 110 may be a first oscillation circuit, wherein the target signal interconnect line 111 is a first oscillation circuit capacitor; and the second analog circuit 120 is a second oscillation circuit, wherein the adjustable capacitor 121 is a second oscillation circuit capacitor.

[0083] Of course, the oscillation generator may also be a ring oscillator. The first analog circuit 110 may be a first ring oscillator; the second analog circuit 120 may be a second ring oscillator. In this case, the output oscillation signal is a frequency signal.

[0084] In order to simplify the structure of the first analog circuit 110 and the second analog circuit 120 and reduce the circuit size, this embodiment further provides a simplified solution for the first ring oscillator and the second ring oscillator, specifically, the first ring oscillator and the second ring oscillator are arranged in a common ring oscillator to reduce the device size. The specific solution is:

[0085] The target signal interconnection line 111 may include at least one group of signal interconnection line combinations 112 ; wherein each group of signal interconnection line combinations 112 includes two signal interconnection lines connected in series.

[0086] Specifically, since the equivalent capacitance corresponding to a single signal interconnection line is too small, the target signal interconnection line 111 can select multiple signal interconnections to increase the equivalent capacitance value of the target signal interconnection line 111, reduce the oscillation frequency output by the ring oscillator, and facilitate testing. Since the evaluation circuit is arranged in a chip in a multi-chip packaged microsystem, the signal interconnections in the target signal interconnection line 111 can be divided into a plurality of (greater than or equal to one) signal interconnection line combinations 112, and the signal interconnections in each signal interconnection line combination 112 are grouped in pairs and connected in series as a whole, so that the input and output ends of each signal interconnection line combination 112 can be located on one side, which is convenient for wiring.

[0087] like Figure 5 FIG. 2 is a connection diagram of a common ring oscillator provided in an embodiment of the present invention, wherein the common ring oscillator includes a delay module 210 and a NAND gate logic circuit 220 .

[0088] Specifically, the output end of the NAND gate logic circuit 220 is connected to the input end of the delay module 210; the output end of the delay module 210 is connected to the input end of the NOT gate logic circuit; in this way, the inverted signal output by the NAND gate logic circuit 220 returns to the input end of the NAND gate logic circuit 220 after the delay of the delay module 210, and is inverted and output again by the NAND gate logic circuit 220, thereby forming a clock frequency signal at the output end of the NAND gate logic circuit 220.

[0089] The delay module 210 includes at least one delay unit 310; wherein each group of signal interconnection line combinations 112 corresponds to a delay unit 310. Figure 6 The figure shows a connection diagram of the delay unit 310 provided in an embodiment of the present invention. The delay unit 310 includes an input buffer 311, a first selector 312, a second selector 313 and an output buffer 314; the output end of the output buffer 314 is connected to the input end of the first selector 312; the first output end of the first selector 312 is connected to the first input end of the second selector 313 through the signal interconnection line combination 112 corresponding to the delay unit 310; the second output end of the first selector 312 and the second input end of the second selector 313 are both grounded through an adjustable capacitor; the output end of the second selector 313 is connected to the input end of the output buffer 314. The first ring oscillator and the second ring oscillator can be switched by the control of the first selector and the second selector in the delay unit.

[0090] The common ring oscillator further includes: a first buffer 230 and a frequency divider 240; the output end of the NAND gate logic circuit 220 is connected to the input end of the frequency divider 240 through the first buffer 230. In this way, through the action of the first buffer 230 and the frequency divider 240, the frequency of the clock frequency signal output by the NAND gate logic circuit 220 is further reduced, which facilitates the subsequent comparison and analysis of the clock frequency signal.

[0091] like Figure 7 Shown Figure 5 FIG. 1 is a waveform diagram of the working process of the common ring oscillator, wherein EN is the enable signal of the common ring oscillator, EV_CTRL is the selection signal of the device to be evaluated (when EV_CTRL=0, the target signal interconnection line 111 is selected, and when EV_CTRL=1, the adjustable capacitor 121 is selected). In this embodiment, the frequency value is used to compare the difference between the two analog signal quantities, and EV_OUT is directly selected as the output signal of the signal comparison module 130, and CFGCAP <k:0>Specifically, it is a capacitance adjustment instruction of the adjustable capacitor 121 .

[0092] Figure 5 The specific working process of the common ring oscillator shown is:

[0093] 1. t0-t1: the enable signal EN is pulled high, and the ring oscillator starts to work; at this time, EV_CTRL is low, and the target signal interconnect line 111 is selected as the device under test; the clock frequency of the output signal EV_OUT is fref;

[0094] 2.t1~t2: EV_CTRL is pulled high, and the internal adjustable capacitor 121 is selected as the device under test; at this time, CFGCAP <k:0>The corresponding value is 1, the clock frequency of the output EV_OUT is fcon_1, and fcon_1 is greater than fref;

[0095] 3. t2-t3: Continue to configure CFGCAP <k:0>The value corresponding to the signal is 2, the clock frequency of the output EV_OUT is fcon_2, and fcon_2 is greater than fref;

[0096] 4. t3~t5: Continue to configure CFGCAP <k:0>The value corresponding to the signal is j (3<=j<=2^K), the clock frequency of the output EV_OUT is fcon_j, compare the size of fcon_j and fref until they are equal or close, then record CFGCAP at this time <k:0>The value corresponding to the signal is eq;

[0097] 5.t5: The enable signal EN is pulled low, the ring oscillator stops working, and the entire signal interconnect equivalent load evaluation process ends. CFGCAP <k:0>The signal retains its corresponding value eq.

[0098] If they are not equal, return to step 4 and continue to configure CFGCAP <k:0>Until Rref and Rcon are equal, and store the control signal CFGCAP at this time <k:0>The corresponding value, the evaluation ends.

[0099] At this time, the control signal CFGCAP <k:0>The capacitance value of the corresponding adjustable capacitor 121 is regarded as the equivalent capacitance of the target signal interconnection line 111 .

[0100] Of course, in practical applications, a capacitor charging and discharging circuit can also be used to construct the first analog circuit 110 and the second analog circuit 120. In this case, the first analog circuit 110 is a first charging and discharging circuit; wherein the target signal interconnection line 111 is a charging and discharging capacitor of the first charging and discharging circuit; and the second analog circuit 120 is a second charging and discharging circuit; wherein the adjustable capacitor 121 is a capacitor of the charging and discharging circuit.

[0101] like Figure 8 FIG. 1 is a connection diagram of an evaluation circuit for an equivalent load of a signal interconnect line in a multi-chip package provided by an embodiment of the present invention, specifically:

[0102] The first charge-discharge circuit includes a first current source It, a first MOS transistor M1, a second MOS transistor M2 and a first capacitor Ctb; the second charge-discharge circuit includes a second current source Ir, a third MOS transistor M3, a fourth MOS transistor M4 and a second capacitor Crb; the first current source It is grounded via the first MOS transistor M1, the target signal interconnection line 111 and the first capacitor Ctb; the end of the target signal interconnection line 111 away from the first capacitor Ctb is grounded via the second MOS transistor M2; the second current source Ir is grounded via the third MOS transistor M3 and the adjustable capacitor; the fourth MOS transistor M4 and the second capacitor Crb are both connected in parallel with the adjustable capacitor; the gate of the first MOS transistor M1 is respectively connected to the gate of the second MOS transistor M2, the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4.

[0103] Specifically, the channel types of the first MOS tube M1 and the second MOS tube M2 are different; the channel types of the third MOS tube M3 and the fourth MOS tube M4 are different; the channel types of the first MOS tube M1 and the third MOS tube M3 are the same. That is, if the first MOS tube M1 and the third MOS tube M3 are PMOS tubes, the second MOS tube M2 and the fourth MOS tube M4 are NMOS tubes; if the first MOS tube M1 and the third MOS tube M3 are NMOS tubes, the second MOS tube M2 and the fourth MOS tube M4 are PMOS tubes.

[0104] Specifically, the capacitance values ​​of the first capacitor Ctb and the second capacitor Crb may be equal, and the current values ​​output by the first current source It and the second current source Ir may be equal, so as to facilitate evaluation.

[0105] The signal comparison module 130 includes a comparator 411 and a D flip-flop 412; the first input end of the comparator 411 is connected to the drain of the first MOS tube M1; the second input end of the comparator 411 is connected to the drain of the third MOS tube M3; the output end of the comparator 411 is connected to the D end of the D flip-flop 412; the gate of the first MOS tube M1 is connected to the CP end of the D flip-flop 412 through an inverter.

[0106] like Fig. 9 Shown Figure 8 The waveform diagram of the working process of the evaluation circuit of the equivalent load of the signal interconnection line in the multi-chip package shown in the figure is as follows:

[0107] 1.t0~t1: The enable signal EN is pulled high, and the evaluation circuit of the equivalent load of the signal interconnection line starts to work; configure CFGCAP <k:0>The corresponding value is 1; the evaluation control signal EV_CTRL is pulled high, and the reference current charges the equivalent load capacitance of the adjustable capacitor 121 and the target signal interconnection line respectively; after a period of time ΔT (determined by the EN_CTRL signal), the evaluation control signal EV_CTRL is pulled low, and the charging is completed. The comparator 411 compares the voltages vref and vcon on the adjustable capacitor 121 and the equivalent capacitance of the target signal interconnection line. If vref is higher than vcon, the result is latched by the D flip-flop 412 and the output EV_OUT is low;

[0108] 2. t1~t2: Continue to configure CFGCAP <k:0>The corresponding value is 2;

[0109] 3. t2~t7: Repeat the operation of t0~t1 stage until the output signal EV_OUT is pulled high, then the capacitance value of the adjustable capacitor and the equivalent load capacitance of the target signal interconnection line are equal or similar, and record CFGCAP <k:0>The value corresponding to the signal is eq;

[0110] 4.t8: The enable signal EN is pulled low, the evaluation circuit stops working, and the entire signal interconnect equivalent load evaluation process ends. CFGCAP <k:0>The signal retains its corresponding value eq.

[0111] The above embodiments have the following beneficial effects:

[0112] 1. For the packaged chip, through this embodiment, the capacitance value of the equivalent load capacitance of the signal interconnect line can be accurately obtained, rather than an approximate range;

[0113] 2. After the evaluation is completed through this embodiment, the configuration signal CFGCAP of the adjustable capacitor 121 is obtained <k:0>=eq can be used to optimize the drive capability of each chip output driver, thereby achieving a good compromise between signal integrity and power integrity.

[0114] Based on the same inventive concept as the method, an embodiment of the present invention also provides a method for obtaining the load of a signal interconnection line, such as Fig.10 The flowchart of the acquisition method is shown. The method is based on any of the evaluation circuits described above, and specifically includes:

[0115] Step 11, obtaining the target analog signal quantity of the target signal interconnection line 111 in the multi-chip package.

[0116] The target analog signal quantity includes a target frequency signal quantity, a target voltage signal quantity or a target current signal quantity.

[0117] Step 12: adjust the capacitance value of the adjustable capacitor 121 so that the difference between the current analog signal amount of the adjustable capacitor 121 and the target analog signal amount is smaller than a set threshold, and obtain the current capacitance value of the adjustable capacitor 121.

[0118] Step 13: Equivalent the current capacitance value to the load of the target signal interconnection line 111 .

[0119] After obtaining the signal interconnection load of the target signal interconnection line 111, the method further includes:

[0120] Step 21 : adjusting the driving capability of the chip corresponding to the target signal interconnection line 111 according to the load of the target signal interconnection line 111 .

[0121] Based on the same inventive concept as the method, an embodiment of the present invention further provides a device for acquiring the load of a signal interconnection line, such as Fig.11 The structure diagram of the acquisition device is shown. The device is based on any of the evaluation circuits described above, and specifically includes:

[0122] A first acquisition module 31 is used to acquire a target analog signal quantity of a target signal interconnect line 111 in a multi-chip package; wherein the target analog signal quantity includes a target frequency signal quantity, a target voltage signal quantity or a target current signal quantity;

[0123] The second acquisition module 32 is used to adjust the capacitance value of the adjustable capacitor 121 so that the difference between the current analog signal amount of the adjustable capacitor 121 and the target analog signal amount is less than a set threshold, and acquire the current capacitance value of the adjustable capacitor 121;

[0124] The third acquisition module 33 is used to convert the current capacitance value into the load of the target signal interconnection line 111 .

[0125] In a possible embodiment, the device further includes:

[0126] The driving capability adjustment module is used to adjust the driving capability of the chip corresponding to the target signal interconnection line 111 according to the signal interconnection load of the target signal interconnection line 111.

[0127] Based on the same inventive concept as the above embodiments, the present invention also provides a multi-chip packaged microsystem, comprising any evaluation circuit described above, wherein the evaluation circuit is arranged in any chip in the multi-chip packaged microsystem.

[0128] like Fig.12 A schematic diagram of the principle of a multi-chip packaged microsystem provided in an embodiment of the present invention, which includes two chips dieA and dieB for realizing different functions, wherein dieA is composed of a core circuit dieA_core and an input-output circuit IOA, and realizes functions such as control and calculation; dieB is composed of a core circuit dieB_core and an input-output circuit IOB, and realizes functions such as storage, digital / analog conversion, and data exchange); signal interconnection lines 31 to 3n realize the physical electrical connection of input and output signals IO_1 to IO_n.

[0129] Relative to Figure 2 , an evaluation circuit (Evaluator) of the equivalent load of the signal interconnection line is added (this embodiment is placed in the dieA chip, and can be flexibly set according to the application scenario requirements), the target signal interconnection line array 3ev_1~3ev_n to be tested, and the adjustable capacitor 121 is configured with the signal interconnection line 3ev_0; wherein, the target signal interconnection line array 3ev_1~3ev_n is set corresponding to the signal interconnection lines 31~3n. CFGCAP of the evaluation circuit of the equivalent load of the signal interconnection line <k:0>, EV_CTRL, and EN signals come from the core circuit dieA_core, and its output signal EV_OUT is connected to the outside of the chip. <k:0>Connected to the output driver of dieA and connected to the output driver of dieB through signal interconnect line 3ev_0.

[0130] Of course, one evaluation circuit as described above may be arranged between every two chips in the memory chip, and one evaluation circuit as described above may be arranged between each chip in the memory chip and the package base.

[0131] Based on the same inventive concept as in the aforementioned embodiment, an embodiment of the present invention further provides a computer system, comprising a multi-chip packaged microsystem, wherein the multi-chip packaged microsystem executes the steps of any of the above-described methods.

[0132] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0133] In the embodiment of the present invention, the actual load of the signal interconnection line is equivalent to an equivalent capacitance according to the actual size of the signal interconnection line. Since the equivalent capacitance is small, it is difficult to measure directly. In the present invention, a first analog circuit is constructed based on the target signal interconnection line to obtain the target analog signal amount of the target signal interconnection line, and a second analog circuit is constructed based on the adjustable capacitor to obtain the capacitance analog signal amount of the adjustable capacitor at different capacitance values. Then, a signal comparison module is used to compare the difference between the capacitance analog signal amount and the target analog signal amount. Finally, the capacitance value of the adjustable capacitor when the difference between the capacitance analog signal amount and the target analog signal amount is less than a set threshold can be equivalent to the load of the target signal interconnection line, thereby accurately evaluating the signal interconnection load in the multi-chip package.

[0134] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0135] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (modules, systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0136] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0137] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0138] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0139] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A circuit for evaluating equivalent load of signal interconnection lines in a multi-chip package, characterized in that: include: A first analog circuit, comprising a target signal interconnection line in a multi-chip package, for obtaining a target analog signal amount of the target signal interconnection line; The target analog signal comprises a target frequency signal, a target voltage signal or a target current signal; A second analog circuit includes an adjustable capacitor, and is used to obtain a capacitance analog signal quantity of the adjustable capacitor at different capacitance values; A signal comparison module, used for obtaining a comparison result between the target analog signal amount and the capacitance analog signal amount, so as to equate the capacitance value of the current adjustable capacitor to the load of the target signal interconnection line when the difference between the capacitance analog signal amount and the target analog signal amount is less than a set threshold; The first analog circuit is a first oscillator circuit; wherein the target signal interconnection line is a capacitor of the first oscillator circuit; The second analog circuit is a second oscillator circuit; wherein the adjustable capacitor is the capacitor of the second oscillator circuit; the first analog circuit is a first ring oscillator; and the second analog circuit is a second ring oscillator; The target signal interconnection line includes at least one group of signal interconnection line combinations; wherein each group of signal interconnection line combinations includes two signal interconnection lines connected in series; The first ring oscillator and the second ring oscillator are arranged in a common ring oscillator; The common ring oscillator comprises a delay module and a NAND gate logic circuit; the output end of the NAND gate logic circuit is connected to the input end of the delay module; the output end of the delay module is connected to the input end of the NAND gate logic circuit; The delay module includes at least one delay unit; wherein each group of signal interconnection line combinations corresponds to a delay unit; The delay unit includes an input buffer, a first selector, a second selector and an output buffer; The output end of the output buffer is connected to the input end of the first selector; the first output end of the first selector is connected to the first input end of the second selector through the signal interconnection line combination corresponding to the delay unit; the second output end of the first selector and the second input end of the second selector are both grounded through the adjustable capacitor; the output end of the second selector is connected to the input end of the output buffer; The common ring oscillator further includes: a first buffer and a frequency divider; The output end of the NAND gate logic circuit is connected to the input end of the frequency divider through the first buffer.

2. The evaluation circuit according to claim 1, characterized in that The target signal interconnection line comprises: The signal interconnection line between any two chips in the multi-chip package, and / or The signal interconnection line between any chip and the package base.

3. A circuit for evaluating equivalent load of signal interconnection lines in a multi-chip package, characterized in that: include: A first analog circuit, comprising a target signal interconnection line in a multi-chip package, for obtaining a target analog signal amount of the target signal interconnection line; The target analog signal comprises a target frequency signal, a target voltage signal or a target current signal; A second analog circuit includes an adjustable capacitor, and is used to obtain a capacitance analog signal quantity of the adjustable capacitor at different capacitance values; A signal comparison module, used for obtaining a comparison result between the target analog signal amount and the capacitance analog signal amount, so as to equate the capacitance value of the current adjustable capacitor to the load of the target signal interconnection line when the difference between the capacitance analog signal amount and the target analog signal amount is less than a set threshold; The first analog circuit is a first charge-discharge circuit; wherein the target signal interconnection line is a charge-discharge capacitor of the first charge-discharge circuit; The second analog circuit is a second charge-discharge circuit; wherein the adjustable capacitor is a charge-discharge capacitor of the second charge-discharge circuit; The first charge-discharge circuit includes a first current source, a first MOS transistor, a second MOS transistor and a first capacitor; the second charge-discharge circuit includes a second current source, a third MOS transistor, a fourth MOS transistor and a second capacitor; The first current source is grounded via the first MOS transistor, the target signal interconnection line and the first capacitor; the target signal interconnection line is also grounded via the second MOS transistor; The second current source is grounded via the third MOS tube and the adjustable capacitor; the fourth MOS tube and the second capacitor are both connected in parallel with the adjustable capacitor; The gate of the first MOS tube is respectively connected to the gate of the second MOS tube, the gate of the third MOS tube and the gate of the fourth MOS tube; The channel types of the first MOS tube and the second MOS tube are different; the channel types of the third MOS tube and the fourth MOS tube are different; the channel types of the first MOS tube and the third MOS tube are the same; The signal comparison module includes a comparator and a D flip-flop; The first input end of the comparator is connected to the drain of the first MOS tube; the second input end of the comparator is connected to the drain of the third MOS tube; the output end of the comparator is connected to the D end of the D flip-flop; the gate of the first MOS tube is connected to the CP end of the D flip-flop through an inverter.

4. The evaluation circuit according to claim 3, characterized in that The target signal interconnection line comprises: The signal interconnection line between any two chips in the multi-chip package, and / or The signal interconnection line between any chip and the package base.

5. A method for acquiring the load of a signal interconnection line based on the evaluation circuit according to any one of claims 1 to 4, characterized in that: The method comprises: Acquire a target analog signal quantity of a target signal interconnection line in a multi-chip package; wherein the target analog signal quantity includes a target frequency signal quantity, a target voltage signal quantity, or a target current signal quantity; Adjusting the capacitance value of the adjustable capacitor so that the difference between the current analog signal amount of the adjustable capacitor and the target analog signal amount is less than a set threshold, and obtaining the current capacitance value of the adjustable capacitor; The current capacitance value is equivalent to the load of the target signal interconnection line.

6. The method for obtaining the load of a signal interconnection line according to claim 5, characterized in that: After the current capacitance value is equivalent to the load of the target signal interconnection line, the method further includes: According to the load of the target signal interconnection line, the driving capability of the chip corresponding to the target signal interconnection line is adjusted.

7. A multi-chip packaged microsystem, characterized in that: include: The evaluation circuit according to any one of claims 1 to 4, wherein the evaluation circuit is arranged in any chip in a multi-chip packaged microsystem.

8. A computer system, characterized in that: A microsystem comprising a multi-chip package, wherein the multi-chip package microsystem executes the steps of the method according to claim 5 or 6.

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