Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a first region and a second region, the first region having a first metal structure, the second region having a second metal structure; forming a device layer on the surface of the first metal structure and the surface of the second metal structure; forming a first through hole in the device layer of the first region, and forming a second through hole in the device layer of the second region; using a selective metal growth process to form a first plug in the first through hole, and forming a second plug in the second through hole. The semiconductor structure and the method for forming the same can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Currently, in the semiconductor manufacturing process, it is a widely used process to form an opening in an interlayer dielectric layer by an etching process, and then deposit a conductive material in the opening to form an electrical connection structure for electrical connection between semiconductor devices.

[0003] However, the performance of existing semiconductor structures is still poor. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, the first region having a first metal structure, the second region having a second metal structure, the substrate surface exposing the top surface of the first metal structure and the top surface of the second metal structure; forming a device layer on the substrate surface, the first metal structure surface and the second metal structure surface, the device layer in the second region having a first device, the projection of the first device on the substrate surface partially or completely overlaps with the top surface of the second metal structure; forming a first through hole in the device layer in the first region, the first through hole exposing part or all of the surface of the first metal structure, forming a second through hole in the device layer in the second region, the second through hole penetrating the first device, and the second through hole exposing part or all of the surface of the second metal structure; using a selective metal growth process to form a first plug in the first through hole and a second plug in the second through hole.

[0006] Optionally, the material of the first metal structure is the same as the material of the second metal structure.

[0007] Optionally, the material of the first plug is the same as the material of the second plug.

[0008] Optionally, the material of the first metal structure, the material of the second metal structure, the material of the first plug, and the material of the second plug are all the same.

[0009] Optionally, a top surface of the first metal structure is flush with a top surface of the second metal structure.

[0010] Optionally, the first device includes a resistance layer.

[0011] Optionally, the material of the resistance layer includes titanium nitride.

[0012] Optionally, the first device further includes a stop layer, and the stop layer is located on the surface of the resistance layer.

[0013] Optionally, the device layer includes a first dielectric layer and a second dielectric layer, the second dielectric layer is located on a surface of the first dielectric layer, and the first device is located between the first dielectric layer and the second dielectric layer.

[0014] Optionally, the method for forming the device layer includes: forming the first dielectric layer on the surface of the substrate, the surface of the first metal structure and the surface of the second metal structure; forming a first device on the surface of the first dielectric layer in the second region; and forming a second dielectric layer on the surface of the first dielectric layer and the first device.

[0015] Optionally, the material of the first dielectric layer includes one of silicon oxide, silicon nitride, tantalum nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride; the material of the second dielectric layer includes one of silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

[0016] Optionally, the substrate includes a base and a third dielectric layer, the third dielectric layer is located on a surface of the base, and the first metal structure and the second metal structure are both located in the third dielectric layer.

[0017] Optionally, a semiconductor device is provided in the substrate of the first region, and the first metal structure is electrically interconnected with the semiconductor device.

[0018] Optionally, the method of forming the first plug and the second plug includes: using a selective growth process to form a plug material layer in the first through hole and the second through hole until the plug material layer is flush with a surface of the second dielectric layer or higher than a surface of the second dielectric layer.

[0019] Optionally, the method of forming the first plug and the second plug further includes: planarizing the plug material layer until it is flush with the surface of the second dielectric layer; and the process of planarizing the plug material layer includes: a chemical mechanical planarization process.

[0020] Optionally, the material of the first metal structure includes one of tungsten and cobalt.

[0021] Optionally, the material of the second metal structure includes one of tungsten and cobalt.

[0022] Optionally, the material of the first plug includes one of tungsten and cobalt.

[0023] Optionally, a material of the second plug includes one of tungsten and cobalt.

[0024] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region, the first region having a first metal structure, the second region having a second metal structure, the substrate surface exposing the top surface of the first metal structure and the top surface of the second metal structure; a device layer located on the substrate surface, the first metal structure surface and the second metal structure surface, the device layer in the second region having a first device, the projection of the first device on the substrate surface partially or completely overlaps with the top surface of the second metal structure; a first through hole located in the device layer in the first region, the first through hole exposing part or all of the surface of the first metal structure, a second through hole located in the device layer in the second region, the second through hole passing through the first device, and the second through hole exposing part or all of the surface of the second metal structure; a first plug formed by a selective metal growth process and located in the first through hole, and a second plug formed by a selective metal growth process and located in the second through hole.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, on the one hand, since the first through hole and the second through hole are formed in the device layer, the first plug is formed in the first through hole, and the second plug is formed in the second through hole, the height difference between the first plug and the second plug formed in the end is reduced. On the other hand, since the first plug and the second plug are formed by a selective metal growth process, the material forming the first plug grows from the bottom of the first through hole, and the material forming the second plug grows from the bottom of the second through hole. Therefore, the height difference between the material of the first plug and the material of the second plug during growth is reduced, which is beneficial to the subsequent planarization process, thereby reducing the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer. At the same time, the material of the first plug and the material of the second plug are difficult to grow on the surface of the device layer, thereby reducing the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer. Since the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer are reduced, and the second through hole passes through the first device, while forming the second plug electrically interconnected with the first device, the influence of the residues on the performance of the semiconductor structure is reduced, thereby improving the performance of the semiconductor structure.

[0027] Furthermore, since the material of the first metal structure is the same as the material of the second metal structure, the difference in material growth rate between the material of the first plug and the material of the second plug is reduced, thereby further reducing the height difference between the material of the first plug and the material of the second plug during growth, which is beneficial in reducing the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer, thereby improving the performance of the semiconductor structure.

[0028] Furthermore, since the material of the first plug is the same as the material of the second plug, the difference in material growth rate between the material of the first plug and the material of the second plug is reduced, thereby further reducing the height difference between the material of the first plug and the material of the second plug during growth, which is beneficial in reducing the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer, thereby improving the performance of the semiconductor structure.

[0029] Furthermore, since a stop layer is formed on the surface of the resistor layer, the oxidation of the resistor layer can be improved, and the resistor layer can be protected during subsequent etching processes in the semiconductor formation process, thereby reducing the impact of subsequent etching processes on the resistor layer and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 4 The invention is a schematic cross-sectional structure diagram of a formation process of a semiconductor structure;

[0031] Figures 5 to 10 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the performance of semiconductor structures is still relatively poor.

[0033] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 5 It is a schematic cross-sectional structure diagram of the formation process of a semiconductor structure.

[0034] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes an A region and a B region, and the substrate 100 has an electrical device therein; forming a first dielectric layer 110 on the surface of the substrate 100; forming a resistor 120 on a portion of the surface of the first dielectric layer 110 in the A region; and forming a second dielectric layer 130 on the surface of the resistor 120 and the exposed surface of the first dielectric layer 110.

[0035] Please refer to Figure 2A first opening 140 is formed in the first dielectric layer 110 and the second dielectric layer 130 in the A region, and the bottom of the first opening 140 exposes a portion of the surface of the electrical device; a second opening 150 is formed in the second dielectric layer 130 in the B region, and the second opening 150 exposes the surface of the resistor 120.

[0036] Please refer to Figure 3 , an initial plug material layer 160 is deposited in the first opening 140 , in the second opening 150 , and on the surface of the second dielectric layer 130 .

[0037] Please refer to Figure 4 , the initial plug material layer 160 is planarized until the top surface of the second dielectric layer 130 is exposed to form a first plug 161 and a second plug 162 .

[0038] In the semiconductor structure formed by the above forming method, a first plug 161 electrically interconnected with the electrical device and a second plug 162 electrically interconnected with the resistor 120 are formed.

[0039] However, on one hand, since the bottom surface of the first opening 140 is located on the surface of the first dielectric layer 110, and the bottom surface of the second opening 150 is located on the surface of the resistor 120, that is, the depth of the first opening 140 is greater than the depth of the second opening 150. Therefore, after the deposited plug material layer 160 forms the initial plug material layer 160, the surface of the initial plug material layer 160 above the resistor 120 will be higher than the surface of the remaining portion, resulting in that when the initial plug material layer 160 is planarized to form the first plug 161 and the second plug 162, it is not only not conducive to achieving a relatively flat surface of the semiconductor structure, but also the residue 163 of the initial plug material layer 160 is easily formed on the surface of the second dielectric layer 130, thereby affecting the performance of the formed semiconductor structure and making the performance of the semiconductor structure worse.

[0040] On the other hand, since the initial plug material layer 160 is formed by a deposition process, the first plug 161 and the second plug 162 are prone to defects such as voids, thereby increasing the contact resistance when the first plug 161 is electrically interconnected with the electrical device, and the contact resistance when the second plug 162 is electrically interconnected with the resistor 120, thereby deteriorating the performance of the semiconductor structure.

[0041] To solve the technical problem, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which improves the performance of the semiconductor structure by reducing the height difference between the first plug and the second plug and simultaneously forming the first plug and the second plug using a selective metal growth process.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 5 to 10 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0044] Please refer to Figure 5 , providing a substrate 100, the substrate 100 includes a first region I and a second region II, the first region I has a first metal structure 101, the second region II has a second metal structure 102, and the surface of the substrate 100 exposes the top surface of the first metal structure 101 and the top surface of the second metal structure 102.

[0045] The substrate 100 is made of semiconductor material.

[0046] In this embodiment, the material of the substrate 100 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0047] In this embodiment, the substrate 100 includes a base (not shown) and a third dielectric layer (not shown), and the third dielectric layer is located on the surface of the substrate. The substrate of the first region I has a semiconductor device in it, and the semiconductor device includes one or all of a PMOS transistor and an NMOS transistor. The substrate 100 also includes an interconnection structure electrically connected to the semiconductor device, and an insulating layer surrounding the semiconductor device and the interconnection structure.

[0048] In this embodiment, the surface of the first metal structure 101 has a first barrier layer (not shown), and the surface of the second metal structure 102 has a second barrier layer (not shown). Specifically, the surface of the substrate 100 exposes the first barrier layer surface and the second barrier layer surface.

[0049] In this embodiment, the first barrier layer and the second barrier layer are made of the same material.

[0050] In this embodiment, the first metal structure 101 and the second metal structure 102 are both located in the third dielectric layer.

[0051] The first metal structure 101 is used for electrically interconnecting with the semiconductor device in the first region I on the one hand, and is used as a metal substrate for growing the material of the first plug when the first plug is subsequently formed by a selective metal growth process on the other hand.

[0052] The second metal structure 102 is used as a metal base for growing a material of the second plug when the second plug is subsequently formed by a selective metal growth process.

[0053] In this embodiment, the first metal structure 101 and the second metal structure 102 are both located in the insulating layer.

[0054] In this embodiment, the material of the insulating layer includes silicon nitride.

[0055] In other embodiments, the material of the insulating layer includes silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0056] In this embodiment, the material of the first metal structure 101 is the same as that of the second metal structure 102 .

[0057] Since the material of the first metal structure 101 is the same as the material of the second metal structure 102, when the first plug and the second plug are subsequently formed by a selective metal growth process, the difference in growth rate between the material of the first plug and the material of the second plug is reduced, thereby further reducing the height difference between the material of the first plug and the material of the second plug during growth, which is beneficial to reducing the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer, thereby improving the performance of the semiconductor structure.

[0058] In another embodiment, the material of the first metal structure 101 is different from the material of the second metal structure 102 .

[0059] In this embodiment, the material of the first metal structure 101 includes one of tungsten and cobalt.

[0060] In this embodiment, the material of the second metal structure 102 includes tungsten or cobalt.

[0061] In this embodiment, the top surface of the first metal structure 101 is flush with the top surface of the second metal structure 102 .

[0062] Since the top surface of the first metal structure 101 is flush with the top surface of the second metal structure 102, when the first plug and the second plug are subsequently formed, the material of the first plug and the material of the second plug start to grow from a plane at the same height, which is beneficial to reducing the height difference between the material of the first plug and the material of the second plug during growth, thereby helping to reduce the residues formed by the material of the first plug and the material of the second plug on the surface of the device layer, thereby improving the performance of the semiconductor structure.

[0063] In another embodiment, the top surface of the first metal structure and the top surface of the second metal structure are not flush.

[0064] In this embodiment, a device layer is subsequently formed on the surface of the substrate 100, the surface of the first metal structure 101, and the surface of the second metal structure 102. The device layer of the second region II has a first device, and the projection of the first device on the surface of the substrate partially or completely overlaps with the top surface of the second metal structure 102. The device layer also includes a first dielectric layer and a second dielectric layer, the second dielectric layer is located on the surface of the first dielectric layer, and the first device is located between the first dielectric layer and the second dielectric layer. For the specific process of forming the device layer, please refer to Figures 6 to 8 .

[0065] Please refer to Figure 6 A first dielectric layer 110 is formed on the surface of the substrate 100 , the surface of the first metal structure 101 , and the surface of the second metal structure 102 .

[0066] The first dielectric layer 110 is used, on the one hand, to protect the substrate 100, the first metal structure 101 and the second metal structure 102, thereby reducing damage to the substrate 100, the first metal structure 101 and the second metal structure 102 caused by the process in the subsequent process; on the other hand, it is used to insulate the first device formed subsequently from the substrate 100.

[0067] The process of forming the first dielectric layer 110 includes an epitaxial process, a spin coating process or a deposition process.

[0068] In this embodiment, the process of forming the first dielectric layer 110 includes a chemical vapor deposition process.

[0069] The material of the first dielectric layer 110 includes one of silicon oxide, silicon nitride, tantalum nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0070] In this embodiment, the material of the first dielectric layer 110 is silicon oxide.

[0071] Please refer to Figure 7 , a first device 113 is formed on the surface of the first dielectric layer 110 in the second region II.

[0072] In this embodiment, the first device 113 includes a resistance layer 111 and a stop layer 112 , and the stop layer 112 is located on the surface of the resistance layer 111 .

[0073] Since the stop layer 112 is formed on the surface of the resistance layer 111, the oxidation condition of the resistance layer 111 can be improved, and the resistance layer 111 can be protected during the subsequent etching process in the semiconductor formation process, so as to reduce the impact of the subsequent etching process on the resistance layer 111 and improve the performance of the semiconductor structure.

[0074] In this embodiment, the method for forming the first device 113 includes: forming a resistor layer material layer (not shown) on the surface of the first dielectric layer 110; forming a stop layer material layer (not shown) on the surface of the resistor layer material layer; forming a first patterned layer (not shown) on a portion of the surface of the stop layer material layer in the second region II; and etching the stop layer material layer and the resistor layer material layer using the first patterned layer as a mask until the surface of the first dielectric layer 110 is exposed.

[0075] The projection of the first patterned layer on the surface of the substrate 100 partially or completely overlaps with the top surface structure of the second metal structure 102 , so that the projection of the first device 113 on the surface of the substrate 100 partially or completely overlaps with the top surface of the second metal structure 102 .

[0076] The projection of the first device 113 on the surface of the substrate 100 partially or completely overlaps with the top surface of the second metal structure 102, which is conducive to the subsequent formation of a second through hole passing through the first device, and then forming a second plug electrically interconnected with the first device in the second through hole using a selective growth process.

[0077] The process of forming the resistance layer material layer includes a deposition process or a metal electroplating process.

[0078] The process of forming the stop layer material layer includes a deposition process or an epitaxial process.

[0079] The process of etching the stop layer material layer and the resistance layer material layer includes a dry etching process or a wet etching process.

[0080] In this embodiment, the material of the resistance layer 111 includes titanium nitride.

[0081] In this embodiment, the material of the stop layer 112 includes silicon nitride.

[0082] Please refer to Figure 8 , a second dielectric layer 120 is formed on the surface of the first dielectric layer 110 and the first device 113 .

[0083] Thus, a device layer (not shown) is formed. The device layer includes a first dielectric layer 110 and a second dielectric layer 120 , and a first device 113 located between the first dielectric layer 110 and the second dielectric layer 120 .

[0084] The second dielectric layer 120 is used to protect the first device 113 , so as to reduce the damage to the first device 113 caused by the process in the subsequent process.

[0085] The process of forming the second dielectric layer 120 includes an epitaxial process, a spin coating process or a deposition process.

[0086] In this embodiment, the process of forming the second dielectric layer 120 includes a chemical vapor deposition process.

[0087] The material of the second dielectric layer 120 includes one of silicon oxide, silicon nitride, tantalum nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide, or silicon nitride oxide.

[0088] In this embodiment, the material of the second dielectric layer 120 is silicon oxide.

[0089] Please refer to Fig. 9 A first through hole 121 is formed in the device layer of the first region I, and the first through hole 121 exposes part or all of the surface of the first metal structure 101; a second through hole 122 is formed in the device layer of the second region II, and the second through hole 122 passes through the first device 113, and the second through hole 122 exposes part or all of the surface of the second metal structure 102.

[0090] The method for forming the first through hole 121 and the second through hole 122 includes: forming a second patterned layer (not shown) on the surface of the second dielectric layer 120, the second patterned layer exposing a portion of the surface of the second dielectric layer 120; using the second patterned layer as a mask, etching the second dielectric layer 120, the first dielectric layer 110 and the first device 113 until the top surface of the first metal structure 101 and the top surface of the second metal structure 102 are exposed.

[0091] In this embodiment, the method for etching the second dielectric layer 120, the first dielectric layer 110 and the first device 113 until the top surface of the first metal structure 101 and the top surface of the second metal structure 102 are exposed includes: using the second patterned layer as a mask, performing a first etching process, etching the second dielectric layer 120 and the first dielectric layer 110 in the first area I, until the surface of the first barrier layer is exposed, and at the same time, etching the second dielectric layer 120 in the second area II, until the surface of the first device 113, that is, the surface of the stop layer 112, is exposed; after performing the first etching process, etching the stop layer 112; 12, performing a second etching process until the surface of the resistance layer 111 is exposed; after performing the second etching process, performing a third etching process on the resistance layer 111 until the surface of the first dielectric layer 110 is exposed; after performing the third etching process, performing a first etching process on the first dielectric layer 110 of the first area I until the surface of the second barrier layer is exposed; after performing the first etching process to etch the first dielectric layer 110 of the first area I, performing a fourth etching process on the first barrier layer and the second barrier layer until the top surface of the first metal structure 101 and the top surface of the second metal structure 102 are exposed.

[0092] It should be noted that, since the etching rate of the first barrier layer by the first etching process is lower than the etching rate of the first dielectric layer 110 and the second dielectric layer 120, the etching rate of the first barrier layer by the second etching process is lower than the etching rate of the stop layer 112, and the etching rate of the first barrier layer by the third etching process is lower than the etching rate of the resistance layer 111, when etching the stop layer 112, the resistance layer 111 and the first dielectric layer 110 of the second region II, the first barrier layer can block the damage to the surface of the first metal structure 101 by the first etching process, the second etching process and the third etching process.

[0093] In this embodiment, the process of forming the first through hole 121 and the second through hole 122 includes a dry etching process or a wet etching process.

[0094] Please refer to Fig.10 , a first plug 130 is formed in the first through hole 121 and a second plug 140 is formed in the second through hole 122 by a selective metal growth process.

[0095] On the one hand, since the first through hole 121 and the second through hole 122 are formed in the device layer, the first plug 130 is formed in the first through hole 121, and the second plug 140 is formed in the second through hole 122, the height difference between the first plug 130 and the second plug 140 formed finally is reduced; on the other hand, since the first plug 130 and the second plug 140 are formed by adopting a selective metal growth process, the material forming the first plug 130 starts to grow from the bottom of the first through hole 121, and the material forming the second plug 140 starts to grow from the bottom of the second through hole 122, therefore, the height difference between the material of the first plug 130 and the material of the second plug 140 during growth becomes smaller, which is beneficial to the subsequent planarization process, thereby reducing the residues formed by the material of the first plug 130 and the material of the second plug 140 on the surface of the device layer; at the same time, the material of the first plug 130 and the material of the second plug 140 are difficult to grow on the surface of the device layer, thereby reducing the residues formed by the material of the first plug 130 and the material of the second plug 140 on the surface of the device layer. Since the residues formed by the materials of the first plug 130 and the second plug 140 on the surface of the device layer are reduced, and the second through hole 122 passes through the first device 113, the second plug 140 electrically interconnected with the first device 113 is formed, while the influence of the residues on the performance of the semiconductor structure is reduced, thereby improving the performance of the semiconductor structure.

[0096] Moreover, since the first plug 130 and the second plug 140 are formed by a selective metal growth process, defects such as voids in the first plug 130 and the second plug 140 can be reduced, which on the one hand improves the quality of the first plug 130 and the second plug 140, and on the other hand reduces the contact resistance of the first plug 130 and the second plug 140, thereby improving the performance of the semiconductor structure.

[0097] In this embodiment, the method of forming the first plug 130 and the second plug 140 includes: using a selective growth process to form a plug material layer (not shown) in the first through hole 121 and the second through hole 122 until the plug material layer is flush with the surface of the second dielectric layer 120 or higher than the surface of the second dielectric layer 120.

[0098] The plug material layer is used to form the first plug 130 and the second plug 140 .

[0099] In this embodiment, the surface of the plug material layer is higher than the surface of the second dielectric layer 120 .

[0100] In this embodiment, after the plug material layer is formed, the plug material layer is planarized until it is flush with the surface of the second dielectric layer 120 .

[0101] The process of planarizing the plug material layer includes: a chemical mechanical planarization process.

[0102] In this embodiment, the first plug 130 , the second plug 140 , the first metal structure 101 , and the second metal structure 102 are made of the same material.

[0103] Since the first plug 130, the second plug 140, the first metal structure 101 and the second metal structure 102 are made of the same material, the material growth rates of the first plug 130 and the second plug 140 are the same, thereby greatly reducing the height difference between the material of the first plug 130 and the material of the second plug 140 during growth, which is greatly beneficial to reducing the residues formed by the material of the first plug 130 and the material of the second plug 140 on the surface of the device layer, thereby improving the performance of the semiconductor structure.

[0104] In another embodiment, the first plug 130 and the second plug 140 are made of the same material, and the material of the first plug 130 and the second plug 140 is different from the material of the first metal structure 101 and the second metal structure 102 .

[0105] Since the material of the first plug 130 and the material of the second plug 140 are the same, the difference in material growth rate between the material of the first plug 130 and the material of the second plug 140 is reduced, thereby further reducing the height difference between the material of the first plug 130 and the material of the second plug 140 during growth, which is beneficial to reducing the residues formed by the material of the first plug 130 and the material of the second plug 140 on the surface of the device layer, thereby improving the performance of the semiconductor structure.

[0106] In other embodiments, the first plug and the second plug are made of different materials.

[0107] In this embodiment, the material of the first plug 130 includes tungsten or cobalt.

[0108] In this embodiment, the material of the second plug 140 includes tungsten or cobalt.

[0109] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please refer to Fig.10, comprising: a substrate 100, the substrate 100 comprising a first region I and a second region II, the first region I having a first metal structure 101, the second region II having a second metal structure 102, the surface of the substrate 100 exposing the top surface of the first metal structure 101 and the top surface of the second metal structure 102; a device layer located on the surface of the substrate 100, the surface of the first metal structure 101 and the surface of the second metal structure 102, the device layer in the second region II having a first device 113, the projection of the first device 113 on the surface of the substrate 100 and the projection of the second metal structure 102 on the surface of the substrate 100 The top surfaces partially or completely overlap; a first through hole 121 located in the device layer of the first zone I, the first through hole 121 exposing part or all of the surface of the first metal structure 101, a second through hole 122 located in the device layer of the second zone II, the second through hole 122 passes through the first device 113, and the second through hole 122 exposes part or all of the surface of the second metal structure 102; a first plug 130 formed by a selective metal growth process located in the first through hole 121, and a second plug 140 formed by a selective metal growth process located in the second through hole 122.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising a first region and a second region, the first region having a first metal structure, the second region having a second metal structure, the surface of the substrate exposing a top surface of the first metal structure and a top surface of the second metal structure; forming a device layer on the surface of the substrate, the surface of the first metal structure and the surface of the second metal structure, wherein the device layer in the second region has a first device, and a projection of the first device on the surface of the substrate partially or completely overlaps with a top surface of the second metal structure; Forming a first through hole in the device layer of the first region, wherein the first through hole exposes part or all of the surface of the first metal structure, and forming a second through hole in the device layer of the second region, wherein the second through hole penetrates the first device, and the second through hole exposes part or all of the surface of the second metal structure; A first plug is formed in the first through hole and a second plug is formed in the second through hole by using a selective metal growth process.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the first metal structure is the same as that of the second metal structure.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The material of the first plug is the same as that of the second plug.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the first metal structure, the material of the second metal structure, the material of the first plug, and the material of the second plug are all the same.

5. The method for forming a semiconductor structure according to claim 1, It is characterized in that A top surface of the first metal structure is flush with a top surface of the second metal structure.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that The first device includes a resistive layer.

7. The method for forming a semiconductor structure according to claim 6, It is characterized in that The material of the resistance layer includes titanium nitride.

8. The method for forming a semiconductor structure according to claim 6, It is characterized in that The first device further includes a stop layer, and the stop layer is located on a surface of the resistance layer.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The device layer includes a first dielectric layer and a second dielectric layer, the second dielectric layer is located on the surface of the first dielectric layer, and the first device is located between the first dielectric layer and the second dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The method for forming the device layer includes: forming the first dielectric layer on the surface of the substrate, the surface of the first metal structure and the surface of the second metal structure; forming a first device on the surface of the first dielectric layer in the second region; and forming a second dielectric layer on the surface of the first dielectric layer and the first device.

11. The method for forming a semiconductor structure according to claim 9, It is characterized in that The material of the first dielectric layer includes one of silicon oxide, silicon nitride, tantalum nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride; the material of the second dielectric layer includes one of silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride or silicon oxynitride.

12. The method for forming a semiconductor structure according to claim 1, It is characterized in that The substrate comprises a base and a third dielectric layer, the third dielectric layer is located on the surface of the base, and the first metal structure and the second metal structure are both located in the third dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that A semiconductor device is disposed in the substrate of the first region, and the first metal structure is electrically interconnected with the semiconductor device.

14. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method for forming the first plug and the second plug includes: using a selective growth process to form a plug material layer in the first through hole and the second through hole until the plug material layer is flush with the surface of the second dielectric layer or higher than the surface of the second dielectric layer.

15. The method for forming a semiconductor structure according to claim 14, It is characterized in that The method for forming the first plug and the second plug further includes: planarizing the plug material layer until it is flush with the surface of the second dielectric layer; and the process for planarizing the plug material layer includes: a chemical mechanical planarization process.

16. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the first metal structure includes one of tungsten and cobalt.

17. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the second metal structure includes one of tungsten and cobalt.

18. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the first plug includes one of tungsten and cobalt.

19. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the second plug includes one of tungsten and cobalt.

20. A semiconductor structure, It is characterized in that include: A substrate, the substrate comprising a first region and a second region, the first region having a first metal structure, the second region having a second metal structure, the surface of the substrate exposing a top surface of the first metal structure and a top surface of the second metal structure; A device layer located on the surface of the substrate, the surface of the first metal structure and the surface of the second metal structure, wherein the device layer in the second region has a first device, and a projection of the first device on the surface of the substrate partially or completely overlaps with a top surface of the second metal structure; a first through hole located in the device layer of the first region, the first through hole exposing a portion or the entire surface of the first metal structure, and a second through hole located in the device layer of the second region, the second through hole penetrating the first device, and the second through hole exposing a portion or the entire surface of the second metal structure; A first plug located in the first through hole is formed by a selective metal growth process, and a second plug located in the second through hole is formed by a selective metal growth process.

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