An autonomous and controllable face recognition device

Abstract

The present invention relates to an autonomous and controllable face recognition device, including a main control module, connected with an image acquisition module, a storage module, a display module and a control terminal; the main control module at least includes a processor, a drive circuit, a self-starting circuit, a power supply circuit and a memory circuit; the drive circuit includes a DVO circuit and a PCI E circuit. The device of the present invention can flexibly adapt to on-site needs by plugging in and out various image modules, acquisition devices, display devices and actuators, etc. The entire design forms an interactive service with the control terminal to meet different business needs and its functional data processing equipment, and has good scalability.

Description

Technical Field

[0001] The present invention relates to the field of face recognition, and in particular to an autonomous and controllable face recognition device. Background Art

[0002] Face recognition technology is based on human facial features. It detects the input face image or video stream first to determine whether there is a face. If there is a face, it further gives the location, size and location information of each face's main facial organs. Based on this information, it further extracts the identity features contained in each face and compares it with known faces to identify the identity of each face. In a broad sense, face recognition actually includes a series of related technologies for building a face recognition system, including face image acquisition, face positioning, face recognition preprocessing, identity confirmation and identity search, etc.; while in a narrow sense, face recognition refers specifically to the technology or system for identity confirmation or identity search through the face.

[0003] Existing equipment is generally not scalable, cannot flexibly adapt to on-site needs, and cannot adapt to different business needs and their functional data. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide an autonomous and controllable face recognition device that overcomes the above problems or at least partially solves the above problems.

[0005] According to one aspect of the present invention, an autonomous and controllable face recognition device is provided, including a main control module, which is connected to an image acquisition module, a storage module, a display module and a control terminal; the main control module includes at least a processor, a drive circuit, a self-starting circuit, a power supply circuit and a memory circuit; the drive circuit includes a DVO circuit and a PCIE circuit.

[0006] In a possible implementation, the main control module also includes a DEBUG debugging circuit, a clock circuit and a timing circuit; the processor is a Loongson2K1000 processor or a Loongson 3A3000.

[0007] In a possible implementation, the self-starting circuit includes an enhanced MOS transistor Q23, an OR gate U62, a Schottky diode D69, a resistor R1084, a resistor R1085, a resistor R1086, a resistor R1087, a capacitor C1103, and a capacitor C1104, wherein the gate terminal of the enhanced MOS transistor Q23 is connected to one end of the resistor R1085 and to one end of the capacitor C1103, the source terminal of the enhanced MOS transistor Q23 is grounded, the drain terminal of the enhanced MOS transistor Q23 is connected to one end of the resistor R1084 and to the first input terminal of the OR gate U62, and the resistor R The other end of 1085 is connected to a 3.3V voltage, the other end of capacitor C1103 is grounded, the other end of resistor R1084 is connected to a 3.3V voltage, the anode end of Schottky diode D69 is connected to one end of resistor R1087 and to the second input end of OR gate U62, the other end of resistor R1087 is connected to a 3.3V voltage, the cathode end of Schottky diode D69 is connected to one end of point-in R1086 and to one end of capacitor C1104, the other end of resistor R1086 is connected to a 3.3V voltage, the other end of capacitor C1104 is grounded, and the output end of OR gate U62 is connected to the processor.

[0008] In one example, a terminal J21 is connected between the output end of the OR gate U62 and the processor, one end of the terminal J21 is connected to the processor and is also connected to one end of a resistor R1088, the other end of the resistor R1088 is connected to one end of a capacitor C1105 and to one end of a touch switch J22, the other end of the capacitor C1105 is grounded, and the other end of the touch switch J22 is grounded.

[0009] In a possible implementation, the image acquisition module uses a 115-degree wide-angle UVC camera in hardware to perform face acquisition, sets the face acquisition size to 680X600, and uses a PCI-E interface gold-plated board D720201 expansion board for connection.

[0010] In a possible implementation, the display module uses the QT framework to design the human-computer interaction interface, and the hardware uses a Feiling 7-inch FPC interface 1024×600 resolution high-end capacitive touch screen; the screen touch part uses the IIC interface, and the touch chip uses GT911.

[0011] In a possible implementation, the display module is connected to the DVO interface of the main control board via a 54P FPC flexible cable.

[0012] In a possible implementation, the storage module uses a Kingston 16GB solid-state hard drive and is connected to the main control module via an external M2 interface.

[0013] In one possible implementation, the memory portion of the storage module uses four K4B4G1646B-HCK0 memory particles, and the clock signal line of each 4GB onboard particle is connected to the processor, and is connected to the DDR3_1V5 power supply in parallel to the C1114 capacitor through R1109 and R1110.

[0014] In a possible implementation, the autonomous and controllable face recognition device is provided with a 5mm inner shell for fixing the main control board.

[0015] The device of the present invention can flexibly adapt to on-site needs by plugging and unplugging various image modules, acquisition devices, display devices and actuators, etc. The entire design forms an interactive service with the control end to meet different business needs and its functional data processing equipment, and has good scalability.

[0016] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1 A diagram showing the internal structure of an autonomous and controllable face recognition device provided by an embodiment of the present invention;

[0019] Figure 2 A basic flow chart of a driver program for an autonomous and controllable face recognition device provided by an embodiment of the present invention;

[0020] Figure 3 A main control module power supply circuit 1 provided in an embodiment of the present invention;

[0021] Figure 4 A second main control module power supply circuit provided by an embodiment of the present invention;

[0022] Figure 5 A main control module power self-starting circuit provided by an embodiment of the present invention;

[0023] Figure 6 A PCIE circuit is a main control module driving circuit provided by an embodiment of the present invention;

[0024] Figure 7A main control module driving circuit DVO circuit provided by an embodiment of the present invention;

[0025] Figure 8 A memory circuit 1 provided in an embodiment of the present invention;

[0026] Fig. 9 A memory circuit 2 provided in an embodiment of the present invention;

[0027] Fig.10 A timing circuit provided by an embodiment of the present invention;

[0028] Fig.11 A schematic diagram of a human-computer interaction interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] The terms "comprises" and "having" and any variations thereof in the description embodiments, claims and drawings of the present invention are intended to cover non-exclusive inclusions, for example, including a series of steps or units.

[0031] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0032] like Figure 1 , an embodiment of the present invention provides an autonomous and controllable face recognition device, comprising:

[0033] The main control module is connected with the image acquisition module, the storage module, the display module and the control terminal.

[0034] The main control module at least includes a processor, a drive circuit, a self-starting circuit, a power circuit and a memory circuit;

[0035] The driving circuit includes a DVO circuit and a PCIE circuit.

[0036] The main control module also includes a DEBUG circuit, a clock circuit and a timing circuit.

[0037] The processor is replaced by Loongson2K1000 processor or Loongson 3A3000.

[0038] The whole module system block diagram is as follows: Figure 1As shown in the figure, the system consists of a main control module, an image acquisition module, a storage module, a display module, and a control terminal. In the image acquisition module, the UVC protocol camera is first connected to the D720201 expansion board, and then connected to the main control module through the PCIE interface to achieve 140M / s bandwidth. The display module is mainly composed of a human-computer interaction interface composed of a Feiling 7-inch capacitive screen, which is connected to the control module through a DVO interface. The storage module is connected to a Kingston 16GB solid-state hard drive with an external M2 interface. The power supply circuit is a 12V, 3A input, which is then processed by the timing circuit and the LDO power supply circuit to supply the corresponding power supply voltage and current to each unit.

[0039] In summary, this design is a hardware that can flexibly adapt to on-site needs by plugging and unplugging various image modules, acquisition devices, display devices, and actuators. The entire design forms an interactive service with the control end to meet different business needs and their functional data processing devices.

[0040] The basic process of the driver is as follows Figure 2 As shown, the system is powered on, the timing circuit is tested, the self-starting circuit capacitor is charged and started, the system self-checks before startup, the file system is started by the bootloader, the underlying drivers such as video, network, and partition are started, the environment variable configuration is tested, the autonomous and controllable face detection service is started automatically, and the system enters the working mode.

[0041] This design consists of a camera, a touch-screen LCD, a shell, and a main control board. It uses a 115-degree non-deformation camera to obtain a color face image of the target. After the face is detected, the face position is framed and displayed on the LCD touch screen, and the facial feature information encoded by the processor is retained locally. During the recognition process, the face image is extracted through the camera, and its facial feature points are extracted through the main control board. All stored facial feature information codes are traversed for comparison and face recognition. Finally, the successfully recognized face image information is deleted to protect privacy and security.

[0042] Power circuit design:

[0043] (1) Power circuit design

[0044] The power module is responsible for the power supply of the entire system. Since each module has a different operating voltage, different voltage outputs need to be designed, such as Figure 3 The ADP5052 integrated universal LDO regulator is used to synchronize its switching frequency to an external clock and set the power-on timing to control power consumption and improve PCB space utilization. Its EN4 terminal is connected to the ACPI_S4N terminal of the processor to control the enable regulation. When the EN4 pin voltage is greater than 0.8V, the regulator is enabled. When the EN4 pin voltage is lower than 0.725V, the regulator is disabled.

[0045] Figure 3 In the embodiment, pin 2 of U60 is connected to 12V voltage, pin 2 is also grounded through two parallel capacitors C1054 and C1055, pin 7 is connected to 5V voltage, pin 8 is grounded through capacitor C1057, pin 4 is grounded, pin 1 is connected to one end of resistor R1053, the other end of resistor R1053 is connected to one end of capacitor C1053, pin 3 is connected to the other end of capacitor C1053 and one end of inductor L15 and one end of Schottky diode D67, the other end of Schottky diode D67 is grounded, inductor L The other end of 15 is connected to one end of resistor R1055, and the end of inductor L15 connected to resistor R1055 outputs a 3.3V voltage, namely node P3V3. Node P3V3 is also grounded through 6 parallel capacitors C91058, C1059, C1060, C1061, C1062, and C1063. Pin 5 is connected to the other end of resistor R1055 and to one end of resistor R1056. The other end of resistor R1056 is grounded. Pin 6 is grounded through capacitor C1056 and resistor R1054, and pin 9 is grounded.

[0046] like Figure 4 The ACPI power circuit enables the pull-up power-on timing circuit design. The 12V3A power input is regulated by the ADP5052 peripheral circuit. First, the RTC clock circuit is powered on. During this period, a 2s delay is required to ensure that the RTC crystal oscillator starts. The VDD in PEST_1V1, VDD, and PLL needs to be powered separately and respectively use the RT9025 voltage regulator. By connecting a current mode buck regulator, a continuous output current of 3A is achieved, providing a fast transient response and a stable loop.

[0047] ADP5052 integrates a universal LDO regulator U61. Pin 44 of U61 is grounded through capacitor C1064, pin 42 is grounded through capacitor C1065, pin 39 is grounded through resistor R1062 and capacitor C1066, pin 37 is connected to 1.5V voltage through resistor R1063, pin 38 is connected to VREG through resistor R1064, pin 38 is also grounded through resistors R1066 and R1065, pin 20 is connected to 1.1V voltage, and pin 46 is connected to ground through resistor R1069 and capacitor C1001 are grounded, pin 48 is connected to LS2K_ACPI_S3N through resistors R1071 and R1070, pin 47 is connected to VREG through resistor R1072, pin 47 is also grounded through resistor R1073, pin 15 is grounded through resistor R1076 and capacitor C1089, pin 14 is connected to LS2K_ACPI_S4N through resistors R1078 and R1077, and pin 5 is connected to 5V voltage through resistor R1080;

[0048] Pin 6 is connected to one end of resistor R1082 and one end of resistor R1083, and the other end of resistor R1083 is grounded. Pin 7 is connected to one end of magnetic bead FB104, and the other end of magnetic bead FB104 is connected to the other end of resistor R926 and VDD_RSM_IN. VDD_RSM_IN is also grounded through 5 parallel capacitors C1098, C1099, C1100, C1101, and C1102. Pin 8 is connected to 5V voltage and one end of capacitor C1097. Pin 11 is grounded and connected to the other end of capacitor C1097. Pin 16 is connected to one end of resistor R1079 and one end of R1081, and the other end of R1081 is grounded. Pin 10 is connected to one end of capacitor C1090 and One end of the inductor L19 is connected, the other end of the inductor L19 is connected to the other end of the resistor R1079 and to P1V5_DDR, P1V5_DDR is also grounded through 6 parallel capacitors C1091, C1092, C1093, C1094, C1095, and C1096, pin 45 is connected to one end of the resistor R1074 and to one end of R1075, the other end of R1075 is grounded, pin 3 is connected to one end of the capacitor C1082 and to one end of the inductor L18, the other end of the inductor L18 is connected to the other end of the resistor R1074 and to P1V5_LS, P1V5_LS is also grounded through 6 parallel capacitors C1083, C1084, C1085, C1086, C1087, and C1088.

[0049] Pin 28 is connected to one end of capacitor C1080, pins 26 and 27 are simultaneously connected to the other end of capacitor C1080 and one end of inductor L17 and to pin 8 of transistor Q22, pin 32 is connected to one end of capacitor C1067, pins 33 and 34 are simultaneously connected to the other end of capacitor C1067 and one end of inductor L16 and to pin 5 of transistor Q22, pin 30 is grounded and connected to one end of resistor R1067 and to one end of resistor R1068, pin 29 is connected to the other end of resistor R1068 and to pin 2 of transistor Q22, pin 31 is connected to the other end of resistor R1067 and to pin 4 of transistor Q22, pin 40 is connected to one end of resistor R1060 and to one end of resistor R1061, and the other end of resistor R1060 is connected to pin 41 of transistor Q22. The end is grounded, the other end of the resistor R1061 is connected to the other end of the inductor L16 and the other end of the inductor L17 and one end of the magnetic bead FB103 and to the 1.1V voltage, the other end of the magnetic bead FB103 is connected to the 1.2V voltage, the end of the magnetic bead FB95 connected to 1.1V is also grounded through 8 parallel capacitors C1068, C1069, C1070, C1071, C1072, C1073, C1074, and C1075, the end of the magnetic bead FB103 connected to 1.2V is also grounded through 4 parallel capacitors C1076, C1077, C1078, and C1079, pin 41 is grounded through resistor R1059, pin 43 is grounded through resistor R1058, and pin 43 is also connected to VREG through resistor R1057. At the same time, pins 1 and 4 of transistor Q22 are grounded.

[0050] Pin 4, pin 9, pin 24, pin 25, pin 35, and pin 36 are all connected to 12V voltage.

[0051] Pin 2, pin 13, pin 17, pin 18, pin 19, pin 21, and pin 23 are grounded.

[0052] After the P12V power supply, it flows into U61, which is a 5-channel integrated power solution with the characteristics of 4-channel buck regulation and 5-channel LDO regulation. Channels 1-4 input P12V power supply, and channel 5 inputs 5V_RSM power supply. Its channels 1 and 2 get P1V1 and P1V2 power supplies. P1V1 mainly powers the VDD pin of the CPU, and P1V2 power supply mainly powers the video interface chip. Its function is to connect the CPU and DVO, HDMI interface bridge; Channel 3 gets P1V5LS power supply, which mainly powers the DDR_VDDE pin of the CPU; Channel 4 gets P1V5DDR power supply, which mainly powers four K4B4G1646B-HCK0 memory chips; Channel 5 gets VDDRSMIN power supply, which mainly powers the VDD_RSM pin of the CPU.

[0053] (2) Self-starting circuit design

[0054] like Figure 5 As shown, the self-starting circuit includes an enhanced MOS tube Q23, an OR gate U62, a Schottky diode D69, a resistor R1084, a resistor R1085, a resistor R1086, a resistor R1087, a capacitor C1103, and a capacitor C1104, wherein:

[0055] The gate terminal of the enhancement MOS transistor Q23 is connected to one end of the resistor R1085 and one end of the capacitor C1103, the source terminal of the enhancement MOS transistor Q23 is grounded, the drain terminal of the enhancement MOS transistor Q23 is connected to one end of the resistor R1084 and the first input terminal of the OR gate U62, the other end of the resistor R1085 is connected to a 3.3V voltage, the other end of the capacitor C1103 is grounded, the other end of the resistor R1084 is connected to a 3.3V voltage, the anode terminal of the Schottky diode D69 is connected to one end of the resistor R1087 and the second input terminal of the OR gate U62, the other end of the resistor R1087 is connected to a 3.3V voltage, the cathode terminal of the Schottky diode D69 is connected to one end of the input R1086 and one end of the capacitor C1104, the other end of the resistor R1086 is connected to a 3.3V voltage, the other end of the capacitor C1104 is grounded, and the output terminal of the OR gate U62 is connected to the processor.

[0056] In one example, a terminal J21 is connected between the output end of the OR gate U62 and the processor, one end of the terminal J21 connected to the processor is also connected to one end of the resistor R1088, the other end of the resistor R1088 is connected to one end of the capacitor C1105 and one end of the touch switch J22, the other end of the capacitor C1105 is grounded, and the other end of the touch switch J22 is grounded. J21 is a terminal, which is normally closed, and is reserved to adapt to the situation where manual start is required in some places. It can be disconnected and connected to the J22 button for manual start.

[0057] like Figure 5 As shown, the P3V3SB power supply is powered on at the same time, the C1103 capacitor begins to charge, and the voltage at the pin 1 end of the Q23 field effect tube, that is, the A branch in the figure, gradually rises. At this time, the Q23 pin 2 end is grounded and the pin 3 end is connected to R1084, which is in a blocking state, so the branch between Q23Y and U62 is high level, or the gate U62 pin 1 is high level. At the same time, due to the action of the D692 Schottky diode, the P3V3SB current passes through R1087 and D692, and charges the C1104 capacitor at the same time as another power supply through R1086. At this time, the voltage at the pin 2 of the gate circuit gradually rises. But it is far less than its pin trigger voltage. At this time, the gate circuit pin 1 is high level, the voltage at the pin 2 is slowly rising (can be seen as a low level), and the pin 3 level is high. As the C1103 capacitor is charged for 1.6s, the level at the Q23 field effect transistor pin 1 reaches the trigger level, the field effect transistor pins 2 and 3 are turned on, and the current flows into the OR gate through R1084 and changes its direction to ground through Q23 pins 3 and 2. At this time, the level of the OR gate pin 1 changes from 3V3 to 0, and the voltage of the OR gate pin 2 is not enough to trigger the gate circuit, which is equivalent to the OR gate pins 1 and 2 are both low, so the OR gate pin 3 level is low at this time. After charging the C1104 capacitor for 2s, the OR gate pin 2 level reaches the trigger level, pin 1 is low, and pin 2 is high, so the OR gate pin 3 level returns to high. During the whole process, the OR gate pin 3 level changes from high level to low level in 1.6s, and from low level to high level in 2s, simulating the whole process of key start so that the CPU can start automatically.

[0058] Driving circuit design:

[0059] (1) PCIE circuit design

[0060] like Figure 6 , PCIE reference clock and device clock need to be of the same source. The AC coupling of the transmit and receive signals requires the connection of a 0.1uF capacitor. When selecting the working mode, PCIE0_PRSNT0-3 is pulled down by the pull-down resistors R1090, R1091, R1092, and R1093 respectively, so that PCIE0 works in 4 X1 modes. Since the onboard USB2.0 cannot meet the image processing data conditions, the PCIE port is connected to the D720201 expansion board to achieve USB3.0 support

[0061] PCIE1_REFCLKP0 and PCIE1_REFCLKN0, PCIE11_TXP0 and PCIE11_TXP1 are reserved for connecting to wifi; PCIE1_REFCLKP1 and PCIE1_REFCLKN1, PCIE11_TXP1 and PCIE11_TXN1 are connected to CON24 to achieve USB3.0 support; PCIE1_PRSTN0 and PCIE1_PRSTN1 are pulled down to ground through R79 and R80; LS2K_PCIE_RSTN is connected to P3V3.

[0062] (2) DVO circuit design

[0063] like Figure 7 , LIO and DVO0 are reused. This design mainly uses the DVO interface to connect the capacitive touch screen. The Loongson main control board is connected to the SiI9022ACNU ultra-low power HDMI transmitter through R1095.

[0064] IOVCC is connected to P3V3 through a magnetic bead; CVCC1_2 and AVCC1_2 are connected to P1V2 through magnetic beads respectively.

[0065] Memory circuit design

[0066] like Figure 8 , 9 The memory part of the storage module uses four K4B4G1646B-HCK0 memory particles, which are the bridge for communication with the CPU, ensuring the normal operation of the internal face recognition service software. In the layout design of DDR, we used the Fly-by topology. The clock signal line of each 4GB onboard particle is connected to the processor, and connected to the DDR3_1V5 power supply through R1109 and R1110 in parallel to the C1114 capacitor; resistors need to be connected to the address line and the control line; the ODT signal should keep a corresponding relationship with the CS. Its characteristic is that the data group does not need to be the same length as the clock signal, which can save more wiring space and support higher signal rates.

[0067] Sequential circuit design

[0068] The timing circuit uses ACPI enable, ACPI_EN pull-up, the timing is as follows Fig.10 shown.

[0069] 1) The 2S delay of T2 is to ensure that the RTC crystal - 32.768K, can fully oscillate.

[0070] 2) When GMAC_VDDE in ④ is 2.5V, keep the above timing. If it is 3.3V, it can be merged into ⑤.

[0071] 3) Among PEST_1V1, VDD and PLL, VDD is powered separately. When using SATA, VDD, PEST_1V1 and PLL are powered by three power chips.

[0072] 4) After RTC_RSMRSTn is released from reset, ACPI_PWRBTNn must be pulled high at a low level for at least 20ms or a low pulse with a pulse width of at least 20ms to trigger the power on.

[0073] Power-on sequence:

[0074] (1) First, P12V input obtains P5V;

[0075] (2) Then P5V enables the RTC-related VDD to power on, and then the RSM_EN-related power supply is powered on after a delay of 2s;

[0076] (3) P5V and RSM_EN are both powered on at this time, so P1V1PG (starting from U34) and LS2K_ACPI_S5N begin to enable power on;

[0077] (4) P12V and LS2K_ACPI_S5N are both powered on, so P3V3 starts to enable power on;

[0078] (5) P12V and P3V3 are both powered on, so P1V5 starts to be powered on;

[0079] (6) P12V and P1V5 are now powered on, so VDD, PEST_1V1, and PLL_1V1 are powered on and the CPU starts to operate normally.

[0080] Design of image acquisition module

[0081] In one example, the image acquisition module uses a 115-degree wide-angle UVC camera in hardware to collect faces, sets the face collection size to 680X600, and uses a PCI-E interface gold-plated board D720201 expansion board for connection.

[0082] In terms of software, first add the kernel driver v4l2 for video devices in the Linux file system to the project file, and call the function interface for controlling and operating video devices under the V4L2 framework, such as opening the device open(), closing the device close(), setting control parameters ioctl(), etc.

[0083] At the application level, the camera frame data is obtained and face detection is implemented based on the OpenCV software library. The detected frame data stream is processed by mask inversion and image stacking, and the video stream display under the viewfinder is obtained in the interactive interface. At the same time, the data stream format is separated from the frame type channel into a GRAY grayscale image, and the histogram mean is processed to make the image clearer. Through OpenCV, multiple coordinate points of the face area in the image are obtained, and the face image is intercepted based on the multiple coordinate points.

[0084] Display module design

[0085] like Fig.11 As shown in the figure, the display module uses the QT framework to design the human-computer interaction interface. The hardware uses a Feiling 7-inch FPC interface 1024×600 resolution high-end capacitive touch screen; the screen touch part uses the IIC interface, and the touch chip uses the GT911. It is connected to the DVO interface of the main control board through a 54P FPC soft cable. In terms of software, by compiling the gt911 touch screen driver, the QT_QPA_PLATFORM operation mode is configured as linuxfb in the system environment variables, and the screen-related parameters such as size, mmSize, offset, etc. are also configured. According to the LCD screen resolution and the human-computer interface design, the camera image display size is set to 680×600.

[0086] Storage module design

[0087] It uses a Kingston 16GB solid-state drive with an M2 interface, which is mainly used to store embedded file systems and facial information, providing a hardware foundation for stand-alone offline operation.

[0088] Shell design

[0089] The outer shell is made of 6063-T5 industrial extruded aluminum alloy, which has good plasticity, good heat dissipation, wear resistance and corrosion resistance. It is designed according to the size of the main control board, with a length of 150mm, a width of 145mm and a height of 68mm. Holes are opened on the left and right sides according to the design of the main control board to leave the position of the socket. A 5mm inner shell is set inside to fix the main control board in it to increase the stability of the equipment.

[0090] How it works

[0091] 1. Working principle of characteristic impedance:

[0092] During the signal propagation along the transmission line, if the signal propagation speed is consistent everywhere on the transmission line, and the capacitance per unit length is the same, then the signal always sees exactly the same instantaneous impedance during the propagation process. Since the impedance remains constant throughout the transmission line, we give a specific name to represent this feature or characteristic of a specific transmission line, which is called the characteristic impedance of the transmission line. Characteristic impedance refers to the value of the instantaneous impedance seen by the signal when it propagates along the transmission line. The characteristic impedance is related to factors such as the board layer where the PCB conductor is located, the material used for the PCB (dielectric constant), the width of the trace, the distance between the conductor and the plane, and has nothing to do with the length of the trace. The characteristic impedance can be calculated using software. In high-speed PCB wiring, the trace impedance of digital signals is generally designed to be 50 ohms, which is an approximate number. It is generally stipulated that the baseband of coaxial cable is 50 ohms, the frequency band is 75 ohms, and the twisted pair (differential) is 100 ohms.

[0093] Common impedance matching methods

[0094] (1) Series terminal matching

[0095] Under the condition that the impedance of the signal source end is lower than the characteristic impedance of the transmission line, a resistor R is connected in series between the signal source end and the transmission line to match the output impedance of the source end with the characteristic impedance of the transmission line, thereby suppressing the re-reflection of the signal reflected from the load end.

[0096] Matching resistor selection principle: The sum of the matching resistor value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. The output impedance of common CMOS and TTL drivers will change with the level of the signal. Therefore, for TTL or CMOS circuits, it is impossible to have a very correct matching resistor, and only a compromise can be considered. The signal network with a chain topology is not suitable for series terminal matching, and all loads must be connected to the end of the transmission line.

[0097] Series matching is the most commonly used terminal matching method. Its advantages are low power consumption, no additional DC load on the driver, no additional impedance between the signal and the ground, and only one resistor element is required.

[0098] Common applications: impedance matching of general CMOS and TTL circuits. USB signals are also sampled using this method for impedance matching.

[0099] (2) Parallel terminal matching

[0100] When the impedance of the signal source is very small, the input impedance of the load end is matched with the characteristic impedance of the transmission line by adding a parallel resistor, so as to eliminate the reflection at the load end. There are two forms of implementation: single resistor and double resistor.

[0101] Matching resistor selection principle: When the input impedance of the chip is very high, for a single resistor, the parallel resistance value at the load end must be close to or equal to the characteristic impedance of the transmission line; for a dual resistor, each parallel resistance value is twice the characteristic impedance of the transmission line.

[0102] The advantage of parallel terminal matching is that it is simple and easy to implement. The obvious disadvantage is that it will bring DC power consumption: the DC power consumption of the single resistor method is closely related to the duty cycle of the signal; the dual resistor method has DC power consumption regardless of whether the signal is high or low, but the current is half that of the single resistor method.

[0103] Common applications: mostly high-speed signal applications.

[0104] 2. How face recognition works:

[0105] The facial image collected in the image acquisition module is extracted using a neural network model. The feature vector of the image is retained. The float threshold is obtained by using the two-dimensional feature vector in the frame data and the feature vector obtained by traversing the database. The threshold of the file traversal that is most similar to the current frame data is obtained, and then the similarity of the facial features in the two images is compared. A new vector (similarity) is obtained by subtracting the vector. When the modulus value of the new vector (similarity) is closer to zero, it proves that the two vectors are more similar. If the similarity is less than the threshold, that is, the image hits the facial feature vector in the database, we think they are the same person.

[0106] Compared with the prior art, the present invention has the following beneficial effects:

[0107] (1) Using domestic core processor

[0108] This design uses domestic core processors to reduce dependence on foreign technologies and products, prevent information security vulnerabilities from leaking user information, improve the security of the equipment, and reduce costs.

[0109] (2) The beneficial effects of not using pictures for intuitive preview

[0110] The present invention deletes the stored facial feature coding information after the face recognition is completed, and does not use the intuitive preview of pictures, which greatly protects the privacy and security of customers. In addition, this device can be operated offline, and the face recognition comparison results are completed directly on the device, which is more confidential.

[0111] (3) Beneficial effects of circuit welding

[0112] Through chip welding, it is found that the difficulty of welding is directly related to the size of the circuit board package. Circuit welding plays a reference and guiding role in the design of printed circuit boards, making the designed printed circuit boards more mature and reliable.

[0113] (4) Beneficial effects of instrument testing

[0114] Instrument testing is also an essential technical means for monitoring the functions and performance of integrated circuit components. Integrated circuit testing is the detection of integrated circuits or modules. By measuring the output response of the integrated circuit and comparing it with the expected output, the device type, physical characteristics, process, functional parameters, environmental characteristics, reliability, etc. are detected to determine or evaluate the functions and performance of integrated circuit components.

[0115] According to the design requirements of the face recognition main control module, the circuit design is constantly modified and improved. According to the packaging form of the DUT, the maximum clock frequency, the resource configuration of the ATE and the interface board shape, the test socket is reasonably selected and the test load board is designed and manufactured. The maximum clock frequency, timing accuracy requirements, number of input and output pins of the device are tested by instruments, and the instruction sequence of the device is tested by programs. Through various tests on the circuit board, not only the operation of the instrument is mastered, but also the actual impact of theoretical design on the circuit is further accumulated. Through several integrated circuit tests, the circuit parameters and integrated circuit circuits under actual conditions are obtained.

[0116] (5) The beneficial effects of designing human-computer interaction interfaces

[0117] The display module uses a human-computer interactive capacitive screen to realize the display function. The benefits of using a capacitive screen are:

[0118] ① There is no need to develop GUI for the designed interaction method, which saves a lot of development time;

[0119] ② Flexible design, allowing for quick functional modifications based on functional requirements;

[0120] ③ It allows designers to focus more on data reception and display, eliminating the trouble of interface design;

[0121] ④The operator interacts with the hardware equipment entirely by touch, which is convenient and intuitive.

[0122] There are other options as alternatives in device selection and hardware design

[0123] (1) Autonomous and controllable face recognition device main control chip

[0124] The self-controlled face recognition equipment currently uses the domestic 2K1000 chip, which can be replaced by the Loongson 3A3000. They are both domestic high-performance, ultra-efficient processor sub-series, and have basic network, collection, processing and control capabilities. The only difference is in power consumption and price.

[0125] (2) DDR3 memory chip

[0126] The memory particles selected in this design are K4B4G1646B-HCK0 onboard particles produced by SAMSUNG, and HXB15H4G160AF produced by Unilc can be used. They all have the advantages of frequency above 800M, low power consumption and heat generation, and good versatility.

[0127] (3) Human-computer interaction display screen

[0128] This design uses Feiling 7-inch FPC interface 1024×600 resolution high-end capacitive touch screen, and FPC interface 800×600 capacitive screen can be used. They all have the same backlight and color, and have slight differences in pixel ratio, contrast, response time, power consumption, etc.

[0129] (4) Hardware interface

[0130] The M2 storage hard drive interface AS0BC21-S40BB-7H can be replaced by AS0BC21-S48BB-7H, they have the same PCB package; the DVO soft cable FPC-0.5 pull-out lower connector can be replaced by F2B54U-A1T3-E; the C891 charging start capacitor can be replaced by a 0.4uf 16V capacitor with the same package.

[0131] In order to solve the problem of slow face recognition speed and improve the security of personal information, the present invention designs an autonomous and controllable face recognition device. During the design process, the impedance matching between the signal source and the load end is used to effectively control the load power and suppress signal reflection. In combination with a variety of face recognition data transmission and processing technologies, the device computing performance is reasonably allocated, the computing efficiency is improved, and face recognition can reach the millisecond level, thereby achieving a fast response of face recognition.

[0132] Moreover, this design uses domestic core processors, which are safer and more reliable than similar products in the industry. In the process of face recognition, only facial feature points are compared and analyzed, and the intuitive preview of pictures is not used, which protects the privacy and security of customers to a great extent. This device can be run offline and stand-alone. The face recognition comparison results are completed directly on the device, and are not loaded through the Internet, which is more confidential. In addition, this device can flexibly adapt to on-site needs by plugging and unplugging various image modules, acquisition devices, display devices, and actuators. The entire design forms an interactive service with the control end to meet different business needs and their functional data processing equipment, which has good scalability.

[0133] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above are only specific implementation methods of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An autonomous and controllable face recognition device, characterized in that: include: A main control module, connected with an image acquisition module, a storage module, a display module and a control terminal; The main control module at least includes a processor, a drive circuit, a self-starting circuit, a power supply circuit and a memory circuit; The driving circuit includes a DVO circuit and a PCIE circuit; The self-starting circuit includes an enhanced MOS tube Q23, an OR gate U62, a Schottky diode D69, a resistor R1084, a resistor R1085, a resistor R1086, a resistor R1087, a capacitor C1103, and a capacitor C1104, wherein: The gate terminal of the enhancement MOS transistor Q23 is connected to one end of the resistor R1085 and one end of the capacitor C1103, the source terminal of the enhancement MOS transistor Q23 is grounded, the drain terminal of the enhancement MOS transistor Q23 is connected to one end of the resistor R1084 and the first input terminal of the OR gate U62, the other end of the resistor R1085 is connected to a 3.3V voltage, the other end of the capacitor C1103 is grounded, the other end of the resistor R1084 is connected to a 3.3V voltage, the anode terminal of the Schottky diode D69 is connected to one end of the resistor R1087 and the second input terminal of the OR gate U62, the other end of the resistor R1087 is connected to a 3.3V voltage, the cathode terminal of the Schottky diode D69 is connected to one end of the input R1086 and one end of the capacitor C1104, the other end of the resistor R1086 is connected to a 3.3V voltage, the other end of the capacitor C1104 is grounded, and the output terminal of the OR gate U62 is connected to the processor; When the working mode is selected, PCIE0_PRSNT0-3 is pulled down by R1090, R1091, R1092, and R1093 pull-down resistors respectively, so that PCIE0 works in 4 X1 modes.

2. The autonomous and controllable face recognition device according to claim 1, characterized in that: The main control module also includes a DEBUG debugging circuit, a clock circuit and a timing circuit; The processor is Loongson2K1000 processor or Loongson 3A3000.

3. The autonomous and controllable face recognition device according to claim 1, characterized in that: A terminal J21 is connected between the output end of the OR gate U62 and the processor. One end of the terminal J21 is connected to the processor and is also connected to one end of a resistor R1088. The other end of the resistor R1088 is connected to one end of a capacitor C1105 and to one end of a touch switch J22. The other end of the capacitor C1105 is grounded, and the other end of the touch switch J22 is grounded.

4. The autonomous and controllable face recognition device according to claim 1, characterized in that: The image acquisition module uses a 115-degree wide-angle UVC camera in hardware to collect faces, sets the size of face collection to 680 × 600, and uses a PCI-E interface gold-plated board D720201 expansion board for connection.

5. The autonomous and controllable face recognition device according to claim 1, characterized in that: The display module uses the QT framework to design the human-computer interaction interface, and the hardware uses a Feiling 7-inch FPC interface 1024×600 resolution high-end capacitive touch screen; the screen touch part uses the IIC interface, and the touch chip uses GT911.

6. The autonomous and controllable face recognition device according to claim 1, characterized in that: The display module is connected to the DVO interface of the main control board through a 54P FPC flexible cable.

7. The autonomous and controllable face recognition device according to claim 1, characterized in that: The storage module uses a Kingston 16GB solid state hard drive and is connected to the main control module via an external M2 interface.

8. The autonomous and controllable face recognition device according to claim 1, characterized in that: The memory part of the storage module uses four K4B4G1646B-HCK0 memory particles. The clock signal line of each 4GB onboard particle is connected to the processor, and is connected to the DDR3_1V5 power supply in parallel to the C1114 capacitor through R1109 and R1110.

9. The autonomous and controllable face recognition device according to claim 1, characterized in that: The autonomous and controllable face recognition device is provided with a 5mm inner shell for fixing the main control board.

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