Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a manufacturing method thereof. The manufacturing method of the chip packaging structure includes the following steps. A carrier having a receiving groove and including a substrate and a stainless steel layer sputtered on the substrate is provided. A chip is arranged in the receiving groove of the carrier. The chip has an active surface and a back surface opposite to each other and a plurality of electrodes arranged on the active surface. A circuit structure layer is formed on the carrier, wherein the circuit structure layer includes a patterned circuit and a plurality of conductive through holes. The patterned circuit is electrically connected to the electrodes of the chip through the conductive through holes. A packaging colloid is formed to cover the active surface and the circuit structure layer of the chip, wherein the active surface of the chip is coplanar with the bottom surface of the packaging colloid. The carrier is removed to expose the bottom surface of the packaging colloid.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] In the well-known coreless process, the edge of the local carrier and the edge of the local circuit board are first combined by adhesive or copper plating. Another conventional method is to use a thin substrate (thickness is, for example, 100 microns) containing glass fiber cloth, with a piece of copper foil on each side and a removable ultra-thin copper foil (thickness is, for example, 3 to 5 microns) attached thereto as a carrier. After the circuit board has undergone multiple processes, the portion with adhesive or copper plating between the carrier and the circuit board is cut off to obtain the circuit board for the packaging process. However, in the well-known coreless process, part of the carrier and part of the circuit board need to be cut off, thereby reducing the size of the circuit board and the carrier after cutting cannot be reused, resulting in increased manufacturing costs.

[0003] In order to solve the above problems, it is conventional to use stainless steel plates as the basis of the carrier. In the process of manufacturing the circuit structure, the stainless steel plates can provide good stability and do not need to be cut when dismantling the plates, so they can be reused, thereby effectively saving manufacturing costs. However, the stainless steel plates are large and heavy, and are often difficult to carry during the manufacturing process. In addition, their edges and corners are relatively sharp, which often causes damage to the substrate itself or the machine.

[0004] In addition, in the conventional chip packaging structure manufacturing method, a dielectric layer, such as prepreg (PP), is first pressed or pressed on the chip. Then, vias are made in the dielectric layer by laser ablation and connected to the electrodes of the chip to complete the fan-out packaging structure. However, the fan-out packaging made through the dielectric layer is more complicated in structure and process, and has a higher cost. Summary of the invention

[0005] The present invention is directed to a chip packaging structure and a manufacturing method thereof, which is relatively safe and simple in manufacturing, and can effectively reduce manufacturing costs and improve product yield.

[0006] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. A carrier is provided. The carrier has a receiving groove and includes a substrate and a stainless steel layer sputtered on the substrate. A chip is configured in the receiving groove of the carrier. The chip has an active surface and a back surface opposite to each other and a plurality of electrodes arranged on the active surface. A circuit structure layer is formed on the carrier, wherein the circuit structure layer includes a patterned circuit and a plurality of conductive through holes. The patterned circuit is electrically connected to the electrodes of the chip through the conductive through holes. A packaging colloid is formed to cover the active surface and the circuit structure layer of the chip, wherein the active surface of the chip is coplanar with the bottom surface of the packaging colloid. The carrier is removed to expose the circuit structure layer.

[0007] In the method for manufacturing a chip packaging structure according to an embodiment of the present invention, the material of the substrate includes a sheet-shaped glass fiber resin substrate, a rolled glass fiber resin substrate or a rolled stainless steel substrate.

[0008] The manufacturing method of the chip packaging structure according to the embodiment of the present invention further includes: before disposing the chip in the receiving groove of the carrier, forming a metal layer on the stainless steel layer. When removing the carrier, the metal layer is removed at the same time.

[0009] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the step of forming a circuit structure layer on the carrier includes: forming a first patterned photoresist layer on the metal layer. The first patterned photoresist layer exposes the electrode and part of the metal layer of the chip. Sputtering the first metal layer and the second metal layer on the first metal layer on the first patterned photoresist layer, and on the electrode and metal layer of the chip exposed by it. Forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer and exposes part of the second metal layer. Performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and on the second metal layer exposed by it. Removing the first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer to form a circuit structure layer and expose the metal layer. The patterned circuit of the circuit structure layer includes a plurality of inner pins and a plurality of outer pins. The inner pins are separated from each other and located above the chip. The outer pins are connected to the inner pins and are extended and arranged on the metal layer.

[0010] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the packaging colloid covers a portion of the metal layer and the active surface of the chip, and encapsulates the inner pins and the conductive through holes.

[0011] The manufacturing method of the chip packaging structure according to the embodiment of the present invention further includes: exposing the back side of the chip and the metal layer thereon when removing the carrier, and forming a surface treatment layer on the metal layer on the back side of the chip.

[0012] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the carrier further has a plurality of recesses, wherein the recesses surround the accommodating groove, and the stainless steel layer is conformally disposed with the substrate.

[0013] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, it also includes: before configuring the chip in the receiving groove of the carrier, forming a metal layer on the stainless steel layer. The metal layer fills the groove to define a plurality of conductive bumps. When the carrier is removed, the conductive bumps on the bottom surface of the packaging colloid and part of the metal layer on the back side of the chip are exposed at the same time.

[0014] In the manufacturing method of the chip packaging structure according to an embodiment of the present invention, the step of forming a circuit structure layer on a carrier includes: forming a first patterned photoresist layer on the metal layer. The first patterned photoresist layer exposes the electrode and part of the metal layer of the chip. Sputtering the first metal layer and the second metal layer on the first metal layer on the first patterned photoresist layer, and on the electrode and metal layer of the chip exposed thereby. Forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer and exposes part of the second metal layer. Performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and on the second metal layer exposed thereby. Removing the first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer to form a circuit structure layer and expose the metal layer.

[0015] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the packaging colloid covers the metal layer and the active surface of the chip, and encapsulates the patterned circuits and the conductive vias.

[0016] The manufacturing method of the chip packaging structure according to the embodiment of the present invention further includes: after removing the carrier, forming a surface treatment layer on the surrounding surface of the conductive bump and on the metal layer on the back side of the chip.

[0017] According to an embodiment of the present invention, a chip packaging structure includes a circuit structure layer, a chip and a packaging colloid. The circuit structure layer includes a patterned circuit and a plurality of conductive vias. The chip has an active surface and a back surface opposite to each other and a plurality of electrodes arranged on the active surface. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. The packaging colloid covers the active surface and the circuit structure layer of the chip, wherein the active surface of the chip is coplanar with the bottom surface of the packaging colloid.

[0018] In an embodiment of the present invention, the patterned circuit of the chip packaging structure includes a plurality of inner pins and a plurality of outer pins. The inner pins are separated from each other and are located above the chip. The packaging colloid covers the inner pins and the conductive through holes, and the outer pins connect the inner pins and extend outside the packaging colloid.

[0019] In an embodiment of the present invention, the chip package structure further includes a surface treatment layer disposed on the back surface of the chip and on the metal layer on the side surface connecting the back surface and the active surface.

[0020] In an embodiment of the present invention, the chip packaging structure further includes a plurality of conductive bumps disposed on the bottom surface of the packaging colloid and electrically connected to the patterned circuit through the conductive through-holes.

[0021] In an embodiment of the present invention, the chip package structure further includes a surface treatment layer disposed on the back side of the chip and the metal layer on the side surface connecting the back side and the active surface and on the surrounding surface of the conductive bump.

[0022] Based on the above, in the manufacturing method of the chip packaging structure of the present invention, a stainless steel layer is formed on the substrate of the carrier by sputtering, so that good stability can be provided during the manufacturing process of the circuit structure layer. Furthermore, the stainless steel layer formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and the stainless steel film and the copper-plated film thereon can be separated mechanically, and the operation is safer and simpler. In addition, when separating the carrier to expose the circuit structure layer, no cutting is required, so the carrier can be reused, thereby effectively saving manufacturing costs.

[0023] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0025] FIG. 1A to FIG. 1I A cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention is shown;

[0026] Figure 1J A schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention is shown;

[0027] FIG. 2A to FIG. 2I A cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention is shown;

[0028] Figure 2J FIG. 4 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0029] Description of Figure Numbers

[0030] 100a1, 100a2, 100b1, 100b2: chip packaging structure;

[0031] 110a, 110b: carrier board;

[0032] 112, 112': substrate;

[0033] 114, 114': stainless steel layer;

[0034] 120, 120', 170: metal layer;

[0035] 130: Chip;

[0036] 131: Active surface;

[0037] 132: Electrode;

[0038] 133: back;

[0039] 135: lateral surface;

[0040] 140: first metal layer;

[0041] 145: second metal layer;

[0042] 150, 150': line structure layer;

[0043] 150a: conductive material layer;

[0044] 152, 152': patterned circuit;

[0045] 153: inner pin;

[0046] 154, 154': conductive through hole;

[0047] 155: external pin;

[0048] 160, 160': encapsulation colloid;

[0049] 162, 162': bottom surface;

[0050] 170', 172: surface treatment layer;

[0051] C, C': accommodating groove;

[0052] C1: notch;

[0053] P1, P1': first patterned photoresist layer;

[0054] P2, P2': second patterned photoresist layer;

[0055] S: surrounding surface;

[0056] T: Conductive bump. DETAILED DESCRIPTION

[0057] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] FIG. 1A to FIG. 1I FIG. 1 is a cross-sectional view of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Regarding the method for manufacturing a chip packaging structure according to the present embodiment, first, please refer to Figure 1A , providing a carrier 110a, wherein the carrier 110a has a receiving groove C and includes a substrate 112 and a stainless steel layer 114 sputtered on the substrate 112. Here, the substrate 112 can be a hard substrate composed of a glass fiber resin substrate and copper foils disposed on opposite sides of the glass fiber resin substrate; or, it can be a rolled glass fiber resin substrate, or a rolled stainless steel substrate; or, it can be a glass substrate electroplated with a titanium layer and a copper layer, all of which belong to the scope of protection of the present invention. The material of the stainless steel layer 114 is, for example, SUS 304 or other suitable models, wherein the thickness of the stainless steel layer 114 is, for example, between 0.05 microns and 0.5 microns. In other words, the stainless steel layer 114 can be regarded as a stainless steel film.

[0059] Next, please refer to Figure 1A , a metal layer 120 is formed on the stainless steel layer 114. Here, the metal layer 120 is conformally disposed with the carrier 110a, wherein the material of the metal layer 120 is, for example, copper, but not limited thereto.

[0060] Next, please refer to Figure 1B , the chip 130 is configured in the receiving groove C of the carrier 110a, wherein the chip 130 has an active surface 131 and a back surface 133 opposite to each other and a plurality of electrodes 132 disposed on the active surface 131. Here, the chip 130 is located on the metal layer 120 corresponding to the receiving groove C of the carrier 110a, and the material of the electrode 132 is, for example, aluminum, but not limited thereto.

[0061] Next, please refer to Figure 1C , a first patterned photoresist layer P1 is formed on the metal layer 120 , wherein the first patterned photoresist layer P1 exposes the electrode 132 of the chip 130 and a portion of the metal layer 120 .

[0062] Next, please refer to Figure 1D, sputtering the first metal layer 140 and the second metal layer 145 on the first metal layer 140 onto the first patterned photoresist layer P1, and onto the exposed electrode 132 of the chip 130 and the metal layer 120. Here, the first metal layer 140 is, for example, a titanium layer, and the second metal layer 145 is, for example, a copper layer; or, the first metal layer 140 is, for example, a chromium layer, and the second metal layer 145 is, for example, a copper layer.

[0063] Next, please refer to Figure 1E , forming a second patterned photoresist layer P2 on the second metal layer 145, wherein the second patterned photoresist layer P2 is located above the first patterned photoresist layer P1 and exposes a portion of the second metal layer 145. Here, the pattern of the first patterned photoresist layer P1 is different from the pattern of the second patterned photoresist layer P2.

[0064] Next, please refer to Figure 1F The second metal layer 145 is used as a plating seed layer to perform an electroplating process to form a conductive material layer 150 a on the second patterned photoresist layer P2 and on the exposed second metal layer 145 .

[0065] Next, please also refer to Figure 1F and Figure 1G , the first patterned photoresist layer P1, the second patterned photoresist layer P2, a portion of the first metal layer 140 and a portion of the second metal layer 145 are removed to form a circuit structure layer 150 and expose the metal layer 120. Thus, the circuit structure layer 150 has been formed on the carrier 110a, wherein the circuit structure layer 150 includes a patterned circuit 152 and a plurality of conductive vias 154, and the patterned circuit 152 is electrically connected to the electrode 132 of the chip 130 through the conductive vias 154. Here, the patterned circuit 152 of the circuit structure layer 150 includes a plurality of inner pins 153 and a plurality of outer pins 155, wherein the inner pins 153 are separated from each other and located above the chip 130, and the outer pins 155 are connected to the inner pins 153 and extend and are configured on the metal layer 120. In addition, the conductive vias 154 are formed by the remaining first metal layer 140, the remaining second metal layer 145 and a portion of the conductive material layer 150a. From the above content, it can be known that the present embodiment does not use a dielectric layer to make the circuit structure layer. Instead, after removing the photoresist, part of the circuit is suspended to form an air bridge structure. At this time, the circuit structure layer 150 can be regarded as a lead frame.

[0066] Afterwards, please refer to Figure 1H, forming an encapsulation 160 to cover the active surface 131 of the chip 130 and the circuit structure layer 150, wherein the active surface 131 of the chip 130 is coplanar with the bottom surface 162 of the encapsulation 160. Here, the encapsulation 160 covers a portion of the metal layer 120 and the active surface 131 of the chip 130, and covers the inner pins 153 and the conductive vias 154.

[0067] Finally, please also refer to Figure 1H and Fig. 1I , remove the carrier 110a and part of the metal layer 120 to expose the bottom surface 162 of the packaging colloid 160. Here, the method of removing the carrier 110a is, for example, placing the packaging colloid 160 face down on a vacuum platform (not shown), and utilizing vacuum to absorb the packaging colloid 160. In addition, the packaging colloid 160 is fixed by a mechanism, and is separated from the metal layer 120 on the carrier 110a along the interface with the stainless steel layer 114. Compared with the conventional method of removing the carrier, the carrier 110a of this embodiment does not need to be cut, so the carrier 110a can be reused, thereby effectively saving manufacturing costs. In addition, the method of removing the metal layer 120 is, for example, etching. At this point, the production of the lead frame type chip packaging structure 100a1 has been completed.

[0068] In terms of structure, please refer to Fig. 1I The chip package structure 100a1 includes a circuit structure layer 150, a chip 130 and an encapsulation colloid 160. The circuit structure layer 150 includes a patterned circuit 152 and a conductive through hole 154. The chip 130 has an active surface 131 and a back surface 133 opposite to each other and an electrode 132 disposed on the active surface 131. The patterned circuit 152 includes an inner pin 153 and an outer pin 155, wherein the inner pins 153 are separated from each other and located above the chip 130, and the inner pin 153 of the patterned circuit 152 is electrically connected to the electrode 132 of the chip 130 through the conductive through hole 154. The encapsulation colloid 160 covers the active surface 131 of the chip 130 and the circuit structure layer 150, wherein the encapsulation colloid 160 covers the inner pin 153 and the conductive through hole 154, and the outer pin 155 connects the inner pin 153 and extends to the outside of the encapsulation colloid 160. In particular, the active surface 131 of the chip 130 is coplanar with the bottom surface 162 of the encapsulant 160 .

[0069] In short, in the manufacturing method of the chip package structure 100a1 of the present embodiment, the stainless steel layer 114 is formed on the substrate 112 of the carrier 110a by sputtering, so that good stability can be provided during the manufacturing process of the circuit structure layer 150. Furthermore, the stainless steel layer 114 formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and is safer and simpler to operate. In addition, the carrier 100a does not need to be cut when separating, so the carrier 100a can be reused, thereby effectively saving manufacturing costs.

[0070] Figure 1J A schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention is shown. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0071] Please refer to Figure 1J ,At Figure 1H After removing the carrier 110a, only a portion of the metal layer 120 is removed, but the metal layer on the side 135 and the back 133 of the chip 130 is retained to form the metal layer 170. Then, a surface treatment layer 172 is formed on the back 133 of the chip 130 on the metal layer 170, wherein the surface treatment layer 172 is disposed on the metal layer 170. Here, the material of the surface treatment layer 172 is, for example, tin, but not limited thereto. At this point, the production of the lead frame type chip package structure 100a2 has been completed.

[0072] Since the chip package structure 100a2 of the present embodiment has a metal layer 170 disposed on the back surface 133 of the chip 130, the metal layer 170 can directly serve as a shielding layer to prevent electromagnetic interference. Compared with the conventional method of additionally disposing a shielding plate or a grounding plate, the chip package structure 100a2 of the present embodiment can have a thinner package thickness and reduce the process cost.

[0073] FIG. 2A to FIG. 2I FIG. 1 is a cross-sectional view of a method for manufacturing a chip package structure according to another embodiment of the present invention. Regarding the method for manufacturing the chip package of this embodiment, first, please refer to Figure 2A, providing a carrier 110b, wherein the carrier 110b has a receiving groove C' and a plurality of notches C1 surrounding the receiving groove C'. The carrier 110b includes a substrate 112' and a stainless steel layer 114' sputtered on the substrate 112'. Here, the stainless steel layer 114' is disposed conformally with the substrate 112'. Here, the substrate 112' may be a hard substrate composed of a glass fiber resin substrate and copper foils disposed on opposite sides of the glass fiber resin substrate; or, a rolled glass fiber resin substrate and a rolled stainless steel substrate; or, a glass substrate electroplated with a titanium layer and a copper layer, all of which belong to the scope of protection of the present invention. The material of the stainless steel layer 114' is, for example, SUS 304 or other suitable models, wherein the thickness of the stainless steel layer 114' is, for example, between 0.05 microns and 0.5 microns. In other words, the stainless steel layer 114' can be regarded as a stainless steel film.

[0074] Next, please refer to Figure 2B , a metal layer 120' is formed on the stainless steel layer 114', wherein the metal layer 120' fills the recess C1 to define a plurality of conductive bumps T. Here, the material of the metal layer 120' is, for example, copper, but not limited thereto.

[0075] Next, please refer to Figure 2B , the chip 130 is configured in the receiving groove C' of the carrier 110b, wherein the chip 130 has an active surface 131 and a back surface 133 opposite to each other and a plurality of electrodes 132 disposed on the active surface 131. Here, the chip 130 is located on the metal layer 120' corresponding to the receiving groove C' of the carrier 110b, and the material of the electrode 132 is, for example, aluminum, but not limited thereto.

[0076] Next, please refer to Figure 2C , a first patterned photoresist layer P1 ′ is formed on the metal layer 120 ′, wherein the first patterned photoresist layer P1 ′ exposes the electrode 132 of the chip 130 and a portion of the metal layer 120 ′.

[0077] Next, please refer to Figure 2D , sputtering the first metal layer 140 and the second metal layer 145 on the first metal layer 140 onto the first patterned photoresist layer P1' and the exposed electrode 132 of the chip 130 and the metal layer 120'. Here, the first metal layer 140 is, for example, a titanium layer, and the second metal layer 145 is, for example, a copper layer; or, the first metal layer 140 is, for example, a chromium layer, and the second metal layer 145 is, for example, a copper layer.

[0078] Next, please refer to Figure 2E, a second patterned photoresist layer P2' is formed on the second metal layer 145, wherein the second patterned photoresist layer P2' is located above the first patterned photoresist layer P1' and exposes a portion of the second metal layer 145. Here, the pattern of the first patterned photoresist layer P1' is different from the pattern of the second patterned photoresist layer P2'.

[0079] Next, please refer to Figure 2F The second metal layer 145 is used as a plating seed layer to perform an electroplating process to form a conductive material layer 150 a ′ on the second patterned photoresist layer P2 ′ and on the exposed second metal layer 145 .

[0080] Next, please also refer to Figure 2F and Figure 2G , the first patterned photoresist layer P1', the second patterned photoresist layer P2', a portion of the first metal layer 140 and a portion of the second metal layer 145 are removed to form a circuit structure layer 150' and expose the metal layer 120'. The circuit structure layer 150' includes a patterned circuit 152' and a plurality of conductive vias 154', wherein the patterned circuit 152' is electrically connected to the electrode 132 of the chip 130 through the conductive vias 154'. Here, the conductive vias 154' are formed by the remaining first metal layer 140, the remaining second metal layer 145 and a portion of the conductive material layer 150a'. At this point, the circuit structure layer 150' has been formed on the carrier 110b.

[0081] Afterwards, please refer to Figure 2H , forming an encapsulation body 160 ′ to cover the active surface 131 of the chip 130 and the circuit structure layer 150 ′, wherein the active surface 131 of the chip 130 and the bottom surface 162 ′ of the encapsulation body 160 ′ are coplanar.

[0082] Finally, please also refer to Figure 2H and Fig.2I When the carrier 110b is removed, the conductive bumps T on the bottom surface 162' of the encapsulant 160' and a portion of the metal layer 120' on the back surface 133 of the chip 130 are exposed. Here, the encapsulant 160' covers the metal layer 120' and the active surface 131 of the chip 130, and encapsulates the patterned circuits 152' and the conductive vias 154'.

[0083] Here, the method of removing the carrier 110b is, for example, placing the packaging colloid 160' downward on a vacuum platform (not shown), and utilizing vacuum to absorb the packaging colloid 160'. In addition, the packaging colloid 160' is fixed by a mechanism, and is separated from the metal layer 120' located on the carrier 110b along the interface with the stainless steel layer 114. Compared to the conventional method of removing the carrier, the carrier 110b of this embodiment does not need to be cut, so the carrier 110b can be reused, thereby effectively saving manufacturing costs. In addition, the method of removing the metal layer 120' is, for example, etching. At this point, the production of the quad flat no-lead (QFN) type chip packaging structure 100b1 has been completed.

[0084] In terms of structure, please refer to Fig.2I , the chip packaging structure 100b1 includes a circuit structure layer 150', a chip 130 and a packaging colloid 160'. The circuit structure layer 150' includes a patterned circuit 152' and a conductive through hole 154'. The chip 130 has an active surface 131 and a back surface 133 opposite to each other and an electrode 132 disposed on the active surface 131. The patterned circuit 152' is electrically connected to the electrode 132 of the chip 130 through the conductive through hole 154'. The packaging colloid 160' covers the active surface 131 of the chip 130 and the circuit structure layer 150'. In particular, the active surface 131 of the chip 130 is coplanar with the bottom surface 162' of the packaging colloid 160'. In addition, the chip packaging structure 100b1 of the present embodiment also includes a conductive bump T, wherein the conductive bump T is disposed on the bottom surface 162' of the packaging colloid 160' and is electrically connected to the patterned circuit 152' through the conductive through hole 154.

[0085] Figure 2J A schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention is shown. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0086] Please refer to Figure 2J ,At Fig.2I After the step of forming the surface treatment layer 170', a surface treatment layer 170' may be formed on the surrounding surface S of the conductive bump T and the metal layer 120' on the back surface 133 of the chip 130. Here, the material of the surface treatment layer 170' is, for example, tin, but not limited thereto. Thus, the manufacturing of the chip package structure 100b2 of the quad flat no-lead (QFN) type has been completed.

[0087] Since the chip package structure 100b2 of the present embodiment has a surface treatment layer 170' disposed on the back surface 133 of the chip 130, the side surface 135 connecting the back surface 133 and the active surface 131, and the surrounding surface S of the conductive bump T, the surface treatment layer 170' can directly serve as a shielding layer to prevent electromagnetic interference. Compared with the conventional method of additionally setting a shielding plate or a grounding plate, the chip package structure 100b2 of the present embodiment can have a thinner package thickness and reduce the process cost.

[0088] In summary, in the manufacturing method of the chip packaging structure of the present invention, a stainless steel layer is formed on the substrate of the carrier by sputtering, so that good stability can be provided during the manufacturing process of the circuit structure layer. Furthermore, the stainless steel layer formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and is safer and simpler to operate. In addition, when separating the carrier to expose the circuit structure layer, no cutting is required, so the carrier can be reused, thereby effectively saving manufacturing costs. In addition, in some embodiments of the chip packaging structure of the present invention, a surface treatment layer can also be added as a shielding layer to prevent electromagnetic interference, which can have a thinner packaging thickness and reduce process costs.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a chip packaging structure, characterized in that: include: Providing a carrier having an accommodating groove and comprising a substrate and a stainless steel layer sputtered on the substrate; Arrange a chip in the receiving groove of the carrier, wherein the chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface; Forming a circuit structure layer on the carrier, wherein the circuit structure layer includes a patterned circuit and a plurality of conductive through holes, and the patterned circuit is electrically connected to the plurality of electrodes of the chip through the plurality of conductive through holes; Forming a packaging colloid to cover the active surface of the chip and the circuit structure layer, wherein the active surface of the chip is coplanar with the bottom surface of the packaging colloid; as well as The carrier board is removed to expose the circuit structure layer.

2. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The material of the substrate includes a sheet-shaped glass fiber resin substrate, a roll-shaped glass fiber resin substrate or a roll-shaped stainless steel substrate.

3. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: Also includes: Before disposing the chip in the receiving groove of the carrier, forming a metal layer on the stainless steel layer; as well as When the carrier is removed, the metal layer is removed at the same time.

4. The method for manufacturing a chip packaging structure according to claim 3, characterized in that: The step of forming the circuit structure layer on the carrier includes: Forming a first patterned photoresist layer on the metal layer, wherein the first patterned photoresist layer exposes the plurality of electrodes of the chip and a portion of the metal layer; Sputtering a first metal layer and a second metal layer on the first metal layer on the first patterned photoresist layer and on the plurality of electrodes of the chip and the metal layer exposed thereby; forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer and exposes a portion of the second metal layer; performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the second metal layer exposed therefrom; and The first patterned photoresist layer, the second patterned photoresist layer, a portion of the first metal layer and a portion of the second metal layer are removed to form the circuit structure layer and expose the metal layer, wherein the patterned circuit of the circuit structure layer includes a plurality of inner pins and a plurality of outer pins, the plurality of inner pins are separated from each other and located above the chip, and the plurality of outer pins are connected to the plurality of inner pins and extend to be arranged on the metal layer.

5. The method for manufacturing a chip packaging structure according to claim 4, characterized in that: The packaging colloid covers a portion of the metal layer and the active surface of the chip, and encapsulates the plurality of inner pins and the plurality of conductive through holes.

6. The method for manufacturing a chip packaging structure according to claim 5, characterized in that: Also includes: When the carrier is removed, the metal layer on the back side of the chip is exposed; as well as A surface treatment layer is formed on the metal layer on the back side of the chip.

7. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The carrier plate also has a plurality of notches, wherein the plurality of notches surround the accommodating groove, and the stainless steel layer is conformally disposed with the substrate.

8. The method for manufacturing a chip packaging structure according to claim 7, characterized in that: Also includes: Before disposing the chip in the receiving groove of the carrier, a metal layer is formed on the stainless steel layer, wherein the metal layer fills the plurality of recesses to define a plurality of conductive bumps; as well as When the carrier is removed, the plurality of conductive bumps on the bottom surface of the packaging body and a portion of the metal layer on the back surface of the chip are exposed at the same time.

9. The method for manufacturing a chip packaging structure according to claim 8, characterized in that: The step of forming the circuit structure layer on the carrier includes: Forming a first patterned photoresist layer on the metal layer, wherein the first patterned photoresist layer exposes the plurality of electrodes of the chip and a portion of the metal layer; Sputtering a first metal layer and a second metal layer on the first metal layer on the first patterned photoresist layer and on the plurality of electrodes of the chip and the metal layer exposed thereby; forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer and exposes a portion of the second metal layer; performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the second metal layer exposed therefrom; and The first patterned photoresist layer, the second patterned photoresist layer, a portion of the first metal layer and a portion of the second metal layer are removed to form the circuit structure layer and expose the metal layer.

10. The method for manufacturing a chip packaging structure according to claim 9, characterized in that: The packaging colloid covers the metal layer and the active surface of the chip, and encapsulates the patterned circuit and the plurality of conductive through holes.

11. The method for manufacturing a chip packaging structure according to claim 10, characterized in that: Also includes: After removing the carrier, a surface treatment layer is formed on the peripheral surfaces of the plurality of conductive bumps and on the metal layer on the back side of the chip.

12. A chip packaging structure, characterized in that: include: A circuit structure layer, including a patterned circuit and a plurality of conductive vias; A chip having an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface, wherein the patterned circuit is electrically connected to the plurality of electrodes of the chip through the plurality of conductive through holes; as well as A packaging colloid covers the active surface of the chip and the circuit structure layer, wherein the active surface of the chip is coplanar with the bottom surface of the packaging colloid, the patterned circuit includes a plurality of inner pins and a plurality of outer pins, the plurality of inner pins are separated from each other and are located above the chip, the packaging colloid covers the plurality of inner pins and the plurality of conductive through holes, and the plurality of outer pins connect the plurality of inner pins and extend outside the packaging colloid.

13. The chip packaging structure according to claim 12, characterized in that: Also includes: The surface treatment layer is disposed on the back surface of the chip and on the metal layer on the side surface connecting the back surface and the active surface.

14. The chip packaging structure according to claim 12, characterized in that: Also includes: A plurality of conductive bumps are disposed on the bottom surface of the packaging colloid and are electrically connected to the patterned circuit through the plurality of conductive through holes.

15. The chip packaging structure according to claim 14, characterized in that: Also includes: The surface treatment layer is disposed on the back surface of the chip, the side surface connecting the back surface and the active surface, and the surrounding surface of the plurality of conductive bumps.

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