Semiconductor packaging

Abstract

The present invention provides a semiconductor package, which includes: a support portion; a semiconductor chip arranged on the support portion and including a plurality of signal pads; a buffer layer arranged on the semiconductor chip; an adhesive layer arranged on the buffer layer; a decompression layer arranged on the adhesive layer; and a molding layer arranged on the decompression layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor package. Background Art

[0002] The semiconductor package is mounted on a substrate and manufactured into various types of semiconductor devices.

[0003] Such a semiconductor package includes a semiconductor chip and a molding layer formed on the semiconductor chip.

[0004] A large number of circuit elements performing predetermined functions are formed in a semiconductor chip.

[0005] The mold layer is formed on the upper surface of the semiconductor chip to protect the semiconductor chip. The mold layer is formed on the upper surface of the semiconductor chip under high pressure, and thus, a high pressure is applied to the semiconductor chip in a process of forming the mold layer.

[0006] However, when a high voltage is applied to a semiconductor chip during a manufacturing process, the high voltage is transferred to a circuit element formed in the semiconductor chip, and thus the electrical characteristics of the circuit element may change. More specifically, when a high voltage is applied to a circuit element, a signal error may occur in the circuit element due to the occurrence of a piezoelectric phenomenon. Summary of the invention

[0007] Technical issues

[0008] The present invention is directed to a semiconductor package capable of reducing the occurrence of a piezoelectric phenomenon in a circuit element of a semiconductor chip in a process of forming a molding layer.

[0009] Problems to be solved according to the embodiments of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art through the following description.

[0010] Technical Solution

[0011] An embodiment of the present invention provides a semiconductor package, which includes: a supporting portion; a semiconductor chip disposed on the supporting portion and including a plurality of signal pads; a buffer layer disposed on the semiconductor chip; an adhesive layer disposed on the buffer layer; a decompression layer disposed on the adhesive layer; and a molding layer disposed on the decompression layer.

[0012] Another embodiment of the present invention provides a semiconductor package, which includes: a supporting portion; a first semiconductor chip and a second semiconductor chip disposed on the supporting portion and each including a plurality of signal pads; a plurality of electrode pads disposed outside the supporting portion and spaced apart from the supporting portion; wires, the wires including a first wire connecting one of the signal pads of the first semiconductor chip with one of the signal pads of the second semiconductor chip, a second wire connecting another signal pad of the first semiconductor chip with one of the electrode pads, and a third wire connecting another signal pad of the second semiconductor chip with another electrode pad; a buffer layer disposed on the first semiconductor chip; an adhesive layer disposed on the buffer layer; a pressure relief layer disposed on the adhesive layer; and a molding layer disposed on the pressure relief layer.

[0013] The present invention also provides a battery management system including the above-mentioned semiconductor package, wherein the second semiconductor chip is provided with a voltage sensing unit, and the first semiconductor chip is provided with a microcontroller, which receives a sensing voltage from the voltage sensing unit and converts the sensing voltage into voltage information data as digital data to send the voltage information data to a main controller.

[0014] Beneficial Effects

[0015] According to an embodiment of the present invention, a decompression layer is formed on a semiconductor chip, so that the pressure applied to the circuit elements formed in the semiconductor chip can be reduced, and the signal error of the circuit elements due to the piezoelectric phenomenon can be minimized. In addition, according to an embodiment of the present invention, a buffer layer is further provided between the semiconductor chip and the decompression layer, so that the pressure applied to the circuit elements formed in the semiconductor chip can be minimized, and the signal error of the circuit elements due to the piezoelectric phenomenon can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic top view of a semiconductor package according to an embodiment of the present invention.

[0017] Figure 2 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0018] Figure 3 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.

[0019] Figure 4 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.

[0020] Figure 5 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.

[0021] Figure 6 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.

[0022] Figure 7a is a block diagram of a battery management system that can be applied to the semiconductor package of the present invention, Figure 7b is a block diagram of a slave controller of a battery management system that can be applied to the semiconductor package of the present invention. DETAILED DESCRIPTION

[0023] Throughout the specification, the same reference numerals represent substantially the same components. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the main points of the present invention, its detailed description is omitted. In addition, the component names used in the following description may be selected in consideration of the convenience of writing the specification, and may be different from the actual product component names.

[0024] The advantages and features of the present invention and the methods for achieving the advantages and features will be apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments of the present invention make the disclosure of the present invention complete, and provide the embodiments of the present invention to fully convey the scope of the present invention to those skilled in the art to which the present invention belongs, and the present invention is limited only by the scope of the claims.

[0025] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to describe the embodiments of the present invention are exemplary, and therefore the present invention is not limited to the contents shown. Throughout the specification, the same reference numerals represent the same components. In addition, in the description of the present invention, when it is determined that the detailed description of the known related art may unnecessarily obscure the main points of the present invention, its detailed description will be omitted.

[0026] When interpreting parts, they should be interpreted as including the error range even if there is no other clear description.

[0027] Each feature of the various embodiments of the present invention may be coupled or combined with each other in part or in whole, various interlocks and drives are technically possible, and each embodiment may be performed independently relative to each other or may be performed together in a related relationship.

[0028] Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a schematic top view of a semiconductor package according to an embodiment of the present invention.

[0030] like Figure 1As shown in , a semiconductor package according to an embodiment of the present invention includes a support part 100 , a semiconductor chip 200 , a plurality of electrode pads 300 , a plurality of wires 400 , a buffer layer 500 , a decompression layer 600 , and a mold layer 700 .

[0031] The support part 100 supports the semiconductor chip 200. The support part 100 is provided to have an area larger than that of the semiconductor chip 200 while overlapping the semiconductor chip 200. The support part 100 may be formed in a shape corresponding to the semiconductor chip 200. For example, when the semiconductor chip 200 is formed in a predetermined quadrilateral shape, the support part 100 may be formed in a quadrilateral shape corresponding to the semiconductor chip 200, but the present invention is not limited thereto.

[0032] The support portion 100 may additionally perform a heat dissipation function, and to this end, the support portion 100 may be made of a metal material having an excellent heat dissipation effect, such as copper (Cu).

[0033] The semiconductor chip 200 may be disposed in a central region of the semiconductor package. The semiconductor chip 200 may be formed of various driving chips for driving a display device, but the present invention is not limited thereto.

[0034] The semiconductor chip 200 is provided with a plurality of signal pads 210. The plurality of signal pads 210 are arranged to be spaced apart from each other in an outer region of the semiconductor chip 200. The plurality of signal pads 210 include a plurality of input signal pads for inputting various signals provided from an external device to a circuit element in the semiconductor chip 200 and a plurality of output signal pads for outputting various signals generated by the circuit element in the semiconductor chip 200 to an external device. The types and positions of the input signal pads and the output signal pads may be changed in various forms known in the art.

[0035] The plurality of electrode pads 300 are disposed to be spaced apart from each other in the outer region of the semiconductor package. The plurality of electrode pads 300 may be formed in a number corresponding to the number of the plurality of signal pads 210 of the semiconductor chip 200, but the present invention is not limited thereto. Similar to the plurality of signal pads 210, the plurality of electrode pads 300 may include a plurality of input electrode pads and a plurality of output electrode pads.

[0036] The plurality of wires 400 electrically connect the plurality of signal pads 210 and the plurality of electrode pads 300 of the semiconductor chip 200. One signal pad 210 and one electrode pad 300 may be electrically connected one-to-one through the wires 400. However, the present invention is not limited thereto, and one wire 400 connected to one signal pad 210 may also be electrically connected to a plurality of electrode pads 300, and a plurality of wires 400 respectively connected to a plurality of signal pads 210 may also be electrically connected to one electrode pad 300.

[0037] The buffer layer 500 is formed on the semiconductor chip 200. The buffer layer 500 may be formed to have a shape corresponding to the shape of the semiconductor chip 200. Specifically, the outermost line of the buffer layer 500 may coincide with the outermost line of the semiconductor chip 200. However, the buffer layer 500 is provided with a plurality of first opening regions 510 to allow the signal pads 210 of the semiconductor chip 200 to be exposed to the outside. That is, the plurality of first opening regions 510 may be formed in a shape corresponding to the plurality of signal pads 210 at positions corresponding to the plurality of signal pads 210.

[0038] The buffer layer 500 is disposed between the semiconductor chip 200 and the decompression layer 600 to prevent the lower surface of the decompression layer 600 from directly contacting the upper surface of the semiconductor chip 200. Therefore, according to an embodiment of the present invention, the buffer layer 500 is further disposed between the semiconductor chip 200 and the decompression layer 600, so that the pressure applied to the circuit elements formed in the semiconductor chip 200 is minimized, and the signal error of the circuit elements due to the piezoelectric phenomenon can be minimized.

[0039] Meanwhile, the buffer layer 500 may also serve to protect the peripheral region of the semiconductor chip 200 not overlapping the decompression layer 600. The buffer layer 500 may be made of an insulating material, and in particular, may be made of an organic insulating material such as polyimide in terms of a buffering effect.

[0040] The decompression layer 600 may be formed to have a shape corresponding to the semiconductor chip 200 while overlapping the semiconductor chip 200, but the present invention is not limited thereto. The decompression layer 600 is formed on the semiconductor chip 200, and the decompression layer 600 is formed not to overlap with the plurality of signal pads 210 so as to allow the plurality of signal pads 210 of the semiconductor chip 200 to be exposed to the outside. Therefore, the decompression layer 600 may be formed in an area that is closer to the inside than the plurality of signal pads 210 while having an area smaller than that of the semiconductor chip 200.

[0041] The decompression layer 600 is used to absorb high voltage generated when forming the mold layer 700 or to prevent high voltage from being directly applied to the semiconductor chip 200. As described above, according to an embodiment of the present invention, the pressure applied to the circuit elements formed in the semiconductor chip 200 is reduced by forming the decompression layer 600 on the semiconductor chip 200, so that signal errors of the circuit elements due to the piezoelectric phenomenon can be minimized.

[0042] Since the decompression layer 600 is formed on the semiconductor chip 200, when the difference between the deformation of the decompression layer 600 and the deformation of the semiconductor chip 200 becomes large at high temperature, the problem of deformation of the semiconductor chip 200 may occur due to the decompression layer 600. When considering this point, it may be preferred that the deviation between the thermal expansion coefficient of the decompression layer 600 and the thermal expansion coefficient of the semiconductor chip 200 is within ±10. For example, when considering the thermal expansion coefficient of the semiconductor chip 200 made of a silicon wafer, it may be preferred that the thermal expansion coefficient of the decompression layer 600 is 2.6ppm / ℃ to 3.0ppm / ℃. In particular, it is most preferred that the thermal expansion coefficient of the decompression layer 600 and the thermal expansion coefficient of the semiconductor chip 200 are the same, and in this case, the decompression layer 600 can be made of the same material as the semiconductor chip 200. For example, the decompression layer 600 can be made of an unprocessed silicon wafer in which a circuit element forming process is not performed.

[0043] The mold layer 700 may be formed to define an outer shape of the semiconductor package. The mold layer 700 may be made of various materials known in the art.

[0044] Figure 2 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0045] like Figure 2 As shown in , the semiconductor package according to the embodiment of the present invention includes a support part 100 , a semiconductor chip 200 , a plurality of electrode pads 300 , a plurality of wires 400 , a buffer layer 500 , a decompression layer 600 , a mold layer 700 , and adhesive layers 810 and 820 .

[0046] The support part 100 is disposed under the semiconductor chip 200 to support the semiconductor chip 200. Although not shown, a heat sink may be additionally configured on a lower surface of the support part 100 to more easily dissipate heat generated from the semiconductor chip 200 to the outside.

[0047] The semiconductor chip 200 is formed on the support part 100 and fixed to the upper surface of the support part 100 by the first adhesive layer 810. A plurality of signal pads 210 are formed in the outer region of the upper surface of the semiconductor chip 200. The plurality of signal pads 210 are electrically connected to the plurality of electrode pads 300 through the plurality of wires 400. Therefore, the upper surfaces of the plurality of signal pads 210 are exposed without being covered by the buffer layer 500 for connection with the plurality of wires 400.

[0048] The plurality of electrode pads 300 are arranged to be spaced apart from each other in the peripheral region of the semiconductor package. That is, the plurality of electrode pads 300 are arranged to be spaced apart from the support portion 100 outside the support portion 100. In particular, the plurality of electrode pads 300 may be arranged on the outermost line of the semiconductor package. The plurality of electrode pads 300 may be arranged at the same height as the support portion 100, but the present invention is not limited thereto.

[0049] The plurality of wires 400 are connected between the plurality of signal pads 210 and the plurality of electrode pads 300 of the semiconductor chip 200. That is, one end of each of the wires 400 is connected to each of the plurality of signal pads 210, and the other end of each of the wires 400 is connected to each of the electrode pads 300.

[0050] The buffer layer 500 is disposed on the upper surface of the semiconductor chip 200. The lower surface of the buffer layer 500 contacts the upper surface of the semiconductor chip 200.

[0051] The buffer layer 500 may be formed on the entire upper surface of the semiconductor chip 200 except for the region overlapping with the plurality of signal pads 210. That is, the buffer layer 500 is provided with a first opening region 510 in the region of each of the plurality of signal pads 210 so that the plurality of signal pads 210 may be exposed. The first opening region 510 is formed to penetrate from the upper surface of the buffer layer 500 to the lower surface. In addition, one end (e.g., the left end) of the buffer layer 500 may be consistent with one end (e.g., the left end) of the semiconductor chip 200, and the other end (e.g., the right end) of the buffer layer 500 may be consistent with the other end (e.g., the right end) of the semiconductor chip 200.

[0052] In order to facilitate the connection between multiple signal pads 210 and multiple wires 400, the thickness of the buffer layer 500 can be configured to be smaller than the thickness of the signal pads 210, so that at least a portion of the signal pads 210 are exposed to the outside of the buffer layer 500, and the upper surface of the signal pads 210 can be formed at a position higher than the upper surface of the buffer layer 500.

[0053] The decompression layer 600 is formed on the buffer layer 500 and is fixed to the upper surface of the buffer layer 500 by the second adhesive layer 820. The decompression layer 600 is formed so as not to overlap with the plurality of signal pads 210. Therefore, one end (e.g., the left end) of the decompression layer 600 does not coincide with one end (e.g., the left end) of each of the buffer layer 500 and the semiconductor chip 200, and the other end (e.g., the right end) of the decompression layer 600 does not coincide with the other end (e.g., the right end) of each of the buffer layer 500 and the semiconductor chip 200.

[0054] In order to absorb the high voltage generated when the molding layer 700 is formed or to prevent the high voltage from being directly applied to the semiconductor chip 200, it is preferred that the decompression layer 600 has a predetermined thickness. It may be preferred that the decompression layer 600 has a thickness of half or more of the thickness of the semiconductor chip 200. In addition, as the thickness of the decompression layer 600 increases, the absorption or blocking effect of the high voltage can be increased, but when the thickness of the decompression layer 600 increases too much, the thickness of the semiconductor package becomes too thick, which is not preferred. When considering this point, it may be preferred that the thickness of the decompression layer 600 is equal to or less than the thickness of the semiconductor chip 200. When considering the thickness range of the conventional ordinary semiconductor chip 200, it is preferred that the thickness of the decompression layer 600 is in the range of 200μm to 500μm.

[0055] The mold layer 700 is formed on the support part 100, the semiconductor chip 200, the plurality of electrode pads 300, the plurality of wires 400, the buffer layer 500, and the decompression layer 600. The mold layer 700 may be formed by a high pressure injection process.

[0056] The adhesive layers 810 and 820 include a first adhesive layer 810 and a second adhesive layer 820. The first adhesive layer 810 is disposed between the support part 100 and the semiconductor chip 200 to adhere the support part 100 and the semiconductor chip 200. The second adhesive layer 820 is disposed between the buffer layer 500 and the decompression layer 600 to adhere the buffer layer 500 and the decompression layer 600.

[0057] The second adhesive layer 820 is formed so as not to overlap with the plurality of signal pads 210. Therefore, one end (e.g., the left end) of the second adhesive layer 820 does not coincide with one end (e.g., the left end) of each of the buffer layer 500 and the semiconductor chip 200, and the other end (e.g., the right end) of the second adhesive layer 820 does not coincide with the other end (e.g., the right end) of each of the buffer layer 500 and the semiconductor chip 200. The second adhesive layer 820 may be formed in the same pattern as the decompression layer 600.

[0058] Figure 3 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention, which is similar to the semiconductor package according to the above Figure 2 The semiconductor package of FIG. 5 is different in that the configuration of the buffer layer 500 is changed. Therefore, the same reference numerals are assigned to the same configuration, and the different configurations will be described below.

[0059] like Figure 3As shown in the figure, the semiconductor chip 200 is provided with a first circuit region 251, a second circuit region 252, and a third circuit region 253. The first circuit region 251, the second circuit region 252, and the third circuit region 253 are circuit regions formed inside the semiconductor chip 200, and are composed of circuit elements that perform different functions according to the semiconductor chip 200. Meanwhile, although only the first to third circuit regions 251, 252, and 253 are shown in the drawings, the semiconductor chip 200 may be additionally provided with more circuit regions.

[0060] The first circuit region 251 is provided with circuit elements that are sensitive to external pressing force and thus have a high probability of generating signal errors due to piezoelectric phenomena, and the second circuit region 252 and the third circuit region 253 are provided with circuit elements that are insensitive to external pressing force and thus have a small or no probability of generating signal errors due to piezoelectric phenomena. Specifically, a bandgap reference circuit or an amplifier circuit may be provided in the first circuit region 251, and the second circuit region 252 and the third circuit region 253 may be provided with other circuits.

[0061] The buffer layer 500 disposed on the upper surface of the semiconductor chip 200 includes a first opening region 510 in a region corresponding to the signal pad 210 and a second opening region 520 in a region corresponding to the first circuit region 251. Like the first opening region 510, the second opening region 520 is formed to penetrate from the upper surface to the lower surface of the buffer layer 500.

[0062] Since the buffer layer 500 includes the second opening region 520, the hole H may be formed in the space between the buffer layer 500, the second adhesive layer 820, and the semiconductor chip 200. When a solid adhesive film is used as the second adhesive layer 820, the second opening region 520 may be left without being filled by the second adhesive layer 820, and thus, the second opening region 520 may remain as the hole H. That is, the hole H may be a space defined by the buffer layer 500, the second adhesive layer 820, and the semiconductor chip 200.

[0063] As described above, according to another embodiment of the present invention, since the buffer layer 500 includes the second opening area 520, when the molding layer 700 is formed, the pressure directly applied to the first circuit area 251 corresponding to the second opening area 520 can be reduced, and therefore, the signal error caused by the piezoelectric phenomenon in the first circuit area 251 can be further reduced.

[0064] Figure 4 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention, which is similar to the above Figure 3The difference is that the hole H is not formed in the second opening area 520. Therefore, the same reference numerals are assigned to the same configuration, and the different configurations will be described below.

[0065] according to Figure 4 , the buffer layer 500 includes a second opening region 520 in a region corresponding to the first circuit region 251. At this time, when the second adhesive layer 820 formed on the buffer layer 500 has a predetermined viscosity and a thickness greater than that of the buffer layer 500, the second opening region 520 may be filled with the second adhesive layer 820 due to pressure applied from the upper side when the molding layer 700 is formed, and therefore, the hole H is not formed in the second opening region 520.

[0066] When the hole H is not formed in the second opening region 520 and is filled with the second adhesive layer 820 , the adhesive force between the semiconductor chip 200 and the decompression layer 600 may be more excellent, and there is an advantage that the problem of expansion or contraction of the hole H does not occur in the future.

[0067] Figure 5 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention, which is similar to the above Figure 3 and Figure 4 The difference is that a portion of the second opening area 520 is filled with the second adhesive layer 820, and at least one hole H is formed in the remaining portion of the second opening area 520. Therefore, the same reference numerals are assigned to the same configuration, and the different configurations will be described below.

[0068] according to Figure 5 , the buffer layer 500 includes a second opening region 520 in a region corresponding to the first circuit region 251. At this time, when the second adhesive layer 820 formed on the buffer layer 500 has a predetermined viscosity and a thickness greater than that of the buffer layer 500, the second opening region 520 may be filled with the second adhesive layer 820 due to pressure applied from the upper side when the molding layer 700 is formed.

[0069] However, the entirety of the second opening region 520 may not be filled with the second adhesive layer 820, but a portion of the second opening region 520 may be filled. Therefore, at least one fine hole H may be formed in the remaining portion of the second opening region 520. The fine hole H may be formed in the space between the second adhesive layer 820 and the semiconductor chip 200.

[0070] Figure 6 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the present invention.

[0071] like Figure 6As shown in , a semiconductor package according to still another embodiment of the present invention includes a support part 100, semiconductor chips 200a and 200b, a plurality of electrode pads 300, a plurality of conductive lines 400a, 400b and 400c, a buffer layer 500, a decompression layer 600, a molding layer 700, and adhesive layers 810, 820 and 830.

[0072] The support part 100 is disposed under the first and second semiconductor chips 200a and 200b to support the first and second semiconductor chips 200a and 200b. Although not shown, a heat sink may be additionally configured on the lower surface of the support part 100 to more easily dissipate heat generated from the semiconductor chips 200 to the outside.

[0073] The semiconductor chips 200 a and 200 b include a first semiconductor chip 200 a formed on a first region A of the support portion 100 and a second semiconductor chip 200 b formed on a second region B of the support portion 100 .

[0074] The first semiconductor chip 200 a is fixed to the upper surface of the first region A of the support part 100 through the first adhesive layer 810 , and the second semiconductor chip 200 b is fixed to the upper surface of the second region B of the support part 100 through the third adhesive layer 830 .

[0075] A plurality of signal pads 210 are formed in the outer region of the upper surface of each of the first semiconductor chip 200a and the second semiconductor chip 200b. The plurality of signal pads 210 are electrically connected to the plurality of electrode pads 300 through a plurality of wires 400a, 400b and 400c. The upper surfaces of the plurality of signal pads 210 disposed on the first semiconductor chip 200a are exposed without being covered by the buffer layer 500 for connection with the first wire 400a and the second wire 400b. In addition, the upper surfaces of the plurality of signal pads 210 disposed on the second semiconductor chip 200b are also exposed for connection with the first wire 400a and the third wire 400c.

[0076] The first semiconductor chip 200a is provided with a circuit element that is sensitive to the reaction of the external pressing force and thus has a high possibility of generating a signal error due to the piezoelectric phenomenon, so the buffer layer 500 and the decompression layer 600 are provided on the upper surface of the first semiconductor chip 200a. On the other hand, the second semiconductor chip 200b is provided with a circuit element that is insensitive to the reaction of the external pressing force and thus has a small or no possibility of generating a signal error due to the piezoelectric phenomenon, so the buffer layer 500 and the decompression layer 600 are not provided on the upper surface of the second semiconductor chip 200b. For example, the first semiconductor chip 200a may include an analog front end (AFE), and the second semiconductor chip 200b may include a microcontroller unit (MCU), but the present invention is not necessarily limited thereto.

[0077] The plurality of electrode pads 300 are arranged to be spaced apart from each other in the peripheral region of the semiconductor package. That is, the plurality of electrode pads 300 are arranged to be spaced apart from the support portion 100 outside the support portion 100. In particular, the plurality of electrode pads 300 may be arranged on the outermost line of the semiconductor package. The plurality of electrode pads 300 may be arranged at the same height as the support portion 100, but the present invention is not limited thereto.

[0078] The plurality of wires 400a, 400b, and 400c connect the plurality of signal pads 210 of the semiconductor chips 200a and 200b with the plurality of electrode pads 300. The plurality of wires 400a, 400b, and 400c include a first wire 400a, a second wire 400b, and a third wire 400c.

[0079] The first wire 400a connects the signal pad 210 disposed on one side (e.g., the left side) of the first semiconductor chip 200a to the signal pad 210 disposed on one side (e.g., the right side) of the second semiconductor chip 200b. The second wire 400b connects the signal pad 210 disposed on the other side (e.g., the right side) of the first semiconductor chip 200a to the electrode pad 300 disposed on one side (e.g., the right side) of the semiconductor package. The third wire 400c connects the signal pad 210 disposed on the other side (e.g., the left side) of the second semiconductor chip 200b to the electrode pad 300 disposed on one side (e.g., the left side) of the semiconductor package.

[0080] The buffer layer 500 is disposed on the upper surface of the first semiconductor chip 200a. That is, the lower surface of the buffer layer 500 contacts the upper surface of the first semiconductor chip 200a.

[0081] The buffer layer 500 may be formed on the entire upper surface of the first semiconductor chip 200a except for the region overlapping with the plurality of signal pads 210 of the first semiconductor chip 200a. That is, the buffer layer 500 is provided with a first opening region 510 in the region of each of the plurality of signal pads 210 of the first semiconductor chip 200a, and one end (e.g., the left end) of the buffer layer 500 may be consistent with one end (e.g., the left end) of the first semiconductor chip 200a, and the other end (e.g., the right end) of the buffer layer 500 may be consistent with the other end (e.g., the right end) of the first semiconductor chip 200a. The first opening region 510 is formed to penetrate from the upper surface of the buffer layer 500 to the lower surface. In addition, in order to facilitate the connection between multiple signal pads 210 and the first and second wires 400a and 400b, the thickness of the buffer layer 500 can be configured to be smaller than the thickness of the signal pads 210 of the first semiconductor chip 200a, and thus, the upper surface of the signal pads 210 can be formed at a position higher than the upper surface of the buffer layer 500.

[0082] The decompression layer 600 is formed on the buffer layer 500 and is fixed to the upper surface of the buffer layer 500 by the second adhesive layer 820. The decompression layer 600 is formed so as not to overlap with the plurality of signal pads 210 of the first semiconductor chip 200a. Therefore, one end (e.g., the left end) of the decompression layer 600 does not coincide with one end (e.g., the left end) of each of the buffer layer 500 and the first semiconductor chip 200a, and the other end (e.g., the right end) of the decompression layer 600 does not coincide with the other end (e.g., the right end) of each of the buffer layer 500 and the first semiconductor chip 200a.

[0083] It is preferable that the thickness of the decompression layer 600 is half or more of the thickness of the first semiconductor chip 200a and is equal to or less than the thickness of the first semiconductor chip 200a. Specifically, it is preferable that the thickness of the decompression layer 600 is in the range of 200 μm to 500 μm.

[0084] The mold layer 700 is formed on the support part 100 , the first and second semiconductor chips 200 a and 200 b , the plurality of electrode pads 300 , the first, second and third conductive lines 400 a , 400 b and 400 c , the buffer layer 500 , and the decompression layer 600 .

[0085] The adhesive layers 810, 820, and 830 include a first adhesive layer 810, a second adhesive layer 820, and a third adhesive layer 830. The first adhesive layer 810 is disposed between the support portion 100 and the first semiconductor chip 200a to adhere the first semiconductor chip 200a to the support portion 100. The second adhesive layer 820 is disposed between the buffer layer 500 and the decompression layer 600 to adhere the decompression layer 600 to the buffer layer 500. The third adhesive layer 830 is disposed between the support portion 100 and the second semiconductor chip 200b to adhere the second semiconductor chip 200b to the support portion 100.

[0086] The second adhesive layer 820 is formed so as not to overlap with the plurality of signal pads 210 of the first semiconductor chip 200a. Therefore, one end (e.g., the left end) of the second adhesive layer 820 does not coincide with one end of each of the buffer layer 500 and the first semiconductor chip 200a, and the other end (e.g., the right end) of the second adhesive layer 820 does not coincide with the other end (e.g., the right end) of each of the buffer layer 500 and the first semiconductor chip 200a. The second adhesive layer 820 may be formed in the same pattern as the decompression layer 600.

[0087] As described above, according to another embodiment of the present invention, by separating circuit elements that are sensitive to external pressing force and therefore have a high possibility of generating signal errors due to piezoelectric phenomena from circuit elements that have a small or no possibility of generating signal errors, and forming a buffer layer 500 and a decompression layer 600 only on the upper surface of a first semiconductor chip 200a including circuit elements with a high possibility of generating signal errors among a plurality of semiconductor chips 200a and 200b formed on a support portion 100, an increase in process and cost caused by the formation of the buffer layer 500 and the decompression layer 600 can be minimized.

[0088] However, in some cases, the buffer layer 500 and the decompression layer 600 may also be formed on the upper surface of the second semiconductor chip 200 b having a small possibility of generating a signal error.

[0089] Meanwhile, although not specifically shown, the configuration of the buffer layer 500 and the second adhesive layer 820 formed on the upper surface of the first semiconductor chip 200a may be as described above. Figures 3 to 5 Make various changes as shown. That is, Figure 3 As shown, a second opening region 520 may be additionally provided in the buffer layer 500, and a hole H may be formed in the second opening region 520; Figure 4 As shown, since the hole H is completely filled with the second adhesive layer 820, the hole H may not be formed in the second opening area 520; and Figure 5As shown, a portion of the second open region 520 may be filled with the second adhesive layer 820 , and at least one hole H may be formed in the remaining portion of the second open region 520 .

[0090] Figure 7a is a block diagram of a battery management system that can be applied to the semiconductor package of the present invention, Figure 7b is a block diagram of a slave controller of a battery management system that can be applied to the semiconductor package of the present invention.

[0091] like Figure 7a As shown in , a battery management system (BMS) includes a master controller 1000 , a slave controller group 2000 , a bus line 3000 , and a battery cell group 4000 .

[0092] The slave controller group 2000 may include first to N-th (N is a positive integer of 2 or more) slave controllers 2100 , 2200 , and 2300 , and the battery cell group 4000 may include first to N-th battery cells 4100 , 4200 , and 4300 .

[0093] The master controller 1000 is connected in parallel with the first to N-th slave controllers 2100, 2200, and 2300 through a first communication channel. The first communication channel may include a bus line 3000 provided between the master controller 1000 and the slave controller group 2000. That is, the master controller 1000 and the first to N-th slave controllers 2100, 2200, and 2300 may share the bus line 3000. In this case, the master controller 1000 may communicate with the first to N-th slave controllers 2100, 2200, and 2300 via the bus line 3000 through a controller area network (CAN) communication.

[0094] The master controller 1000 may bidirectionally communicate with each of the first to N-th slave controllers 2100, 2200, and 2300 through a first communication channel. For example, the master controller 1000 may control battery cell balancing through bidirectional communication with the first to N-th slave controllers 2100, 2200, and 2300. Specifically, each of the first to N-th slave controllers 2100, 2200, and 2300 may transmit voltage information data and temperature information data of a battery cell to the master controller 1000. In this case, the master controller 1000 may analyze the voltage information data and temperature information data of each of the first to N-th battery cells 4100, 4200, and 4300 to calculate cell balancing information data for balancing of the first to N-th battery cells 4100, 4200, and 4300. Then, the master controller 1000 may transmit the cell balancing information data to each of the first to N-th slave controllers 2100, 2200, and 2300. Each of the first to N-th slave controllers 2100 , 2200 , and 2300 may perform battery cell balancing according to the cell balancing information data.

[0095] In addition, the main controller 1000 may analyze the voltage information data and the temperature information data of each of the first to N-th battery cells to calculate the state of charge (SOC), state of health (SOH), and safety information of each of the first to N-th battery cells. The main controller 1000 may control the switching unit that switches the connection between the first to N-th battery cells 4100, 4200, and 4300 and the power source or the load according to the state of charge (SOC), state of health (SOH), and safety information to control the charging and discharging of each of the first to N-th battery cells.

[0096] The master controller 1000 is serially connected to the first to N-th slave controllers 2100, 2200, and 2300 through the second communication channel in a daisy chain method. Figure 7a As shown, the master controller 1000 may be connected to the first to Nth slave controllers 2100 , 2200 , and 2300 in a ring structure.

[0097] The main controller 1000 may receive the instruction signal via the first to N-th slave controllers 2100, 2200, and 2300 through the second communication channel. The instruction signal may be a signal indicating safety information of the first to N-th battery cells. When the first instruction signal is input, the main controller 1000 may determine that the voltage and temperature of the first to N-th battery cells 4100, 4200, and 4300 are normal, and when the second instruction signal is input, the main controller 1000 may determine that the voltage and temperature of at least one of the first to N-th battery cells are abnormal.

[0098] The main controller 1000 uniformly controls the battery management system (BMS) and thus may be referred to as a battery master controller, and each of the first to Nth slave controllers 2100, 2200, and 2300 controls the first to Nth battery cells and thus may be referred to as unit module controllers.

[0099] The battery cell group 4000 may include a first battery cell to an Nth battery cell 4100, 4200, and 4300. Each of the first battery cell to the Nth battery cell 4100, 4200, and 4300 may include a secondary battery capable of charging and discharging. For example, the secondary battery of each of the first battery cell to the Nth battery cell 4100, 4200, and 4300 may be implemented as any one of a nickel-cadmium (Ni-Cd) battery, a nickel-hydrogen (Ni-H) battery, and a lithium (Li) battery, but the present invention is not limited thereto. Each of the first battery cell to the Nth battery cell 4100, 4200, and 4300 may include a plurality of secondary batteries, and in this case, the secondary batteries may be connected in series.

[0100] As described above, according to an embodiment of the present invention, the main controller 1000 communicates with the plurality of slave controllers 2100, 2200, and 2300 using a plurality of communication channels (e.g., a first communication channel and a second communication channel). As a result, even if a problem occurs in the first communication channel corresponding to the main communication channel, the main controller 1000 can receive a command signal indicating whether the voltage and temperature of at least one of the first to N-th battery cells 4100, 4200, and 4300 are normal or abnormal through the second communication channel corresponding to the sub-communication channel.

[0101] like Figure 7b As shown in , the battery management system according to the embodiment of the present invention includes a first slave controller 2100 and a first battery unit 4100 .

[0102] The first slave controller 2100 includes a microcontroller 2110 and a voltage sensing unit 2120. In this case, the microcontroller 2110 may be composed of the above Figure 6The first semiconductor chip 200a is formed, and the voltage sensing unit 2120 can be formed by the above Figure 6 The second semiconductor chip 200 b is formed.

[0103] The microcontroller 2110 receives the first sensing voltage and the second sensing voltage from the voltage sensing unit 2120, and receives the sensed temperature of the first battery cell 4100 from the temperature receiving terminal TT. The microcontroller 2110 converts the first sensing voltage into voltage information data as digital data, and converts the sensed temperature into temperature information data as digital data, so as to send the converted data to the master controller through the first communication channel. The microcontroller 2110 determines whether the first battery cell 4100 is overcharged, over-discharged, or overheated based on the second sensing voltage and the sensed temperature, and sends an instruction signal to the second slave controller 2200.

[0104] Specifically, the microcontroller 2110 may include a central processing unit 2111 , a communication module 2112 , an analog-to-digital converter 2113 , a comparator 2114 , and a command signal output unit 2115 .

[0105] The central processing unit 2111 receives voltage information data and temperature information data from the analog-to-digital converter 2113. The central processing unit 2111 outputs the voltage information data and the temperature information data to the communication module 2112 so as to send the voltage information data and the temperature information data to the master controller 1000 through the first communication channel. In addition, the central processing unit 2111 receives control information data from the communication module 2112 and controls the first battery unit 4100 according to the control information data. For example, the central processing unit 2111 may receive cell balancing data as an example of control information data to control the cell balancing of the first battery unit 4100 according to the cell balancing data. In this case, the first slave controller 2100 may further include a cell balancing unit connected to the first battery unit 4100. The cell balancing unit may include a switch for forming a discharge path in each of the secondary batteries of the first battery unit 4100. The central processing unit 2111 may output a switch signal for controlling the switch of the cell balancing unit according to the cell balancing information data to the cell balancing unit.

[0106] The communication module 2112 is a module for communicating with the main controller 1000 through the first communication channel. The communication module 2112 converts the voltage information data and the temperature information data received from the central processing unit 2111 into a communication packet suitable for the first communication channel to transmit the converted packet to the main controller 1000 through the third transmission terminal TX3. In addition, the communication module 2112 converts the communication packet transmitted from the main controller 1000 through the third reception terminal RX3 into control information data to output the converted data to the central processing unit 2111.

[0107] The analog-to-digital converter 2113 receives a first sensing voltage from the voltage sensing unit 2120 through the first terminal T1 and the second terminal T2, and receives a sensed temperature of the first battery cell 4100 through the temperature receiving terminal TT. The analog-to-digital converter 2113 converts the first sensing voltage into voltage information data as digital data, and converts the sensed temperature into temperature information data as digital data. The analog-to-digital converter 2113 outputs the voltage information data and the temperature information data to the central processing unit 2111.

[0108] The comparator 2114 receives the second sensing voltage from the voltage sensing unit 2120 through the third terminal T3, and receives the sensed temperature of the first battery cell 4100 through the temperature receiving terminal TT. The comparator 2114 compares the second sensing voltage with the first voltage threshold and the second voltage threshold, compares the sensed temperature with the first temperature threshold and the second temperature threshold, and then outputs a comparison signal according to the comparison result.

[0109] Specifically, when the second sensing voltage has a value between the first voltage threshold and the second voltage threshold and the sensing temperature has a value between the first temperature threshold and the second temperature threshold, the comparator 2114 outputs a first comparison signal. When the second sensing voltage has a value greater than or equal to the first voltage threshold or less than or equal to the second voltage threshold, or when the sensing temperature has a value greater than or equal to the first temperature threshold or less than or equal to the second temperature threshold, the comparator 2114 outputs a second comparison signal.

[0110] The first voltage threshold may be a voltage threshold as a reference for overcharge of the first battery cell 4100, and the second voltage threshold may be a voltage threshold as a reference for overdischarge of the first battery cell 4100. The first voltage threshold may be greater than the second voltage threshold. In addition, the first temperature threshold may be a temperature threshold as a reference for overheating of the first battery cell 4100, and the second temperature threshold may be a temperature threshold as a reference for low temperature of the first battery cell 4100. The first temperature threshold may be greater than the second temperature threshold.

[0111] The command signal output unit 2115 outputs the command signal to the fourth transmission terminal TX4 according to the command signal transmitted through the fourth reception terminal RX4 and the comparison signal from the comparator 2114. In addition, when the second command signal is input through the fourth reception terminal RX4, the command signal output unit 2115 outputs the second command signal to the fourth transmission terminal TX4 without change.

[0112] The voltage sensing unit 2120 may include a first voltage sensing unit 2121 and a second voltage sensing unit 2122. Each of the first voltage sensing unit 2121 and the second voltage sensing unit 2122 is connected to both ends of the first battery cell 4100 to sense the voltage of the battery cell 4100. For example, each of the first voltage sensing unit 2121 and the second voltage sensing unit 2122 may be connected to both ends of each of the secondary batteries of the first battery cell 4100 through the fourth terminal T4, thereby sensing the voltage of each of the secondary batteries 4110 and 4120.

[0113] The first voltage sensing unit 2121 outputs at least one sensing voltage sensed from the first battery cell 4100 as a first sensing voltage to the analog-to-digital converter 2113 through the first terminal T1 and the second terminal T2. The first voltage sensing unit 2121 may transmit the first sensing voltage to the analog-to-digital converter 2113 in the form of a differential signal using two signal lines.

[0114] The second voltage sensing unit 2122 outputs at least one sensing voltage sensed from the first battery cell 4100 as a second sensing voltage to the comparator 2114 through the third terminal T3. The second voltage sensing unit 2122 may transmit the second sensing voltage to the comparator 2114 using one signal line.

[0115] The first sensing voltage is converted into voltage information data by the analog-to-digital converter 2113 and sent to the main controller 1000 through the first communication channel, and the second sensing voltage is compared with the first voltage threshold and the second voltage threshold in the comparator 2114. That is, the first sensing voltage is a value for analyzing cell balance, state of charge (SOC), state of health (SOH), and safety information in the main controller 1000, but the second sensing voltage is a value to be compared with the first voltage threshold corresponding to the upper threshold and the second voltage threshold corresponding to the lower threshold. Therefore, it is important to send the first sensing voltage more accurately than the second sensing voltage. Therefore, according to an embodiment of the present invention, by sending the first sensing voltage to the analog-to-digital converter 2113 in the form of a differential signal using two signal lines, the first sensing voltage can be sent with a more accurate value than when sending using one signal line. In addition, according to an embodiment of the present invention, by sending the second sensing voltage using one signal line, the circuit complexity can be reduced and the cost can be reduced.

[0116] Embodiments of the present invention have been described in more detail with reference to the accompanying drawings, but the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but are intended to describe, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects, rather than restrictive. The scope of protection of the present invention should be interpreted by the claims, and all technical spirits within their equivalent range should be interpreted as being included in the scope of rights of the present invention.

Claims

1. A semiconductor package, comprising: Supporting part; a semiconductor chip disposed on the support portion and comprising a plurality of signal pads; a buffer layer, the buffer layer being disposed on the semiconductor chip; an adhesive layer, the adhesive layer being disposed on the buffer layer; a pressure relief layer, the pressure relief layer being disposed on the adhesive layer; as well as a molding layer, the molding layer being disposed on the pressure relief layer, The semiconductor chip includes a first circuit region and a second circuit region. wherein the buffer layer includes a second opening region penetrating the buffer layer in a region corresponding to the first circuit region, and Wherein, a hole is formed by the second opening area of ​​the buffer layer between the lower surface of the adhesive layer and the upper surface of the first circuit area.

2. The semiconductor package according to claim 1, wherein The buffer layer includes a first opening region in a region corresponding to each of the plurality of signal pads such that upper surfaces of the plurality of signal pads are exposed.

3. The semiconductor package according to claim 2, wherein: The thickness of the buffer layer is smaller than the thickness of each of the plurality of signal pads, and the height of an upper surface of each of the plurality of signal pads is greater than the height of an upper surface of the buffer layer.

4. The semiconductor package according to claim 1, wherein: One end of the buffer layer is consistent with one end of the semiconductor chip, and the other end of the buffer layer is consistent with the other end of the semiconductor chip.

5. The semiconductor package according to claim 1, wherein The adhesive layer and the stress relief layer do not overlap with the plurality of signal pads, and One end of each of the adhesive layer and the decompression layer does not coincide with one end of the semiconductor chip, and the other end of each of the adhesive layer and the decompression layer does not coincide with the other end of the semiconductor chip.

6. The semiconductor package according to claim 1, wherein The thickness of the decompression layer is half or more of the thickness of the semiconductor chip and is less than or equal to the thickness of the semiconductor chip.

7. The semiconductor package according to claim 1, wherein: The deviation between the thermal expansion coefficient of the decompression layer and the thermal expansion coefficient of the semiconductor chip is within ±10.

8. The semiconductor package according to claim 1, wherein: The thickness of the decompression layer is in the range of 200 μm to 500 μm, and the thermal expansion coefficient of the decompression layer is in the range of 2.6 ppm / °C to 3.0 ppm / °C.

9. The semiconductor package according to claim 1, wherein: The second opening region is filled with the adhesive layer.

10. The semiconductor package according to claim 1, wherein A bandgap reference circuit or an amplifier circuit is arranged in the first circuit area.

11. The semiconductor package according to claim 1, wherein The thickness of the adhesive layer is greater than the thickness of the buffer layer.

12. A semiconductor package, comprising: Supporting part; a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being disposed on the support portion and each including a plurality of signal pads; a plurality of electrode pads disposed outside the support portion and spaced apart from the support portion; wires, the wires comprising a first wire connecting one of the signal pads of the first semiconductor chip with one of the signal pads of the second semiconductor chip, a second wire connecting another signal pad of the first semiconductor chip with one of the electrode pads, and a third wire connecting another signal pad of the second semiconductor chip with another electrode pad; a buffer layer, wherein the buffer layer is disposed on the first semiconductor chip; an adhesive layer, the adhesive layer being disposed on the buffer layer; a pressure relief layer, the pressure relief layer being disposed on the adhesive layer; as well as a molding layer, the molding layer being disposed on the pressure relief layer, The first semiconductor chip includes a first circuit region and a second circuit region. wherein the buffer layer includes a second opening region penetrating the buffer layer in a region corresponding to the first circuit region, and Wherein, a hole is formed by the second opening area of ​​the buffer layer between the lower surface of the adhesive layer and the upper surface of the first circuit area.

13. The semiconductor package according to claim 12, wherein: The buffer layer and the stress relief layer are not disposed on the second semiconductor chip.

14. The semiconductor package according to claim 12, wherein: The buffer layer includes a first opening region in a region corresponding to each of the plurality of signal pads so that upper surfaces of the plurality of signal pads are exposed, and The thickness of the buffer layer is smaller than the thickness of each of the plurality of signal pads, and the height of an upper surface of each of the plurality of signal pads is greater than the height of an upper surface of the buffer layer.

15. The semiconductor package according to claim 12, wherein: One end of the buffer layer is consistent with one end of the first semiconductor chip, and the other end of the buffer layer is consistent with the other end of the first semiconductor chip, The adhesive layer and the stress relief layer do not overlap with the plurality of signal pads, and One end of each of the adhesive layer and the decompression layer does not coincide with one end of the first semiconductor chip, and the other end of each of the adhesive layer and the decompression layer does not coincide with the other end of the first semiconductor chip.

16. The semiconductor package according to claim 12, wherein: The thickness of the decompression layer is half or more of the thickness of the first semiconductor chip and is less than or equal to the thickness of the first semiconductor chip, and A deviation between a thermal expansion coefficient of the decompression layer and a thermal expansion coefficient of the first semiconductor chip is within ±10.

17. The semiconductor package according to claim 12, wherein: The thickness of the adhesive layer is greater than the thickness of the buffer layer.

18. A battery management system, comprising a semiconductor package, in, The semiconductor package comprises: Supporting part; a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being disposed on the support portion and each including a plurality of signal pads; a plurality of electrode pads disposed outside the support portion and spaced apart from the support portion; wires, the wires comprising a first wire connecting one of the signal pads of the first semiconductor chip with one of the signal pads of the second semiconductor chip, a second wire connecting another signal pad of the first semiconductor chip with one of the electrode pads, and a third wire connecting another signal pad of the second semiconductor chip with another electrode pad; a buffer layer, wherein the buffer layer is disposed on the first semiconductor chip; an adhesive layer, the adhesive layer being disposed on the buffer layer; a pressure relief layer disposed on the adhesive layer; and a molding layer, the molding layer being disposed on the pressure relief layer, wherein the second semiconductor chip is provided with a voltage sensing unit, and the first semiconductor chip is provided with a microcontroller, the microcontroller receives a sensing voltage from the voltage sensing unit and converts the sensing voltage into voltage information data as digital data to send the voltage information data to a main controller, The first semiconductor chip includes a first circuit region and a second circuit region. wherein the buffer layer includes a second opening region penetrating the buffer layer in a region corresponding to the first circuit region, and Wherein, a hole is formed by the second opening area of ​​the buffer layer between the lower surface of the adhesive layer and the upper surface of the first circuit area.

19. The battery management system according to claim 18, wherein: The microcontroller arranged in the first semiconductor chip includes: an analog-to-digital converter, which converts a first sensing voltage received from the voltage sensing unit into voltage information data as digital data; a communication module, which is configured to communicate with the main controller; a central processing unit, which is configured to receive control information data from the communication module and control the battery cell according to the control information data; a comparator, which is configured to receive a second sensing voltage from the voltage sensing unit and compare the second sensing voltage with a threshold voltage value; and an instruction signal output unit, which is configured to output an instruction signal according to a comparison signal from the comparator.

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