Ferroelectric memory device including series select gate transistor and method of forming the same

Abstract

A ferroelectric memory cell includes a series connection of a select gate transistor and a ferroelectric memory transistor that turns on and off the ferroelectric memory cell. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory cell may be a planar structure, wherein both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor may be formed as a buried wire. Alternatively, the ferroelectric memory cell may include a vertical stack of vertical semiconductor channels.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 454,458 filed on June 27, 2019 and U.S. non-provisional patent application serial number 16 / 454,475, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor memory devices, and in particular, to ferroelectric memory devices including series select gate transistors and methods of forming the same. Background Art

[0004] Ferroelectric materials are materials that show spontaneous polarization of charges in the absence of an applied electric field. The net polarization P of the charges within the ferroelectric material is non-zero in the minimum energy state. Therefore, spontaneous ferroelectric polarization of the material occurs, and the ferroelectric material accumulates surface charges of opposite polarity types on two opposing surfaces. The polarization P of the ferroelectric material shows hysteresis as a function of the applied voltage V. The product of the remnant polarization and the coercive field of a ferroelectric material is a measure used to characterize the effectiveness of a ferroelectric material.

[0005] A ferroelectric memory device is a memory device that includes a ferroelectric material for storing information. The ferroelectric material acts as a memory material for the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed in two different orientations (e.g., "up" or "down" polarization positions based on atomic positions in the lattice (such as oxygen and / or metal atom positions)) to store information in the ferroelectric material. The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring the current flowing through a semiconductor channel disposed adjacent to the ferroelectric material in an adjacent field effect transistor ferroelectric memory device. Summary of the invention

[0006] According to one embodiment of the present disclosure, a memory device including at least one ferroelectric memory cell is provided. Each ferroelectric memory cell in the at least one ferroelectric memory cell includes: a corresponding first field effect transistor, the corresponding first field effect transistor including a first semiconductor channel extending between a first active region and a second active region located in a semiconductor substrate, a first gate dielectric disposed at a peripheral region of a trench extending downward from a top surface of the semiconductor substrate and located between the first active region and the second active region, and a first gate electrode located inside the trench above the first gate dielectric, wherein the first semiconductor channel covers below a horizontal portion of the first gate dielectric; and a corresponding second field effect transistor, the corresponding second field effect transistor including a second semiconductor channel extending between the second active region and a third active region, a second gate dielectric including a ferroelectric material layer covering the second semiconductor channel, and a second gate electrode covering the second gate dielectric.

[0007] According to another aspect of the present disclosure, a method for forming a memory device including at least one ferroelectric memory cell is provided. Each of the at least one ferroelectric memory cell is formed by: forming a trench, a first active region, a second active region, and a third active region in an upper portion of a semiconductor substrate, wherein the trench is formed between the first active region and the second active region; forming a stack of a first gate dielectric and a first gate electrode in the trench; and forming a stack of a second gate electrode and a second gate dielectric over a portion of the semiconductor substrate between the second active region and the third active region, the second gate dielectric comprising a ferroelectric material layer. A first semiconductor channel is formed below the first gate dielectric between the first active region and the second active region; and a second semiconductor channel is formed below the second gate dielectric between the second active region and the third active region.

[0008] According to another aspect of the present disclosure, a memory device including at least one ferroelectric memory cell is provided. Each of the at least one ferroelectric memory cells is located above a substrate and includes: a corresponding first field effect transistor, the corresponding first field effect transistor including a first vertical semiconductor channel, a first gate dielectric contacting the sidewall of the first vertical semiconductor channel, and a portion of a first conductive layer contacting the first gate dielectric; a corresponding second field effect transistor, the corresponding second field effect transistor including a second vertical semiconductor channel, a second gate dielectric including a ferroelectric material layer and contacting the sidewall of the second vertical semiconductor channel and contacting the top or bottom of the first vertical semiconductor channel, and a portion of a second conductive layer contacting the second gate dielectric; a corresponding first active region, the corresponding first active region connected to the bottom end of the stack of the first vertical semiconductor channel and the second vertical semiconductor channel; and a corresponding second active region, the corresponding second active region connected to the top end of the stack of the first vertical semiconductor channel and the second vertical semiconductor channel.

[0009] According to another aspect of the present disclosure, a method for forming a memory device including at least one ferroelectric memory cell is provided. Each ferroelectric memory cell in the at least one ferroelectric memory cell is formed above a substrate by: forming a corresponding first active region: forming a corresponding stack of a first field effect transistor and a second field effect transistor, the second field effect transistor covering the first field effect transistor above or below the first active region, wherein the first field effect transistor includes a first vertical semiconductor channel, a first gate dielectric contacting the sidewall of the first vertical semiconductor channel, and a portion of a first conductive layer contacting the first gate dielectric, and the second field effect transistor includes a second vertical semiconductor channel, a second gate dielectric including a ferroelectric material layer and contacting the sidewall of the second vertical semiconductor channel and contacting the top or bottom of the first vertical semiconductor channel, and a portion of a second conductive layer contacting the second gate dielectric; and forming a corresponding second active region on the top of the corresponding stack of the first vertical semiconductor channel and the second vertical semiconductor channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and Figure 1B is a circuit diagram of an exemplary memory array including ferroelectric memory cells according to an embodiment of the present disclosure. Figure 1C and Figure 1D is shown for operation Figure 1A and Figure 1B 1 and 2. A table of exemplary voltages for corresponding single-level cells and multi-level cells in a circuit of FIG.

[0011] Figure 2Ais a vertical cross-sectional view of the first exemplary structure after forming a dielectric isolation structure in an upper region of a semiconductor substrate according to the first embodiment of the present disclosure.

[0012] Figure 2B yes Figure 2A A top view of the first exemplary structure. The vertical plane A-A' is Figure 2A A plane of a vertical section.

[0013] Figure 2C is along Figure 2B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0014] Figure 3A is a vertical cross-sectional view of a first exemplary structure after forming an active region according to the first embodiment of the present disclosure.

[0015] Figure 3B yes Figure 3A A top view of the first exemplary structure. The vertical plane A-A' is Figure 3A A plane of a vertical section.

[0016] Figure 3C is along Figure 3B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0017] Figure 4A is a vertical cross-sectional view of the first exemplary structure after forming a linear trench according to the first embodiment of the present disclosure.

[0018] Figure 4B yes Figure 4A A top view of the first exemplary structure. The vertical plane A-A' is Figure 4A A plane of a vertical section.

[0019] Figure 4C is along Figure 4B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0020] Figure 5A is a vertical cross-sectional view of the first exemplary structure after forming a first gate dielectric strip and a first gate electrode line according to the first embodiment of the present disclosure.

[0021] Figure 5B yes Figure 5A A top view of the first exemplary structure. The vertical plane A-A' is Figure 5A A plane of a vertical section.

[0022] Figure 5C is along Figure 5BA vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0023] Fig. 6A is a vertical cross-sectional view of the first exemplary structure after forming a second gate dielectric strip and a second gate electrode line according to the first embodiment of the present disclosure.

[0024] Figure 6B yes Fig. 6A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 6A A plane of a vertical section.

[0025] Fig. 7A is a vertical cross-sectional view of the first exemplary structure after forming a first interconnect level dielectric layer, a source contact via structure, and a source line according to the first embodiment of the present disclosure.

[0026] Figure 7B yes Fig. 7A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 7A A plane of a vertical section.

[0027] Fig. 8A is a vertical cross-sectional view of the first exemplary structure after forming a second interconnect level dielectric layer, a drain contact via structure, and a bit line according to the first embodiment of the present disclosure.

[0028] Figure 8B yes Fig. 8A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 8A A plane of a vertical section.

[0029] Figure 8C is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0030] Fig. 9A is a vertical cross-sectional view of a second exemplary structure after forming first level discrete memory openings through a first alternating stack of first level insulating layers and first level spacer material layers according to the second embodiment of the present disclosure.

[0031] Fig. 9B yes Fig. 9A A top view of the second exemplary structure. Plane AA' is Fig. 9A A plane of a vertical section.

[0032] Fig. 10A is a vertical cross-sectional view of a second exemplary structure after forming a first gate dielectric according to the second embodiment of the present disclosure.

[0033] Fig. 10Byes Fig. 10A A top view of the second exemplary structure. Plane AA' is Fig. 10A A plane of a vertical section.

[0034] Fig.11A is a vertical cross-sectional view of a second exemplary structure after forming a first vertical semiconductor channel according to the second embodiment of the present disclosure.

[0035] Fig. 11B yes Fig.11A A top view of the second exemplary structure. Plane AA' is Fig.11A A plane of a vertical section.

[0036] Fig. 12A is a vertical cross-sectional view of a second exemplary structure after forming a second gate dielectric material layer according to the second embodiment of the present disclosure.

[0037] Fig. 12B yes Fig. 12A A top view of the second exemplary structure. Plane AA' is Fig. 12A A plane of a vertical section.

[0038] Fig.13A is a vertical cross-sectional view of a second exemplary structure after forming a second gate dielectric according to the second embodiment of the present disclosure.

[0039] Fig. 13B yes Fig.13A A top view of the second exemplary structure. Plane AA' is Fig.13A A plane of a vertical section.

[0040] Fig.14A is a vertical cross-sectional view of a second exemplary structure after forming a second vertical semiconductor channel according to the second embodiment of the present disclosure.

[0041] Fig. 14B yes Fig.14A A top view of the second exemplary structure. Plane AA' is Fig.14A A plane of a vertical section.

[0042] Fig.15A is a vertical cross-sectional view of a second exemplary structure after forming a first backside trench according to the second embodiment of the present disclosure.

[0043] Fig. 15B yes Fig.15A A top view of the second exemplary structure. Plane AA' is Fig.15A A plane of a vertical section.

[0044] Fig.16Ais a vertical cross-sectional view of a second exemplary structure after forming a first backside recess according to a second embodiment of the present disclosure.

[0045] Fig. 16B yes Fig.16A A top view of the second exemplary structure. Plane AA' is Fig.16A A plane of a vertical section.

[0046] Fig.17A is a vertical cross-sectional view of a second exemplary structure after forming a first level conductive layer, a first backside trench fill structure, and a first contact level dielectric layer according to the second embodiment of the present disclosure.

[0047] Fig. 17B is along Fig.17A A vertical cross-sectional view of the second exemplary structure taken along the plane BB'. Fig.17A A plane of a vertical section.

[0048] Fig.18A is a vertical cross-sectional view of a second exemplary structure after forming a first contact via cavity according to the second embodiment of the present disclosure.

[0049] Fig.18B yes Fig.18A A top view of the second exemplary structure. Plane AA' is Fig.18A A plane of a vertical section.

[0050] Fig.19A is a vertical cross-sectional view of a second exemplary structure after forming a bit line level conductive material layer including a first contact via structure according to the second embodiment of the present disclosure.

[0051] Fig.19B yes Fig.19A A top view of the second exemplary structure. Plane AA' is Fig.19A A plane of a vertical section.

[0052] Fig. 20A is a vertical cross-sectional view of a second exemplary structure after forming a bit line according to the second embodiment of the present disclosure.

[0053] Fig. 20B yes Fig. 20A A top view of the second exemplary structure. Plane AA' is Fig. 20A A plane of a vertical section.

[0054] Fig.21A is a vertical cross-sectional view of a second exemplary structure after forming a second contact level dielectric layer and a second contact via structure according to the second embodiment of the present disclosure.

[0055] Fig. 21B yes Fig.21A A top view of the second exemplary structure. Plane AA' is Fig.21A A plane of a vertical section.

[0056] Fig.22A is a vertical cross-sectional view of a second exemplary structure after forming a second level discrete memory opening through a second alternating stack of second level insulating layers and second level spacer material layers according to the second embodiment of the present disclosure.

[0057] Fig. 22B yes Fig.22A A top view of the second exemplary structure. Plane AA' is Fig.22A A plane of a vertical section.

[0058] Fig.23 is a vertical cross-sectional view of the second exemplary structure after forming a third gate dielectric and a third vertical semiconductor channel according to the second embodiment of the present disclosure.

[0059] Fig.24 is a vertical cross-sectional view of the second exemplary structure after forming a fourth vertical semiconductor channel according to the second embodiment of the present disclosure.

[0060] Fig.25 is a vertical cross-sectional view of the second exemplary structure after forming a second backside trench, replacing the second level spacer material layer with a second conductive layer, and forming a second backside trench fill structure according to the second embodiment of the present disclosure.

[0061] Fig.26A is a vertical cross-sectional view of a second exemplary structure after forming a source conductive material layer according to the second embodiment of the present disclosure.

[0062] Fig.26B yes Fig.26A A top view of the second exemplary structure. Plane AA' is Fig.26A A plane of a vertical section.

[0063] Fig.27A is a vertical cross-sectional view of the third exemplary structure after forming first-level line trenches through the first alternating stack of first-level insulating layers and first-level spacer material layers according to the third embodiment of the present disclosure.

[0064] Fig.27B yes Fig.27A A top view of the third exemplary structure. Plane AA' is Fig.27A A plane of a vertical section.

[0065] Fig.28Ais a vertical cross-sectional view of a third exemplary structure after forming a first gate dielectric and a first vertical semiconductor channel material portion according to the third embodiment of the present disclosure. Fig.28B yes Fig.28A A top view of the third exemplary structure. Plane AA' is Fig.28A A plane of a vertical section.

[0066] Fig.28C , Fig.28D and Fig.28E is a vertical cross-sectional view of steps in forming an alternative configuration of a third exemplary structure.

[0067] Fig.29A is a vertical cross-sectional view of a third exemplary structure after forming a first vertical semiconductor channel and a first dielectric core according to the third embodiment of the present disclosure. Fig.29B yes Fig.29A A top view of the third exemplary structure. Plane AA' is Fig.29A A plane of a vertical section.

[0068] Fig.29C is a vertical cross-sectional view of an alternative configuration of the third exemplary structure.

[0069] Fig. 30A is a vertical cross-sectional view of a third exemplary structure after forming a second gate dielectric according to the third embodiment of the present disclosure.

[0070] Fig. 30B yes Fig. 30A A top view of the third exemplary structure. Plane AA' is Fig. 30A A plane of a vertical section.

[0071] Fig.31A is a vertical cross-sectional view of the third exemplary structure after forming a second vertical semiconductor channel according to the third embodiment of the present disclosure.

[0072] Fig.31B yes Fig.31A A top view of the third exemplary structure. Plane AA' is Fig.31A A plane of a vertical section.

[0073] Fig.32A is a vertical cross-sectional view of a third exemplary structure after forming a second dielectric core according to the third embodiment of the present disclosure. Fig.32B yes Fig.32A A top view of the third exemplary structure. Plane AA' is Fig.32A A plane of a vertical section.

[0074] Fig.32C , Fig.32D and Fig.32E is a vertical cross-sectional view of steps in forming an alternative configuration of a third exemplary structure.

[0075] Fig.33A is a vertical cross-sectional view of a third exemplary structure after forming a laterally alternating sequence of memory pillar structures and dielectric pillar structures according to the third embodiment of the present disclosure.

[0076] Fig.33B yes Fig.33A A top view of the third exemplary structure. Plane AA' is Fig.33A A plane of a vertical section.

[0077] Fig.34A is a vertical cross-sectional view of a third exemplary structure after forming a first backside trench according to a third embodiment of the present disclosure.

[0078] Fig.34B yes Fig.34A A top view of the third exemplary structure. Plane AA' is Fig.34A A plane of a vertical section.

[0079] Fig.35A is a vertical cross-sectional view of a third exemplary structure after forming a first backside recess according to a third embodiment of the present disclosure.

[0080] Fig.35B yes Fig.35A A top view of the third exemplary structure. Plane AA' is Fig.35A A plane of a vertical section.

[0081] Fig.36A is a vertical cross-sectional view of the third exemplary structure after forming a first-level conductive layer and a first backside trench-fill structure according to the third embodiment of the present disclosure.

[0082] Fig.36B is along Fig.36A A vertical cross-sectional view of the third exemplary structure taken along plane BB'. Fig.36A A plane of a vertical section.

[0083] Fig.37A is a vertical cross-sectional view of a third exemplary structure after forming a first contact level dielectric layer and a first contact via cavity according to the third embodiment of the present disclosure.

[0084] Fig.37B yes Fig.37A A top view of the third exemplary structure. Plane AA' is Fig.37A A plane of a vertical section.

[0085] Fig.38Ais a vertical cross-sectional view of a third exemplary structure after forming a bit line level conductive material layer including a first contact via structure according to the third embodiment of the present disclosure.

[0086] Fig.38B yes Fig.38A A top view of the third exemplary structure. Plane AA' is Fig.38A A plane of a vertical section.

[0087] Fig.39A is a vertical cross-sectional view of a third exemplary structure after forming a bit line according to the third embodiment of the present disclosure.

[0088] Fig.39B yes Fig.39A A top view of the third exemplary structure. Plane AA' is Fig.39A A plane of a vertical section.

[0089] Fig.40A is a vertical cross-sectional view of the third exemplary structure after forming a second contact level dielectric layer and a second contact via structure according to the third embodiment of the present disclosure.

[0090] Fig.40B yes Fig.40A A top view of the third exemplary structure. Plane AA' is Fig.40A A plane of a vertical section.

[0091] Fig.41A is a vertical cross-sectional view of the third exemplary structure after forming second level line trenches through the second alternating stack of second level insulating layers and second level spacer material layers according to the third embodiment of the present disclosure.

[0092] Fig.41B yes Fig.41A A top view of the third exemplary structure. Plane AA' is Fig.41A A plane of a vertical section.

[0093] Fig.42 is a vertical cross-sectional view of a third exemplary structure after forming a third gate dielectric according to the third embodiment of the present disclosure.

[0094] Fig.43A is a vertical cross-sectional view of the third exemplary structure after forming a third vertical semiconductor channel and a third dielectric core according to the third embodiment of the present disclosure.

[0095] Fig.43B yes Fig.43A A top view of the third exemplary structure. Plane AA' is Fig.43A A plane of a vertical section.

[0096] Fig.44A is a vertical cross-sectional view of the third exemplary structure after forming a fourth gate dielectric, a fourth vertical semiconductor channel, and a fourth dielectric core according to the third embodiment of the present disclosure.

[0097] Fig.44B yes Fig.44A A top view of the third exemplary structure. Plane AA' is Fig.44A A plane of a vertical section.

[0098] Fig.45A is a vertical cross-sectional view of the third exemplary structure after forming a second backside trench, replacing the second level spacer material layer with a second level conductive layer, and forming a second backside trench filling structure according to the third embodiment of the present disclosure.

[0099] Fig.45B yes Fig.45A A top view of the third exemplary structure. Plane AA' is Fig.45A A plane of a vertical section.

[0100] Fig.46A is a vertical cross-sectional view of a third exemplary structure after forming a conductive material layer according to the third embodiment of the present disclosure.

[0101] Fig.46B yes Fig.46A A top view of the third exemplary structure. Plane AA' is Fig.46A A plane of a vertical section. DETAILED DESCRIPTION

[0102] As described above, embodiments of the present disclosure relate to ferroelectric memory transistors including a series select gate transistor connected to a read line and methods of forming the same, various aspects of which are described in detail herein. During operation of the device, the select gate transistor reduces disturbances of the ferroelectric memory transistor.

[0103] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise indicated, elements with the same reference numerals are assumed to have the same composition and the same function, and unless otherwise indicated, are assumed to have the same thickness range.

[0104] Unless otherwise indicated, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element that is "on" a second element may be located on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is a conductive path composed of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of its components.

[0105] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0106] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0107] See also Figure 1A and Figure 1B, a circuit diagram of an exemplary memory array according to an embodiment of the present disclosure is shown. A ferroelectric memory cell (e.g., a memory cell) UC includes a series connection of a first field effect transistor, referred to herein as a selection gate transistor (labeled "SG") and a second field effect transistor, referred to herein as a ferroelectric memory transistor (labeled "FeFET")). The gate dielectric of the first field effect transistor SG is referred to herein as a first gate dielectric, and includes a non-ferroelectric gate dielectric material, and preferably excludes ferroelectric material. The gate dielectric of the second field effect transistor FeFET is referred to herein as a second gate dielectric, and includes a ferroelectric gate dielectric material. The first field effect transistor SG includes a first semiconductor channel extending between a first active region and a second active region. As used herein, the "active region" of a field effect transistor may be a source region or a drain region. The second field effect transistor FeFET includes a second semiconductor channel. If there is no active region between the first field effect transistor and the second field effect transistor, the active region of the second field effect transistor FeFET may include the same first active region and second active region as in the first field effect transistor SG (for example, as will be described with respect to the second embodiment and the third embodiment in which the first field effect transistor and the second field effect transistor share the same channel). Alternatively, if the active region is located between the first field effect transistor and the second field effect transistor, the active region of the second field effect transistor may include the third active region and the second active region, which second active region also serves as the active region of the first field effect transistor (for example, the second active region may be a common doped semiconductor material portion, which serves as the active region of the first field effect transistor and the second field effect transistor, as will be described below with respect to the first embodiment).

[0108] Each first active region (eg, source region) of the ferroelectric memory cell UC may be connected to a corresponding source line SL, which is connected along Figure 1A The conductive line extending horizontally in the circuit, all cells (eg, memory cells) UC share the same source line SL. Figure 1B In the circuit, the unit cells UC in the same column share the same source line SL, but the unit cells in different columns are connected to different source lines SL. Another active region of the ferroelectric memory unit cell UC (for example, a drain region that may correspond to the second active region or the third active region) may be connected to a corresponding bit line BL, which is a conductive line and may extend laterally in a direction parallel to the longitudinal direction of the bit line BL.

[0109] In one embodiment, each first gate electrode of the first field effect transistor SG contacting the first gate dielectric may include a portion of a corresponding conductive line, referred to herein as a read line RL, which is activated during a read operation, as will be described below with respect to Figure 1C and Figure 1D The read line RL may also be referred to as a selection gate electrode line, a channel gate electrode line, or an access gate electrode line.

[0110] Each second gate electrode of the second field effect transistor FeFET contacting the second gate dielectric may include a portion of a corresponding conductive line, which is referred to herein as a word line WL. In one embodiment, the word line may be parallel to the read line and may or may not be perpendicular to the source line SL and the bit line BL. In the first embodiment, a two-dimensional array of ferroelectric memory cells UC may be provided. Alternatively, in the second and third embodiments, multiple two-dimensional arrays of ferroelectric memory cells UC may be vertically stacked to provide a three-dimensional array of ferroelectric memory cells UC.

[0111] Figure 1C and Figure 1D is shown for operation Figure 1A and Figure 1B Table of exemplary voltages for the circuit. Figure 1C The negative voltage control scheme (columns 2, 3 and 4) is shown. Figure 1B Single-level (SLC) memory cells (UC), operating in a positive voltage control scheme (columns 5, 6, and 7) Figure 1B Single-level memory cells (UC), operating in a negative voltage control scheme (columns 8, 9 and 10) Figure 1A Example voltages of a single-level memory cell (UC). Figure 1D The negative voltage control scheme (columns 2, 3 and 4) is shown. Figure 1B Multi-level (MLC) memory cells (UC), operating in a positive voltage control scheme (columns 5, 6 and 7) Figure 1B Multi-level memory cells (UC) of FIG. 1, operating in a negative voltage control scheme (columns 8, 9, and 10) Figure 1A 1. Example voltages for a multi-level memory cell (UC) of FIG. 1. The voltages shown are exemplary, and other suitable voltages may be used for different device sizes and materials.

[0112] like Figure 1C and Figure 1D As shown in columns 2, 3 and 4 of the table in Figure 1BThe negative voltage control scheme of the individual source line circuit of the selected memory cell UC is set to a high negative voltage for writing / inhibiting, a high positive voltage for erasing / inhibiting, and to 0V or a low positive / negative voltage for reading / inhibiting. The unselected sub-line WL is set to a lower negative voltage for writing / inhibiting, a lower positive voltage for erasing / inhibiting, and to 0V for reading / inhibiting. The bit line BL is set to 0V / low negative voltage for writing / inhibiting, 0V / low positive voltage for erasing / inhibiting, and to V dd The source line SL is set to 0V / lower negative voltage for writing / inhibiting, 0V / lower positive voltage for erasing / inhibiting, and to 0V for reading / inhibiting. The selected read line RL (i.e., the select gate electrode line of the selected memory cell) is allowed to float during writing and erasing, and is set to V dd for read / inhibit. Thus, the select gate transistor floats during write and erase, and is turned on or off during read. The unit of operation is each page of the device.

[0113] As shown in columns 5, 6, and 7 of these tables, for Figure 1B The selected word line WL is set to a high positive voltage for write / inhibit, 0V for erase / inhibit, and to 0V or a low positive / negative voltage for read / inhibit. The unselected sub-lines WL are set to a lower positive voltage for write / inhibit, a lower positive voltage for erase / inhibit, and to 0V for read / inhibit. The bit line BL is set to 0V / low positive voltage for write / inhibit, high positive voltage / 0V for erase / inhibit, and to V dd The source line BL is set to 0V / low positive voltage for writing / inhibiting, high positive voltage / 0V for erasing / inhibiting, and set to 0V for reading / inhibiting. The selected read line RL (i.e., the select gate electrode line of the selected memory cell) is allowed to float during writing and erasing, and is set to V dd for read / inhibit. Thus, the select gate transistor floats during write and erase, and is turned on or off during read. The unit of operation is each page of the device.

[0114] like Figure 1C and Figure 1D As shown in columns 8, 9 and 10 of the table in Figure 1AThe negative voltage control scheme of the common source line circuit of the embodiment of the present invention is as follows: the selected word line WL is set to a high negative voltage for writing / inhibiting, a high positive voltage for erasing / inhibiting, and is set to 0V or a low positive / negative voltage for reading / inhibiting. The unselected sub-lines WL are set to a lower negative voltage for writing / inhibiting, a lower positive voltage for erasing / inhibiting, and is set to 0V for reading / inhibiting. The bit line BL is set to 0V / low negative voltage for writing / inhibiting, 0V / low positive voltage for erasing / inhibiting, and is set to V dd The source line SL is set to 0V / lower negative voltage for writing / inhibiting, 0V / lower positive voltage for erasing / inhibiting, and to 0V for reading / inhibiting. The selected read line RL (i.e., the select gate electrode line of the selected memory cell) is set to 0V for writing and erasing, and to V dd / 0V for read / inhibit. Therefore, the select gate transistor SG is off during write and erase, and is on or off during read. The operation unit is each page of the device.

[0115] See also FIG. 2A to FIG. 2C The first exemplary structure according to the first embodiment of the present disclosure includes a semiconductor substrate 108, which includes a substrate semiconductor layer 109 at least at an upper portion thereof. The substrate semiconductor layer 109 includes a doped semiconductor material having a first conductivity type. The atomic concentration of the dopant of the first conductivity type in the substrate semiconductor layer 109 may be between 1.0×10 14 / cm 3 To 1.0×1018 / cm 3 , but smaller and larger dopant concentrations may also be used. For example, the semiconductor substrate 108 may include a commercially available silicon wafer. The substrate semiconductor layer 109 may include a doped well in the upper surface of the semiconductor substrate 108 or an epitaxial semiconductor layer located above the upper surface of the semiconductor substrate 108.

[0116] At least one optional pad dielectric layer (not shown) may be deposited on the top surface of the substrate semiconductor layer 109. The at least one pad dielectric material layer may include a dielectric material that may be used as a stop layer during a subsequent planarization process. For example, the at least one pad dielectric material layer may include a silicon nitride layer.

[0117] A first line groove extending laterally along a first horizontal direction hd1 (e.g., a bit line direction) may be formed in an upper region of the substrate semiconductor layer 109. The first line grooves may have a uniform width and may be laterally spaced apart along a second horizontal direction hd2 (e.g., a word line direction) perpendicular to the first horizontal direction hd1. The depth of the first line grooves may be in the range of 50 nm to 300 nm, but smaller and larger depths may also be used. The width of the first line grooves may be a photolithography critical dimension, i.e., the minimum dimension that can be printed for a given photolithography tool with a single exposure process and development process. For example, the width of the first line grooves may be in the range of 20 nm to 200 nm, but smaller and larger widths may also be used.

[0118] A dielectric material such as silicon oxide may be deposited in the first line trenches by a conformal deposition process or a self-planarization deposition process. Excess portions of the dielectric material overlying the at least one pad dielectric layer may be removed by a planarization process, which may employ chemical mechanical polishing (CMP) and / or recess etching. The top surface of the remaining portions of the dielectric material may be vertically recessed so that each remaining portion of the dielectric material has a top surface that is substantially coplanar with the top surface of the substrate semiconductor layer 109. Each remaining portion of the dielectric material fills a corresponding first line trench and is referred to herein as a dielectric isolation structure 12. At least one pad dielectric layer that is selective to the dielectric isolation structure 12 and the substrate semiconductor layer 109 may then be removed. Removal of the first material is "selective" to the second material if the removal rate of the first material is at least three times the removal rate of the second material. Each portion of the substrate semiconductor layer 109 located between adjacent pairs of dielectric isolation structures 12 is referred to herein as a semiconductor track region, where a semiconductor channel and an active region of a transistor are subsequently formed.

[0119] See also FIG. 3A to FIG. 3C , a photoresist layer may be applied over the top surface of the substrate semiconductor layer 109 and may be photolithographically patterned to form linear openings extending along a second horizontal direction hd2. The width of each linear opening in the patterned photoresist layer may be a photolithographic critical dimension, so that a high-density ferroelectric memory cell may be formed. Dopants of a second conductivity type opposite to the first conductivity type may be implanted into the line openings in the patterned photoresist layer. Each implanted region of the substrate semiconductor layer 109 constitutes an active region (132, 134, 136). Each active region (132, 134, 136) may include a dopant of the second conductivity type in a range of atomic concentrations from 5.0×1018 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations may also be used.

[0120] The active regions (132, 134, 136) are spaced laterally along a first horizontal direction. In one embodiment, adjacent pairs of ferroelectric memory cells may be spaced laterally along a first horizontal direction hd1 and may have a pair of mirrored layouts having a symmetry plane perpendicular to the first horizontal direction hd1. In this case, a repeating unit including a third active region 136, a second active region 134, a first active region 132, a second active region 134, and a third active region 136 may be repeated between each adjacent pair of dielectric isolation structures 12 along the first horizontal direction hd1, so that the first active region 132 is shared between adjacent pairs of repeating units. In this configuration, the first active region 132 includes a source region of an adjacent first field effect transistor SG, the second active region 134 includes a shared source region / drain region of both the first field effect transistor and the second field effect transistor, and the third active region 136 includes a drain region of the second field effect transistor FeFET. Source region 132 is electrically connected to source line SL, drain region 136 is connected to bit line BE, and shared source / drain region 134 may include a dummy region not connected to any external line or electrode. The patterned photoresist layer may then be removed, for example, by ashing.

[0121] Corresponds to Figure 1A and Figure 1B The region where the ferroelectric memory unit cell (i.e., memory cell) UC is located is referred to herein as a unit cell region UCA. Each unit cell region UCA includes a region of at least a portion of the first active region 132, the second active region 134, and at least a portion of the third active region 136 in the upper portion of the semiconductor substrate 108. The first active region 132, the second active region 134, and the third active region 136 of each ferroelectric memory unit cell are laterally spaced apart along the first horizontal direction hd1. In one embodiment, each of the first active region 132, the second active region 134, and the third active region 136 in each ferroelectric memory unit cell may be formed with a corresponding pair of sidewalls extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0122] See also FIG. 4A to FIG. 4C, a groove may be formed between each adjacent pair of the first active area 132 and the second active area 134. In one embodiment, a patterned etch mask layer 77 may be applied over the semiconductor substrate 108 and may be patterned photolithographically to form a linear opening extending along the second horizontal direction hd2. In one embodiment, the patterned etch mask layer 77 may include a patterned photoresist layer. The linear opening covers the area between a row of first active areas 132 and an adjacent row of second active areas 134. The pattern in the patterned etch mask layer 77 may be transferred through the upper portion of each semiconductor track region (i.e., each portion of the substrate semiconductor layer 109 located between adjacent pairs of dielectric isolation structures 12) by an anisotropic etching process, and through each unmasked portion of the dielectric isolation structure 12 to form a second linear groove 121. The anisotropic etching process may etch the semiconductor material of the substrate semiconductor layer 108 and the dielectric material of the dielectric isolation structure 12 at substantially the same etching rate. Alternatively, the anisotropic etching process may include multiple anisotropic etching steps for etching the semiconductor material of the substrate semiconductor layer 108 and / or the dielectric material of the dielectric isolation structure 12, so that each vertical recessed surface of the substrate semiconductor layer 108 and each vertical recessed surface of the dielectric isolation structure 12 are formed at approximately the same depth.

[0123] In general, the second linear trench 121 can be formed between adjacent pairs of the first active region 132 and the second active region 134 by anisotropically etching the upper portion of the semiconductor substrate 108. The upper portion of the semiconductor track region and the upper portion of the dielectric isolation structure 12 can be anisotropically etched during the formation of the second linear trench 121. In one embodiment, the sidewalls of the second linear trench 121 can be laterally spaced apart from the adjacent first active region 132 and the adjacent second active region 134 by the remaining portion of the semiconductor track region doped with the first conductivity type. Alternatively, the sidewalls of the first active region 132 and / or the second active region 134 can be physically exposed in each second linear trench 121.

[0124] In one embodiment, the bottom surfaces of the first active region 132, the second active region 134, and the third active region 136 may be located in a horizontal plane that is located above a horizontal plane including the bottom surface of the dielectric isolation structure 12. In one embodiment, the bottom surface of the second linear trench 121 may be located in a horizontal plane that is located above a horizontal plane including the bottom surface of the dielectric isolation structure 12. The bottom surface of the second linear trench 121 may be at the same depth as, located above, or located below a horizontal plane including the bottom surfaces of the first active region 132, the second active region 134, and the third active region 136. In one embodiment, the depth of the second linear trench 121 may be in a range of 40 nm to 250 nm as measured from the top surface of the substrate semiconductor layer 109, but smaller and larger thicknesses may also be employed.

[0125] See also FIG. 5A to FIG. 5C , a conformal gate dielectric material layer may be formed on the physically exposed surface of the second line groove and on the top surface of the semiconductor substrate 108. The conformal gate dielectric material layer includes a non-ferroelectric gate dielectric material, such as silicon oxide and / or a non-ferroelectric metal oxide material. The conformal gate dielectric material layer may be formed by a conformal formation process such as thermal oxidation and / or a chemical vapor deposition process. The thickness of the conformal gate dielectric material layer may be within 1 nm to 10 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0126] The first conductive gate electrode material layer may be formed on the conformal gate dielectric material layer. The first conductive gate material layer includes at least one gate electrode material, such as a heavily doped semiconductor material, a metal, a metal alloy, a metal semiconductor alloy (e.g., silicide), or a conductive metal compound (e.g., a metal nitride). The first conductive gate electrode material layer may fill the entire volume of each second linear trench 121.

[0127] A planarization process may be performed to remove portions of the first conductive gate electrode material layer and the conformal gate dielectric material layer from above a horizontal plane including the top surface of the semiconductor substrate 108. A chemical mechanical polishing process and / or a recess etching process may be used for the planarization process. Each remaining portion of the conductive gate electrode layer constitutes a continuous conductive line, which is referred to herein as a first gate electrode line 126. The first gate electrode line 126 corresponds to Figure 1A and Figure 1B The read line RL is shown. Each portion of the first gate electrode line 126 covering the semiconductor track region of the substrate semiconductor layer 108 constitutes a first gate electrode. Each first gate electrode line 126 includes a plurality of first gate electrodes.

[0128] The portion of the conformal gate dielectric material layer covering the top surface of the semiconductor substrate 108 can be removed by a planarization process. Each remaining portion of the conformal gate dielectric material layer located in the corresponding second linear trench constitutes a first gate dielectric strip 120. Each first gate dielectric strip 120 includes a plurality of gate dielectrics that contact a corresponding one of the semiconductor track regions of the substrate semiconductor layer 108.

[0129] The first gate dielectric strip 120 and the first gate electrode line 126 may be formed in each second line groove 121. The first gate dielectric strip 120 may include all first gate dielectrics in the corresponding row of ferroelectric memory cells, which are arranged along the second horizontal direction and have corresponding areas overlapping with the areas of the second line groove 121. The first gate electrode line 126 may include all first gate electrodes in the corresponding row of ferroelectric memory cells. The first gate dielectric and the first gate electrode form a plurality of stacks in each second line groove 121.

[0130] Each region of the substrate semiconductor layer 109 overlying the first gate dielectric (ie, a portion of the first gate dielectric strip 120) constitutes a first semiconductor channel 133. The first semiconductor channel 133 is formed under each first gate dielectric between respective adjacent pairs of first and second active regions 132, 134.

[0131] Each first gate dielectric strip 120 and thus each first gate dielectric strip may be disposed at a peripheral region of the second line trench 121 that extends downward from the top surface of the semiconductor substrate 108 and is located between adjacent pairs of first active regions 132 and second active regions 134 arranged along the second horizontal direction hd2. A first gate electrode line 126 including a plurality of first gate electrodes may be located above each first gate dielectric strip 120. Each first gate electrode is located inside the second line trench 121. Each first semiconductor channel 133 is located below a horizontal portion of the first gate dielectric.

[0132] The first field effect transistors (i.e., select gate transistors SG) are formed on the semiconductor substrate 108. Each of the first field effect transistors includes a first semiconductor channel 133 extending between a first active region 132 and a second active region 134 located in the semiconductor substrate 108 (e.g., in the substrate semiconductor layer 109), a first gate dielectric including a portion of the first gate dielectric strip 120 and having a U-shaped vertical cross-sectional profile, and a first gate electrode including a portion of the first gate electrode line 126.

[0133] See also Fig. 6A and Figure 6B, an optional gate dielectric material layer may be formed on the top surface of the semiconductor substrate 108 (e.g., in the substrate semiconductor layer 109). The optional gate dielectric material layer may include a non-ferroelectric gate dielectric material, such as silicon oxide and / or a non-ferroelectric metal oxide material. The optional gate dielectric material layer may be formed by oxidation of a surface portion of the substrate semiconductor layer 109 and / or by deposition of a gate dielectric material. The thickness of the gate dielectric material layer (if present) may be in the range of 0.5 nm to 6 nm, such as 1 nm to 3 nm, although lesser and greater thicknesses may also be employed.

[0134] A continuous ferroelectric material layer may be formed over the top surface of the semiconductor substrate 108 as a continuous material layer. As used herein, "ferroelectric material" refers to a crystalline material that exhibits spontaneous electric polarization in the absence of an external electric field. The ferroelectric material may be an insulating ferroelectric material. In one embodiment, the continuous ferroelectric material layer includes an orthorhombic hafnium oxide layer, which contains at least one dopant selected from Al, Zr and / or Si. Other suitable ferroelectric materials may also be used, such as titanate ferroelectric materials (e.g., barium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate ("PLZT"), etc.). The continuous ferroelectric material layer may have a thickness in the range of 3nm to 60nm, such as 6nm to 30nm, but smaller and larger thicknesses may also be used. In one embodiment, the continuous ferroelectric material layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0135] In one embodiment, the continuous ferroelectric material layer may be formed directly on the top surface of the optional gate dielectric material layer. Alternatively, the optional gate dielectric material layer may be omitted and the continuous ferroelectric material layer may be formed directly on the top surface of the substrate semiconductor layer 109. Generally speaking, the continuous ferroelectric material layer may be formed over the top surface of the semiconductor substrate 108 and the first gate electrode (which includes a portion of the first gate electrode line 126).

[0136] A second conductive gate electrode material layer may be formed over the continuous ferroelectric material layer by depositing a conductive gate electrode material. The conductive gate electrode material may include heavily doped semiconductor materials, metals, metal alloys, metal semiconductor alloys, and / or conductive metal compounds such as metal nitrides.

[0137] The second conductive gate electrode material layer, the continuous ferroelectric material layer and the optional gate dielectric material layer can be patterned into a gate stack structure. For example, a photoresist layer can be applied above the second conductive gate electrode material layer and can be patterned photolithographically to form a pattern (e.g., a rectangle) located between corresponding adjacent pairs of a row of second active areas 134 and a row of third active areas 136. Each row of second active areas 134 extends laterally along the second horizontal direction hd2, and each row of third active areas 136 extends laterally along the second horizontal direction hd2. Each patterned rectangle of the photoresist layer can have a uniform width along the first horizontal direction. An anisotropic etching process is performed to etch the second conductive gate electrode material layer, the continuous ferroelectric material layer and the optional gate dielectric material layer that are not masked by the photoresist layer. Each adjacent group of the second conductive gate electrode material layer, the continuous ferroelectric material layer and the remaining portion of the optional gate dielectric material layer constitutes a gate stack structure (150, 156).

[0138] Each gate stack structure (150, 156) includes a second gate dielectric 150 and a second gate electrode 156. Each second gate electrode 156 includes a patterned remaining portion of a second conductive gate electrode material layer. Each second gate dielectric 150 includes a ferroelectric material layer 152 and an optional non-ferroelectric dielectric layer 151. Each ferroelectric material layer 152 is a remaining patterned portion of a continuous ferroelectric material layer 152. Each non-ferroelectric dielectric layer 151 is a remaining patterned portion of an optional gate dielectric material layer. Each surface portion of the substrate semiconductor layer 109 located below the second gate dielectric 150 constitutes a second semiconductor channel 135.

[0139] The stack of the second gate dielectric 150 and the second gate electrode 156 may extend continuously over the second semiconductor channel 135 of the corresponding row arranged along the second horizontal direction hd2. The second gate dielectric 150 may include all the second gate dielectrics within the corresponding row of the ferroelectric memory cells arranged along the second horizontal direction hd2. The second gate electrode 156 may include all the second gate electrodes within the corresponding row of the ferroelectric memory cells.

[0140] Each second gate electrode includes a patterned portion of a second conductive gate material layer, and each second gate dielectric includes a patterned portion of a continuous ferroelectric material layer. A second semiconductor channel 135 is formed below each second gate dielectric between a corresponding second active region 134 and a corresponding third active region 136. A stack of a second gate electrode 156 including a ferroelectric material layer 152 and a second gate dielectric 150 is formed above a portion of the semiconductor substrate 108 located between each adjacent pair of the second active regions 134 and the third active regions 136.

[0141] The second field effect transistors (e.g., ferroelectric memory transistors, FeFETs) are disposed on the semiconductor substrate 108. Each second field effect transistor includes a second semiconductor channel 135 extending between a corresponding second active region 134 and a corresponding third active region 136, a second gate dielectric 150 covering the second semiconductor channel 135 and including a ferroelectric material layer 152, and a second gate electrode 156 covering the second gate dielectric 150.

[0142] A two-dimensional array of ferroelectric memory cells is provided. The two-dimensional array of ferroelectric memory cells may include multiple rows of ferroelectric memory cells. Each row of ferroelectric memory cells may include multiple ferroelectric memory cells arranged along a second horizontal direction hd2. The multiple rows of ferroelectric memory cells may be arranged along a first horizontal direction hd1 to provide a two-dimensional array of ferroelectric memory cells.

[0143] A subset of the first active regions 132 of the two-dimensional array of ferroelectric memory cells can be shared by corresponding adjacent pairs of ferroelectric memory cells arranged along the first horizontal direction hd1. The first active region 132, the second active region 134, and the third active region 136 within each ferroelectric memory cell are laterally spaced apart along the first horizontal direction hd1.

[0144] See also Fig. 7A and Figure 7B , a first interconnect level dielectric layer 160 may be deposited over the first exemplary structure. The first interconnect level dielectric layer 160 may include a single dielectric material layer, or may include multiple dielectric material layers. The first interconnect level dielectric layer 160 includes a dielectric material such as undoped silicate glass, doped silicate glass, and / or organosilicate glass. Optionally, the first interconnect level dielectric layer 160 is a dielectric liner, such as a silicon nitride liner or a dielectric metal oxide liner.

[0145] A via cavity may be formed through the first interconnect level dielectric layer 160. The via cavity includes a source contact via cavity extending to the first active region 132 or to the third active region 136, and a gate contact via cavity extending to the second gate electrode 156.

[0146] In addition, line cavities may be formed in an upper portion of the first interconnect level dielectric layer 160. The line cavities include source line cavities overlying source contact via cavities of a corresponding row, and word line cavities overlying gate contact via cavities of a corresponding row. The line cavities may extend laterally along a second horizontal direction hd2.

[0147] At least one conductive material may be deposited in the via cavity and the line cavity. The at least one conductive material may include a metal liner (such as a TiN liner) and a metal fill material (such as W). Excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the first interconnect level dielectric layer 160 by a planarization process, which may employ chemical mechanical polishing and / or recess etching. Each remaining portion of the at least one conductive material filling a corresponding one of the source contact via cavities constitutes a source contact via structure 172, and each remaining portion of the at least one conductive material filling a corresponding one of the gate contact via cavities constitutes a gate contact via structure 176. Each remaining portion of the at least one conductive material filling a corresponding one of the source line cavities constitutes a source line 182 (which corresponds to Figure 1A and Figure 1B The source line SL in the word line cavity, and each remaining portion of the at least one conductive material filling a corresponding one of the word line cavities constitutes a word line 186 (which corresponds to Figure 1A and Figure 1B The word line WL in the diagram.

[0148] The via cavities and line cavities and the corresponding contact via and line structures in these cavities may be formed by a dual damascene patterning process, which employs two photolithography exposure processes, two photolithography development processes, two anisotropic etching processes, and fills the two cavities with corresponding conductive via and line structures. Alternatively, the via cavities and line cavities and the corresponding contact via and line structures in these cavities may be formed by two single damascene processes, each of which employs a corresponding photolithography exposure process, a corresponding photolithography development process, a corresponding anisotropic etching process, and a corresponding separate filling process with conductive via or line structures.

[0149] In one embodiment, the gate contact via structure 176 may be formed in the region of the ferroelectric memory cell, that is, in the array region including the ferroelectric memory cell. In this case, the word line 186 may extend laterally in the array region along the second horizontal direction hd2. In an alternative embodiment, the gate contact via structure 176 may be formed in a peripheral region at an end portion of a corresponding one of the second gate electrode pads 156. In this case, the word line 186 may be formed in the peripheral region and may or may not extend laterally above the memory array region. The source line 182 extends laterally along the second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1. In one embodiment, the source contact via structure 172 may contact a corresponding one of the first active regions 132, and each of the first active regions 132 in a plurality of ferroelectric memory cells may be connected to a corresponding one of the source lines 182. In an alternative embodiment, the source contact via structure 172 may contact a corresponding one of the third active regions 136 , and each of the third active regions 136 within the plurality of ferroelectric memory cells may be connected to a corresponding one of the source lines 182 .

[0150] See also FIG. 8A to FIG. 8C , a second interconnect level dielectric layer 190 may be deposited over the first interconnect level dielectric layer 160. The second interconnect level dielectric layer 190 may include a single dielectric material layer, or may include multiple dielectric material layers. The second interconnect level dielectric layer 190 includes a dielectric material such as undoped silicate glass, doped silicate glass, and / or organosilicate glass. Optionally, the second interconnect level dielectric layer 190 is a dielectric liner, such as a silicon nitride liner or a dielectric metal oxide liner.

[0151] A via cavity may be formed through the second interconnect level dielectric layer 190. The via cavity includes a drain contact via cavity that extends to the third active region 136, or alternatively to the first active region 132 that is not contacted by the source contact via structure 172. For example, if the source contact via structure 172 contacts the first active region 132, the drain contact via cavity extends to the third active region 136, and if the source contact via structure 172 contacts the third active region 136, the drain contact via cavity extends to the first active region 132.

[0152] In addition, line cavities may be formed in an upper portion of the second interconnect level dielectric layer 190. The line cavities include a bit line cavity overlying a corresponding one of the semiconductor track regions. Each bit line cavity may extend laterally along a first horizontal direction hd1 and may overly a corresponding group of first active regions 132, second active regions 134, third active regions 136, first semiconductor channels 133, and second semiconductor channels 135.

[0153] At least one conductive material may be deposited in the drain contact via cavity and the bit line cavity. The at least one conductive material may include a metal liner (such as a TiN liner) and a metal fill material (such as W). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the second interconnect level dielectric layer 190 by a planarization process, which may employ chemical mechanical polishing and / or recess etching. Each remaining portion of the at least one conductive material filling a corresponding one of the drain contact via cavities constitutes a drain contact via structure 196, and each remaining portion of the at least one conductive material filling a corresponding one of the bit line cavities constitutes a bit line 198 (which corresponds to Figure 1A and Figure 1B The bit line BL in the circuit).

[0154] The via cavities and line cavities and the corresponding contact via and line structures in these cavities may be formed by a dual damascene patterning process, which employs two photolithography exposure processes, two photolithography development processes, two anisotropic etching processes, and fills the two cavities with corresponding conductive via and line structures. Alternatively, the via cavities and line cavities and the corresponding contact via and line structures in these cavities may be formed by two single damascene processes, each of which employs a corresponding photolithography exposure process, a corresponding photolithography development process, a corresponding anisotropic etching process, and a corresponding separate filling process with conductive via or line structures.

[0155] In one embodiment, the source contact via structure 172 may contact a corresponding one of the first active regions 132, and the drain contact via structure 196 may contact a corresponding one of the third active regions 136. Alternatively, the source contact via structure 172 may contact a corresponding one of the third active regions 136, and the drain contact via structure 196 may contact a corresponding one of the first active regions 132. The bit line 198 may extend laterally in a first horizontal direction hd1 over the semiconductor substrate 108. Each of the first active regions 132 within a plurality of ferroelectric memory cells is connected to a corresponding first element, which is a source line 182 or a bit line 198. Each of the third active regions 136 within the row of ferroelectric memory cells is connected to a second element, which is a bit line 198 or a source line 182. In this case, each first element is a source line 182 and each second element is a bit line 198 , or each first element is a bit line 198 and each second element is a source line 182 .

[0156] See also Figures 1A to 8CThe memory device of the first embodiment includes at least one ferroelectric memory cell, wherein each of the at least one ferroelectric memory cell includes: a corresponding first field effect transistor SG, the first field effect transistor SG including a first semiconductor channel 133 extending between a first active region 132 and a second active region 134 located in a semiconductor substrate 108, a first gate dielectric (e.g., a first gate dielectric strip 120) disposed at a peripheral region of a trench (i.e., a second linear trench 121) extending downward from a top surface of the semiconductor substrate 108 and located between the first active region 132 and the second active region 134; A portion), and a first gate electrode (for example, a portion of the first gate electrode line 126) located inside a trench above the first gate dielectric, wherein the first semiconductor channel 133 is covered below the horizontal portion of the first gate dielectric; and a corresponding second field effect transistor FeFET, the corresponding second field effect transistor FeFET including a second semiconductor channel 135 extending between the second active area 134 and the third active area 136, a second gate dielectric 150 including a ferroelectric material layer 152 covering the second semiconductor channel 135, and a second gate electrode 156 covering the second gate dielectric.

[0157] In one embodiment, the top surface of the first gate electrode is located in the same horizontal plane as the top surface of the semiconductor substrate 108. In one embodiment, the first gate dielectric has a U-shaped vertical cross-sectional profile and includes a pair of vertical portions and a horizontal portion adjacent to the bottom end of each of the pair of vertical portions. In one embodiment, each of the pair of vertical portions of the first gate dielectric and the horizontal portion of the first gate dielectric have the same material composition and the same thickness throughout.

[0158] In one embodiment, each of the first active region 132 , the second active region 134 , and the third active region 136 has a top surface within a horizontal plane that includes a top surface of the semiconductor substrate 108 (which may include a top surface of the substrate semiconductor layer 109 ).

[0159] In one embodiment, a bottom surface of the second gate dielectric lies within a horizontal plane that includes a top surface of the semiconductor substrate 108 ; and a top surface of the first gate dielectric lies within a horizontal plane that includes the top surface of the semiconductor substrate 108 .

[0160] In one embodiment, the at least one ferroelectric memory cell includes at least one row of ferroelectric memory cells (which may be arranged along a second horizontal direction hd2); and the row of ferroelectric memory cells includes: a first gate dielectric strip 120, which includes each of these first gate dielectrics within the row of ferroelectric memory cells; a first gate electrode line 126, which includes each of these first gate electrodes within the row of ferroelectric memory cells; a second gate dielectric 150 within the row of ferroelectric memory cells; and a second gate electrode 156 within the row of ferroelectric memory cells.

[0161] The first active region 132, the second active region 134 and the third active region 136 in each ferroelectric memory unit cell are spaced apart laterally along the first horizontal direction hd1. And the ferroelectric memory unit cells in the row of ferroelectric memory unit cells are spaced apart laterally along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1 by the dielectric isolation structure 12 located in the semiconductor substrate 108 and extending laterally along the first horizontal direction hd1.

[0162] In one embodiment, the first semiconductor channel 133 and the second semiconductor channel 135 have corresponding doping of a first conductivity type; and the first active region 132, the second active region 134 and the third active region 136 have a uniform width along the second horizontal direction hd1 and have doping of a second conductivity type opposite to the first conductivity type.

[0163] In one embodiment, each of the first active regions 132 within the row of ferroelectric memory cells is connected to a corresponding first element selected from a corresponding one of the source line 182 and the bit line 198; each of the third active regions 136 within the row of ferroelectric memory cells is connected to a corresponding second element selected from a corresponding one of the bit line 198 and the source line 182, the corresponding second element being different from the corresponding first element; the source line 182 is overlaid on the semiconductor substrate 108 and extends laterally along the second horizontal direction hd2; and the bit line 198 is overlaid on the semiconductor substrate 108 and extends laterally along the first horizontal direction hd1.

[0164] In one embodiment, the at least one row of ferroelectric memory cells includes multiple rows of ferroelectric memory cells arranged along a first horizontal direction hd1; the multiple rows of ferroelectric memory cells constitute a two-dimensional array of ferroelectric memory cells; and a subset of the first active region 132 of the two-dimensional array of ferroelectric memory cells is shared by corresponding adjacent pairs of ferroelectric memory cells arranged along the first horizontal direction hd1.

[0165] In one embodiment, the second gate dielectric and the second gate electrode have vertically coinciding sidewalls overlying the top surface of the semiconductor substrate 108; and the first gate dielectric has a lateral extent greater than the first gate electrode by twice the thickness of the vertical portion of the first gate dielectric.

[0166] See also Fig. 9A and Fig. 9B The second exemplary structure according to the second embodiment of the present disclosure includes a substrate 8 and a first alternating stack of first-level insulating layers 32 and first-level spacer material layers between respective vertically adjacent pairs of first-level insulating layers 32. The substrate 8 may include a substrate semiconductor layer 9 and a single-crystalline doped semiconductor material layer 6, which serves as a common active region of a vertical field effect transistor subsequently formed by the first alternating stack.

[0167] The substrate semiconductor layer 9 may include a top portion of a semiconductor substrate (e.g., a silicon wafer), a doped well in a top portion of a semiconductor substrate, or a semiconductor layer located above the substrate. For example, the substrate semiconductor layer 9 includes a doped semiconductor material having a first conductivity type. In one embodiment, the substrate semiconductor layer 9 may include a doped single crystal doped semiconductor material having a first conductivity type. The atomic concentration of the dopant of the first conductivity type in the substrate semiconductor layer 9 may be in the range of 1.0×10 14 / cm 3 to 1.0×10 18 / cm 3 The single crystal doped semiconductor material layer 6 may include a doped well in the top portion of the semiconductor substrate or a doped semiconductor layer located above the substrate. The doped semiconductor material layer 6 includes a doped semiconductor material having a second conductivity type that is opposite to the first conductivity type. The atomic concentration of the dopant of the second conductivity type in the single crystal doped semiconductor material layer 6 may be within a range of 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3The thickness of the single crystal doped semiconductor material layer 6 may be in the range of 50 nm to 500 nm, but smaller and larger dopant concentrations may also be employed. In one embodiment, each of the substrate semiconductor layer 9 and the single crystal doped semiconductor material layer 6 may include respective single crystal doped silicon epitaxially aligned with each other. In one embodiment, the single crystal doped semiconductor material layer 6 may be formed by implanting or diffusing a dopant of the second conductivity type into an upper portion of the semiconductor substrate including the substrate semiconductor layer 9, and by converting the implanted upper portion of the substrate semiconductor layer 9 into the single crystal doped semiconductor material layer 6. Alternatively, the single crystal doped semiconductor material layer 6 may be epitaxially grown on top of the substrate semiconductor layer 9.

[0168] The first-level insulating layer 32 includes an insulating material, such as undoped silicate glass, doped silicate glass, or organic silicate glass. The thickness of each first-level insulating layer 32 can be in the range of 20nm to 200nm, but smaller and larger thicknesses can also be used. The first-level spacer material layer can be formed as a first-level sacrificial material layer 42 that can be replaced with a first-level conductive layer. Alternatively, the first-level spacer material layer can be formed as a first-level conductive layer. Although the present disclosure is described using an embodiment in which the first-level spacer material layer is formed as a first-level sacrificial material layer 42, an embodiment in which the first-level spacer material layer is formed as a first-level conductive layer is explicitly contemplated herein. In this case, a processing step for replacing the first-level sacrificial material layer 42 with a first-level conductive layer is not necessary. The thickness of each first-level spacer material layer can be in the range of 20nm to 200nm, but smaller and larger thicknesses can also be used.

[0169] In one embodiment, the first alternating stack (32, 42) may include three first-level insulating layers 32 and two first-level sacrificial material layers 42. A two-dimensional array of discrete openings through the first alternating stack (32, 42) may be formed, for example, by applying a photoresist layer and patterning it, and transferring the pattern in the photoresist layer through the first alternating stack (32, 42) by using an anisotropic etching process. The two-dimensional array of discrete openings is referred to herein as a two-dimensional array of first-level discrete memory openings 49. Each first-level discrete memory opening 49 may have a corresponding circular or elliptical horizontal cross-sectional shape. The maximum lateral dimension of each first-level discrete memory opening 49 may be in the range of 20nm to 400nm, such as 40nm to 200nm, but smaller and larger maximum lateral dimensions may also be used. A portion of the top surface of the single-crystalline doped semiconductor material layer 6 may be physically exposed at the bottom of each first-level discrete memory opening 49.

[0170] Generally speaking, a vertical layer stack of a first insulating layer 32, a first spacer material layer (such as a first sacrificial material layer 42), a second insulating layer 32, a second spacer material layer (such as a second sacrificial material layer 42), and a third insulating layer 32 can be formed above the single crystal doped semiconductor material layer 6. Each of the first spacer material layer and the second spacer material layer can be formed as a corresponding conductive layer or can be subsequently replaced with a corresponding conductive layer. Each portion of the single crystal doped semiconductor material layer 6 located below the first level discrete memory opening 49 constitutes a first active region, which can be a source region or a drain region of a corresponding vertical field effect transistor. At least one opening can be formed through the vertical layer stack so that the top surface of the corresponding first active region is physically exposed below each opening in the at least one opening. The at least one opening through the vertical layer stack may include a plurality of first level discrete memory openings 49 that are laterally spaced apart from each other.

[0171] See also Fig. 10A and Fig. 10B , the first gate dielectric 20 can be formed at the bottom portion of each first-level discrete memory opening 49 by conformal deposition of the first gate dielectric material layer and anisotropic etching processes. Optionally, a sacrificial filling material (such as a photoresist material) can be deposited in the first-level discrete memory opening 49 and can be vertically recessed so that the recessed surface of the sacrificial filling material is located between the first sacrificial material layer 42 and the second sacrificial material layer 42. In this case, an isotropic etching process can be used to remove the cylindrical portion of the first gate dielectric material layer from above the top surface of the portion of the sacrificial filling material. The sacrificial filling material can then be removed, for example, by ashing. Each remaining portion of the first gate dielectric material layer constitutes a first gate dielectric 20, which can have a corresponding tubular shape.

[0172] See also Fig.11A and Fig. 11B, the first vertical semiconductor channel 33 may be formed by depositing a doped first semiconductor material having a first conductivity type in a lower portion of each of the first level discrete memory openings 49. In one embodiment, each first vertical semiconductor channel 33 may be formed by a selective epitaxial process that grows the first semiconductor material from a physically exposed surface of the single crystalline doped semiconductor material layer 6. In this case, each first vertical semiconductor channel 33 may include a first single crystalline epitaxial semiconductor material epitaxially aligned with the single crystalline doped semiconductor material layer 6. If the first gate dielectric material layer has not been recessed before forming the first vertical semiconductor channel 33, the first gate dielectric material layer is recessed by selective etching to be flush with the top of the first vertical semiconductor channel 33. Then, a top portion 33T of the first vertical semiconductor channel 33 is epitaxially grown on the first vertical semiconductor channel 33 above the first gate dielectric 20. The top portion 33T of the first vertical semiconductor channel 33 contacts the sidewall of the insulating layer 32 exposed in the memory opening 49. The top surface of each first vertical semiconductor channel 33 (e.g., the top surface of the top portion 33T thereof) may be located at or above the topmost surface of the first gate dielectric 20 within the same first level discrete memory opening 49. A first memory cavity 49' exists within each unfilled volume of the first level discrete memory openings 49.

[0173] See also Fig. 12A and Fig. 12B , at least one second gate dielectric material layer (52L, 50L) may be formed by a corresponding conformal deposition process. The at least one second gate dielectric material layer (52L, 50L) may include a continuous ferroelectric material layer 52L and an optional non-ferroelectric gate dielectric material layer 50L. The continuous ferroelectric material layer 52L may include any material that can be used for the ferroelectric material layer 152 of the first exemplary structure. The non-ferroelectric gate dielectric material layer 50L (if present) may include any non-ferroelectric gate dielectric material.

[0174] See also Fig.13A and Fig. 13B , an anisotropic etching process may be performed to remove horizontal portions of the at least one second gate dielectric material layer (52L, 50L). Each remaining cylindrical portion of the at least one second gate dielectric material layer (52L, 50L) constitutes a second gate dielectric (52, 50). Each second gate dielectric (52, 50) includes a ferroelectric material layer 52 and an optional non-ferroelectric gate dielectric 50. The top surface of the first vertical semiconductor channel 33 is exposed in the first memory cavity 49'.

[0175] See also Fig.14A and Fig. 14B, the second vertical semiconductor channel 35 can be formed in each first memory cavity 49' by depositing a second semiconductor material. In one embodiment, each second vertical semiconductor channel 35 can be formed by a selective epitaxial process that grows the second semiconductor material from the physically exposed surface of the corresponding first vertical semiconductor channel 33. In this case, each second vertical semiconductor channel 35 can include a second single crystal epitaxial semiconductor material (e.g., single crystal silicon) epitaxially aligned with the single crystal doped semiconductor material layer 6 through the corresponding first single crystal epitaxial semiconductor material of the first vertical semiconductor channel 33. Each second vertical semiconductor channel 35 can include a second single crystal epitaxial semiconductor material epitaxially aligned with the corresponding first single crystal epitaxial semiconductor material.

[0176] Each second gate dielectric (52, 50) may include a ferroelectric material layer 52 and may contact a bottom portion of a sidewall of the second vertical semiconductor channel 35. In general, FIG. 10A to FIG. 11B The processing steps and FIG. 12A to FIG. 14B The order of the processing steps can be reversed. Therefore, the second vertical semiconductor channel 35 can be formed above or below the first vertical semiconductor channel 33. Each second gate dielectric (52, 50) can contact the top or bottom of the first vertical semiconductor channel 33. Each second vertical semiconductor channel 35 can include a second single crystal epitaxial semiconductor material, which is epitaxially aligned with the corresponding first single crystal epitaxial semiconductor material overlying the first vertical semiconductor channel 33 above or below. Each vertical stack of the first vertical semiconductor channel 33 and the second vertical semiconductor channel 33 constitutes a portion of a ferroelectric memory cell.

[0177] See also Fig.15A and Fig. 15B A first backside groove 79 extending vertically through the first alternating stack (32, 42) can be formed by applying a photoresist layer above the first alternating stack (32, 42) and patterning it to form a linear opening extending in a horizontal direction (such as a second horizontal direction hd2) in the photoresist layer, and transferring the pattern of the linear opening through the second alternating stack (32, 42) by performing an anisotropic etching process.

[0178] See also Fig.16A and Fig. 16B The first backside recess 43 may be formed by etching the first level sacrificial material layer 42 that is selective to the first level insulating layer 32, the first gate dielectric 20, the second gate dielectric (52, 50), and the single crystalline doped semiconductor material layer 6. For example, if the first level sacrificial material layer 42 includes silicon nitride, wet etching using hot phosphoric acid may be performed to form the first backside recess 43.

[0179] See also Fig.17A and Fig. 17B , at least one conductive material may be deposited in the first backside recess 43 by a conformal deposition process to form the first level conductive layer 46. The at least one conductive material may include, for example, a metal liner material such as TiN and a metal filling material such as W. Excess portions of the at least one conductive material in the first backside trench 79 and above the topmost first level insulating layer 32 may be removed by an isotropic recess etching process.

[0180] Dielectric material may be deposited in first backside trenches 79 and over topmost first level insulating layer 32. Each portion of dielectric material filling first backside trenches 79 constitutes first backside trench filling structure 76. Planar portions of dielectric material deposited over topmost first level insulating layer 32 constitute first contact level dielectric layer 47.

[0181] See also Fig.18A Fig.18B , a first contact via cavity 39 may be formed through the first contact-level dielectric layer 47 above a corresponding one of the second vertical semiconductor channels 35. A top surface of the second vertical semiconductor channel 35 may be physically exposed at the bottom of each first contact via cavity 39. In one embodiment, the first contact via cavity 39 may be elongated along a horizontal direction such as the first horizontal direction hd1. In one embodiment, the first contact via cavity 39 may be laterally offset along the second horizontal direction hd2 such that the lateral extent of the first contact via cavity 39 between adjacent pairs of first backside trench filling structures 76 has no overlap within the lateral extent along the second horizontal direction hd2, or has a minimal overlap along the second horizontal direction hd2.

[0182] See also Fig.19A and Fig.19B , conductive material may be deposited in the first contact via cavity 39 and on the top surface of the first contact level dielectric layer 47. The deposited conductive material filling the first contact via cavity 39 and covering the first contact level dielectric layer 47 constitutes a bit line level conductive material layer (38L, 138L). The bit line level conductive material layer (38L, 138L) includes a first contact via structure 38V filling the first contact via cavity 39 and a planar conductive material layer covering the first contact level dielectric layer 47.

[0183] In one embodiment, the bit line level conductive material layer (38L, 138L) may be formed by performing a selective epitaxial process of growing a single crystalline semiconductor material from the physically exposed surface of the second vertical semiconductor channel 35. The single crystalline semiconductor material portion may grow from the physically exposed surface of the second vertical semiconductor channel 35 and fill each of the first contact via cavities 39, and grow over the top surface of the first contact level dielectric layer 47. The single crystalline grains grown through different first contact via cavities 39 may contact each other and form a crystalline epitaxial semiconductor material layer 38L including a plurality of single crystalline semiconductor material grains epitaxially aligned with a corresponding one of the second vertical semiconductor channels 35 and contacting each other at a grain boundary GB located between regions of the first contact via cavities 39. In one embodiment, the grain boundary GB does not overlie any of the first contact via cavities 39. The assembly of all single-crystalline grains (ie, single-crystalline semiconductor material portions) constitutes a multi-grain epitaxial semiconductor layer 38L including a plurality of epitaxial semiconductor material grains, wherein each epitaxial semiconductor material grain is epitaxially aligned with an underlying second vertical semiconductor channel 35 .

[0184] Optionally, a peripheral portion of the bitline-level conductive material layer (38L, 138L) is formed by a non-selective semiconductor deposition process to form a polycrystalline semiconductor layer 138L. The polycrystalline epitaxial semiconductor layer 38L and the optional polycrystalline semiconductor layer 138L may be planarized, for example, by chemical mechanical polishing, to provide a flat top surface. The polycrystalline epitaxial semiconductor layer 38L and the optional polycrystalline semiconductor layer 138L may be doped with a dopant of the second conductivity type by in-situ doping or by ion implantation. The polycrystalline epitaxial semiconductor layer 38L and the optional polycrystalline semiconductor layer 138L may include an atomic concentration of 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The second conductivity type dopant may be within a range of 100 to 100, but smaller and larger dopant concentrations may also be used. The combination of the polycrystalline epitaxial semiconductor layer 38L and the polycrystalline semiconductor layer 138L constitutes a bit line level conductive material layer (38L, 138L).

[0185] See also Fig. 20A and Fig. 20B A photoresist layer (not shown) may be applied over the bit line level conductive material layer (38L, 138L) and may be photolithographically patterned to form line patterns extending laterally along the first horizontal direction hd1. Each line pattern may cover a corresponding one of the first contact via structures 38V. In one embodiment, each line pattern of the photoresist layer may cover only one first conductive via structure 38V between each laterally adjacent pair of first backside trench fill structures 76.

[0186] An anisotropic etching process may be performed to transfer a line pattern through the bit line level conductive material layer (38L, 138L). The bit line level conductive material layer (38L, 138L) may be patterned into a plurality of discrete portions, wherein each discrete portion includes a bit line 38 and a first contact via structure 38V. Each bit line 38 is a conductive line structure including a plurality of single crystal grains 38A epitaxially aligned with a corresponding one of the single crystal epitaxial semiconductor material portions of the underlying ferroelectric memory cell, and optionally including a polycrystalline line portion 38B including a doped semiconductor material having a doping of the second conductivity type.

[0187] Generally speaking, the ferroelectric memory cell UC includes a vertical stack of a lower field effect transistor and an overlying field effect transistor. The lower field effect transistor and the overlying field effect transistor can be formed in each opening of at least one opening (i.e., the first level discrete memory opening 49) through the vertical layer stack (32, 42). The lower field effect transistor includes a first field effect transistor (e.g., Figure 1A and Figure 1B The select gate transistor SG shown) and the second field effect transistor (eg, Figure 1A and Figure 1B The ferroelectric memory transistor FeFET shown in the figure is one of them, and the overlying field effect transistor includes the other of the first field effect transistor and the second field effect transistor. The second field effect transistor covers on or below the first field effect transistor.

[0188] The first field effect transistor SG includes a first vertical semiconductor channel 33, a first gate dielectric 20 contacting the sidewall of the first vertical semiconductor channel 33, and a portion of the first level conductive layer 46 contacting the first gate dielectric 20. Each first vertical semiconductor channel 33 and each second vertical semiconductor channel 35 of each ferroelectric memory unit cell UC includes a corresponding single crystal epitaxial semiconductor material portion epitaxially aligned with the single crystal doped semiconductor material layer 6. A vertical stack of the first field effect transistor SG and the second field effect transistor FeFET is formed above the first active region, which can be a source region connected to a conductive source line or a doped semiconductor source line. For example, Figure 1A and Figure 1B The source line SL shown may include a single crystalline doped semiconductor material layer 6. A corresponding second active region may be formed on the top of the corresponding stack of the first vertical semiconductor channel 33 and the second vertical semiconductor channel 35. Each second active region may be a drain region located in a first contact via structure 38V connected to a bit line 38. The bit line 38 corresponds to Figure 1A and Figure 1B The bit line BE in.

[0189] A plurality of ferroelectric memory cells UC may be formed within the plurality of first-level discrete memory openings 49. Each of the first-level discrete memory openings 49 may have a closed horizontal cross-sectional shape and may extend continuously through each of the three insulating layers 32, the first conductive layer 46RL, and the second conductive layer 46WL. Each of the first gate dielectric 20 and the second gate dielectric (52, 50) is located inside the corresponding first-level discrete memory opening 49. The first conductive layer 46RL may correspond to Figure 1A and Figure 1B The second conductive layer 46WL may correspond to the read line RL of Figure 1A and Figure 1B The word line WL may surround the second vertical semiconductor channel 35.

[0190] The first active region (which may be implemented as a single-crystal doped semiconductor material layer 6), the first conductive layer 46, the second conductive layer 46, and the second active region (such as implemented as a first contact via structure 38V and / or a bit line 38) are vertically spaced apart from each other by three insulating layers 32 that are vertically spaced apart from each other. In one embodiment, the outer sidewalls of the second gate dielectric (52, 50) are vertically coincident with the outer sidewalls of the first gate dielectric 20.

[0191] In one embodiment, the interface between the first conductive layer 46RL and the first gate dielectric 20 is vertically coincident with the interface between the second conductive layer 46WL and the second gate dielectric (52, 50). Each of the insulating layers 32 has a sidewall that contacts the first gate dielectric 20 or the second gate dielectric (52, 50) and vertically coincides with the interface between the first conductive layer 46RL and the first gate dielectric 20. The manufacturing process of the second exemplary device of the second embodiment can be stopped at this point.

[0192] Optionally, in Fig. 20A and Fig. 20B Another device level including another array of cells is formed above the device shown. Fig.21A and Fig. 21B , a second contact level dielectric layer 97 may be formed above and between the bit lines 38. A second contact via cavity may be formed through the second contact level dielectric layer 97 such that the top surface of the underlying bit line 38 is physically exposed. A second contact via structure 88 may be formed in the second contact via cavity by deposition and planarization of at least one conductive material.

[0193] In one embodiment, the second contact via structure 88 may include a doped semiconductor material having a doping of the second conductivity type. The second contact via structure 88 may include an atomic concentration of 5.0×10 18 / cm 3 Up to 2.0×1021 / cm 3 , but smaller and larger dopant concentrations may also be used. In one embodiment, the second contact via structures 88 may include a single crystalline doped semiconductor material within the underlying single crystalline grains of the underlying bit line 38. In this case, the second contact via structures 88 may be formed by a selective epitaxial process that grows a single crystalline semiconductor material portion from a physically exposed single crystalline surface of the bit line 38. In one embodiment, each second contact via structure 88 may have the same area overlap as the underlying first via structure in the first contact via structure 38V and / or may be located in the same area as the underlying first via structure in the first contact via structure 38V.

[0194] See also Fig.22A and Fig. 22B , a second alternating stack (82, 92) of second-level insulating layers 82 and second-level spacer material layers may be formed over the second contact-level dielectric layer 97. The second-level insulating layers 82 include insulating materials such as undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of each second-level insulating layer 82 may be in the range of 20 nm to 200 nm, although smaller and larger thicknesses may also be employed. The second-level spacer material layer may be formed as a second-level sacrificial material layer 92 that may subsequently be replaced with a second-level conductive layer. Alternatively, the second-level spacer material layer may be formed as a second-level conductive layer. Although the present disclosure is described using an embodiment in which the second-level spacer material layer is formed as a second-level sacrificial material layer 92, embodiments in which the second-level spacer material layer is formed as a second-level conductive layer are explicitly contemplated herein. In this case, a processing step for replacing the second-level sacrificial material layer 92 with a second-level conductive layer is not necessary. The thickness of each second-level spacer material layer may be in the range of 20 nm to 200 nm, although smaller and larger thicknesses may also be employed.

[0195] In one embodiment, the second alternating stack (82, 92) may include three second-level insulating layers 82 and two second-level sacrificial material layers 92. A two-dimensional array of discrete openings passing through the second alternating stack (82, 92) may be formed, for example, by applying a photoresist layer and patterning it, and transferring the pattern in the photoresist layer through the second alternating stack (82, 92) using an anisotropic etching process. The two-dimensional array of discrete openings is referred to herein as a two-dimensional array of second-level discrete memory openings 99. Each second-level discrete memory opening 99 may have a corresponding circular or elliptical horizontal cross-sectional shape. The maximum lateral dimension of each secondary discrete memory opening 99 may be in the range of 20nm to 400nm, such as 40nm to 200nm, but smaller and larger maximum lateral dimensions may also be used. A portion of the top surface of the second contact through-hole structure 88 may be physically exposed at the bottom of each second-level discrete memory opening 99.

[0196] See also Fig.23 , a third gate dielectric (102, 100) can be formed at the lower portion of each second-level discrete memory opening 99. Each third gate dielectric (102, 100) includes a ferroelectric material layer 102 and an optional non-ferroelectric gate dielectric 100, and can be formed by depositing and anisotropically etching continuous ferroelectric material layers and non-ferroelectric gate dielectric layers. For example, a sacrificial filling material can be deposited and recessed so that the top surface of the sacrificial filling material portion is located at the level of the middle second-level insulating layer 82 of the three second-level insulating layers 82, and the upper region of each remaining tubular portion of the continuous ferroelectric material layer and the non-ferroelectric gate dielectric layer is removed by isotropically etching the unmasked portion of the remaining portion of the continuous ferroelectric material layer and the non-ferroelectric gate dielectric layer. The sacrificial filling material portion can then be removed, for example, by ashing.

[0197] The third vertical semiconductor channel 85 can be grown from the physically exposed surface of the second contact via structure 88. In one embodiment, the third vertical semiconductor channel 85 can include a doped single crystalline semiconductor material having a first conductivity type. Each third vertical semiconductor channel 85 can provide the same function as the second vertical semiconductor channel 35, and each third gate dielectric (102, 100) can provide the same function as the second gate dielectric (52, 50).

[0198] See also Fig.24 , you can execute Fig. 10A , Fig. 10B , Fig.11A and Fig. 11BThe fourth gate dielectric 70 and the fourth vertical semiconductor channel 83 are formed by a process step of forming the fourth gate dielectric 70 and the fourth vertical semiconductor channel 83. The fourth gate dielectric 70 may include any material that can be used for the first gate dielectric 20. The fourth vertical semiconductor channel 83 may include a doped single crystalline semiconductor material having a first conductivity type and may be formed by selective epitaxy. According to the second embodiment of the present disclosure, the top surface of the fourth vertical semiconductor channel 83 may be coplanar with the top surface of the topmost second-level insulating layer in the second-level insulating layer 82.

[0199] See also Fig.25 , a photoresist layer can be applied above the second alternating stack (82, 92) and patterned to form a linear opening extending in a horizontal direction (such as a second horizontal direction hd2) in the photoresist layer, and the pattern of the linear opening can be transferred through the second alternating stack (82, 92) by performing an anisotropic etching process to form a second backside groove extending vertically through the second alternating stack (82, 92).

[0200] The second backside recess may be formed by etching the second level sacrificial material layer 92 having selectivity to the second level insulating layer 82, the third gate dielectric (102, 100), the fourth gate dielectric 70, and the second contact level dielectric layer 97. For example, if the second level sacrificial material layer 82 includes silicon nitride, wet etching using hot phosphoric acid may be performed to form the second backside recess.

[0201] The second level conductive layer 96 may be formed by depositing at least one conductive material in the second backside recess by a conformal deposition process. The at least one conductive material may include, for example, a metal liner material such as TiN and a metal fill material such as W. Excess portions of the at least one conductive material in the second backside trench and above the topmost second insulating layer 82 may be removed by an isotropic recess etching process.

[0202] The dielectric material may be deposited in the second backside trenches and over the topmost second insulating layer 82. Each portion of the dielectric material filling the second backside trench constitutes a second backside trench filling structure 78. The planar portion of the dielectric material deposited over the topmost second insulating layer 82 may be removed by a planarization process such as recess etching and / or chemical mechanical polishing.

[0203] See also Fig.26A and Fig.26B , a conductive material may be deposited on the physically exposed top surface of the fourth vertical semiconductor channel 83. The deposited conductive material covering the fourth vertical semiconductor channel 83 constitutes a source-line level conductive material layer 7.

[0204] In one embodiment, the source-line level conductive material layer 7 may be formed by performing a selective epitaxial process to grow a single crystalline semiconductor material from physically exposed surfaces of the fourth vertical semiconductor channel 83. The single crystalline semiconductor material portion may be grown from physically exposed surfaces of the fourth vertical semiconductor channel 83.

[0205] The single crystal grains grown from different fourth vertical semiconductor channels 83 may contact each other and form a crystalline epitaxial semiconductor material layer including a plurality of single crystal semiconductor material grains epitaxially aligned with a corresponding one of the fourth vertical semiconductor channels 83 and contacting each other at a grain boundary GB located between regions of the fourth vertical semiconductor channels 83. In one embodiment, the grain boundary GB does not overlie any of the fourth vertical semiconductor channels 83. The assembly of all the single crystal grains (i.e., the single crystal semiconductor material portions) constitutes a multi-grain epitaxial semiconductor layer 7A including a plurality of epitaxial semiconductor material grains, each of which is epitaxially aligned with an underlying fourth vertical semiconductor channel 83.

[0206] Optionally, the peripheral portion of the source-line level conductive material layer 7 may be deposited by a non-selective semiconductor deposition process to form a polycrystalline semiconductor layer 7B. The polycrystalline epitaxial semiconductor layer 7A and the optional polycrystalline semiconductor layer 7B may be planarized, for example, by chemical mechanical polishing, to provide a flat top surface. The polycrystalline epitaxial semiconductor layer 7A and the optional polycrystalline semiconductor layer 7B may be doped with a dopant of the second conductivity type by in-situ doping or by ion implantation. The polycrystalline epitaxial semiconductor layer 7A and the optional polycrystalline semiconductor layer 7B may include an atomic concentration of 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The second conductivity type dopant may be within a range of , but smaller and larger dopant concentrations may also be used. The polycrystalline epitaxial semiconductor layer 7A and the polycrystalline semiconductor layer 7B constitute the source-line level conductive material layer 7 (eg, Figure 1B , and a second source line as shown).

[0207] A third active region (e.g., a source region or source line including a portion of the source-line level conductive material layer 7) may be formed on top of the respective stacks of the third vertical semiconductor channel 85 and the fourth vertical semiconductor channel 83. Each of the at least one ferroelectric memory unit cell (UC1, UC2) includes a respective vertical stack of ferroelectric memory unit cells.

[0208] Generally speaking, a stack of a third field effect transistor and a fourth field effect transistor may be formed above a second active region, which may include a combination of a first contact via structure 38V, a bit line 38, and a second contact via structure 88. The fourth field effect transistor may be overlaid on or below the third field effect transistor. The third field effect transistor (e.g., another ferroelectric memory transistor FeFET) includes a third vertical semiconductor channel 85, a third gate dielectric (102, 100) including an additional ferroelectric material layer 102 and contacting the sidewalls of the third vertical semiconductor channel 85, and a portion of the third conductive layer 96 contacting the third gate dielectric (102, 100). The fourth field effect transistor (e.g., another selection gate transistor SG) includes a fourth vertical semiconductor channel 83, a fourth gate dielectric 70 contacting the sidewalls of the fourth vertical semiconductor channel 83 and contacting the top or bottom of the second vertical semiconductor channel 85, and a portion of the fourth conductive layer 96 contacting the fourth gate dielectric 70.

[0209] In one embodiment, at least one ferroelectric memory cell (UC1, UC2) of the ferroelectric memory device of the present disclosure may include at least one vertical stack of a first-level ferroelectric memory cell UC1 and a second-level ferroelectric memory cell UC2. The second-level ferroelectric memory cell UC2 covers the first-level ferroelectric memory cell UC1 above or below, and has an area overlap with the first-level ferroelectric memory cell UC1 in a plan view along a vertical direction, and the vertical direction is a direction perpendicular to the top surface of the semiconductor substrate 8. In one embodiment, each vertical stack of the first-level ferroelectric memory cell UC1 and the second-level ferroelectric memory cell UC2 includes a lower ferroelectric memory cell and an overlying ferroelectric memory cell, and the overlying ferroelectric memory cell is farther from the substrate 8 than the lower ferroelectric memory cell.

[0210] Each ferroelectric memory cell (UC1, UC2) may include a corresponding first field effect transistor (i.e., a selection gate transistor SG, such as the first field effect transistor of the first-level ferroelectric memory cell UC1 or the fourth field effect transistor of the second-level ferroelectric memory cell UC2) and a corresponding second field effect transistor (i.e., a ferroelectric memory transistor FeFET, such as the second field effect transistor of the first-level ferroelectric memory cell UC1 or the third field effect transistor of the second-level ferroelectric memory cell UC2). In one embodiment, the second field effect transistor of the first-level ferroelectric memory cell UC1 covers the first field effect transistor of the first-level ferroelectric memory cell UC1, and the second field effect transistor of the second-level ferroelectric memory cell UC2 (such as the third field effect transistor including the third gate dielectric (102, 100)) covers the first field effect transistor of the second-level ferroelectric memory cell UC2 (such as the fourth field effect transistor including the fourth gate dielectric 70).

[0211] In one embodiment, the first active region (e.g., the first source or the first source line) of the underlying ferroelectric memory cell is located in a single crystalline doped semiconductor material layer 6 (e.g., the first source line) having a lateral extent along a second horizontal direction hd2 that is greater than the width of a conductive structure (such as the bit line 38) along the second horizontal direction hd2. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1. The second active region of the overlying ferroelectric memory cell may include a conductive material layer (such as a source-line level conductive material layer 7, i.e., the second source line) having a lateral extent along the second horizontal direction hd2 that is greater than the width of a conductive structure (such as the bit line 38) along the second horizontal direction hd2. The first source line and the second source line may be electrically separated, as Figure 1B As shown, they can also be electrically connected to each other ( Fig.26A and Fig.26B ), such as Figure 1A shown.

[0212] The shared third active region (e.g., drain region) of the lower ferroelectric memory unit cell and the overlying ferroelectric memory unit cell includes a shared bit line 38, which extends laterally along the first horizontal direction between the lower ferroelectric memory unit cell and the overlying ferroelectric memory unit cell. Alternatively, the individual drain regions 38V, 88 of each unit cell are electrically connected to the shared bit line 38.

[0213] See also Fig.27A and Fig.27B The third exemplary structure according to the third embodiment of the present disclosure can be obtained by forming the first-level line trench 149 instead of the first-level discrete memory opening 49. Fig. 9A and Fig. 9B The second exemplary structure shown is obtained. The first-level linear grooves 149 may have a corresponding uniform width everywhere and extend laterally in the horizontal direction. An embodiment is shown herein, in which the first-level linear grooves 149 extend laterally in the second horizontal direction.

[0214] See also Fig.28A and Fig.28B , you can execute Fig. 10A and Fig. 10B The first gate dielectric 20 is formed by a first vertical semiconductor channel material portion 33' and a first vertical semiconductor channel material portion 33' is epitaxially grown. Each of the first vertical semiconductor channel material portions 33' includes a single crystalline semiconductor material (e.g., single crystalline silicon) that can be subsequently patterned to form a plurality of vertical semiconductor channels. A line cavity 149 exists within each unfilled volume of the first level line trench 149.

[0215] FIG. 28C to FIG. 28E1 shows the steps of forming an alternative configuration of the third exemplary structure. In this alternative configuration, the first vertical semiconductor channel 33 includes a polycrystalline semiconductor layer (e.g., polysilicon) that is deposited in the first level line trench 149 and then etched back. Specifically, as Fig.28C As shown, a thin film polysilicon first vertical semiconductor channel material layer 33L is deposited in the first level line trench 149 and is optionally recessed. Fig.28D As shown, the horizontal portion of the first vertical semiconductor channel material layer 33L is removed by anisotropic etching to form the first vertical semiconductor channel 33 and expose the layer 6 at the bottom of the first level line trench 149. Fig.28E As shown, the first dielectric core 25 is then deposited over the first vertical semiconductor channel 33 in the first-level linear trench 149 and recessed to be flush with the top of the first vertical semiconductor channel 33. If the first vertical semiconductor channel 33 is not recessed in the previous step, the first vertical semiconductor channel 33 may be recessed together with the first dielectric core 25.

[0216] See also Fig.29A and Fig.29B , a sacrificial spacer (not shown) can be formed on the sidewall of the upper region of the first level line trench 149 by conformal deposition and anisotropic etching of a sacrificial spacer material. The sacrificial spacer material may include a silicon oxide material (such as borosilicate glass), a silicon germanium alloy, a carbon-based material (such as amorphous carbon), or a polymer material with a high etching rate. The central portion of the first vertical semiconductor channel material portion 33' can be removed by an anisotropic etching process to physically expose the top surface of the single-crystalline doped semiconductor material layer 6. The remaining portion of the first vertical semiconductor channel material portion 33 constitutes a vertical semiconductor channel 33.

[0217] A dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass may be deposited in the cavity formed by removing the central portion of the first vertical semiconductor channel material portion 33'. The dielectric material may be vertically recessed to form the first dielectric core 25. A sacrificial spacer selective to the first dielectric core 25 and the first vertical semiconductor channel 33 may be removed.

[0218] Fig.29C An alternative configuration is shown in which the vertical semiconductor channel 33 comprises a thin film polycrystalline semiconductor layer. Fig.28E After the step shown, the top portion 33T of the first vertical semiconductor channel 33 grows on the first vertical semiconductor channel 33 above the first gate dielectric 20, as shown in FIG. Fig.29C shown.

[0219] See also Fig. 30A and Fig. 30B , you can execute Fig. 12A , Fig. 12B , Fig.13A and Fig. 13B The second gate dielectrics (50, 52) are formed by processing steps of: Each second gate dielectric (50, 52) includes a ferroelectric material layer 52 and an optional non-ferroelectric gate dielectric 50.

[0220] See also Fig.31A and Fig.31B , you can execute Fig.14A and Fig. 14B The second vertical semiconductor channel 35 is formed by a processing step.

[0221] See also Fig.32A and Fig.32B , a photoresist layer (not shown) may be applied over the topmost first level insulating layer 32 and may be photolithographically patterned to form an opening overlying the central region of the second vertical semiconductor channel 35. An anisotropic etching process may be performed to etch through the second vertical semiconductor channel 35 and physically expose the top surface of the first dielectric core 25. A dielectric material may be deposited and planarized to form a second dielectric core 27. The second dielectric core 27 may include undoped silicate glass, doped silicate glass, or organosilicate glass.

[0222] FIG. 32C to FIG. 32E Steps for forming an alternative configuration of the third exemplary structure are shown. In this alternative configuration, the first vertical semiconductor channel 33 and the second vertical semiconductor channel 35 include a polycrystalline semiconductor layer (eg, polysilicon) that is deposited in the line trench 149 and then etched back. FIG. 32C to FIG. 32E Follow the steps in FIG. 28C to FIG. 28E , Fig.29C and FIG. 30A to FIG. 30B Specifically, Fig.32C As shown, a thin film polysilicon second vertical semiconductor channel material layer 35L is deposited in the line cavity 149' in the first level line trench 149 and is optionally recessed. Fig.32D As shown, the horizontal portion of the second vertical semiconductor channel material layer 35L is removed by anisotropic etching to form the second vertical semiconductor channel 35 and expose the layer 33T at the bottom of the line cavity 149'. Fig.32E As shown, the second dielectric core 27 is then deposited over the second vertical semiconductor channel 35 in the line cavity 149' and recessed to be flush with the top of the second vertical semiconductor channel 35. If the second vertical semiconductor channel 35 is not recessed in the previous step, the second vertical semiconductor channel 35 can be recessed together with the second dielectric core 27. Regardless of whether the vertical semiconductor channels (33, 35) include single crystalline semiconductor material or polycrystalline semiconductor material, the subsequent process steps of the third embodiment are the same as the main configuration and alternative configurations of the third exemplary structure.

[0223] See also Fig.33A and Fig.33B , a photoresist layer (not shown) may be applied over the topmost first level insulating layer in the first level insulating layer 32 and may be photolithographically patterned to form a plurality of rows of openings arranged along the second horizontal direction hd2. Each row of openings in the photoresist layer may overlie a corresponding one of the first level line trenches 149. Each opening may extend laterally from one sidewall of the underlying first level line trench 149 to another sidewall of the underlying first level line trench 149. In one embodiment, the openings in the photoresist layer may include rectangular openings.

[0224] Anisotropic etching is performed to transfer the pattern in the photoresist layer through the structure filling the first level line grooves 149. A column cavity extending vertically through each layer in the first level alternating stack (32, 42) can be formed by the anisotropic etching process. The top surface of the single crystal doped semiconductor material layer 6 can be physically exposed at the bottom of each column cavity. Each group of material portions filling the first level line grooves 149 is divided into a plurality of discrete material portions, which are referred to herein as first level memory column structures 58.

[0225] Each first level memory pillar structure 58 includes a pair of first gate dielectrics 20, a pair of first vertical semiconductor channels 33, a first dielectric core 25, a pair of second gate dielectrics (52, 50), a pair of second vertical semiconductor channels 35 and a second dielectric core 27. Each component within the first level memory pillar structure 58 is as shown in Fig.32A or Fig.32E The photoresist layer may then be removed, for example by ashing.

[0226] Dielectric material such as undoped silicate glass, doped silicate glass or organosilicate glass can be deposited in the pillar cavities by a conformal deposition process or a self-planarization deposition process (such as spin coating). Excess portions of the dielectric material can be removed from the top surface of the topmost first-level insulating layer of the first-level insulating layer 32. Each remaining portion of the dielectric material that fills the corresponding rectangular pillar cavity constitutes a first-level dielectric pillar structure 22. A laterally alternating sequence of first-level memory pillar structures 58 and first-level dielectric pillar structures 22 is formed in each of the first-level line grooves 149.

[0227] Each first level memory pillar structure 58 includes components of a ferroelectric memory cell. A row of ferroelectric memory cells is formed within each first level line trench 149. The ferroelectric memory cells within each first level line trench 149 are arranged along the second horizontal direction hd2.

[0228] See also Fig.34A and Fig.34B , you can execute Fig.15A and Fig. 15B The processing steps are performed to form a first backside trench 79 extending through the first level alternating stack (32, 42).

[0229] See also Fig.35A and Fig.35B , you can execute Fig.16A and Fig. 16B The first back side recessed portion 43 is formed by the processing steps.

[0230] See also Fig.36A and Fig.36B , you can execute Fig.17A and Fig. 17B to form a first-level conductive layer 46 , a first backside trench filling structure 76 and a first contact-level dielectric layer 47 .

[0231] See also Fig.37A and Fig.37B , you can execute Fig.18A and Fig.18B The first contact via cavity 39 is formed by a step of forming a first contact through-hole cavity 39 through the first contact-level dielectric layer 47 over a corresponding one of the second vertical semiconductor channels 35. The top surface of the second vertical semiconductor channel 35 can be physically exposed at the bottom of each first contact through-hole cavity 39. In one embodiment, the first contact through-hole cavity 39 can be elongated along a horizontal direction such as the first horizontal direction hd1. In one embodiment, the first contact through-hole cavity 39 can be laterally offset along the second horizontal direction hd2 so that the lateral extent of the first contact through-hole cavity 39 between adjacent pairs of first backside trench filling structures 76 has no overlap within the lateral extent along the second horizontal direction hd2, or has a minimum overlap along the second horizontal direction hd2.

[0232] In one embodiment, each of the first contact via cavities 39 can be laterally offset from a geometric center of an underlying second vertical semiconductor channel in the second vertical semiconductor channel 35 along a first horizontal direction hd1. In one embodiment, a top surface of the second gate dielectric (52, 50) can be physically exposed at the bottom of each first contact via cavity 39. In one embodiment, a top surface of a topmost first insulating layer in the first level insulating layer 32 can be physically exposed at the bottom of the first contact via cavity 39. In general, the layout of the first contact via cavities 39 can be selected so that only one second vertical semiconductor channel 35 is physically exposed below each first contact via cavity 35, and sufficient lateral spacing is provided between adjacent pairs of first contact via cavities 39 to avoid electrical shorts between first contact via structures subsequently formed therein.

[0233] See also Fig.38A and Fig.28B , you can execute Fig.19A and Fig.19B The processing steps are to form a bit line level conductive material layer (38L, 138L), which may include a first contact via structure 38V filling the first contact via cavity 39 and a planar conductive material layer covering the first contact level dielectric layer 47. If the first vertical semiconductor channel and the second vertical semiconductor channel (33, 35) include single crystal semiconductor materials, the bit line level conductive material layer (38L, 138L) may include a polycrystalline epitaxial semiconductor layer 38L and a polycrystalline semiconductor layer 138L. Alternatively, if the first vertical semiconductor channel and the second vertical semiconductor channel (33, 35) include polycrystalline semiconductor materials, the bit line level conductive material layer includes a polycrystalline semiconductor layer.

[0234] See also Fig.39A and Fig.39B , you can execute Fig. 20A and Fig. 20B The processing steps are to pattern the bit line level conductive material layer (38L, 138L) into a plurality of discrete portions, wherein each discrete portion includes a bit line 38 and a first contact via structure 38V. Each bit line 38 is a conductive line structure that may include a plurality of single crystal grains 38A, which are epitaxially aligned with a corresponding one of the single crystal epitaxial semiconductor material portions of the underlying ferroelectric memory cell, and optionally include a polycrystalline line portion 38B, which includes a doped semiconductor material having a second conductivity type. Alternatively, each bit line 38 includes a polycrystalline semiconductor material, a metal or a metal alloy, a metal silicide and / or a conductive metal nitride.

[0235] Generally speaking, the ferromagnetic memory cell UC includes a vertical stack of a lower field effect transistor and an overlying field effect transistor. The lower field effect transistor and the overlying field effect transistor can be formed in each opening of at least one opening (i.e., the first-level discrete memory opening 49) passing through the vertical layer stack (32, 42). The lower field effect transistor includes one of a first field effect transistor (e.g., a selection gate transistor SG) and a second field effect transistor (e.g., a ferroelectric memory transistor FeFET), and the overlying field effect transistor includes the other of the first field effect transistor and the second field effect transistor. The second field effect transistor covers the first field effect transistor on or below.

[0236] The first field effect transistor includes a first vertical semiconductor channel 33, a first gate dielectric 20 contacting the sidewall of the first vertical semiconductor channel 33, and a portion of the first conductive layer 46 contacting the first gate dielectric 20. Each first vertical semiconductor channel 33 and each second vertical semiconductor channel 35 of each lower ferroelectric memory unit cell UC includes a corresponding single crystal epitaxial semiconductor material portion epitaxially aligned with the single crystal doped semiconductor material layer 6. A vertical stack of a first field effect transistor and a second field effect transistor is formed above the first active region, the first active region including the single crystal doped semiconductor material layer 6. A corresponding second active region can be formed on the top of the corresponding stack of the first vertical semiconductor channel 33 and the second vertical semiconductor channel 35. Each second active region includes a first contact via structure 38V electrically connected to a bit line 38.

[0237] A plurality of ferroelectric memory cells UC may be formed within a plurality of first-level discrete memory openings 49. Each of the first-level discrete memory openings 49 may have a closed horizontal cross-sectional shape and may extend continuously through each of the three insulating layers 32, the first conductive layer 46RL, and the second conductive layer 46WL. Each of the first gate dielectric 20 and the second gate dielectric (52, 50) is located inside the corresponding first-level discrete memory opening 49. Each of the first conductive layer 46RL and the second conductive layer 46WL surrounds the corresponding first vertical semiconductor channel 33 and the second vertical semiconductor channel 36.

[0238] The first active region (e.g., source line including the single crystal doped semiconductor material layer 6), the first conductive layer 46RL, the second conductive layer 46WL, and the second active region (e.g., drain region located in the via structure 38V and electrically connected to the bit line 38) are vertically spaced apart from each other by respective ones of the three insulating layers 32 that are vertically spaced apart from each other. In one embodiment, the outer sidewalls of the second gate dielectric (52, 50) are vertically coincident with the outer sidewalls of the first gate dielectric 20.

[0239] In one embodiment, the interface between first conductive layer 46RL and first gate dielectric 20 is vertically coincident with the interface between second conductive layer 46WL and second gate dielectric (52, 50). Each of insulating layers 32 has sidewalls that contact first gate dielectric 20 or second gate dielectric (52, 50) and are vertically coincident with the interface between first conductive layer 46RL and first gate dielectric 20. The process for forming the third exemplary structure may be completed at this stage.

[0240] Optionally, you can execute Fig.21A and Fig. 21B The processing steps are to form a second contact level dielectric layer 97 above and between the bit lines 38, such as Fig.40A and Fig.40B A second contact via cavity may be formed through the second contact level dielectric layer 97 so that the top surface of the underlying bit line 38 is physically exposed. A second contact via structure 88 may be formed in the second contact via cavity by deposition and planarization of at least one conductive material.

[0241] In one embodiment, the second contact via structure 88 may include a doped semiconductor material having a doping of the second conductivity type. The second contact via structure 88 may include an atomic concentration of 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 , but smaller and larger dopant concentrations may also be used. In one embodiment, the second contact via structures 88 may include a single crystalline doped semiconductor material within the underlying single crystalline grains of the underlying bit line 38. In this case, the second contact via structures 88 may be formed by a selective epitaxial process that grows a single crystalline semiconductor material portion from a physically exposed single crystalline surface of the bit line 38. In one embodiment, each second contact via structure 88 may have the same area overlap as the underlying first via structure in the first contact via structure 38V and / or may be located in the same area as the underlying first via structure in the first contact via structure 38V.

[0242] See also Fig.41A and Fig.41B , a second alternating stack of second-level insulating layers 82 and second-level sacrificial material layers 92 may be formed over the second contact-level dielectric layer 97. Second-level line trenches 199 may be formed through the second alternating stack (82, 92) such that the top surfaces of the two rows of second contact via structures 88 are physically exposed at the bottom of each second-level line trench 199. In one embodiment, each second-level line trench 199 may have an area that overlaps and / or has the same area as the underlying first-level line trench 149. The second-level line trenches 199 may have a corresponding uniform width throughout and extend laterally in a horizontal direction such as a second horizontal direction hd2.

[0243] See also Fig.42 , you can execute Fig.22A and Fig. 22B The processing steps to form the third gate dielectric (102, 100) each third gate dielectric (102, 100) may include a ferroelectric material layer 102 and an optional non-ferroelectric gate dielectric 100.

[0244] See also Fig.43A and Fig.43B , you can execute Fig.23 A and Fig.23B to form third vertical semiconductor channel material portions, which may be epitaxial semiconductor material portions including a plurality of single crystal grains grown from a corresponding one of the second contact via structures 88. These third vertical semiconductor channel material portions may be vertically recessed so that the top surface of the recessed portion of the third vertical semiconductor channel material portion is located at the level of the middle one of the second-level insulating layers 82.

[0245] A sacrificial spacer (not shown) may be formed on the sidewall of the upper region of the second level line trench by conformal deposition and anisotropic etching of a sacrificial spacer material. The sacrificial spacer material may include a silicon oxide material (such as borosilicate glass), a silicon germanium alloy, a carbon-based material (such as amorphous carbon), or a polymer material having a high etching rate. The central portion of the third vertical semiconductor channel material portion may be removed by an anisotropic etching process to physically expose the top surface of the second contact dielectric layer 97. The remaining portion of the third vertical semiconductor channel material portion constitutes a third vertical semiconductor channel 85.

[0246] A dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass may be deposited in the cavity formed by removing the central portion of the third vertical semiconductor channel material portion. The dielectric material may be vertically recessed to form a third dielectric core 77. A sacrificial spacer selective to the third dielectric core 77 and the third vertical semiconductor channel 85 may be removed.

[0247] See also Fig.44A and Fig.44B As shown, you can execute Fig.24 The processing steps of the fourth gate dielectric 70 and the fourth vertical semiconductor channel material portion are formed. The central portion of the fourth vertical semiconductor channel material portion can be removed and replaced with a dielectric material to form a fourth dielectric core 75.

[0248] A photoresist layer (not shown) may be applied over the topmost second level insulating layer 82 and may be photolithographically patterned to form a plurality of rows of openings arranged along the second horizontal direction hd2. Each row of openings in the photoresist layer may overlie a corresponding one of the second level line trenches 199. Each opening may extend laterally from one sidewall of the underlying second level line trench 199 to another sidewall of the underlying second level line trench 199. In one embodiment, the openings in the photoresist layer may include rectangular openings.

[0249] Anisotropic etching is performed to transfer the pattern in the photoresist layer through the structure filling the second-level line groove 199. A column cavity extending vertically through each layer in the second-level alternating stack (32, 42) can be formed by anisotropic etching process. The top surface of the second contact level dielectric layer 97 can be physically exposed at the bottom of each column cavity. Each group of material portions filling the second-level line groove 199 is divided into a plurality of discrete material portions, which are referred to as second-level memory column structures 108 in this article. Each second-level memory column structure 108 includes a pair of third gate dielectrics (102, 100), a pair of third vertical semiconductor channels 85, a third dielectric core 77, a pair of fourth gate dielectrics 70, a pair of fourth vertical semiconductor channels 83 and a fourth dielectric core 75. Each component within the second-level memory column structure 108 is a patterned remainder of a corresponding larger structure provided before forming the column cavity. The photoresist layer can then be removed, for example, by ashing.

[0250] Dielectric materials such as undoped silicate glass, doped silicate glass or organosilicate glass can be deposited in the column cavities by a conformal deposition process or a self-planarization deposition process (such as spin coating). Excess portions of the dielectric material can be removed from above the top surface of the topmost one of the second-level insulating layers 82. Each remaining portion of the dielectric material filling the corresponding column cavity constitutes a second-level dielectric column structure 72. A laterally alternating sequence of second-level memory column structures 108 and second-level dielectric column structures 72 is formed in each of the second-level line grooves 199.

[0251] Each second level memory pillar structure 108 includes components of a ferroelectric memory cell. A row of ferroelectric memory cells is formed within each second level line trench 199. The ferroelectric memory cells within each second level line trench 199 are arranged along a second horizontal direction hd2.

[0252] See also Fig.45A and Fig.45B , you can execute Fig.25 The processing steps are as follows to form a second backside trench, a second backside recess, a second level conductive layer 96 and a second backside trench filling structure 78.

[0253] See also Fig.46A and Fig.46B , you can execute Fig.26A and Fig.26BThe processing steps to form the source-line level conductive material layer 7. In one embodiment, the source-line level conductive material layer 7 can be formed by performing a selective epitaxial process of growing a single crystalline semiconductor material from the physically exposed surface of the fourth vertical semiconductor channel 83. The single crystalline semiconductor material portion can be grown from the physically exposed surface of the fourth vertical semiconductor channel 83. The single crystalline grains grown from different fourth vertical semiconductor channels 83 can contact each other and form a crystalline epitaxial semiconductor material layer including a plurality of single crystalline semiconductor material grains, which are epitaxially aligned with a corresponding one of the fourth vertical semiconductor channels 83 and contact each other at the grain boundaries GB located between the regions of the fourth vertical semiconductor channels 83. In one embodiment, the grain boundaries GB do not cover any of the fourth vertical semiconductor channels 83. The group of all the single crystalline grains (i.e., the single crystalline semiconductor material portion) constitutes a multi-grain epitaxial semiconductor layer 7A including a plurality of epitaxial semiconductor material grains, wherein each epitaxial semiconductor material grain is epitaxially aligned with the underlying fourth vertical semiconductor channel 83.

[0254] Optionally, the peripheral portion may be formed by a non-selective semiconductor deposition process to form a polycrystalline semiconductor layer 7B. The polycrystalline epitaxial semiconductor layer 7A and the optional polycrystalline semiconductor layer 7B may be planarized, for example, by chemical mechanical polishing, to provide a flat top surface. The polycrystalline epitaxial semiconductor layer 7A and the optional polycrystalline semiconductor layer 7B may be doped with a dopant of the second conductivity type by in-situ doping or by ion implantation. The polycrystalline epitaxial semiconductor layer 7A and the optional polycrystalline semiconductor layer 7B may include an atomic concentration of 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The second conductivity type dopant may be within a range of 100,000,000,000, but smaller and larger dopant concentrations may also be used. The combination of the polycrystalline epitaxial semiconductor layer 7A and the polycrystalline semiconductor layer 7B constitutes the source-line level conductive material layer 7. Alternatively, the source-line level conductive material layer 7 may include doped polycrystalline semiconductor material, metal or metal alloy, metal silicide and / or conductive metal nitride.

[0255] A third active region (including source-line level conductive material layer 7) may be formed on top of respective stacks of third and fourth vertical semiconductor channels 85 and 83. Each of the at least one ferroelectric memory unit cell (UC1, UC2) includes respective vertical stacks of ferroelectric memory unit cells.

[0256] See also Figures 1A to 1D as well as FIG. 9A to FIG. 46B, and according to various embodiments of the present disclosure, a memory device including at least one ferroelectric memory cell (UC, UC1, UC2) is provided. Each of the at least one ferroelectric memory cell is located above a substrate (such as a semiconductor substrate 8) and includes: a corresponding first field effect transistor (such as a first field effect transistor of a first-level ferroelectric memory cell UC1 or a fourth field effect transistor of a second-level ferroelectric memory cell UC2), the corresponding first field effect transistor including a first vertical semiconductor channel (33 or 83), a first gate dielectric (20 or 70) contacting a sidewall of the first vertical semiconductor channel (33 or 83), and a portion of a first conductive layer (46 or 96) contacting the first gate dielectric (20 or 70); and a corresponding second field effect transistor (such as a second field effect transistor of a first-level ferroelectric memory cell UC1 or a third field effect transistor of a second-level ferroelectric memory cell UC2), the corresponding second field effect transistor including a second vertical semiconductor channel (35 or 85), a ferroelectric material layer (52 or 102) and contacting the second vertical semiconductor channel. a second gate dielectric {(52, 50) or (102, 100)} that contacts the sidewalls of the semiconductor channel (35 or 85) and the top or bottom of the first vertical semiconductor channel (35 or 85), and a portion of the second conductive layer (46 or 96) that contacts the second gate dielectric {(52, 50) or (102, 100)}; a corresponding first active region (which may include a single-crystalline doped semiconductor material layer 6 or a combination of a first contact via structure 38V and a second contact via structure 88), the corresponding first active region connected to the bottom of the stack of the first vertical semiconductor channel (33 or 83) and the second vertical semiconductor channel (35 or 85); and a corresponding second active region (which may include a source-line level conductive material layer 7 or a combination of a first contact via structure 38V and a second contact via structure 88), the corresponding second active region connected to the top of the stack of the first vertical semiconductor channel (33 or 83) and the second vertical semiconductor channel (35 or 85);

[0257] In one embodiment, the first active region, the first conductive layer (46 or 96), the second conductive layer (46 or 96), and the second active region are vertically spaced apart from each other by three insulating layers (32 or 82) that are vertically spaced apart from each other.

[0258] In one embodiment, the outer sidewalls of the second gate dielectric {(52, 50) or (102, 100)} are vertically coincident with the outer sidewalls of the first gate dielectric (20 or 70). In one embodiment, the interface between the first conductive layer (46 or 96) and the first gate dielectric (20 or 70) is vertically coincident with the interface between the second conductive layer (46 or 96) and the second gate dielectric {(52, 50) or (102, 100)}; and each of the insulating layers (32 or 82) has a sidewall that contacts the first gate dielectric (20 or 70) or the second gate dielectric {(52, 50) or (102, 100)} and is vertically coincident with the interface between the first conductive layer (46 or 96) and the first gate dielectric (20 or 70).

[0259] In one embodiment, a memory device includes a memory opening (49 or 99) having a closed horizontal cross-sectional shape and extending continuously through each of three insulating layers (32 or 82), a first conductive layer (46 or 96) and a second conductive layer (46 or 96); each of a first gate dielectric (20 or 70) and a second gate dielectric {(52, 50) or (102, 100)} is located inside the memory opening (49 or 99); and each of the first conductive layer (46 or 96) and the second conductive layer (46 or 96) surrounds a corresponding first vertical semiconductor channel (33 or 83) and a second vertical semiconductor channel (35 or 85).

[0260] In one embodiment, a memory device includes a line groove (149 or 199) having a width along a first horizontal direction hd1 and extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, wherein each of three insulating layers (32 or 82), a first conductive layer (46 or 96) and a second conductive layer (46 or 96) is located on one side of the line groove (149 or 199); each of a first gate dielectric (20 or 70) and a second gate dielectric {(52, 50) or (102, 100)} is located inside the line groove (149 or 199) and extends laterally along the second horizontal direction hd2; and each of the first conductive layer (46 or 96) and the second conductive layer (46 or 96) extends laterally along the second horizontal direction hd2 and optionally has a uniform width along the first horizontal direction hd1.

[0261] In one embodiment, the first gate dielectric (20, 70) includes and / or consists essentially of a non-ferroelectric material. In one embodiment, the second gate dielectric {(52, 50) or (102, 100)} is vertically separated from the first gate dielectric (20 or 70) by a portion of the first vertical semiconductor channel (33 or 83) or by a portion of the second vertical semiconductor channel (35 or 85).

[0262] In one embodiment, each first active region includes a portion of a single crystal doped semiconductor material layer 6; each first vertical semiconductor channel 33 includes a first single crystal epitaxial semiconductor material epitaxially aligned with the single crystal doped semiconductor material layer 6; and each second vertical semiconductor channel 35 includes a second single crystal epitaxial semiconductor material epitaxially aligned with the corresponding first single crystal epitaxial semiconductor material.

[0263] In one embodiment, at least one ferroelectric memory cell (UC, UC1, UC2) includes a two-dimensional array of ferroelectric memory cells extending laterally along a first horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; each stack of a first vertical semiconductor channel 33 and a second vertical semiconductor channel 35 has a bottom end contacting a single crystal doped semiconductor material layer 6; the memory device includes a plurality of second active regions, the plurality of second active regions including conductive wires (such as corresponding bit lines 38) extending laterally along the first horizontal direction hd1; each conductive wire contacts the top of the stack of the first vertical semiconductor channel 33 and the second vertical semiconductor channel 35; and the conductive wires are laterally spaced apart along the second horizontal direction hd2.

[0264] In one embodiment, the at least one ferroelectric memory cell includes at least one vertical stack of a first-level ferroelectric memory cell UC1 and a second-level ferroelectric memory cell UC2; the second-level ferroelectric memory cell UC2 covers the first-level ferroelectric memory cell UC1 and has an area overlapping with the first-level ferroelectric memory cell UC1 in a plan view along the vertical direction; the second field effect transistor of the first-level ferroelectric memory cell UC1 covers the first field effect transistor of the first-level ferroelectric memory cell UC1; and the second field effect transistor of the second-level ferroelectric memory cell UC2 (such as a third field effect transistor including a third gate dielectric (102, 100)) covers the first field effect transistor of the second-level ferroelectric memory cell UC2 (such as a fourth field effect transistor including a fourth gate dielectric 70).

[0265] In one embodiment, each vertical stack of the first-level ferroelectric memory cell UC1 and the second-level ferroelectric memory cell UC2 includes a lower ferroelectric memory cell (which is one of the first-level ferroelectric memory cell UC1 and the second-level ferroelectric memory cell UC2) and an overlying ferroelectric memory cell (which is the other of the first-level ferroelectric memory cell UC1 and the second-level ferroelectric memory cell UC2), and the overlying ferroelectric memory cell is farther from the substrate (such as the semiconductor substrate 8) than the lower ferroelectric memory cell; and the second active region of the lower ferroelectric memory cell and the first active region of the overlying ferroelectric memory cell include a common structure, which includes a conductive wire structure (such as a bit line 38) extending laterally along a first horizontal direction hd1 between the lower ferroelectric memory cell and the overlying ferroelectric memory cell.

[0266] In one embodiment, the first active region of the lower ferroelectric memory cell includes a single crystal doped semiconductor material layer 6, which has a lateral extent along a second horizontal direction hd2 that is larger than the width of a conductive line structure (such as a bit line 38) along the second horizontal direction hd2, and the second horizontal direction hd2 is perpendicular to the first horizontal direction hd1; and the second active region of the overlying ferroelectric memory cell includes a conductive material layer (such as a source-line level conductive material layer 7), which has a lateral extent along the second horizontal direction hd2 that is larger than the width of the conductive line structure along the second horizontal direction hd2.

[0267] In one embodiment, each first vertical semiconductor channel (33 or 83) and each second vertical semiconductor channel (35 or 85) of each lower ferroelectric memory cell includes a corresponding single crystal epitaxial semiconductor material portion epitaxially aligned with the single crystal doped semiconductor material layer 6; and the conductor structure includes a plurality of single crystal grains, which are epitaxially aligned with a corresponding one of the single crystal epitaxial semiconductor material portions of the lower ferroelectric memory cell.

[0268] Various embodiments of the present disclosure may provide at least one ferroelectric memory cell, which may be a two-dimensional array of ferroelectric memory cells or a three-dimensional array of ferroelectric memory cells. Each first field effect transistor is used as an access transistor, which selects or deselects a ferroelectric memory cell including a corresponding first field effect transistor. The ferroelectric memory layer (52 or 102) of the second field effect transistor is used as a memory element for storing information. The ferroelectric memory layer (52 or 102) may be used as a single-bit memory element for storing 0 or 1, or may be used as a multi-level memory element configured to store a data bit selected from at least three possible data values.

[0269] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A memory device, the memory device comprising a row of ferroelectric memory cells on a semiconductor substrate and a dielectric isolation structure embedded in the semiconductor substrate, wherein each ferroelectric memory cell in the row of ferroelectric memory cells comprises: a corresponding first field effect transistor including a first semiconductor channel extending between a first active region and a second active region located in the semiconductor substrate, a first gate dielectric disposed at a peripheral region of a portion of a linear trench extending downward from a top surface of the semiconductor substrate and located between the first active region and the second active region, and a first gate electrode located above the first gate dielectric, wherein the first semiconductor channel is overlaid below a horizontal portion of the first gate dielectric; and a corresponding second field effect transistor, the corresponding second field effect transistor comprising a second semiconductor channel extending between the second active region and the third active region, a second gate dielectric comprising a ferroelectric material layer overlying the second semiconductor channel, and a second gate electrode overlying the second gate dielectric, wherein: The dielectric isolation structures extend laterally along a first horizontal direction and are laterally spaced apart along a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; The linear trench extends horizontally along the second horizontal direction and extends vertically from a horizontal plane including a top surface of the semiconductor substrate into each of the dielectric isolation structures and into each portion of the semiconductor substrate located between adjacent pairs of the dielectric isolation structures; and The first gate electrode line of each of the first gate electrodes contained in the row of ferroelectric memory cells is located in the line groove and covers each of the first semiconductor channels in the row of ferroelectric memory cells and covers each recessed surface of the dielectric isolation structure that forms a portion of the bottom surface of the line groove. 2 . The memory device of claim 1 , wherein a top surface of the first gate electrode is located in the same horizontal plane as a top surface of the semiconductor substrate. 3 . The memory device of claim 1 , wherein the first gate dielectric has a U-shaped vertical cross-sectional profile and includes a pair of vertical portions and a horizontal portion adjacent to a bottom end of each of the pair of vertical portions. 4 . The memory device of claim 3 , wherein each of the pair of vertical portions of the first gate dielectric and the horizontal portion of the first gate dielectric have a same material composition and a same thickness throughout. 5 . The memory device of claim 1 , wherein each of the first active region, the second active region, and the third active region has a top surface within a horizontal plane, the horizontal plane including a top surface of the semiconductor substrate.

6. The memory device according to claim 5, wherein: a bottom surface of the second gate dielectric located within the horizontal plane including the top surface of the semiconductor substrate; and A top surface of the first gate dielectric is located within the horizontal plane including the top surface of the semiconductor substrate.

7. The memory device according to claim 1, wherein: The first active region, the second active region and the third active region within each ferroelectric memory unit cell are laterally spaced apart along a first horizontal direction; as well as The ferroelectric memory cells within the row of ferroelectric memory cells are laterally spaced apart along the second horizontal direction by the dielectric isolation structure.

8. The memory device according to claim 7, wherein: The first semiconductor channel and the second semiconductor channel have respective dopings of a first conductivity type; and The first active region, the second active region, and the third active region have uniform widths along the second horizontal direction and have doping of a second conductivity type opposite to the first conductivity type.

9. The memory device according to claim 7, wherein: each of the first active regions within the row of ferroelectric memory cells is connected to a respective first element selected from a respective one of a source line and a bit line; each of the third active regions within the row of ferroelectric memory cells is connected to a respective second element selected from the respective one of the bit line and the source line, the respective second element being different from the respective first element; The source line covers the semiconductor substrate and extends laterally along the second horizontal direction; as well as The bit line covers the semiconductor substrate and extends laterally along the first horizontal direction.

10. The memory device of claim 9, wherein: The memory device includes a plurality of rows of ferroelectric memory cells arranged along the first horizontal direction; The plurality of rows of ferroelectric memory cells form a two-dimensional array of ferroelectric memory cells; as well as A subset of the first active regions of the two-dimensional array of ferroelectric memory cells is shared by corresponding adjacent pairs of ferroelectric memory cells arranged along the first horizontal direction.

11. The memory device of claim 1 , wherein: the second gate dielectric and the second gate electrode having vertically coincident sidewalls overlying the top surface of the semiconductor substrate; and The first gate dielectric has a lateral extent greater than the first gate electrode by twice the thickness of a vertical portion of the first gate dielectric.

12. The memory device of claim 1 , wherein the first gate dielectric strip of each of the first gate dielectrics within the row of ferroelectric memory cells is located in the line groove and contacts a pair of side walls of a first gate electrode strip and a bottom surface of the first gate electrode strip, the pair of side walls of the first gate electrode strip extending laterally along the second horizontal direction, and the bottom surface of the first gate electrode strip extending along the second horizontal direction. 13 . The memory device of claim 12 , wherein the first gate dielectric strip has a U-shaped vertical cross-sectional profile and includes a horizontal extending portion contacting a pair of vertical extending portions. 14 . The memory device of claim 13 , wherein the pair of vertically extending portions of the first gate dielectric strips contact a recessed surface and a pair of sidewalls of each of the dielectric isolation structures. 15 . The memory device of claim 14 , wherein the pair of vertically extending portions of the first gate dielectric strip contact a pair of sidewalls of the semiconductor substrate between each pair of laterally adjacent dielectric isolation structures.

16. The memory device of claim 13, wherein the horizontally extending portion of the first gate dielectric strip contacts a top surface of each first semiconductor channel within the row of ferroelectric memory cells. 17 . The memory device of claim 16 , wherein the horizontally extending portion of the first gate dielectric strip contacts a recessed surface of each of the dielectric isolation structures.

18. The memory device of claim 12, wherein the first gate dielectric strip has a top surface within the horizontal plane including a top surface of the semiconductor substrate.

19. The memory device of claim 1, wherein a bottom surface of the dielectric isolation structure is located below a horizontal plane including a bottom surface of the line trench.

20. The memory device of claim 1, wherein a first gate electrode strip has a top surface within the horizontal plane including a top surface of the semiconductor substrate.

21. A memory device comprising at least one ferroelectric memory unit cell, wherein each of the at least one ferroelectric memory unit cell is located above a substrate and comprises: a respective first field effect transistor including a first vertical semiconductor channel, a first gate dielectric contacting a sidewall of the first vertical semiconductor channel, and a portion of a first conductive layer contacting the first gate dielectric; a corresponding second field effect transistor, the corresponding second field effect transistor comprising a second vertical semiconductor channel, a second gate dielectric comprising a ferroelectric material layer and contacting a sidewall of the second vertical semiconductor channel and contacting a top end or a bottom end of the first vertical semiconductor channel, and a portion of a second conductive layer contacting the second gate dielectric; a first active region connected to a bottom end of the stack of the first vertical semiconductor channel and the second vertical semiconductor channel; as well as A second active region is connected to a top end of the stack of the first vertical semiconductor channel and the second vertical semiconductor channel. 22 . The memory device of claim 21 , wherein the first active region, the first conductive layer, the second conductive layer, and the second active region are vertically spaced apart from each other by three insulating layers vertically spaced apart from each other.

23. The memory device of claim 22, wherein an outer sidewall of the second gate dielectric vertically coincides with an outer sidewall of the first gate dielectric.

24. The memory device of claim 23, wherein: an interface between the first conductive layer and the first gate dielectric vertically coincides with an interface between the second conductive layer and the second gate dielectric; as well as Each of the insulating layers has a sidewall that contacts the first gate dielectric or the second gate dielectric and vertically coincides with an interface between the first conductive layer and the first gate dielectric.

25. The memory device of claim 22, wherein: The memory device includes a memory opening having a closed horizontal cross-sectional shape and continuously extending through each of the three insulating layers, the first conductive layer, and the second conductive layer; each of the first gate dielectric and the second gate dielectric being located within the memory opening; as well as Each of the first conductive layer and the second conductive layer surrounds the first vertical semiconductor channel and the second vertical semiconductor channel.

26. The memory device of claim 22, wherein: The memory device includes a line trench having a width along a first horizontal direction and extending laterally along a second horizontal direction perpendicular to the first horizontal direction, wherein each of the three insulating layers, the first conductive layer, and the second conductive layer is located on one side of the line trench; Each of the first gate dielectric and the second gate dielectric is located inside the line trench and extends laterally along the second horizontal direction; as well as Each of the first conductive layer and the second conductive layer extends laterally along the second horizontal direction.

27. The memory device of claim 21, wherein the first gate dielectric comprises a non-ferroelectric material.

28. The memory device of claim 21, wherein the second gate dielectric is vertically spaced apart from the first gate dielectric by a portion of the first vertical semiconductor channel or by a portion of the second vertical semiconductor channel.

29. The memory device of claim 21, wherein: Each first active region includes a portion of a layer of single crystalline doped semiconductor material; Each first vertical semiconductor channel comprises a first single crystalline epitaxial semiconductor material epitaxially aligned with the single crystalline doped semiconductor material layer; as well as Each second vertical semiconductor channel includes a second single crystalline epitaxial semiconductor material in epitaxial alignment with a corresponding first single crystalline epitaxial semiconductor material.

30. The memory device of claim 29, wherein: at least one ferroelectric memory unit cell comprises a two-dimensional array of ferroelectric memory unit cells extending laterally along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction; Each stack of the first vertical semiconductor channel and the second vertical semiconductor channel has a bottom end contacting the single crystalline doped semiconductor material layer; The memory device includes a plurality of second active regions, the plurality of second active regions including corresponding conductive lines extending laterally along the first horizontal direction; Each conductive line contacts a top end of the stack of the first vertical semiconductor channel and the second vertical semiconductor channel; and The conductive lines are laterally spaced apart along the second horizontal direction.

31. The memory device of claim 21, wherein: The at least one ferroelectric memory unit cell comprises at least one vertical stack of a first level ferroelectric memory unit cell and a second level ferroelectric memory unit cell; The second-level ferroelectric memory unit cell covers the first-level ferroelectric memory unit cell and has an area overlapping with the first-level ferroelectric memory unit cell in a plan view along the vertical direction; The second field effect transistor of the first level ferroelectric memory unit cell covers the first field effect transistor of the first level ferroelectric memory unit cell; and The second field effect transistor of the second-level ferroelectric memory unit cell covers the first field effect transistor of the second-level ferroelectric memory unit cell.

32. The memory device of claim 31 , wherein: Each vertical stack of the first level ferroelectric memory unit cells and the second level ferroelectric memory unit cells includes a lower ferroelectric memory unit cell and an overlying ferroelectric memory unit cell, the overlying ferroelectric memory unit cell being farther from the substrate than the lower ferroelectric memory unit cell; and The second active region of the lower ferroelectric memory unit cell and the first active region of the overlying ferroelectric memory unit cell include a common structure, and the common structure includes a conductive line structure extending laterally along a first horizontal direction between the lower ferroelectric memory unit cell and the overlying ferroelectric memory unit cell.

33. The memory device of claim 32, wherein: The first active region of the lower ferroelectric memory cell comprises a layer of single-crystal doped semiconductor material, the layer of single-crystal doped semiconductor material having a lateral extent along a second horizontal direction greater than a width of the conductive line structure along the second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; as well as The second active region of the overlying ferroelectric memory cell includes a layer of conductive material having a lateral extent along the second horizontal direction that is greater than the width of the conductive line structure along the second horizontal direction.

34. The memory device of claim 33, wherein: Each first vertical semiconductor channel and each second vertical semiconductor channel of each underlying ferroelectric memory unit cell comprises a corresponding single crystalline epitaxial semiconductor material portion epitaxially aligned with the single crystalline doped semiconductor material layer; and The conductive line structure includes a plurality of single crystalline grains epitaxially aligned with a corresponding one of the single crystalline epitaxial semiconductor material portions of the underlying ferroelectric memory cell.

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