Semiconductor components

Abstract

The present invention discloses a semiconductor component, comprising a first routing line, a second routing line and a third routing line. The first routing line, the second routing line and the third routing line are each continuous and equipotential routing lines. The first routing line, the second routing line and the third routing line only use two conductor layers of a semiconductor structure. In a crossing interval of the first routing line, the second routing line and the third routing line, the first routing line crosses the second routing line once, the first routing line crosses the third routing line once, and the second routing line crosses the third routing line once.

Description

Technical Field

[0001] The present invention relates to a semiconductor component, and in particular to a winding structure of a semiconductor component. Background Art

[0002] Figure 1 The semiconductor structure includes a substrate 110, an oxide layer 120, a metal layer 130, an oxide layer 135, and a metal layer 140 from bottom to top in the vertical direction (z direction). The metal layer 130 may be an ultra-thick metal (UTM) layer, and the metal layer 140 may be a re-distribution layer (RDL). The oxide layer 120 may include other metal layers (not shown). Generally speaking, the resistance of the ultra-thick metal layer is smaller than that of the re-distribution layer, and the resistance of the metal layer in the oxide layer 120 is about several dozen times that of the ultra-thick metal layer.

[0003] Semiconductor devices often include intersecting traces, and the intersecting traces must be fabricated on a plurality of metal layers. Figure 2 The local wiring of a conventional semiconductor device is shown. The wiring 210, the wiring 220 and the wiring 230 intersect each other. The wiring 210 is located on the upper metal layer (e.g. Figure 1 The metal layer 140 of FIG. 1 is provided, and the trace 220 is located in the middle metal layer (eg Figure 1 The metal layer 130 of FIG. 1 is located on the bottom metal layer (eg Figure 1 Since the metal layer in the oxide layer 120 has a high resistance, the trace 230 must be made wider to withstand high current. However, a wider trace will increase parasitic capacitance, causing the characteristics of the semiconductor device to deteriorate. Summary of the invention

[0004] In view of the shortcomings of the prior art, one object of the present invention is to provide a semiconductor component to reduce the use of conductor layers.

[0005] The present invention discloses a semiconductor component, comprising a first routing line, a second routing line and a third routing line. The first routing line comprises a first line segment, a second line segment and a third line segment connected in sequence. The second routing line comprises a fourth line segment, a fifth line segment, a sixth line segment, a seventh line segment and an eighth line segment connected in sequence. The third routing line comprises a ninth line segment, a tenth line segment and an eleventh line segment connected in sequence. The first line segment, the fourth line segment and the ninth line segment are substantially parallel, and the third line segment, the eighth line segment and the eleventh line segment are substantially parallel. The second line segment intersects with the tenth line segment and the seventh line segment, and the fifth line segment intersects with the tenth line segment. The first routing line, the second routing line and the third routing line are each continuous and equipotential routing lines.

[0006] The present invention further discloses a semiconductor component, comprising a first routing line, a second routing line and a third routing line. The first routing line, the second routing line and the third routing line are each continuous and equipotential routing lines. The first routing line, the second routing line and the third routing line only use two conductor layers of a semiconductor structure. In a crossing interval of the first routing line, the second routing line and the third routing line, the first routing line crosses the second routing line once, the first routing line crosses the third routing line once, and the second routing line crosses the third routing line once.

[0007] The present invention further discloses a semiconductor component, which has a layered structure including a first layer, a second layer and a third layer. The semiconductor component includes a first routing line, a second routing line and a third routing line. The first routing line extends from the first layer to the third layer, and includes a first continuous line segment located between the first layer and the third layer but not belonging to the first layer and the third layer. The second routing line extends from the second layer to the second layer through the third layer, and includes a second continuous line segment that does not belong to the first layer and the second layer. The third routing line extends from the third layer to the first layer, and includes a third continuous line segment located between the first layer and the third layer but not belonging to the first layer and the third layer. The first routing line, the second routing line and the third routing line are each continuous and equipotential routing lines. The first routing line, the second routing line and the third routing line use only two conductor layers of a semiconductor structure. The first continuous line segment intersects with the second continuous line segment and the third continuous line segment, and the second continuous line segment intersects with the third continuous line segment.

[0008] The present invention further discloses a semiconductor component, comprising a first routing line, a second routing line, a third routing line and a fourth routing line. The first routing line, the second routing line, the third routing line and the fourth routing line are each continuous and equipotential routing lines. The first routing line, the second routing line, the third routing line and the fourth routing line only use two conductor layers of a semiconductor structure. In a crossing interval of the first routing line, the second routing line, the third routing line and the fourth routing line, the first routing line crosses the second routing line once, the first routing line crosses the third routing line once, the first routing line crosses the fourth routing line once, the second routing line crosses the fourth routing line once, and the third routing line crosses the fourth routing line once.

[0009] The semiconductor component of the present invention can use a small amount of conductor layers to complete the winding. Compared with the conventional technology, the semiconductor component of the present invention can avoid using conductor layers with higher resistance values ​​to improve the characteristics of the semiconductor component.

[0010] The features, implementation and effects of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a semiconductor structure;

[0012] Figure 2 Local winding of a conventional semiconductor device;

[0013] Figure 3 A local winding of a semiconductor component according to an embodiment of the present invention;

[0014] Figure 4 A structural diagram of a semiconductor device according to an embodiment of the present invention;

[0015] Figure 5 is a structural diagram of a semiconductor component according to another embodiment of the present invention;

[0016] Figure 6 A local winding of a semiconductor component according to another embodiment of the present invention;

[0017] Figure 7 A structural diagram of a semiconductor device according to another embodiment of the present invention; and

[0018] Figure 8 for Figure 3 The equivalent structure of the local winding of a semiconductor component. DETAILED DESCRIPTION

[0019] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.

[0020] The disclosure of the present invention includes a semiconductor device. Since some components included in the semiconductor device of the present invention may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention.

[0021] Figure 3 The figure shows a local wiring of a semiconductor device according to an embodiment of the present invention. Figure 3It is a top view of a semiconductor component. The local wiring of the semiconductor component includes a routing 310 (including a line segment 310-a, a line segment 310-b and a line segment 310-c connected in sequence), a routing 320 (including a line segment 320-a, a line segment 320-b, a line segment 320-c, a line segment 320-d and a line segment 320-e connected in sequence), and a routing 330 (including a line segment 330-a, a line segment 330-b and a line segment 330-c connected in sequence). In the figure, the black line segments are made in the first conductor layer of the semiconductor structure, and the gray line segments are made in the second conductor layer of the semiconductor structure. The first conductor layer can be one of an ultra-thick metal layer and a redistribution layer, and the second conductor layer is the other. The line segments of different conductor layers are connected by penetrating structures (such as vias or via arrays) at penetration positions 340-a, 340-b, 340-c and 340-d. Therefore, although each trace (trace 310 , 320 or 330 ) may include line segments located in different conductor layers, each trace is a continuous trace with equal potential.

[0022] The semiconductor device of the present invention is Figure 1 The xy plane shown is a layered structure, including Figure 3 The LA layer, LB layer and LC layer are shown. Line segment 310-a and line segment 330-c are located in the LA layer, and line segment 310-a extends through line segment 330-c, and vice versa; line segment 320-a and line segment 320-e are located in the LB layer, and line segment 320-a extends through line segment 320-e, and vice versa; line segment 330-a and line segment 310-c are located in the LC layer, and line segment 330-a extends through line segment 310-c, and vice versa.

[0023] Line segment 310-b is a continuous line segment connecting line segment 310-a and line segment 310-c. Line segment 310-b is located between the LA layer and the LC layer, but does not belong to the LA layer and the LC layer. Line segment 320-b, line segment 320-c and line segment 320-d together constitute a continuous line segment connecting line segment 320-a and line segment 320-e. The continuous line segments (i.e., line segment 320-b, line segment 320-c and line segment 320-d) do not belong to the LA layer and the LB layer. Line segment 330-b is a continuous line segment connecting line segment 330-a and line segment 330-c. Line segment 330-b is located between the LA layer and the LC layer, but does not belong to the LA layer and the LC layer.

[0024] Figure 3Three intervals are marked, namely, interval I1, interval I2 and interval I3 (the three together constitute the intersection interval), and the routing 310, routing 320 and routing 330 are substantially parallel to each other in the portion outside the intersection interval. More specifically, line segment 310-a, line segment 320-a and line segment 330-a are substantially parallel to each other, and line segment 330-c, line segment 320-e and line segment 310-c are substantially parallel to each other. In the intersection interval, routing 310 crosses routing 320 once, routing 310 crosses routing 330 once, and routing 320 crosses routing 330 once. More specifically, after routing 320 enters the intersection interval, it first traces through line segment 320-b in interval I1 to line segment 320-c located in interval I2 and belonging to the LB layer, and then traces through line segment 320-d in interval I3 to line segment 320-e belonging to the LB layer. After entering the intersection section, line 330 passes through line segment 330-b to line segment 330-c. In section I1, line segment 320-b intersects line segment 330-b (i.e., line 320 intersects line 330). After entering the intersection section, line 310 first extends a distance (i.e., the length of section I1), and then passes through line segment 310-b to line segment 310-c. In section I2, line segment 310-b intersects line segment 330-b (i.e., line 310 intersects line 330), and in section I3, line segment 310-b intersects line segment 320-d (i.e., line 310 intersects line 320).

[0025] like Figure 3 As shown, the semiconductor component of the present invention uses only two conductor layers in the semiconductor structure to achieve the mutual crossing of three traces. Such a structure can avoid the semiconductor component being made in a conductor layer with a higher resistance, thereby improving the characteristics of the semiconductor component.

[0026] Figure 4 4 is a structural diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 400 is a three-turn inductor (i.e., the semiconductor device 400 is a layered structure), including an end point 401 and an end point 402. The line segment between the framed range 410 and the framed range 420 belongs to the first turn of the inductor, the line segment between the framed range 420 and the framed range 430 belongs to the second turn of the inductor, and the line segment within the framed range 430 belongs to the third turn of the inductor. The second turn is located between the first turn and the third turn. See also Figure 3 and Figure 4 ,when Figure 3When the structure is applied to the semiconductor device 400, the trace 310 connects the first circle and the third circle of the semiconductor device 400, the trace 330 connects the third circle and the first circle of the semiconductor device 400, and the trace 320 connects the second circle of the semiconductor device 400. In other words, the LA layer corresponds to the first circle of the semiconductor device 400, the LB layer corresponds to the second circle of the semiconductor device 400, and the LC layer corresponds to the third circle of the semiconductor device 400.

[0027] Figure 5 This is a structural diagram of a semiconductor component of another embodiment of the present invention. Semiconductor component 500 is a transformer, including a first inductor and a second inductor. The first inductor has terminals 501 and 502 as endpoints, and the second inductor has terminals 503 and 504 as endpoints. Semiconductor component 500 includes a first circle, a second circle, a third circle, and a fourth circle arranged in sequence from the outside to the inside. In other words, semiconductor component 500 is a layered structure. The first circle and the third circle belong to the first inductor, and the second circle and the fourth circle belong to the second inductor. In the figure, the black line segment is made in the first conductor layer of the semiconductor structure, the dark gray line segment is made in the second conductor layer of the semiconductor structure, and the light gray line segment directly connected to the terminal 504 is made in the third conductor layer of the semiconductor structure, and the third conductor layer is different from the first conductor layer and the second conductor layer.

[0028] See also Figure 3 and Figure 5 ,when Figure 3 When the structure is applied to the semiconductor component 500, the trace 310 connects the first and third turns of the semiconductor component 500 (that is, the outer and inner turns of the first inductor are connected), the trace 320 connects the second turn of the semiconductor component 500 (that is, the outer turn of the second inductor is connected); the trace 330 connects the first and third turns of the semiconductor component 500 (that is, the outer and inner turns of the first inductor are connected). In other words, the LA layer corresponds to the first turn of the semiconductor component 500, the LB layer corresponds to the second turn of the semiconductor component 500, and the LC layer corresponds to the third turn of the semiconductor component 500.

[0029] Figure 6 A local wiring diagram of a semiconductor device according to another embodiment of the present invention is shown. Figure 66 is a top view of a semiconductor device. The local wiring of the semiconductor device includes a trace 610 (including a line segment 610-a, a line segment 610-b, and a line segment 610-c connected in sequence), a trace 620 (including a line segment 620-a, a line segment 620-b, a line segment 620-c, a line segment 620-d, and a line segment 620-e connected in sequence), a trace 630 (including a line segment 630-a, a line segment 630-b, a line segment 630-c, a line segment 630-d, and a line segment 630-e connected in sequence), and a trace 640 (including a line segment 640-a, a line segment 640-b, and a line segment 640-c connected in sequence). Although each trace (trace 610, 620, 630, or 640) may include segments located in different conductor layers, each trace is a continuous trace with equal potential.

[0030] The semiconductor device of the present invention is Figure 1 The xy plane shown is a layered structure, including the LA layer, LB layer, LC layer and LD layer shown in the figure. Line segment 610-a and line segment 640-c are located in the LA layer, and the extension of line segment 610-a passes through line segment 640-c, and vice versa; line segment 620-a and line segment 620-e are located in the LB layer, and the extension of line segment 620-a passes through line segment 620-e, and vice versa; line segment 630-a and line segment 630-e are located in the LC layer, and the extension of line segment 630-a passes through line segment 630-e, and vice versa; line segment 640-a and line segment 610-c are located in the LD layer, and the extension of line segment 640-a passes through line segment 610-c, and vice versa.

[0031] Line segment 610-b is a continuous line segment connecting line segment 610-a and line segment 610-c. Line segment 610-b is located between the LA layer and the LD layer, but does not belong to the LA layer and the LD layer. Line segment 620-b, line segment 620-c and line segment 620-d together constitute a continuous line segment connecting line segment 620-a and line segment 620-e. The continuous line segments (i.e., line segment 620-b, line segment 620-c and line segment 620-d) do not belong to the LB layer, the LC layer and the LD layer. Line segment 630-b, line segment 630-c and line segment 630-d together constitute a continuous line segment connecting line segment 630-a and line segment 630-e. The continuous line segments (i.e., line segment 630-b, line segment 630-c and line segment 630-d) do not belong to the LA layer, the LB layer and the LC layer. Line segment 640 - b is a continuous line segment connecting line segment 640 - a and line segment 640 - c . Line segment 640 - b is located between the LA layer and the LD layer, but does not belong to the LA layer and the LD layer.

[0032] Figure 6Three intervals are marked, namely, interval I1, interval I2 and interval I3 (the three together constitute the intersection interval), and the lines 610, 620, 630 and 640 are substantially parallel to each other in the portion outside the intersection interval. More specifically, line segments 610-a, 620-a, 630-a and 640-a are substantially parallel to each other, and line segments 640-c, 620-e, 630-e and 610-c are substantially parallel to each other. In the intersection interval, line 610 crosses line 620, line 630 and line 640 once respectively, and line 640 crosses line 620 and line 630 once respectively. More specifically, after entering the intersection interval, line 610 passes through line segment 610-b to line segment 610-c. After entering the crossover section, the line 620 first passes through the line segment 620-b in the section I1 to the line segment 620-c located in the section I2 and belonging to the LA layer, and then passes through the line segment 620-d in the section I3 to the line segment 620-e belonging to the LB layer. After entering the crossover section, the line 630 first passes through the line segment 630-b in the section I1 to the line segment 630-c located in the section I2 and belonging to the LD layer, and then passes through the line segment 630-d in the section I3 to the line segment 630-e belonging to the LC layer. After entering the crossover section, the line 640 passes through the line segment 640-b to the line segment 640-c. In the section I1, the line segment 610-b crosses the line segment 620-b (i.e., the line 610 crosses the line segment 620) and the line segment 630-b crosses the line segment 640-b (i.e., the line 630 crosses the line segment 640). In interval I2, line segment 610-b intersects line segment 640-b (i.e., line 610 intersects line 640). In interval I3, line segment 620-d intersects line segment 640-b (i.e., line 620 intersects line 640) and line segment 630-d intersects line segment 610-b (i.e., line 630 intersects line 610).

[0033] Figure 6 The winding only uses two conductor layers in the semiconductor structure. Such a structure can avoid semiconductor components being made in conductor layers with higher resistance, thereby improving the characteristics of semiconductor components.

[0034] Figure 7 FIG. 7 is a structural diagram of a semiconductor component of another embodiment of the present invention. The semiconductor component 700 is a transformer, including a first inductor and a second inductor. The first inductor has terminals 701 and 702 as end points, and the second inductor has terminals 703 and 704 as end points. The semiconductor component 700 includes a first circle, a second circle, a third circle, and a fourth circle arranged in sequence from the outside to the inside. In other words, the semiconductor component 700 is a layered structure. The first circle and the fourth circle belong to the first inductor, and the second circle and the third circle belong to the second inductor.

[0035] See also Figure 6 and Figure 7 ,when Figure 6 When the structure is applied to the semiconductor component 700, the trace 610 connects the first and fourth turns of the semiconductor component 700 (that is, the outer turn and the inner turn of the first inductor are connected), the trace 620 connects the second turn of the semiconductor component 700 (that is, the outer turn of the second inductor is connected), the trace 630 connects the third turn of the semiconductor component 700 (that is, the inner turn of the second inductor is connected), and the trace 640 connects the first and fourth turns of the semiconductor component 700 (that is, the outer turn and the inner turn of the first inductor are connected). In other words, the LA layer corresponds to the first turn of the semiconductor component 700, the LB layer corresponds to the second turn of the semiconductor component 700, the LC layer corresponds to the third turn of the semiconductor component 700, and the LD layer corresponds to the fourth turn of the semiconductor component 700.

[0036] Figure 8 for Figure 3 In this embodiment, line segment 320-f (black line segment in the upper layer) corresponds to a continuous line segment composed of line segment 320-b and line segment 320-c, and line segment 320-g (gray line segment in the lower layer) corresponds to a continuous line segment composed of line segment 320-d and line segment 320-e.

[0037] Since those with ordinary knowledge in the art can understand the implementation details and variations of the method invention of this case through the disclosure of the device invention of this case, in order to avoid redundancy, repeated descriptions are omitted here without affecting the disclosure requirements and feasibility of the method invention. Please note that the shapes, sizes, proportions, layers, and circles of the components in the above-mentioned figures are only for illustration and are for those with ordinary knowledge in the art to understand the present invention, and are not used to limit the present invention.

[0038] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person having ordinary knowledge in the technical field may make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application defined in this specification.

[0039]

Explanation of symbols

[0040] 110 substrate

[0041] 120, 135 oxide layer

[0042] 130, 140 Metal layer

[0043] 210, 220, 230, 310, 320, 330, 610, 620, 630, 640 routing

[0044] 310-a, 310-b, 310-c, 320-a, 320-b, 320-c, 320-d, 320-e, 330-a, 330-b, 330-c, 610-a, 610-b, 610-c, 62 0-a, 620-b, 620-c, 620-d, 620-e, 630-a, 630-b, 630-c, 630-d, 630-e, 640-a, 640-b, 640-c, 320-f, 320-g line segment

[0045] 340-a, 340-b, 340-c, 340-d through position

[0046] LA, LB, LC, LD layers

[0047] I1, I2, I3 interval

[0048] 400, 500, 700 semiconductor components

[0049] 401, 402, 501, 502, 503, 504, 701, 702, 703, 704 endpoints 410, 420, 420, 430 select the range.

Claims

1. A semiconductor component, comprising: A first routing line formed by a first line segment, a second line segment and a third line segment connected in sequence; A second routing line formed by a fourth line segment, a fifth line segment, a sixth line segment, a seventh line segment and an eighth line segment connected in sequence; and A third routing line formed by a ninth line segment, a tenth line segment and an eleventh line segment connected in sequence; in, The first line segment, the fourth line segment and the ninth line segment are substantially parallel, and the third line segment, the eighth line segment and the eleventh line segment are substantially parallel; The second line segment intersects the tenth line segment and the seventh line segment, and the fifth line segment intersects the tenth line segment; and The first routing line, the second routing line and the third routing line use only two conductor layers of a semiconductor structure, and line segments of different conductor layers are connected by a through structure at a through position. The first wiring, the second wiring and the third wiring are all continuous wirings with equal potential. 2 . The semiconductor device according to claim 1 , wherein the sixth line segment is substantially parallel to the first line segment. 3 . The semiconductor device as claimed in claim 1 , wherein the first line segment extends through the eleventh line segment, the fourth line segment extends through the eighth line segment, and the ninth line segment extends through the third line segment. 4 . The semiconductor device according to claim 1 , wherein the first line segment, the third line segment, the fourth line segment, the eighth line segment, the ninth line segment, and the eleventh line segment are implemented in a same conductor layer.

5. The semiconductor component according to claim 1, wherein the semiconductor component is an inductor, the inductor comprises a first coil, a second coil and a third coil, the first trace connects the first coil and the third coil, the second trace connects the second coil, and the third trace connects the third coil and the first coil. 6 . The semiconductor device according to claim 1 , wherein the semiconductor device is a transformer, the transformer comprises a first inductor and a second inductor, the first trace and the third trace are part of the first inductor, and the second trace is part of the second inductor.

7. A semiconductor component comprising: A first routing line formed by a first line segment, a second line segment and a third line segment connected in sequence; A second routing line formed by a fourth line segment, a fifth line segment, a sixth line segment, a seventh line segment and an eighth line segment connected in sequence; and A third routing line formed by a ninth line segment, a tenth line segment and an eleventh line segment connected in sequence; in, The first line segment, the fourth line segment and the ninth line segment are substantially parallel, and the third line segment, the eighth line segment and the eleventh line segment are substantially parallel; Wherein, the first routing line, the second routing line and the third routing line are each continuous routing lines with equal potential; The first routing line, the second routing line and the third routing line only use two conductor layers of a semiconductor structure, and line segments of different conductor layers are connected by a through structure at a through position; and In an intersection section of the first routing line, the second routing line and the third routing line, the first routing line intersects the second routing line once, the first routing line intersects the third routing line once, and the second routing line intersects the third routing line once.

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