Connectivity testing for wafer-to-wafer alignment and bonding

Abstract

The first workpiece includes a first active pad, a first test pad, and a second test pad located on a main surface of the first workpiece, and the first test pad is electrically connected to the second test pad. The second workpiece includes a second active pad, a third test pad, and a fourth test pad located on a main surface of the second workpiece. The first workpiece and the second workpiece are joined along an interface between the main surface of the first workpiece and the main surface of the second workpiece to join the first active pad with the second active pad, join the first test pad with the third test pad, and join the second test pad with the fourth test pad. The connectivity detection circuit tests the electrical connectivity between the third test pad and the fourth test pad.

Description

Background Art

[0001] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, and non-mobile computing devices. Semiconductor memories may include non-volatile memories or volatile memories. Non-volatile memories allow information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND-type flash memory and NOR-type flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0002] Charge trapping materials can be used in non-volatile memory devices to store charge representing a data state. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure. An example of a 3D memory structure is a bit cost scalable (BiCS) architecture, which includes a stack of alternating conductive layers and dielectric layers. Memory holes are formed in the stack, and then vertical NAND strings are formed by filling the memory holes with materials including charge trapping layers to form vertical columns of memory cells. Each memory cell can store one or more data bits.

[0003] The non-volatile memory may be connected to a control circuit that performs memory access operations such as read and write operations. The non-volatile memory may be disposed in a semiconductor chip or die, with the control circuit disposed on a separate chip or die. The chips may be physically connected via bonding pads to allow electrical coupling of circuits on the respective chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Like numbered elements refer to common parts in different figures.

[0005] Figure 1 is a perspective view of a 3D stacked non-volatile memory device.

[0006] Figure 2 is a memory device (such as Figure 1 Functional block diagram of a 3D stacked non-volatile memory device 100).

[0007] Figure 3 is a block diagram depicting one embodiment of a controller.

[0008] Figure 4 is a perspective view of a portion of one embodiment of a three-dimensional monolithic memory structure.

[0009] Figure 4A is a block diagram of a memory structure with two planes.

[0010] Figure 4B Depicted is a top view of a portion of a block of memory cells.

[0011] Figure 4C A cross-sectional view of a portion of a block of memory cells is depicted.

[0012] Figure 4D A view depicting the select gate layer and the word line layer.

[0013] Figure 4E is a cross-sectional view of a vertical column of memory cells.

[0014] Figure 4F is a schematic diagram of multiple NAND strings.

[0015] FIG. 5A to FIG. 5B An array workpiece including pads for bonding is shown.

[0016] FIG. 6A to FIG. 6B A control circuit workpiece including pads for bonding is shown.

[0017] 7A to 7C Wafer-to-wafer bonding and the resulting structure are shown.

[0018] Figure 8 An example of a control circuit coupled to a memory structure via wafer-to-wafer bonding is shown.

[0019] 9A to 9E An example of a structure for electrical connectivity detection is shown.

[0020] FIG. 10A to FIG. 10B An example of a connectivity detection circuit using a comparator is shown.

[0021] FIG. 11A to FIG. 11B An example of a connectivity detection circuit using an XOR gate is shown.

[0022] FIG. 12A to FIG. 12B An on-chip connectivity detection circuit in an array workpiece is shown.

[0023] FIG. 13A to FIG. 13D Connectivity detection using on-chip components and off-chip components is shown.

[0024] Fig.14 An example of a method including detecting electrical connectivity to identify misalignment is shown.

[0025] Fig.15 An example of a method that includes discarding in response to determining a misalignment is shown.

[0026] Fig.16 A flow diagram is shown that includes actions responsive to determining alignment / misalignment. DETAILED DESCRIPTION

[0027] In some examples presented here, wafer-to-wafer bonding is used to bond relative pads of two workpieces (e.g., to bond an array wafer containing a memory array to a control circuit wafer containing a control circuit) to form a combined workpiece. The pads of each array die of the array wafer can be bonded to the corresponding pads of the corresponding control circuit wafer. Wafer-to-wafer bonding can provide a large number of individual connections between such dies. In order to form a good connection, the workpieces are aligned before bonding. After bonding, the interface of the bonding is hidden, and it is not easy to determine the alignment. In some cases, the alignment can vary on the workpiece so that some dies are aligned, while other dies of the same workpiece are not aligned. Rapid detection of misalignment can provide feedback to allow rapid correction of the alignment and / or bonding process, thereby reducing losses, and can allow early identification of bad components, thereby saving testing time.

[0028] Electrical connectivity between pads of opposing workpieces for wafer-to-wafer bonding can be detected and used to determine whether the workpieces are aligned or misaligned. For example, test pads can be provided on opposing surfaces, and connectivity detection circuits can detect electrical connectivity through the test pads. Connectivity detection circuits can be provided on the chips of the workpieces to be bonded, and connectivity indications can be obtained from such circuits at the start of wafer-level testing to provide rapid feedback. Opposing workpieces may include passive components connected to the test pads (e.g., the test pads may be connected together by one or more conductive paths).

[0029] For example, the connectivity detection circuit may be included in the control circuit workpiece and may be connected to the test pads on the control circuit workpiece, while the corresponding test pads of the array workpiece are simply connected through conductive paths. This may not require additional process steps, for example by using passive components in the array workpiece, thereby keeping the implementation simple.

[0030] Figures 1 to 4F One example of a memory system that can be used to implement the techniques presented herein is described. Figure 11 is a perspective view of a three-dimensional (3D) stacked non-volatile memory device. The memory device 100 includes a substrate 101. On and above the substrate are exemplary cell blocks formed of memory cells, including BLK0 and BLK1 (non-volatile memory device elements). Also on the substrate 101 is a peripheral region 104, which has supporting circuits for the blocks. The substrate 101 may also carry circuits below the blocks, together with one or more lower metal layers, which are patterned in conductive paths to carry signals of the circuits. These blocks are formed in a middle region 102 of the memory device. In an upper region 103 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuits. Each cell block includes a stacked region of memory cells, wherein the alternating layers of the stack represent word lines. Although only two blocks are depicted as examples, additional blocks extending in the x-direction and / or the y-direction may be used.

[0031] In an exemplary implementation, the length of the plane in the x direction represents the direction in which the word line signal path extends (the word line direction or the SGD line direction), the width of the plane in the y direction represents the direction in which the bit line signal path extends (the bit line direction), and the z direction represents the height of the memory device.

[0032] Figure 2 is an exemplary memory device (such as Figure 1 Functional block diagram of a 3D stacked non-volatile memory device 100). Figure 2The components depicted in are circuits. The memory system 100 includes one or more memory dies 108. Each memory die 108 includes a three-dimensional memory structure 126 of memory cells (such as, for example, a 3D array of memory cells), a control circuit 110, and a read / write circuit 128. In other embodiments, a two-dimensional array of memory cells may be used. The memory structure 126 is addressable by word lines via a decoder 124 (row decoder) and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks 150, including SB1, SB2, ..., SBp (sense circuits), and allows pages of memory cells to be read or programmed in parallel. In some systems, the controller 122 is included in the same memory device as one or more memory dies 108, such as a memory device 100 (e.g., a removable memory card). However, in other systems, the controller may be separate from the memory die 108. In some embodiments, the controller will be located on a die other than the memory die. In some embodiments, one controller 122 will communicate with multiple memory dies 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transferred between the host 140 and the controller 122 via the data bus 120, and between the controller 122 and one or more memory die 108 via the line 118. In one embodiment, the memory die 108 includes a set of input and / or output (I / O) pins connected to the line 118.

[0033] The memory structure 126 may include one or more arrays of memory cells, including 3D arrays. The memory structure may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (but not in) a single substrate such as a wafer, with no intervening substrates. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of an array of memory cells having active areas disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0034] The control circuit 110 cooperates with the read / write circuit 128 to perform memory operations (e.g., erase, program, read, etc.) on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. The temperature detection circuit 113 is configured to detect temperature and can be any suitable temperature detection circuit known in the art. In one embodiment, the state machine 112 is programmed by software. In other embodiments, the state machine 112 does not use software and is completely implemented in hardware (e.g., circuit). In one embodiment, the control circuit 110 includes registers, ROM fuses, and other storage devices for storing default values ​​(such as reference voltages and other parameters).

[0035] The on-chip address decoder 114 provides an address interface between the addresses used by the host 140 or the controller 122 to the hardware addresses used by the decoder 124 and the decoder 132. The power control module 116 controls the power and voltage provided to the word lines and bit lines during memory operations. It may include drivers for the word line layer (discussed below) in a 3D configuration, select transistors (e.g., SGS and SGD transistors described below), and source lines. The power control module 116 may include a charge pump for generating voltages. The sense block includes a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0036] Any one or any combination of the control circuit 110, state machine 112, decoders 114 / 124 / 132, temperature detection circuit 113, power control module 116, sensing block 150, read / write circuit 128, and controller 122 may be considered as one or more control circuits (or management circuits) that perform the functions described herein.

[0037] The controller 122 (circuit in one embodiment) may include one or more processors 122c, ROM 122a, RAM 122b, memory interface 122d and host interface 122e, all of which are interconnected. One or more processors 122c are an example of a control circuit. Other embodiments may use a state machine or other custom circuit designed to perform one or more functions. The storage device (ROM 122a, RAM 122b) includes code, such as an instruction set, and the processor 122c is operable to execute the instruction set to provide the functions described herein. Alternatively or in addition, the processor 122c can access code from a storage device in a memory structure, such as a reserved area of ​​a memory cell connected to one or more word lines. The memory interface 122d that communicates with ROM 122a, RAM 122b and processor 122c is a circuit that provides an electrical interface between the controller 122 and the memory die 108. For example, the memory interface 122d can change the format or timing of a signal, provide a buffer, isolate surges, latch I / O, etc. Processor 122C may give commands to control circuit 110 (or any other component of memory die 108) via memory interface 122d. Host interface 122e, which communicates with ROM 122a, RAM 122b, and processor 122c, is a circuit that provides an electrical interface between controller 122 and host 140. For example, host interface 122e may change the format or timing of signals, provide a buffer, isolate surges, latch I / O, etc. Commands and data from host 140 are received by controller 122 via host interface 122e. Data sent to host 140 is transmitted via host interface 122e.

[0038] The multiple memory elements in the memory structure 126 can be configured so that they are connected in series or so that each element is individually accessible. As a non-limiting example, a flash memory device in a NAND configuration (NAND flash memory) typically contains memory elements connected in series. A NAND string is an example of a group of memory cells and select gate transistors connected in series.

[0039] A NAND flash memory array can be configured so that the array is composed of multiple NAND strings consisting of multiple memory cells that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are exemplary, and memory cells can be configured in other ways.

[0040] Memory cells may be arranged in an ordered array in a single memory device level, such as in multiple rows and / or columns. However, memory elements may be arranged in irregular or non-orthogonal configurations, or in structures that are not considered arrays.

[0041] The three-dimensional memory array is arranged so that the memory cells occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., x, y and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0042] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., along the y-direction), each column having a plurality of memory cells. The vertical columns may be arranged in a two-dimensional configuration, e.g., arranged in an xy plane, thereby producing a three-dimensional arrangement of memory cells, wherein the memory cells are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a three-dimensional memory array.

[0043] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. Three-dimensional memory arrays may also be designed in NOR configurations as well as ReRAM configurations.

[0044] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by those of ordinary skill in the art.

[0045] Figure 3 is a block diagram of an exemplary memory system 100, which depicts more details of the controller 122. In one embodiment, Figure 3The system is a solid state drive (SSD). As used herein, a flash memory controller is a device that manages data stored on a flash memory and communicates with a host such as a computer or electronic device. In addition to the specific functions described herein, a flash memory controller may have various functions. For example, a flash memory controller may format the flash memory to ensure that the memory operates properly, map out bad flash memory cells, and allocate spare memory cells to replace failed cells in the future. Some of the spare cells may be used to accommodate firmware to operate the flash memory controller and implement other features. In operation, when the host needs to read data from the flash memory or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to read / write data, the flash memory controller may convert the logical address received from the host into a physical address in the flash memory. (Alternatively, the host may provide a physical address). The flash memory controller may also perform various memory management functions, such as, but not limited to, wear leveling (allocating writes to avoid wearing out a specific memory block that would otherwise be repeatedly written) and garbage collection (after a block is full, only valid data pages are moved to a new block, so that the complete block can be erased and reused).

[0046] The communication interface between the controller 122 and the non-volatile memory die 108 may be any suitable flash memory interface, such as switch mode 200, 400, or 800. In one embodiment, the memory system 100 may be a card-based system, such as a secure digital (SD) or micro secure digital (micro-SD) card. In an alternative embodiment, the memory system 100 may be part of an embedded memory system. For example, the flash memory may be embedded within a host, such as in the form of a solid state disk (SSD) drive installed in a personal computer.

[0047] In some embodiments, the memory system 100 includes a single channel between the controller 122 and the non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, there may be 2, 4, 8, or more channels between the controller and the memory die, depending on the capabilities of the controller. In any of the embodiments described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and the memory die.

[0048] like Figure 3 As depicted, the controller 122 includes a front end module 208 that interfaces with a host, a back end module 210 that interfaces with one or more non-volatile memory dies 108, and various other modules that perform functions that will now be described in detail.

[0049] Figure 3The components of the controller 122 depicted in the can take the form of, for example, packaged functional hardware units (e.g., circuits) designed for use with other components, portions of program code (e.g., software or firmware) that can be executed by a (micro)processor or processing circuit (or one or more processors) that generally performs a specific function of the related functions, or independent hardware or software components that interface with a larger system. For example, each module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware, or a combination thereof. Alternatively or in addition, each module may include or contain software stored in a processor readable device (e.g., a memory) to program one or more processors of the controller 122 to perform the functions described herein. Figure 3 The architecture depicted in this example may (or may not) use Figure 2 An exemplary implementation of the components of controller 122 (ie, RAM, ROM, processor, interfaces) is depicted in FIG.

[0050] Referring again to the modules of controller 122, buffer manager / bus controller 214 manages buffers in random access memory (RAM) 216 and controls internal bus arbitration of controller 122. Read only memory (ROM) 218 ​​stores system boot code. Figure 3 122, but in other embodiments, one or both of RAM 216 and ROM 218 may be located within the controller. In still other embodiments, portions of the RAM and ROM may be located within the controller 122 and outside the controller. Furthermore, in some implementations, the controller 122, RAM 216, and ROM 218 may be located on separate semiconductor dies.

[0051] The front-end module 208 includes a host interface 220 and a physical layer interface 222 (PHY) that provide an electrical interface with a host or a next-level storage controller. The type of host interface 220 can be selected depending on the type of memory used. Examples of host interface 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 can be a communication interface that facilitates the transmission of data, control signals, and timing signals.

[0052] The backend module 210 includes an error correction controller (ECC) engine, namely, an ECC engine 224, which encodes data bytes received from the host and decodes and corrects data bytes read from the non-volatile memory. The command sequencer 226 generates command sequences, such as programming command sequences and erase command sequences, for transmission to the non-volatile memory tube core 108. The RAID (Redundant Array of Independent Tube Cores) module 228 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the memory device 100. In some cases, the RAID module 228 can be part of the ECC engine 224. It should be noted that the RAID parity can be added as an additional tube core or multiple tube cores, as the common name implies, but can also be added within the existing tube core, for example, as an additional plane, or an additional block, or an additional WL within a block. The ECC engine 224 and the RAID module 228 both calculate redundant data, which can be used to recover when an error occurs and can be regarded as an example of a redundant encoder. The ECC engine 224 and the RAID module 228 may be considered together to form a combined redundant encoder 234. The memory interface 230 provides command sequences to the non-volatile memory die 108 and receives status information from the non-volatile memory die 108. In one embodiment, the memory interface 230 may be a double data rate (DDR) interface, such as a switched mode 200, 400, or 800 interface. The flash control layer 232 controls the overall operation of the back end module 210.

[0053] Figure 3 Additional components of the memory system 100 shown include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory die 108. The memory system 100 also includes other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with the controller 122. In alternative embodiments, one or more of the physical layer interface 222, the RAID module 228, the media management layer 238, and the buffer management / bus controller 214 are optional components that are not necessary in the controller 122.

[0054] A flash translation layer (FTL) or media management layer (MML) 238 may be integrated as part of the flash management that can handle flash errors and interface with the host. Specifically, the MML may be a module in the flash management and may be responsible for the internals of the NAND management. Specifically, the MML 238 may include an algorithm in the memory device firmware that converts writes from the host into writes to the flash memory 126 of the memory die 108. The MML 238 may be required because: 1) the flash memory may have limited endurance; 2) the flash memory 126 may only be written to multiple pages; and / or 3) unless the flash memory 126 is erased as a block (i.e., a block may be considered as the minimum erase unit), it may not be written. The MML 238 understands these potential limitations of the flash memory 126, which may not be visible to the host. Therefore, the MML 238 attempts to convert writes from the host into writes to the flash memory 126.

[0055] The controller 122 may interact with one or more memory dies 108. In one embodiment, the controller 122 and the plurality of memory dies (together forming the memory system 100) implement a solid state drive (SSD) that may emulate, replace, or be used in place of a hard disk drive within a host (such as a NAS device) or the like. Alternatively, the SSD need not function as a hard disk drive.

[0056] Figure 4 is a perspective view of a portion of a three-dimensional memory structure 126 including a plurality of memory cells. For example, Figure 4 A portion of a memory block is shown. The depicted structure includes a set of bit lines BL, which are located above a stack of alternating dielectric layers and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes alternating dielectric layers and conductive layers between 108 and 216, for example, 96 data word line layers, 8 selection layers, 4 dummy word line layers, and 108 dielectric layers. More or less than 108 to 216 layers may also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four "fingers" by local interconnects LI. Figure 4 Only two fingers and two local interconnects LI are shown. Below and between the alternating dielectric and word line layers is the source line layer SL. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, the memory hole is labeled MH. Note that Figure 4In FIG. 1 , the dielectric layers are depicted as a perspective view so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping layer to form a vertical column of memory cells. Each memory cell can store one or more bits of data. 4A to 4F More details of three-dimensional memory structure 126 are provided.

[0057] Figure 4A 304 is a block diagram illustrating an exemplary organization of a memory structure 126, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes may also be used. In one embodiment, for two plane memories, the block IDs are typically such that even blocks belong to one plane and odd blocks belong to another plane; therefore, plane 302 includes blocks 0, 2, 4, 6, ..., and plane 304 includes blocks 1, 3, 5, 7, .... In one embodiment, a block of memory cells is an erase unit. That is, all memory cells of a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize the memory structure 126 to enable signaling and selection circuits.

[0058] FIG. 4B to FIG. 4F An exemplary 3D NAND structure is depicted. Figure 4B is a block diagram depicting a top view of a portion of one block from memory structure 126 . Figure 4B The portion of the box depicted in corresponds to Figure 4A Section 306 of Box 2. From Figure 4B It can be seen that Figure 4B The blocks depicted in FIG. extend in the direction of 332. In one embodiment, the memory array will have 60 layers. Other embodiments have fewer or more than 60 layers. However, Figure 4B Only the top layer is shown.

[0059] Figure 4B A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select transistors and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B Vertical columns 422, 432, 442, and 452 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of the vertical columns are provided below. Figure 4BThe block depicted in FIG. 1 extends in the direction of arrow 330 and in the direction of arrow 332, so that the block includes more Figure 4B More vertical columns depicted in

[0060] Figure 4B Also depicted is a set of bit lines 425 , including bit lines 411 , 412 , 413 , 414 , . . . 419 . Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0061] Figure 4B The block depicted in includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various layers to the source lines below the vertical columns. Local interconnects 402, 404, 406, 408, and 410 are also used to divide each layer of the block into four regions; for example, Figure 4B The top layer depicted in is divided into regions 420, 430, 440, and 450, which are called fingers. In the layer implementing the blocks of memory cells, these four regions are called word line fingers, which are separated by local interconnects. In one embodiment, the word line fingers on the common level of the block are connected together at the ends of the block to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In an exemplary embodiment, the bit line is connected to only one vertical column in each of the regions 420, 430, 440, and 450. In this embodiment, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line fingers on the same level connected together); therefore, the system uses source side select lines and drain side select lines to select one (or another subset) of the four to be subjected to memory operations (programming, verification, reading, and / or erasing).

[0062] although Figure 4B It is shown that each region has four rows of vertical columns in a block, and four regions have sixteen rows of vertical columns, but these exact numbers are exemplary embodiments. Other embodiments may include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block.

[0063] Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0064] Figure 4C A portion of an embodiment of a three-dimensional memory structure 126 is depicted, showing the Figure 4B The cross-sectional view cuts through vertical columns 432 and 434 and region 430 (see Figure 4B ). Figure 4C The structure includes: four drain side selection layers SGD0, SGD1, SGD2 and SGD3; four source side selection layers SGS0, SGS1, SGS2 and SGS3; four dummy word line layers DD0, DD1, DS0 and DS1; and forty-eight data word line layers WLL0 to WLL47, which are used to connect to data memory cells. Other embodiments may implement more or less than four drain side selection layers, more or less than four source side selection layers, more or less than four dummy word line layers, and more or less than forty-eight word line layers (e.g., 96 word line layers). Vertical columns 432 and 434 are depicted as protruding through the drain side selection layers, source side selection layers, dummy word line layers, and word line layers. In one embodiment, each vertical column includes a NAND string. For example, vertical column 432 includes NAND string 484. Below the vertical column and the layers listed below are the substrate 101, the insulating film 454 on the substrate, and the source line SL. The NAND strings of the vertical column 432 have source terminals at the bottom of the stack and drain terminals at the top of the stack. Figure 4B Consistent, Figure 4C A vertical column 432 is shown connected to a bit line 414 via a connector 415. Local interconnects 404 and 406 are also depicted.

[0065] Bit line 414 is connected to pad 416 through via 417. Additional bit lines coupled to additional vertical columns are similarly connected. Multiple bit lines may extend above such a memory structure and may be connected to multiple blocks through block select circuits. Such bit lines are connected to pads that may be exposed along the top surface (major surface) of the workpiece so that they can be used to make electrical connections. Similarly, word lines (e.g., WLL0 to WLL47), dummy word lines (e.g., DD0-1, DS0-1), and select lines (e.g., SGD0 to SGD3) may be connected through vias ( Figure 4C The word line layers may be coupled to pads on the major surface of the workpiece (e.g., pads coplanar with pad 416) (not shown). For example, the word line layers may be arranged in a stepped "staircase" arrangement in an outer region (outside of the region where the memory cells are formed) such that each word line layer is exposed and contactable by a via.

[0066] For ease of reference, drain side selection layers SGD0, SGD1, SGD2, and SGD3; source side selection layers SGS0, SGS1, SGS2, and SGS3; dummy word line layers DD0, DD1, DS0, and DS1; and word line layers WLL0 to WLL47 are collectively referred to as conductive layers. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten or metal silicide). In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers are dielectric layers DL0 to DL59. For example, dielectric layer DL49 is above word line layer WLL43 and below word line layer WLL44. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0067] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0 to WLL47 are connected to memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, and DS1 are connected to dummy memory cells. Dummy memory cells do not store user data, while data memory cells are eligible to store user data. Drain side selection layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND string to the bit line. Source side selection layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND string to the source line SL.

[0068] Figure 4D Depicted Figure 4C 47). As described above with respect to the conductive layers of the partially depicted block (SGD0, SGD1, SGD2, SGD3, SGS0, SGS1, SGS2, SGS3, DD0, DD1, DS0, DS1 and WLL0 to WLL47). Figure 4B As described, in one embodiment, local interconnects 402, 404, 406, 408, and 410 divide each conductive layer into four regions or fingers. For example, word line layer WLL31 is divided into regions 460, 462, 464, and 466. For word line layers (WLL0 to WLL31), these regions are referred to as word line fingers; for example, word line layer WLL46 is divided into word line fingers 460, 462, 464, and 466. In one embodiment, four word line fingers on the same level are connected together. In another embodiment, each word line finger operates as a separate word line.

[0069] The drain side select gate layer SGD0 (top layer) is also divided into regions 420, 430, 440 and 450, also referred to as fingers or select line fingers. In one embodiment, four select line fingers on the same level are connected together. In another embodiment, each select line finger operates as a separate word line.

[0070] Figure 4E A portion of a vertical column 432 is depicted. Figure 4C 4 is a cross-sectional view of region 429 of . In one embodiment, the vertical columns are circular and include four layers; however, in other embodiments, more or less than four layers may be included, and other shapes may be used. In one embodiment, vertical column 432 includes an inner core 470 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 470 is a polysilicon channel, namely channel 471. Materials other than polysilicon may also be used. Note that channel 471 is connected to the bit line. Surrounding channel 471 is a tunneling dielectric 472. In one embodiment, tunneling dielectric 472 has an ONO structure. Surrounding tunneling dielectric 472 is a charge trapping layer 473, such as (for example) silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0071] Figure 4E Dielectric layers DLL49, DLL50, DLL51, DLL52, and DLL53 are depicted, as well as word line layers WLL43, WLL44, WLL45, WLL46, and WLL47. Each of the word line layers includes a word line region 476 surrounded by an aluminum oxide layer 477, which is surrounded by a blocking oxide layer 478 (SiO2). The physical interaction of the word line layers with the vertical columns forms a memory cell. Therefore, in one embodiment, the memory cell includes a channel 471, a tunneling dielectric 472, a charge trapping layer 473, a blocking oxide layer 478, an aluminum oxide layer 477, and a word line region 476. For example, word line layer WLL47 and a portion of vertical column 432 constitute memory cell MC1. Word line layer WLL46 and a portion of vertical column 432 constitute memory cell MC2. Word line layer WLL45 and a portion of vertical column 432 constitute memory cell MC3. Word line layer WLL44 and a portion of vertical column 432 constitute memory cell MC4. Word line layer WLL43 and a portion of vertical column 432 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still still be storage cells.

[0072] When programming a memory cell, electrons are stored in a portion of a charge trapping layer 473 associated with the memory cell. In response to an appropriate voltage on the word line region 476, these electrons are attracted from the channel 471 into the charge trapping layer 473 through the tunnel dielectric 472. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming of the non-volatile memory system is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate induced drain leakage (GIDL).

[0073] Figure 4F Physical word lines WLL0 to WLL47 are shown extending across the entire block. Figure 4 The structure of G corresponds to 4A to 4F Portion 306 in block 2 includes bit lines 411, 412, 413, 414, ... 419. Within the block, each bit line is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to the associated bit line. It can also be considered that the block is divided into four sub-blocks SB0, SB1, SB2, and SB3. Sub-block SB0 corresponds to a vertical NAND string controlled by SGD0 and SGS0, sub-block SB1 corresponds to a vertical NAND string controlled by SGD1 and SGS1, sub-block SB2 corresponds to a vertical NAND string controlled by SGD2 and SGS2, and sub-block SB3 corresponds to a vertical NAND string controlled by SGD3 and SGS3.

[0074] Although Figures 4 to 4F An exemplary memory system is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein. For example, floating gate memory (e.g., NAND-type and NOR-type flash memory), ReRAM memory, magnetoresistive memory (e.g., MRAM), and phase change memory (e.g., PCRAM) may also be used.

[0075] An example of a ReRAM memory includes a reversible resistance switching element arranged in an array of crosspoints accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0076] Magnetoresistive memory (MRAM) stores data via a magnetic storage element. The element is formed of two ferromagnetic plates, each of which can maintain magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match that of an external magnetic field to store memory. This configuration is called a spin valve and is the simplest structure of an MRAM bit. The memory device is built from a grid of such memory cells. In one embodiment for programming a non-volatile memory system, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When a current passes through them, an induced magnetic field is generated.

[0077] Phase change memory (PCRAM) exploits the unique behavior of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by changing the coordination state of the germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes (continuous or non-continuous) vibrations or pulse trains of sound, current, voltage light or other waves.

[0078] At the end of a successful programming process (with verification), the threshold voltage of the memory cell should be within one or more distributions of the threshold voltage for programmed memory cells or within the distribution of the threshold voltage for erased memory cells, as appropriate. FIG. 5 shows an exemplary threshold voltage distribution for a memory cell array when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one bit of data per memory cell, two bits of data, four bits of data, or five bits of data). FIG. 5 shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) S0 represents an erased memory cell. The other seven threshold voltage distributions (data states) S1 to S17 represent programmed memory cells, and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. In one embodiment, data values ​​are assigned to threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory is erroneously shifted to its neighboring physical state, only one bit will be affected.

[0079] Figure 5A A non-volatile memory, such as memory structure 126 , is shown after forming interconnects and bonding features. Figure 5A A cross-section of a workpiece 500 is shown, which includes a substrate 501, for example, a silicon substrate, such as a silicon wafer (e.g., a 300 mm wafer) or a portion of a wafer. The term workpiece can refer to the substrate (e.g., a wafer or a portion of a wafer) and the components formed in or on the substrate, including electronic components such as active components, interconnect layers, dielectric layers, and bond pads. On and above the substrate 501 is an intermediate region 502, which may include a block of non-volatile memory cells (e.g., including Figure 1 BLK0 and BLK1 are shown, which have Figures 4 to 4F 126). In the upper region 503 (interconnect region) of the workpiece 500, one or more metal layers are patterned in conductive paths to carry electrical signals. These may include bit lines (e.g., Figure 4CThe patterned metal layers are separated by dielectric layers (e.g., silicon dioxide or other insulators) that provide electrical isolation. Above the upper region 503 is a bonding region 504 that includes bonding pads (e.g., pads 416) that are connected to conductive paths of the upper region 503 and / or components of the middle region 502 and / or substrate 501 to provide electrical coupling to non-volatile memory cells in the middle region 502 through conductive traces of the upper region 503. The bonding region 504 may include a dielectric layer, wherein the bonding pads are formed in or on the dielectric layer so that the pads are exposed at the surface 506 (the primary surface) and can be bonded to opposing bonding pads in a wafer-to-wafer bonding process.

[0080] Figure 5B A top view of a portion of a major surface 506 of a workpiece 500 is shown, showing pads 508a to 508d (which may include active pads coupled to bit lines, word lines, dummy word lines, select gate lines, and test pads provided for testing purposes) and 416 (previously shown in Figure 4C 5. The bonding region 504 may include a dielectric layer extending around the pads and isolating adjacent pads. The pads may be made of a suitable electrical conductor, such as copper or a copper alloy containing copper, or other suitable metal or metal alloy.

[0081] Fig. 6A shows a control circuit including such Figure 3An example of a workpiece 600 of control circuitry for a memory controller 122 is shown. Workpiece 600 includes a substrate 601, such as a silicon wafer (e.g., a 300 mm wafer) or a portion of a wafer. Above and above substrate 601 is an intermediate region 602, which may include control circuitry formed on (and / or in) substrate 601. For example, the intermediate region may include a CMOS (complementary metal oxide semiconductor) circuit including circuitry of controller 122 formed in an active region of substrate 601. In an upper region 603 (interconnect region) of workpiece 600, one or more metal layers are patterned in conductive paths to carry electrical signals. These may include traces extending laterally and through holes extending vertically relative to the main surface of the substrate. Such conductive paths may form electrical connections between different circuits (e.g., connecting components of controller 122). The patterned metal layers are separated by dielectric layers (e.g., silicon dioxide or other insulators) that provide electrical isolation. Above the upper region 603 is a bonding region 604 that includes bonding pads connected to conductive paths of the upper region 603 and / or components of the intermediate region 602 and / or substrate 601 to provide electrical coupling with circuits in the intermediate region 602 through the conductive paths of the upper region 603. The bonding region 604 may include a dielectric layer with the bonding pads formed in or on the dielectric layer such that the bonding pads are exposed at the surface 606 (the primary surface) and may be bonded to opposing bonding pads in a wafer-to-wafer bonding process.

[0082] Figure 6B A top view of a portion of a major surface 606 of a workpiece 600 is shown, showing an exposed pad including pads 608a to 608d (which may include active pads and test pads provided for testing purposes) and pad 616. The bonding region 604 may include a dielectric layer extending around the pad and isolating adjacent pads. The pad may be made of a suitable electrical conductor such as copper or a copper alloy containing copper, or other suitable metal or metal alloy.

[0083] Pads 608a to 608d and 616 may be arranged to connect with corresponding pads of another workpiece for a wafer-to-wafer bonding process. For example, pad 616 may be positioned so that when workpieces 500 and 600 are aligned and bonded, pad 616 is bonded to pad 416, and thus bit line 414 may be controlled by control circuitry in middle region 602 of workpiece 600. Workpiece 500 may include a plurality of memory dies, and workpiece 600 may include an equal number of control circuit dies in a corresponding pattern (e.g., a one-to-one pattern such that for each memory die of workpiece 500, there is a corresponding control circuit die of workpiece 600). Opposing pairs of dies have corresponding pad patterns such that when the workpieces are precisely aligned, each pad is aligned with a corresponding pad of the opposing die so that the control circuitry of workpiece 600 is electrically connected to the memory cells of workpiece 500.

[0084] Fig. 7A The process of wafer-to-wafer bonding of workpiece 500 and workpiece 600 is shown. Substrate 501 is processed to manufacture memory arrays (eg, memory structures 126), interconnect structures, and pads for bonding, as described above with reference to FIG. 5A to FIG. 5B As discussed above, workpiece 500 is formed. Substrate 601 is processed to manufacture control circuits (e.g., logic circuits formed as CMOS circuits), interconnect structures, and pads for bonding, as described above with reference to FIG. 6A to FIG. 6B As discussed, workpiece 600 is formed. Then in this example, workpiece 500 is flipped (either workpiece may be flipped) so that major surface 506 of workpiece 500 is opposite to major surface 606 of workpiece 600. Workpieces 500 and 600 are aligned so that corresponding dies are aligned in pairs and pads on such die pairs are aligned for bonding. Subsequently, with workpieces 500 and 600 aligned, pressure and / or heat or other conditions are applied to workpieces 500 and 600 to bond corresponding pads together, thereby forming an electrical connection between the memory array of workpiece 500 and the control circuit of workpiece 600 (i.e., bonding along the interface between major surfaces 506 and 606). The bonded workpieces 500 and 600 form a combined workpiece 700 including die pairs, each pair including a memory array die and a control circuit die forming a memory system. A combined workpiece or a portion of such a workpiece may be referred to as a CMOS bonded array (CbA), and a single chip formed in this manner may be referred to as a CbA chip.

[0085] Figure 7B A combined workpiece 700 is shown that includes the workpiece 600 and the workpiece 500. As can be seen, the joint region 504 of the workpiece 500 is in contact with the joint region 604 of the workpiece 600 along the interface 701 (ie, the interface between the major surfaces of the workpieces 500, 600).

[0086] Figure 7C A portion of a composite workpiece 700 is shown, including a substrate 601, an intermediate region 602 (including active components formed as components of a CMOS chip within and on the substrate 601), an upper region 603 (including conductive paths formed by traces and vias separated by dielectrics), and a bonding region 604, which includes pads bonded to corresponding pads of the bonding region 504. Through the conductive paths of the upper region 503, the pads of the bonding region 504 are coupled to memory array elements formed on the substrate 501 in the intermediate region 502.

[0087] Although pads along the major surfaces of workpieces 500, 600 may be bonded together and may not be exposed after bonding, additional pads may be provided for connection to other circuits (e.g., external circuits connected to the combined workpiece 700) and may be exposed for bonding and / or probing. Exposed pads 720 in workpiece 600 are exposed by openings 722 extending through workpiece 500. One or more such openings may be provided in each die of workpiece 500 so that designated pads of workpiece 600 remain exposed after wafer-to-wafer bonding of workpieces 500, 600. For example, an opening may be etched through workpiece 500 before (or after) wafer-to-wafer bonding. Although one exposed pad (pad 720) is shown, it should be understood that any number of exposed pads may be provided. For example, pads may be provided for interacting with a host, receiving power, testing, and other purposes.

[0088] The manufacturing process used to form workpiece 500 may be completely different from the manufacturing process used to form workpiece 600. For example, although the memory structure 126 of workpiece 500 includes multiple active areas above the substrate surface in a 3D structure, the logic circuit of workpiece 600 may be formed in a single active area. The logic circuit may be formed by a CMOS process, while the memory structure 126 uses a process step suitable for 3D memory manufacturing, which may be different from the CMOS process step. Therefore, the number of layers and materials used may be different. The device size and tolerances may also be different. And the thermal budget may be different. Embedding the logic circuit in a workpiece (such as workpiece 500) may require additional process steps because the same process steps used to form the memory structure 126 may be incompatible with the process steps for forming the logic circuit. Therefore, the logic circuit provided in the peripheral area (e.g., CMOS or other logic circuits in the peripheral area 104) may be formed separately. This increases the number of process steps, thereby increasing the risk of damage and generating thermal budget issues.

[0089] although Figure 2 The memory die 108 is shown to include a plurality of peripheral regions (eg, Figure 1Although various circuits other than memory structure 126 (e.g., control circuit 110, read / write circuit 128, and row decoder 124) are examples of peripheral regions 104 of the array workpiece, reducing or eliminating logic circuits in the array workpiece can reduce the number of processing steps required and reduce thermal budget issues. Wafer-to-wafer bonding provides a relatively large area for bonding a large number of pads, so that a wide interface can be provided between the array workpiece and the control circuit workpiece. This can be advantageous for bonding with Figure 2 For example, in some examples, some or all of the control circuitry 110, read / write circuitry 128, and row decoder 124 shown on memory die 108 may be located on a control circuit artifact rather than on the same die as memory structure 126. This may allow the array artifact to be manufactured with little or no logic circuitry (e.g., no CMOS components), which may significantly simplify manufacturing and reduce thermal budget issues.

[0090] Figure 8 Shows Figure 2 An alternative arrangement of the arrangement can be achieved by wafer-to-wafer bonding. Figure 8 An example of a control circuit formed in a control circuit die 808 (e.g., the control circuit die in workpiece 600) is shown, which is coupled to a memory structure 126 formed in an array die 810 (e.g., the array die in workpiece 500). Common components such as Figure 2 As can be seen, control circuit 110, read / write circuit 128, and row decoder 124 (which may be formed by a CMOS process) are located in control circuit die 808. Controller 122 is also located in control circuit die 808. Control circuit 110, read / write circuit 128, row decoder 124, and controller 122 may be formed by conventional processes (e.g., CMOS processes) such that adding control circuit 110, read / write circuit 128, and row decoder 124 to a die including controller 122 may require few or no additional process steps (i.e., the same process steps used to manufacture controller 122 may also be used to manufacture control circuit 110, read / write circuit 128, and row decoder 124). Therefore, while moving such circuits away from a die (such as memory die 108) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as control circuit die 808) may not require any additional process steps.

[0091] Figure 8The read / write circuit 128 is shown coupled to the memory structure 126 via an electrical path 812. For example, the electrical path 812 can provide an electrical connection between the read / write circuit 128 and the bit line of the memory structure 126. The electrical path can extend from the read / write circuit 128 in the control circuit die 808 through a pad (e.g., pad 616) on the control circuit die that is bonded to a corresponding pad (e.g., pad 416) on the array die 810 that is connected to the bit line of the memory structure 126. Each bit line of the memory structure 126 can have a corresponding electrical path in the electrical path 812, including a pair of bonding pads connected to the read / write circuit 128. Similarly, the row decoder circuit 124 is coupled to the memory structure 126 via an electrical path 814. Each electrical path in the electrical path 814 can correspond to a word line, a dummy word line, or a selected gate line. Additional electrical paths can also be provided between the control circuit die 808 and the array die 810.

[0092] It should be understood that accurate alignment of the pads between the array workpiece and the control circuit workpiece may be required to form a functional memory system. If the pads are not accurately aligned, no electrical connection is formed or a poor electrical connection is formed, and the control circuit cannot interact properly with the memory cell. Misalignment of a workpiece (e.g., workpieces 500, 600) may cause the combined workpiece (e.g., combined workpiece 700) to be scrapped (i.e., all dies may be discarded), which represents a loss and is generally undesirable. In some cases, some dies may be aligned while other dies are misaligned (e.g., due to greater forces and / or non-uniformities). Such die-level misalignments may not be immediately apparent. Although testing can identify problems caused by misalignment, such testing may require a significant amount of time, and problems caused by alignment and / or bonding may continue to occur while the test is performed until the misalignment is identified as the source and the problem is resolved. Significant losses may occur during such a period of time before the problem is identified and resolved. In a test such as Figure 8 In the arrangement shown, with a large number of bonding connections to accommodate a non-volatile memory array, the pads can be small and the potential for misalignment is greater. Therefore, misalignment may need to be a concern in such a design.

[0093] Aspects of the present technology allow misalignment of workpieces joined by wafer-to-wafer bonding, including die-level misalignment, to be quickly identified so that appropriate action can be taken. Simple on-die circuitry can be used to detect misalignment to give die-by-die information about alignment. This can be done before the combined wafer is cut into individual dies (e.g., immediately after wafer-to-wafer bonding, or shortly after wafer-to-wafer bonding) so that results can be obtained quickly and any process-induced problems can be quickly resolved. This can reduce the number of scrapped dies by allowing misalignment problems to be identified more quickly and corrective action to be taken more quickly.

[0094] An exemplary technique includes providing opposing pairs of test pads on the surface where wafer-to-wafer bonding is to be performed (e.g., on surfaces 506, 606), where the pads on one workpiece are electrically connected together. Electrical connectivity between the opposing pads is then checked. If the pads are properly bonded, the electrical connectivity is good. If the pads are not bonded (e.g., due to misalignment), the electrical connectivity may be poor (e.g., an open circuit).

[0095] Fig.9A Test pads 930a to 930d are shown disposed on the surface 506 of the array workpiece 500. The test pads 930a to 930d may be distributed in any suitable manner. For example, the test pads may be located at or near a corner of the die, or may be relatively close together at a specific location in the die. Each die may have one or more groups of test pads, wherein each group has two or more test pads. This allows alignment to be tested die by die.

[0096] Fig. 9B Test pads 936a to 936d are shown disposed on the surface 606 of the control circuit workpiece 600. The test pads 936a to 936d may be arranged to correspond to the test pads 930a to 930d (i.e., the test pads are laid out so that when the surfaces 506, 606 are subjected to wafer-to-wafer bonding, the test pads 930a to 930d should be aligned with the test pads 936a to 936d.

[0097] Fig. 9C Test pads 930a to 930d and test pads 936a to 930d are shown to be misaligned. Although test pad 930a is designed to align with test pad 936a and thus be electrically connected, test pads 930a and 936a are misaligned and therefore do not overlap and do not join together during bonding. Similarly, test pads 930b and 936b do not overlap and do not join, test pads 930c and 936c do not overlap and do not join, and test pads 930d and 936d do not overlap and do not join. The misalignment examples shown relate to non-overlap and non-joining between relative pads. Aspects of the present invention technology can be used to detect misalignment where there is no overlap as shown, or detect when there is some overlap and / or some joining and is not limited to the situation shown.

[0098] Fig.9D A cross-sectional view of a portion of workpiece 500 including test pads 930a-930b and a portion of workpiece 600 including test pads 936a-936b is shown. Test pad 930a is electrically connected to test pad 930b via a conductive path 938 (e.g., via a metal trace and a via connecting test pads 930a-930b to the trace). Fig.9DThe case where the parts of workpieces 500 and 600 are partially aligned and therefore the test pads are joined and electrically connected is shown. Specifically, test pad 930a is joined to test pad 936a, and test pad 930b is joined to test pad 936b. Test pad 936 is connected to node A through a conductive path, and test pad 936b is connected to node B through another conductive path. Node A and node B may be located in workpiece 600 and may be connected to an appropriate connectivity detection circuit (e.g., a circuit configured to test electrical connectivity formed in a control circuit of workpiece 600 or elsewhere) so that the electrical connectivity between node A and node B can be tested. In the case where the test pads are aligned as shown, it can be seen that since test pad 936a is connected to test pad 936b through relative test pads 930a to 930b and conductive path 938, node A is electrically connected to node B. Thus, testing the electrical connectivity of the structure will find good connectivity (ie, there is low resistance between nodes A and B, and current can flow between nodes A and B with minimal voltage drop, so that both nodes A and B are at approximately the same voltage).

[0099] Fig.9E Parts of the workpieces 500, 600 are shown to be misaligned, such that the test pad 930a is not bonded to the test pad 936a and the test pad 930b is not bonded to the test pad 936b (eg, as shown in FIG. 1 ). Fig. 9C ). Because these test pads are not bonded, there is little or no electrical connectivity between test pad 936a and test pad 936b. Therefore, when the electrical connectivity between node A and node B is measured, the electrical connectivity will be poor (e.g., high resistance indicates an open circuit state, so that the nodes may be at different voltages), which indicates that the test pads are misaligned and therefore indicates that at least some portions of the workpieces 500, 600 are misaligned. Connectivity between two such nodes can be quickly detected in a variety of ways so that misalignment can be quickly identified and appropriate action can be taken.

[0100] In one arrangement, the connectivity detection circuit is located in workpiece 600 (control circuit workpiece) and can be formed as a CMOS logic circuit using the same process as forming the control circuit, while the components shown in workpiece 500 (array workpiece), including test pads 930a, 930b and conductive paths 938, are passive components that can be formed using the same process steps as forming the conductive paths of workpiece 500. One or more of nodes A and B may alternatively be located off-chip or may be connected to off-chip components, so that some or all of the connectivity detection circuit may be located outside of workpiece 600 (e.g., external test equipment).

[0101] Fig. 10AA first example of a connectivity detection circuit 1000 is shown, which may be coupled to FIG. 9D to FIG. 9E Node A and node B of the circuit are connected to test the electrical connectivity between node A and node B. Inputs from node A and node B are provided to a multiplexer 1002 (MUX), which selects one of the inputs (according to a select signal) and provides it on an output 1004. Output 1004 from multiplexer 1002 is provided as an input signal to a comparator 1008, which receives a second input 1006 having a reference voltage Vref. When enabled (according to an enable signal), comparator 1008 provides an output 1010 (a flag in this example) indicating whether the voltage on the selected node (node ​​A or node B) is greater than voltage Vref. Therefore, the voltage on either or both nodes can be compared with the reference voltage to see if the two nodes are at a voltage indicating electrical connectivity. For example, a voltage greater than Vref can be applied to conductive path 938 (through one of node A or node B, or otherwise) so that if node A and node B are electrically connected to conductive path 938, they will have a voltage greater than Vref. The two nodes may be checked (e.g., selected in series) to determine whether the test pads 936a-936b are aligned with the test pads 930a-930b, and therefore the portion of the workpiece 500, 600 containing the test pads is aligned. If either node shows a voltage less than the reference voltage Vref, this indicates that there is no connectivity and the test pads are misaligned (and therefore, the portion of the workpiece 500, 600 is misaligned).

[0102] Although in FIG. 9D to FIG. 9E Examples and Fig. 10A Two nodes are shown in FIG. 1 , but it should be understood that aspects of the present technology can be applied to any number of nodes connected to corresponding test pads (e.g., connected to Fig. 9B four nodes of the four test pads). Fig. 10B An example of a connectivity detection circuit 1020 that can be used to check the electrical connectivity of N nodes (where N can be any number), each node coupled to a corresponding test pad (e.g., N=4, where each node is coupled to Fig. 9B 1008). The connectivity detection circuit 1020 includes components similar to those of the connectivity detection circuit 1000, and similar components are numbered in a similar manner. Multiplexer 1022 is an N-input multiplexer so that a voltage from any of the N nodes can be selected and set on output 1004 as an input to comparator 1008. The N test pads can be arranged in a certain pattern to detect electrical connectivity at various locations in the combined workpiece (e.g., at different locations in each tube core).

[0103] Fig.11A An example of a connectivity detection circuit 1100 including an exclusive OR (XOR) gate 1102 coupled to nodes A and B is shown. An output 1104 may indicate whether there is a difference between the voltages at nodes A and B (i.e., if both nodes are at a high voltage or both are at a low voltage, the XOR condition is not satisfied and the output 1104 may provide a logic low signal, and if one node is at a high voltage and the other node is at a low voltage, the XOR condition is satisfied and the output 1104 may provide a logic high signal). Thus, a logic low signal may indicate good electrical connectivity between nodes A and B, while a logic high signal may indicate poor electrical connectivity between nodes A and B, which further indicates poor alignment of portions of the workpieces 500, 600.

[0104] Fig. 11B An example of a connectivity detection circuit 1120 including an XOR gate 1122 is shown, in which the XOR gate is an N-input XOR gate so that the voltages at N nodes can be compared (where N can be any number, such as four or more). All nodes can be connected together by design (e.g., by wafer-to-wafer bonding using directly connected relative test pads) so that if the test pads are bonded together, all nodes should be at the same voltage (e.g., should be at the voltage of conductive path 938). If one or more nodes are not at the same voltage, this indicates poor conductivity, which in turn indicates that one or more pairs of test pads are misaligned. Therefore, the output 1124 can provide a logic low signal when all nodes are at the same level, and can provide a high logic signal when one or more nodes are at different levels.

[0105] A connectivity detection circuit (eg, connectivity detection circuits 1000, 1020, 1100, 1120 above) may be implemented in a workpiece, such as Fig. 12A , which shows a connectivity detection circuit 1200 located in the workpiece 600 (e.g., formed by CMOS logic components in an active layer in the workpiece 600). Although in this example, the connectivity detection circuit 1200 is formed directly below the corresponding test pads 363a to 363b, it should be understood that the location of the connectivity detection circuit is not limited to such a location.

[0106] Fig. 12BAnother illustration of the location of the connectivity detection circuit 1200 relative to the test pads 363a to 363d in a portion of the workpiece 600 is shown. In this example, the connectivity detection circuit 1200 is coupled to the test pads 363a to 363d through a conductive path so that the distribution of the test pads is not limited to the area above the connectivity detection circuit. For example, the test pads can be distributed at different locations around the die, where each die in the wafer has a certain test pad pattern to test alignment on a die-by-die basis.

[0107] Although the above examples show connectivity detection circuitry located on the chip, at least some portions of the connectivity detection circuitry may be formed off-chip. Fig. 7A After the process shown, some wafer-level testing (ie, testing before the combined wafer is diced into individual dies) may be performed on the combined workpiece (eg, combined workpiece 700). Fig.13A Examples of certain connectivity detection circuit components 1300 formed on a chip (eg, in workpiece 600 ) and usable with off-chip components (eg, external test equipment) to detect connectivity between node A and node B are shown. Fig.13A Node A is shown connected to a current sink 1304, which in this example is a ground connection, via a switch 1302 (shown as a transistor). Switch 1302 is controlled by an input 1306 (e.g., by a voltage applied to the gate of the transistor) to selectively connect node A to current sink 1304. Node B is connected to an exposed pad 1310 (a voltage monitoring pad, “VMON pad”). Exposed pad 1310 may be a pad formed on workpiece 600 that is exposed after wafer-to-wafer bonding and can be probed during testing (e.g., similar to exposed pad 720 exposed through opening 722). When a suitable external device is connected to exposed pad 1310, the external device in conjunction with component 1300 can detect connectivity between node A and node B and thereby determine alignment / misalignment of at least a portion of the combined workpiece. Examples of alignment / misalignment using an external device are described in detail below. FIG. 13B to FIG. 13D Shown in.

[0108] Fig. 13B An example is shown in which test pads 936a and 936c of workpiece 600 (control circuit workpiece) are coupled to exposed pads 1320a, 1320c, while test pads 936b and 936d are coupled to on-chip components 1322. Area 1324 including exposed pads 1320a, 1320c is designed to align with openings in the corresponding workpiece during wafer-to-wafer bonding, so that exposed pads 1320a, 1320c remain exposed after wafer-to-wafer bonding and can be used for wafer-level testing. On-chip components 1322 may include, for example, current sinks (e.g., Fig.13A The switch 1302 and the current sink 1304) or the voltage source (for example, to provide a predetermined voltage to the test pads 936b, 936d) are connected.

[0109] Fig. 13C The feature structure of the workpiece 500 (array workpiece) is shown, and the workpiece includes test pads 930a to 930d and conductive paths 938 (in FIG. 9D to FIG. 9E 1320a, 1320c). Conductive path 1330 similarly connects test pads 930c and 930d, so that these test pads are similarly connected together. Opening 1334 extends through workpiece 500 so that after wafer-to-wafer bonding, pads on workpiece 600 such as exposed pads 1320a, 1320c remain exposed. Therefore, opening 1334 is designed to align with area 1324 of workpiece 600.

[0110] Fig.13D Testing after wafer-to-wafer bonding of workpieces 500, 600 is shown, wherein exposed pads 1320a, 1320c are exposed through openings 1334 in workpiece 500. Probes 1340a, 1340c coupled to external test equipment 1338 are placed in contact with exposed pads 1320a, 1320c. For example, where on-chip component 1322 is configured to sink current (e.g., current sink 1304), external test equipment 1338 may be configured to provide current to probes 1340a and 1340c and measure the current flowing (i.e., may include a current source and an ammeter coupled to the probes). If the current flowing through a given probe is less than a threshold current, this indicates poor electrical connectivity between the test pads. For example, if the current flowing through probe 1340a is less than a threshold current, this indicates poor connectivity between test pads 936a and 936b (which are coupled to current sinks in on-chip component 1322), thereby indicating that these test pads are misaligned with corresponding test pads 930a, 930b. In the case where on-chip component 1322 is configured to provide a predetermined voltage to test pads 936b, 936d, external test equipment can detect the voltage (e.g., using a method similar to that for FIG. 10A to FIG. 11B 600 ). It will be appreciated that where connectivity detection circuitry is provided on chip (e.g., in workpiece 600 ), an indication of alignment / misalignment may be provided to external test equipment via exposed pads as part of wafer level testing (e.g., a one-bit alignment / misalignment indicator may be provided for each die of the assembled workpiece).

[0111] One or more of the components shown above may be used in a variety of different ways according to the methods described herein. For example, Fig.14An example of a method is shown, the method including: aligning 1440 a major surface of an array workpiece including a memory array with an opposing major surface of a control circuit workpiece including a control circuit (e.g., aligning workpiece 500 with workpiece 600); joining active pads on the major surface of the array workpiece with active pads on the major surface of the control circuit workpiece to electrically couple the memory array and the control circuit 1442 (e.g., joining active pads 508a to 508d and 608a to 608d to couple word lines, bit lines, etc.); and joining 1444 test pads on the major surface of the array workpiece with test pads on the major surface of the control circuit workpiece (e.g., joining test pads 930a to 930d and 936a to 936d). The method also includes detecting electrical connectivity between test pads on a major surface of the control circuit workpiece to identify misalignment 1446 of test pads on a major surface of the array workpiece with test pads on a major surface of the control circuit workpiece (e.g., using circuitry as shown in one or more of the above examples to detect electrical connectivity between test pads 936a, 936b).

[0112] The electrical connectivity test can indicate alignment / misalignment, which can be used to determine which further steps to perform on the assembled workpiece, for example, whether the assembled workpiece should be scrapped (if misaligned) or whether the workpiece should undergo further testing and / or processing (if aligned). Thus, the electrical connectivity test can serve as a quick test that quickly indicates a problem and avoids extensive testing when misalignment occurs.

[0113] Fig.15 An example of the results of using electrical connectivity detection is shown, including: after detecting electrical connectivity, in response to determining that the test pads are aligned, determining whether the test pads are aligned based on the results of detecting electrical conductivity 1550; performing additional testing of the array workpiece and the control circuit workpiece 1552 (for example, continuing with a large number of wafer-level tests); and in response to determining that the test pads are misaligned, discarding the array workpiece and the control circuit workpiece (for example, discarding the combined wafer or any combined die that has misalignment).

[0114] Fig.16 A method is shown, the method comprising: detecting electrical connectivity 1660 (eg, as described in any of the examples above); and after detecting electrical connectivity, determining whether a test pad is aligned 1662 based on a result of detecting electrical conductivity. Fig.16It is shown that, in response to determining the test pad alignment 1664, additional testing of the array workpiece and the control circuit workpiece is performed 1666, and the array workpiece and the control circuit workpiece are then diced into a plurality of dies, each die including a memory array and a control circuit 1668. For example, wafer-level testing may be performed to test the functionality of the circuits including the memory array and the control circuit, and if those results are successful, the wafer may be diced into individual dies, which may then be further processed (e.g., packaged, subjected to die-level testing, configured / initialized, incorporated into a larger assembly, etc.). Fig.16 It is also shown that in response to determining that the test pads are misaligned 1664, the array workpiece and the control circuit workpiece are discarded 1670 (i.e., the combined wafer or one or more combined dies of the combined wafer are scrapped), and one or more parameters of the alignment and bonding process applied to the additional array workpiece and the additional control circuit workpiece are modified 1672. Therefore, in some cases, feedback can be provided based on the results of the electrical connectivity test to improve the alignment and bonding of the wafers. Such feedback can be provided quickly so that problems can be resolved before a large number of production wafers are scrapped. The electrical connectivity test according to any of the above examples can be implemented shortly or immediately after wafer-to-wafer bonding, so that any problems can be quickly identified and corrected.

[0115] An example of an apparatus includes: a first workpiece, the first workpiece including a first active pad, a first test pad, and a second test pad located on a main surface of the first workpiece, the first test pad being electrically connected to the second test pad; a second workpiece, the second workpiece including a second active pad, a third test pad, and a fourth test pad located on a main surface of the second workpiece, the first workpiece and the second workpiece being joined along an interface between the main surface of the first workpiece and the main surface of the second workpiece to join the first active pad to the second active pad, the first test pad to the third test pad, and the second test pad to the fourth test pad; and a connectivity detection circuit, the connectivity detection circuit being used to test the electrical connectivity between the third test pad and the fourth test pad.

[0116] In one example, the connectivity detection circuit is located in the second workpiece. In one example, the connectivity detection circuit includes a comparator to compare the voltage at the fourth test pad with a reference voltage. In one example, the connectivity detection circuit also includes a multiplexer to selectively couple the third test pad and the fourth test pad, thereby comparing the voltage at the third test pad and the fourth test pad with the reference voltage. In one example, the connectivity detection circuit includes an exclusive OR (XOR) circuit coupled to the second test pad and the third test pad. In one example, the third test pad is connected to a current sink, the fourth test pad is connected to an exposed pad, and the connectivity detection circuit includes a current source and an ammeter coupled to the exposed pad. In one example, the first workpiece is an array workpiece including a memory array, and the second workpiece is a control circuit workpiece including a control circuit. In one example, the first active pad is connected to a bit line and a word line in the memory array, and the second active pad is connected to a read / write circuit and a row decoder circuit in the control circuit workpiece. In one example, the memory array is a 3D non-volatile memory array monolithically formed in one or more physical levels having an array of memory cells in an active region disposed above a silicon substrate. In one example, the first workpiece includes an additional test pad in addition to the first test pad and the second test pad, the second workpiece includes a corresponding additional test pad in addition to the third test pad and the fourth test pad, and the connectivity detection circuit is configured to test the electrical connectivity of the joint between the additional test pad and the corresponding additional test pad.

[0117] An example of a method includes: aligning a major surface of an array workpiece including a memory array with an opposite major surface of a control circuit workpiece including a control circuit; joining active pads on the major surface of the array workpiece with active pads on the major surface of the control circuit workpiece to electrically couple the memory array and the control circuit; joining test pads on the major surface of the array workpiece with test pads on the major surface of the control circuit workpiece; and detecting electrical connectivity between the test pads on the major surface of the control circuit workpiece to identify misalignment of the test pads on the major surface of the array workpiece with the test pads on the major surface of the control circuit workpiece.

[0118] In one example, the method further includes: after detecting electrical connectivity, determining whether the test pads are aligned according to the result of detecting the electrical conductivity; in response to determining that the test pads are aligned, performing additional tests of the array workpiece and the control circuit workpiece; and in response to determining that the test pads are misaligned, discarding the array workpiece and the control circuit workpiece. In one example, the method further includes, in response to determining that the test pads are aligned, subsequently cutting the array workpiece and the control circuit workpiece into a plurality of dies, each of which includes a memory array and a control circuit. In one example, the method further includes, in response to determining that the test pads are misaligned, modifying one or more parameters of the alignment and bonding process applied to the additional array workpiece and the additional control circuit workpiece. In one example, detecting electrical connectivity between the test pads on the main surface of the control circuit workpiece to identify misalignment includes determining electrical connectivity by a connectivity detection circuit located on the control circuit workpiece. In one example, detecting electrical connectivity between the test pads on the main surface of the control circuit workpiece includes comparing a voltage from one or more test pads on the main surface of the control circuit workpiece with another voltage from another test pad on the main surface of the control circuit workpiece or with a reference voltage. In one example, detecting electrical connectivity between test pads on a major surface of a control circuit workpiece to identify misalignment includes coupling a connectivity detection circuit to one or more exposed pads on the control circuit workpiece.

[0119] An example of a nonvolatile memory device includes: an array workpiece including an array of nonvolatile memory cells; a control circuit workpiece including a control circuit, the control circuit workpiece wafer-to-wafer bonded to the array workpiece so that the control circuit is electrically coupled to the nonvolatile memory cell array; and a device for detecting electrical connectivity between pads on the control circuit workpiece and pads on the array workpiece to identify misalignment between the array workpiece and the control circuit workpiece.

[0120] In one example, the means for detecting electrical connectivity is located in the control circuit workpiece and includes means for comparing a voltage from a first pad on the control circuit workpiece with a voltage from a second pad on the control circuit workpiece or a reference voltage. In one example, the means for detecting electrical connectivity is coupled to pads on the control circuit workpiece through one or more exposed pads on the control circuit workpiece.

[0121] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0122] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0123] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0124] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0125] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0126] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A storage device, comprising: a first workpiece, the first workpiece comprising a first active pad, a first test pad, and a second test pad located on a major surface of the first workpiece, the first test pad being electrically connected to the second test pad via a conductive path in the first workpiece; a second workpiece, the second workpiece comprising a second active pad, a third test pad, and a fourth test pad located on a main surface of the second workpiece, the first workpiece and the second workpiece being joined along an interface between the main surface of the first workpiece and the main surface of the second workpiece to join the first active pad with the second active pad, to join the first test pad with the third test pad, and to join the second test pad with the fourth test pad; and A connectivity detection circuit in the second workpiece, the connectivity detection circuit is configured to test the electrical connectivity between the third test pad and the fourth test pad, the connectivity detection circuit includes an XOR circuit coupled to the fourth test pad and the third test pad to compare the voltage at the fourth test pad with the voltage at the third test pad. 2 . The memory device of claim 1 , wherein the connectivity detection circuit is formed by CMOS logic components in an active layer in the second workpiece. 3 . The storage device of claim 1 , wherein the first workpiece is a first silicon wafer, and the second workpiece is a second silicon wafer. 4 . The memory device of claim 3 , wherein the first silicon wafer includes a plurality of memory dies formed by a first manufacturing process, and the second silicon wafer includes a plurality of control circuit dies formed by a second manufacturing process. 5 . The memory device according to claim 1 , wherein the XOR circuit is coupled to more than four test pads of the second workpiece to compare voltages at the more than four test pads.

6. The storage device of claim 1, wherein the conductive paths in the first workpiece include passive components. 7 . The memory device according to claim 1 , wherein the first workpiece is an array workpiece including a memory array, and the second workpiece is a control circuit workpiece including a control circuit.

8. The memory device of claim 7, wherein the first active pad is connected to a bit line and a word line in the memory array, and the second active pad is connected to a read / write circuit and a row decoder circuit in the control circuit workpiece.

9. The memory device of claim 7, wherein the memory array is a 3D nonvolatile memory array monolithically formed in one or more physical levels of a memory cell array having an active region disposed above a silicon substrate.

10. The storage device of claim 1, wherein the first workpiece includes additional test pads in addition to the first test pad and the second test pad, the second workpiece includes corresponding additional test pads in addition to the third test pad and the fourth test pad, and the connectivity detection circuit is configured to test the electrical connectivity of the joint between the additional test pad and the corresponding additional test pad.

11. A method of operating a storage device, comprising: aligning a major surface of an array workpiece including a memory array with an opposing major surface of a control circuit workpiece including control circuits; bonding active pads on the major surface of the array workpiece to active pads on the major surface of the control circuit workpiece to electrically couple the memory array and the control circuit; bonding the test pads on the major surface of the array workpiece to the test pads on the major surface of the control circuit workpiece, the test pads on the major surface of the array workpiece being electrically connected together through one or more conductive paths in the array workpiece; and The electrical connectivity between the test pads on the main surface of the control circuit workpiece is then detected by a connectivity detection circuit located in the control circuit workpiece, including performing an XOR operation on the voltages at the test pads on the main surface of the control circuit to determine whether there is a difference between the voltages at the test pads to identify misalignment between the test pads on the main surface of the array workpiece and the test pads on the main surface of the control circuit workpiece.

12. The method according to claim 11, further comprising: After detecting the electrical connectivity, determining whether the test pads are aligned according to the result of detecting the electrical conductivity; In response to determining the test pad alignment, performing additional testing of the array workpiece and the control circuit workpiece; and In response to determining that the test pads are misaligned, the array workpiece and the control circuit workpiece are discarded.

13. The method of claim 12, further comprising, in response to determining the test pad alignment, subsequently dicing the array workpiece and the control circuit workpiece into a plurality of dies, each die comprising a memory array and a control circuit.

14. The method of claim 12, further comprising modifying one or more parameters of alignment and bonding processes applied to additional array workpieces and additional control circuit workpieces in response to determining that the test pads are misaligned.

15. The method of claim 11, wherein detecting electrical connectivity between the test pads on the major surface of the control circuit workpiece to identify misalignment comprises determining electrical connectivity through CMOS logic components in an active layer of the control circuit workpiece forming the connectivity detection circuit.

16. A method according to claim 15, wherein detecting the electrical connectivity between the test pads on the main surface of the control circuit workpiece includes comparing the voltage from one or more test pads on the main surface of the control circuit workpiece with another voltage from another test pad on the main surface of the control circuit workpiece or with a reference voltage.

17. A method according to claim 11, wherein detecting the electrical connectivity between the test pads on the main surface of the control circuit workpiece to identify misalignment includes performing the XOR operation on more than four voltages at more than four test pads on the main surface of the control circuit to determine whether there is a difference between the more than four voltages at the more than four test pads.

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