Conductive Interconnect and Method of Forming the Same

Abstract

The present disclosure relates to conductive interconnects and methods of forming conductive interconnects. Some embodiments include a method of forming an integrated assembly. An arrangement of conductive posts extending through an insulating block is formed. The upper surface of the conductive posts is recessed to form a cavity. An insulating liner is formed within the cavity to line a lateral outer perimeter of the cavity. The recessed surface of the conductive posts is exposed at a bottom of the lined cavity. A conductive wide region is formed over the insulating block. A portion of the conductive wide region extends into the cavity and is configured as an interconnect. The conductive wide region is patterned into a plurality of conductive structures. One of the conductive structures includes the interconnect.

Description

Technical Field

[0001] The present invention relates to integrated assemblies, memory arrays, conductive interconnects, and methods of forming conductive interconnects. Background Art

[0002] Memories are typically incorporated into integrated circuit systems. Memories can be used, for example, in computer systems for storing data.

[0003] Memories can be provided as large arrays of memory cells. Word lines (access lines) and bit lines (digit lines, sense lines) can be provided across the array such that individual memory cells can be uniquely addressed by a combination of a word line and a bit line.

[0004] Conductive interconnects can be used to electrically couple circuitry from a lower level to circuitry at an upper level; and in some embodiments, can be used to couple word lines to control circuitry (e.g., driver circuitry) and / or to couple bit lines to sense circuitry (e.g., sense amplifier circuitry).

[0005] An ongoing goal of integrated circuit fabrication is to increase the level of integration (i.e., scale circuitry to smaller dimensions). Word lines and bit lines can become increasingly compact on memory arrays with increased levels of integration.

[0006] Difficulties are encountered in increasing the level of integration of memories because it becomes increasingly difficult to make proper connections to word lines and bit lines. There is a desire to develop new conductive interconnects suitable for connecting to word lines and bit lines, as well as new methods of fabricating such interconnects. There may also be a desire for new conductive interconnects suitable for connecting to compact integrated circuit components other than word lines and bit lines.

[0007] Examples of difficulties encountered in electrically connecting to word lines and bit lines are described with reference to FIGS. 1 - 4.

[0008] Referring Figure 1A and 1B , assembly 300 includes an electrical interconnect 302 extending through an insulating block 304. The electrical interconnect couples a lower conductive structure 306 to an upper conductive structure 308b. The upper conductive structure 308b is shown as one of a plurality of similar conductive lines 308 (other conductive lines are labeled 308a and 308c). The conductive line 308 can be a word line or a bit line.

[0009] The electrical interconnect 302 is shown as including a conductive lining 310 that laterally surrounds a conductive core 312. The lining 310 can include a metal nitride (e.g., titanium nitride or tungsten nitride), and the conductive core 312 can include a metal (e.g., tungsten). The lining 310 can be provided to enhance adhesion of the metal for the conductive core 312 and / or to provide a seed layer during deposition / growth of the metal for the conductive core 312.

[0010] Figure 1A and 1B illustrate a desired arrangement in which only center line 308b is electrically coupled to interconnect 302. However, as integration levels increase, problems can arise that cause one or both of conductive lines 308a and 308c to short to interconnect 302. For example, Figure 2A and 2B illustrate assembly 300 in a problematic arrangement in which line 308c is shorted to interconnect 302 (such a short occurs in Figure 2B the illustrated region 314 shown). The short can be caused by misalignment of line 308c (as shown) and / or by misalignment of interconnect 302.

[0011] It is desirable to reduce or prevent the intractable shorting problems referred to in reference Figure 2A and 2B described.

[0012] There may need to be a significant overlap between conductive line 308b and core 312, such that the resistance can be reduced compared to a configuration in which the overlap is primarily with liner 310 rather than core 312. Figure 3 A top view of interconnect 302 in a desired arrangement is shown, where core 312 is a substantial majority of the upper surface of interconnect 302. Figure 3 The arrangement of Figure 1A provides an opportunity for significant overlap (shown in Figure 4 ) between core 312 and conductive line 308b. However, in practice, 312 can have significantly different configurations, as shown in Figure 4 . Specifically, the core can end up being a narrow region along the upper surface of interconnect 302. This can reduce the desired overlap between core 312 and conductive line 308b, creating a problematic resistance. Also,

[0013] It is desirable to develop an improved architecture in which the contact between a conductive line (e.g., 308b) and the underlying interconnect (e.g., 302) is consistent across an integrated arrangement and has a desired low resistance. SUMMARY OF THE INVENTION

[0014] One embodiment of the present disclosure provides a method of forming an integrated assembly, which includes: forming an arrangement including conductive posts extending through an insulating block; recessing an upper surface of the conductive posts to form a cavity; forming an insulating liner in the cavity to line a lateral perimeter of an exterior of the cavity, a recessed surface of the conductive posts being exposed at a bottom of the lined cavity; forming a conductive wide region over the insulating block, a portion of the conductive wide region extending into the cavity and configured as a vertically extending interconnect; and patterning the conductive wide region into a plurality of conductive structures; one of the conductive structures including the vertically extending interconnect.

[0015] Another embodiment of the present disclosure provides a method of forming an integrated assembly, which includes: forming an opening extending through an insulating block to reach an upper surface of a first conductive structure; forming a conductive plug in the opening in electrical contact with the upper surface of the first conductive structure; a substantially planar surface extending across the insulating block and the conductive plug; recessing the conductive plug to form a cavity over a remaining portion of the conductive plug; forming an insulating spacer in the cavity to narrow the cavity, an upper surface of the conductive plug being exposed at a bottom of the narrowed cavity; forming a conductive wide region over the insulating block, a portion of the conductive wide region extending into the cavity and configured as a vertically extending interconnect; and patterning the conductive wide region into a plurality of second conductive structures; one of the second conductive structures including the vertically extending interconnect and being electrically coupled to the first conductive structure through the conductive plug and the vertically extending interconnect.

[0016] Yet another embodiment of the present disclosure provides a method of forming an integrated assembly, which includes: forming an opening extending through an insulating block to reach an upper surface of a first conductive structure; forming a lining material in the opening to line sidewalls of the opening; forming a core material in the opening and along the lined sidewalls of the opening; forming a substantially planar surface extending across the insulating block, the lining material, and the core material; recessing at least a portion of the core material and the lining material to form a cavity over a remaining portion of the core material; forming an insulating spacer in the cavity to narrow the cavity, an upper surface of the core material being exposed at a bottom of the narrowed cavity; forming a conductive wide region over the insulating block, a portion of the conductive wide region extending into the cavity and configured as a vertically extending interconnect; and patterning the conductive wide region into a plurality of second conductive structures; one of the second conductive structures including the vertically extending interconnect and being electrically coupled to the first conductive structure through the core material and the vertically extending interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A and 1BIs a schematic cross-sectional side view and a schematic top view of a region of an existing technology integrated assembly. Figure 1A The view of Figure 1B is along line A-A of

[0018] Figure 2A and 2B Is a schematic cross-sectional side view and a schematic top view of a region of another existing technology integrated assembly. Figure 2A The view of Figure 2B is along line A-A of

[0019] Figure 3 and 4 Is a schematic top view of a region of an existing technology integrated assembly.

[0020] Figures 5 - 9 Is a schematic cross-sectional side view of a region of an integrated assembly at a sequential processing stage of an example method.

[0021] Figure 9A Is Figure 9 A schematic top view of a region of the integrated assembly of Figure 9 The view of Figure 9A is along line A-A of

[0022] Figures 10 - 12 Is a schematic cross-sectional side view of a region of an integrated assembly at a sequential processing stage of an example method. Figure 10 The processing stage of Figure 9 can be after the processing stage of

[0023] Figure 12A Is Figure 12 A schematic top view of a region of the integrated assembly of Figure 12 The view of Figure 12A is along line A-A of

[0024] Figure 13 and 14 Is a schematic cross-sectional side view of a region of an integrated assembly at a sequential processing stage of an example method. Figure 13 The processing stage of Figure 12 can be after the processing stage of

[0025] Figure 14A Is Figure 14 A schematic top view of a region of the integrated assembly of Figure 14 The view of Figure 14A is along line A-A of

[0026] Figures 15 - 17 Is a schematic cross-sectional side view of a region of an integrated assembly at a sequential processing stage of an example method. Figure 15 The processing stage ofFigure 9 after the processing stage of

[0027] Figure 17A is Figure 17 a schematic top view of a region of an integrated assembly of Figure 17 The view of Figure 17A is along line A-A of

[0028] Figures 18 - 20 is a schematic cross-sectional side view of a region of an integrated assembly at sequential processing stages of an example method. Figure 18 The processing stage of Figure 9 can be after the processing stage of

[0029] Figure 20A is Figure 20 a schematic top view of a region of an integrated assembly of Figure 20 The view of Figure 20A is along line A-A of

[0030] Figure 21 is a schematic view of a region of an example memory array. DETAILED DESCRIPTION

[0031] Some embodiments include methods of forming conductive interconnects. The conductive interconnects can be used, for example, to couple conductive lines (e.g., word lines, digit lines, etc.) to underlying logic circuitry (e.g., word line driver circuitry, sense amplifier circuitry, etc.). Refer to Figures 5 - 21 for a description of example embodiments.

[0032] Refer to Figure 5 , the assembly 10 includes an insulating block 12 over a conductive structure 14.

[0033] The insulating block 12 includes an insulating material 16. Such insulating materials can include any suitable composition; and in some embodiments, can include silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, etc., consisting primarily of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, etc., or made of silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, etc.

[0034] The conductive structure 14 includes a conductive material 18. The material 18 can include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the material 18 can include one or more of copper (Cu), silver (Ag), aluminum (Al), tungsten (W), platinum (Pt), palladium (Pd), conductively doped silicon, metal nitride, metal silicide, etc.

[0035] The conductive structure 14 may be referred to as a first conductive structure that differentiates it from other conductive structures formed in subsequent processing stages.

[0036] The conductive structure 14 may be electrically coupled to a logic circuit system (not shown); the logic circuit system may be, for example, one or both of a word line driver circuit system and a sense amplifier circuit system. The logic circuit system may include CMOS and may be located below the conductive structure 14. In some embodiments, the conductive structure 14 may be supported by a substrate (not shown), and the logic circuit system may be located above such a substrate and below the conductive structure 14.

[0037] The substrate may include a semiconductor material; and may include, for example, single crystal silicon, consist essentially of single crystal silicon, or consist of single crystal silicon. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any structure that includes a semiconductor material, including but not limited to bulk semiconductor materials, such as semiconductor wafers (alone or in assemblies that include other materials), and semiconductor material layers (alone or in assemblies that include other materials). The term "substrate" refers to any support structure, including but not limited to the semiconductor substrates described above. In some applications, the substrate may correspond to a semiconductor substrate that contains one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0038] Reference Figure 6 , an opening 20 is formed that extends through the insulating block 12 to reach the upper surface 15 of the conductive structure 14. The opening 20 has sidewalls 21. The sidewalls 21 are shown as being slightly tapered. In other embodiments, the sidewalls 21 may be more tapered, less tapered, or even non-tapered. Also, although the sidewalls are shown as being vertical, in other embodiments, at least some regions of the sidewalls may be curved.

[0039] In the illustrated embodiment, the opening 20 stops at the top surface 15 of the conductive structure 14. In other embodiments, the opening 20 may penetrate into the conductive structure 14.

[0040] Reference Figure 7 , a conductive lining material 22 is formed over the block 12 and within the opening 20. The lining material 22 lines the sidewalls 21 of the opening 20.

[0041] The lining material 22 may include any suitable composition. For example, the lining material 22 may include one or more of metal nitrides, metal silicides, and metal carbides, consist primarily of one or more of metal nitrides, metal silicides, and metal carbides, or consist of one or more of metal nitrides, metal silicides, and metal carbides. In some embodiments, the lining material 22 may include one or both of tungsten nitride and titanium nitride.

[0042] Reference Figure 8 Within the opening 20 and along the lined sidewall 21, a conductive core material 24 is formed.

[0043] The conductive core material 24 can include any suitable conductive composition; for example, one or more of various metals (such as titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (such as metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (such as conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive core material 24 can include one or more metals, consist essentially of one or more metals, or consist of one or more metals. For example, the conductive core material 24 can include tungsten, consist essentially of tungsten, or consist of tungsten.

[0044] The lining material 22 can be used to enhance the adhesion of the core material 24 and / or can be used as a seed layer to promote the growth of the core material 24 during the deposition of such core materials.

[0045] In the illustrated embodiment, the lining material 22 is a single uniform composition, and the core material 24 is also a single uniform composition. In other embodiments, the lining material 22 can include a laminate of two or more different compositions, and / or the core material 24 can include a laminate of two or more different compositions.

[0046] Reference Figure 9 , the assembly 10 undergoes planarization (e.g., chemical mechanical polishing, CMP) to form a generally planar surface 25 that extends across the insulating block 12, the lining material 22, and the core material 24. The surface 25 is referred to as "generally planar" to indicate that the surface is planar within reasonable fabrication and measurement tolerances.

[0047] The formation of the generally planar surface 25 removes excess materials 22 and 24 above the insulating block 12, patterns the remaining lining material 22 into a conductive lining 26 within the opening 20, and patterns the remaining core material 24 into a conductive core structure (conductive plug) 28 within the opening. As Figure 9A shown in the top view of

[0048] The lining 26 laterally surrounds the outer peripheral surface (outer perimeter) 27 of the core structure 28. Figure 9 The lining 26 and the core structure 28 together form a structure (conductive pillar) 30. Such a structure has a width (horizontal dimension) W 1 along the cross-section of

[0049] Such a width can be in the range of, for example, from about 10 nanometers (nm) to about 50 nm.

[0050] The conductive post 30 can be regarded as including a liner 26 to serve as an upwardly open conductive container 29, and including a conductive plug 28 within such an upwardly open conductive container. The conductive plug 28 is electrically coupled to the conductive structure 14 through the conductive material 22 of the conductive container 29.

[0051] Reference Figure 10 , the upper surface of the conductive post 30 is recessed to form a cavity 40. The recessed upper surface 42 of the conductive post 30 is along the bottom of the cavity 40. In the illustrated embodiment, the liner 26 is also etched during the formation of the cavity 40.

[0052] The cavity 40 can be formed by any suitable etching. In some embodiments, the core material 24 includes tungsten, and the liner material 22 includes one or both of titanium nitride and tungsten nitride. In such embodiments, the etching used to form the cavity 40 can be wet etching using an ammonia-containing etchant. Alternatively, the etching can be dry etching using one or more of CF, BCl, and O; where the chemical formula indicates the main components rather than a specific stoichiometry.

[0053] The cavity 40 can be formed to any suitable depth D, and in some embodiments, such a depth can include dimensions in the range from about 5% to about 40% of the original height H shown in Figure 9 . Alternatively, Figure 9 the height H can be regarded as the first vertical dimension, and the post 30 can be regarded as having a second vertical dimension V to the recessed upper surface 42 at the Figure 10 processing stage of 1 ; where such a second vertical dimension is in the range from about 60% to about 95% of the first vertical dimension.

[0054] In some embodiments, the cavity 40 can be regarded as removing a part of the conductive plug 28 (core material 24) to leave a remaining part of the conductive plug 28 (core material 24) below the cavity 40.

[0055] The recessed surface 42 has a lateral dimension (width) W along the Figure 10 cross-section of 2 . In some embodiments, the width W 2 can be in the range from about 8 nm to about 40 nm. In some embodiments, at the Figure 9 processing stage of 1 , the width W of the upper surface of the conductive post 30 Figure 10 can be referred to as the first width, and at the 2 processing stage of

[0056] Reference Figure 11, a layer 44 of insulating material 46 is formed above the insulating block 12 and within the cavity 40. The insulating material 46 can include any suitable composition. In some embodiments, the insulating material 46 can include one or more oxides (e.g., aluminum oxide, hafnium oxide, zirconium oxide, silicon dioxide, etc.), consist essentially of one or more oxides (e.g., aluminum oxide, hafnium oxide, zirconium oxide, silicon dioxide, etc.), or consist of one or more oxides (e.g., aluminum oxide, hafnium oxide, zirconium oxide, silicon dioxide, etc.). In some embodiments, the insulating material 46 can include one or both of silicon dioxide and silicon nitride, consist essentially of one or both of silicon dioxide and silicon nitride, or consist of one or both of silicon dioxide and silicon nitride.

[0057] Any suitable method can be utilized to deposit the insulating material 46. In some embodiments, one or both of atomic layer deposition (ALD) and chemical vapor deposition (CVD) can be utilized to deposit the insulating material 46 to achieve a desired conformal lining of the material 46 along the peripheral surface of the cavity 40. In some embodiments, the insulating material 46 can include silicon dioxide initially deposited by CVD using tetraethyl orthosilicate (TEOS).

[0058] The material 46 can have any suitable thickness T. In some embodiments, such thickness can be in the range of about 2 nm to about 20 nm.

[0059] Reference Figure 12 , anisotropically etching the material 46 is to pattern such material into spacers (liner rings) 48 within the cavity 40. The spacers line the outer lateral perimeter of the cavity 40. A region 50 of the recessed surface 42 is exposed at the bottom of the lined cavity. In some embodiments, the spacer 48 can be regarded as narrowing the cavity 40, and the region 50 can be regarded as the portion of the upper surface of the plug 28 that is exposed at the bottom of the narrowed cavity.

[0060] The material 46 can be anisotropically etched by any suitable process. In some embodiments, the material 46 can include silicon dioxide and can be dry etched using one or more of Cf, BCl, and O, where the chemical formula indicates the main components rather than a specific stoichiometry.

[0061] Figure 12A Shown Figure 12 is a top view of the assembly 10 at a processing stage. The spacer (liner ring) 48 is shown laterally surrounding the exposed region 50 of the plug 28. In the illustrated embodiment, a portion of the liner 26 remains exposed along the outer peripheral surface of the spacer 46. In other words, the region of the liner material 22 is not covered by the insulating spacer 48.

[0062] Reference Figure 13, a conductive wide region 52 is formed above the insulating block 12. A portion of the conductive wide region extends into the cavity 40. Such a portion is configured as a vertically extending interconnect 54. In the illustrated embodiment, the bottom surface 55 of the vertically extending interconnect 54 directly abuts the upper surface 42 of the conductive plug 28.

[0063] The lowermost portion of the vertically extending interconnect 54 (i.e., the portion directly abutting the upper surface 42 of the plug 28) has a horizontal dimension (width) W along Figure 13 the cross-section of 3 . In some embodiments, such width can be in the range from about 5 nm to about 20 nm.

[0064] The wide region 52 includes a conductive material 56. Such a conductive material can include any suitable conductive composition; for example, one or more of various metals (such as titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (such as metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (such as conductively doped silicon, conductively doped germanium, etc.).

[0065] Referring to Figure 14 , the conductive wide region 52 is patterned into conductive structures 58. The illustrated conductive structures are labeled 58a, 58b, and 58c such that they can be distinguished from each other.

[0066] The central conductive structure 58b includes the vertically extending interconnect 54. In some embodiments, the conductive structure 58b can be referred to as the second conductive structure. Such a second conductive structure is electrically coupled to the first conductive structure 14 through the connection including the conductive plug 28 (core material 24) and the vertically extending interconnect 54.

[0067] The conductive structure 58b has a width (horizontal dimension) W along Figure 14 the cross-section of 4 . Such a width can be, for example, greater than or equal to about 30 nm.

[0068] Figure 14The column 30 can be regarded as corresponding to the conductive interconnect 60, and the structure 58 can be regarded as corresponding to a word line or a bit line. The conductive interconnect 60 can be used to couple the structure 58b to the logic circuitry 62. In the illustrated embodiment, such logic circuitry is below the structure 58 and can be below the memory array including the structure 58. In other embodiments, at least some of the logic circuitry 62 can be in other orientations; for example, laterally outside the memory array, above the memory array, etc. The logic circuitry 62 can include CMOS. In some embodiments, the structure 58 can correspond to a bit line, and the logic circuitry 62 can include sense amplifier circuitry coupled to such bit lines. In some embodiments, the structure 58 can correspond to a word line, and the logic circuitry 62 can include word line driver circuitry coupled to such word lines.

[0069] The logic circuitry 62 is shown to be supported by a substrate 64. The substrate 64 can correspond to a semiconductor substrate and, in some embodiments, can include single crystal silicon.

[0070] A gap is provided between the substrate 64 and the conductive structure 14 to indicate that other materials and / or components can be provided between the substrate 64 and the conductive structure 14.

[0071] Figure 14 The configuration of advantageously couples the component 58b to the conductive plug 28 (core material 24) through the vertically extending interconnect 54. The interconnect 54 can represent a large number of substantially identical interconnects formed across the assembly; where the term "substantially identical" means identical within reasonable fabrication and measurement tolerances. The interface 61 between the interconnect 54 and the core material 24 can have a desired low resistance provided that the materials 56 and 24 are compatible to achieve such a low resistance. In some embodiments, the compositions of the materials 24 and 56 can be the same as each other (e.g., both can include tungsten). The interface 61 can represent a large number of substantially identical interfaces formed across the assembly 10. The interfaces 61 of the assembly 10 can be fabricated with high uniformity such that the resistance across all interfaces is substantially the same, which can improve the performance of the devices formed according to the embodiments described herein relative to conventional devices.

[0072] Figure 14A Shown Figure 14 A top view of the assembly 10 is shown. The structure 58 is shown as a line (e.g., a word line, a bit line, etc.) extending across the region of the assembly. The line 58b is above the interconnect 54 (where such interconnects are shown in a dashed view in Figure 14A to indicate that it is below most of the line 58b).

[0073] The conductive material 22 of the liner 26 surrounds the perimeter of the insulating spacer 48. This can be suitable for some embodiments. In other embodiments, the exposed liner 26 can be problematic because in the presence of the above reference Figure 2BIn the case of misalignment of the type described, it may be shorted to an adjacent line (58a or 58c). In some embodiments, the exposed area of the lining material 22 may be eliminated by forming a spacer 48 that extends over the entire lining material 22. Refer to Figures 15 - 17 for examples describing such embodiments.

[0074] Refer to Figure 15 , which shows the assembly 10 at a processing stage after the processing stage of Figure 9 . Figure 15 The processing stage of Figure 10 is similar to the processing stage of Figure 15 , except that the lining material 22 is recessed more completely in the processing stage of

[0075] Refer to Figure 16 , and a spacer (liner) 48 is formed by a process similar to the process described above with reference to Figure 11 and 12 . The spacer 48 is above the recessed upper surface 27 of the lining 26. Thus, the lining 26 is not exposed along the top of the assembly 10.

[0076] Refer to Figure 17 , and a conductive structure 58 is formed by a process similar to the process described above with reference to Figure 13 and 14 . Figure 17A Shows Figure 17 a top view of the assembly 10 of Figure 17A . The assembly of Figure 14A is similar to the assembly of Figure 17A , except that the upper surface of the lining 26 is not exposed in the processing stage of

[0077] Figures 18 - 20 This can reduce the problem of shorting that exists in the case of one or more inadvertent misalignments in the structures 58a - c. Figures 15 - 17 Show a process similar to the process of Figure 18 , except that in the processing stage of Figure 20A , the lining material 22 is completely recessed (i.e., the lining material 22 and the core material 24 are recessed to approximately the same level). Figure 20 Shows Figure 20A a top view of the assembly 10 of Figure 17A .

[0078] Figure 10 and 15 show that the recess of the lining material 22 is less than the recess of the core material 24, and Figure 18The embodiment shows the liner material 22 recessed to approximately the same extent as the core material 24. In other embodiments (not shown), the recess of the liner material 22 may be greater than the recess of the core material 24.

[0079] In some embodiments, the structures 58a-c may be word lines or bit lines extending across the memory array. Refer to Figure 21 Describe the example memory array 70. The memory array includes digit lines (bit lines) DL1-DL4 extending along the columns of the array, and includes word lines WL1-WL4 extending along the rows of the array. Memory cells 68 are addressed by the word lines and digit lines; where each memory cell is uniquely addressed by a combination including one of the word lines and one of the digit lines. The memory cells may be dynamic random access memory (DRAM) cells or any other suitable memory cells. If the memory cells are DRAM cells, then each of the memory cells may include a transistor and a capacitor, or may include any other suitable combination of transistors and capacitors. Figure 21 The memory array of may be regarded as generally representing any suitable memory array, including for example a three-dimensional cross-point memory array.

[0080] The word line (e.g., WL1) is shown coupled to a word line driver circuit system (indicated as word line driver), and the digit line (e.g., DL1) is shown coupled to a sense amplifier circuit system (indicated as sense amplifier). The word line driver circuit system and the sense amplifier circuit system may be in Figure 14 , 17 and the logic circuit system 62 of 20. At least some portions of the word line driver circuit system and / or at least some portions of the sense amplifier circuit system may be directly below the memory cells 68 of the memory array 70.

[0081] The assemblies and structures discussed above may be used within an integrated circuit (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into an electronic system. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any one of a wide range of systems: such as cameras, wireless devices, displays, chip sets, set-top boxes, games, lighting, transportation vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, airplanes, etc.

[0082] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method known now or to be developed, the methods including for example atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0083] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. The terms are considered synonymous in this disclosure. In some cases the term "dielectric" and in other cases the term "insulating" (or "electrically insulating") can be used within this disclosure to provide a variation in language to simplify the underlying basis within the following claims, rather than to indicate any significant chemical or electrical differences.

[0084] The terms "electrically connected" and "electrically coupled" can both be used in this disclosure. The terms are considered synonymous. In some instances one term is utilized and in other instances the other term may be used to provide a variation in language within this disclosure to simplify the underlying basis within the appended claims.

[0085] The specific orientation of the various embodiments in the figures is for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims pertain to any structure having the described relationships between the various features, whether the structure is in the specific orientation of the respective figures or rotated relative to such orientation.

[0086] Unless otherwise specified, the cross-sectional views in the accompanying description show only the features within the cross-sectional plane and not the material behind the cross-sectional plane, in order to simplify the figures.

[0087] When a structure is referred to as being "on another structure", "adjacent to another structure", or "against another structure", the structure may be directly on the other structure or there may also be an intervening structure. In contrast, when a structure is referred to as being "directly" "on" another structure, "directly adjacent", or "directly against" another structure, there is no intervening structure. The terms "directly below", "directly above", etc. do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate vertical alignment.

[0088] A structure (e.g., a layer, material, etc.) can be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying substrate (e.g., a wafer). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0089] Some embodiments include a method of forming an integrated assembly. An arrangement of conductive pillars extending through an insulating block is formed. The upper surfaces of the conductive pillars are recessed to form cavities. An insulating liner is formed within the cavities to line the outer lateral perimeter of the cavities. The recessed surfaces of the conductive pillars are exposed at the bottom of the lined cavities. A conductive wide region is formed above the insulating block. A portion of the conductive wide region extends into the cavities and is configured as a vertically extending interconnect. The conductive wide region is patterned into a plurality of conductive structures. One of the conductive structures includes the vertically extending interconnect.

[0090] Some embodiments include a method of forming an integrated assembly. An opening is formed that extends through an insulating block to reach an upper surface of a first conductive structure. A conductive plug is formed within the opening that is in electrical contact with the upper surface of the first conductive structure. A substantially planar surface extends across the insulating block and the conductive plug. The conductive plug is recessed to form a cavity above a remaining portion of the conductive plug. An insulating spacer is formed within the cavity to narrow the cavity. An upper surface of the conductive plug is exposed at a bottom of the narrowed cavity. A conductive wide region is formed above the insulating block. A portion of the conductive wide region extends into the cavity and is configured as a vertically extending interconnect. The conductive wide region is patterned into a plurality of second conductive structures. One of the second conductive structures includes the vertically extending interconnect and is electrically coupled to the first conductive structure through the conductive plug and the vertically extending interconnect.

[0091] Some embodiments include a method of forming an integrated assembly. An opening is formed that extends through an insulating block to reach an upper surface of a first conductive structure. A liner material is formed within the opening to line sidewalls of the opening. Core material is formed within the opening and along the lined sidewalls of the opening. A substantially planar surface extends across the insulating block, the liner material, and the core material. At least a portion of the core material and the liner material is recessed to form a cavity above a remaining portion of the core material. An insulating spacer is formed within the cavity to narrow the cavity. An upper surface of the core material is exposed at a bottom of the narrowed cavity. A conductive wide region is formed above the insulating block. A portion of the conductive wide region extends into the cavity and is configured as a vertically extending interconnect. The conductive wide region is patterned into a plurality of second conductive structures. One of the second conductive structures includes the vertically extending interconnect and is electrically coupled to the first conductive structure through the core material and the vertically extending interconnect.

[0092] As provided, the subject matter disclosed herein has been described in language that is more specific or less specific with respect to structural and method features. However, it is understood that the claims are not limited to the specific features shown and described, since the devices disclosed herein include example embodiments. Accordingly, the claims have the full scope as set forth in writing and should be properly interpreted according to the doctrine of equivalents.

Claims

1. A method of forming an integrated assembly, which comprises: forming an arrangement including a conductive lining and conductive posts extending through an insulating block; recessing upper surfaces of the conductive lining and the conductive posts to form a cavity, the recessing causing a portion of the conductive lining to extend in height above the upper surfaces of the conductive posts; forming an insulating liner in the cavity to line an outer lateral perimeter of the cavity, recessed surfaces of the conductive posts being exposed at a bottom of the lined cavity; forming a conductive wide region above the insulating block, a portion of the conductive wide region extending into the cavity and configured as a vertically extending interconnect; and patterning the conductive wide region into a plurality of conductive structures; one of the conductive structures including the vertically extending interconnect.

2. The method according to claim 1, wherein the vertically extending interconnect abuts directly against the recessed surface of the conductive post.

3. The method according to claim 1, wherein the recessed surface of the conductive post has a horizontal dimension in a range from 8 nm to 40 nm along a cross-section.

4. The method according to claim 3, wherein a lowermost portion of the vertically extending interconnect includes a horizontal dimension in a range from 5 nm to 20 nm along the cross-section.

5. The method according to claim 3, wherein an uppermost portion of the one conductive structure among the conductive structures includes a horizontal dimension greater than or equal to 30 nm along the cross-section.

6. The method according to claim 3, wherein the conductive post has a first vertical dimension along the cross-section before the recessing and a second vertical dimension to an upper surface of the recessing; and wherein the second vertical dimension is in a range from 60% to 95% of the first vertical dimension.

7. The method according to claim 6, wherein the first vertical dimension is in a range from 100 nm to 500 nm.

8. The method according to claim 1, wherein the insulating liner includes silicon dioxide.

9. The method according to claim 1, wherein the insulating liner includes silicon nitride.

10. The method according to claim 1, wherein the conductive posts include metal.

11. The method according to claim 1, wherein the conductive posts include tungsten.

12. A method of forming an integrated assembly, which comprises: forming an opening extending through an insulating block to reach an upper surface of a first conductive structure; forming a conductive lining and a conductive plug in the opening in electrical contact with the upper surface of the first conductive structure; forming a generally planar surface extending across the insulating block, the conductive lining, and the conductive plug; recessing the conductive plug to form a cavity above a remaining portion of the conductive plug; forming an insulating spacer in the cavity to narrow the cavity, the insulating spacer being separated from the insulating block by the conductive lining, an upper surface of the conductive plug being exposed at a bottom of the narrowed cavity; forming a conductive wide region above the insulating block, a portion of the conductive wide region extending into the cavity and configured as a vertically extending interconnect; and Pattern the conductive region into a plurality of second conductive structures, one of the second conductive structures including the vertically extending interconnect and being electrically coupled to the first conductive structure through the conductive plug and the vertically extending interconnect.

13. The method according to claim 12, wherein forming the insulating spacer comprises: forming a layer of insulating material over the insulating block and within the cavity; and anisotropically etching the layer of insulating material to form the insulating spacer from the insulating material.

14. The method according to claim 13, wherein the insulating material comprises one or more oxides.

15. The method according to claim 13, wherein the insulating material comprises silicon dioxide.

16. The method according to claim 13, wherein the insulating material comprises silicon nitride.

17. The method according to claim 13, wherein both ALD and CVD are utilized to form the layer of insulating material.

18. The method according to claim 12, wherein the conductive plug comprises a metal.

19. The method according to claim 12, wherein the conductive plug comprises tungsten.

20. The method according to claim 12, wherein the vertically extending interconnect abuts directly against the upper surface of the conductive plug.

21. A method of forming an integrated assembly, which comprises: forming an opening extending through an insulating block to reach the upper surface of a first conductive structure; forming a liner material within the opening to line the sidewalls of the opening; utilizing the liner material as a seed material for forming a core material within the opening and along the lined sidewalls of the opening; forming a generally planar surface extending across the insulating block, the liner material, and the core material; recessing at least a portion of the core material and the liner material to form a cavity over the remaining portion of the core material; forming an insulating spacer within the cavity to narrow the cavity, the upper surface of the core material being exposed at the bottom of the narrowed cavity; forming a conductive region over the insulating block, a portion of the conductive region extending into the cavity and configured as a vertically extending interconnect; pattern the conductive region into a plurality of second conductive structures, one of the second conductive structures including the vertically extending interconnect and being electrically coupled to the first conductive structure through the core material and the vertically extending interconnect; and wherein the liner material includes a portion that extends in height above the core material.

22. The method according to claim 21, wherein the core material comprises one or more metals, and wherein the liner material comprises a metal nitride.

23. The method according to claim 21, wherein the core material comprises tungsten, and wherein the liner material comprises one or both of titanium nitride and tungsten nitride.

24. The method according to claim 21, wherein the insulating spacer comprises one or both of silicon dioxide and silicon nitride.

25. The method according to claim 21, wherein the insulating spacer comprises silicon dioxide.

26. The method according to claim 21, wherein the recessing recesses at least a portion of the liner material such that all of the remaining liner material is covered by the insulating spacer.

27. The method according to claim 21, wherein the recessing recesses the liner material and the core material to an equal level.

28. The method according to claim 21, wherein a region of the liner material is not covered by the insulating spacer.

29. The method according to claim 21, wherein the vertically extending interconnect is in direct abutment with the upper surface of the core material.

30. The method according to claim 21, wherein the generally planar surface has a first horizontal dimension across the liner material and the core material along a cross-section, wherein the first horizontal dimension is in the range from 10 nm to 50 nm; and wherein the upper surface of the core material has a second horizontal dimension along the cross-section after the recessing, wherein the second horizontal dimension is in the range from 8 nm to 40 nm.

31. The method according to claim 30, wherein the lowermost portion of the vertically extending conductive interconnect includes a horizontal dimension in the range from 5 nm to 20 nm along the cross-section.

32. The method according to claim 21, wherein the first conductive structure is electrically coupled to a logic circuit system; and wherein the second conductive structure includes a word line or a digit line.

33. The method according to claim 32, wherein the logic circuit system includes one or both of a sense amplifier circuit system and a word line driver circuit system.

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