Method for detecting defects in semiconductor wafer and semiconductor wafer defect detection system

Abstract

A semiconductor wafer defect detection system captures a test image of a semiconductor wafer. The system analyzes the test image using an analysis model trained using a machine learning process. The analysis model generates a simulated integrated circuit layout based on the test image. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layout with a reference integrated circuit layout.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor processing. Embodiments of the present disclosure relate more particularly to detecting defects in semiconductor wafers during semiconductor processing. Background Art

[0002] The fabrication of integrated circuits is typically accomplished by subjecting semiconductor wafers to a large number of processing steps. The processing steps typically result in the formation of a large number of transistors in a highly complex arrangement in conjunction with a semiconductor substrate. The processing steps also result in the formation of dielectric layers, metal interconnects, vias, plugs, and other integrated circuit structures and components.

[0003] During processing of semiconductor wafers, it is often beneficial to perform defect reviews between processing steps. However, many of the features formed on semiconductor wafers are very small. Detecting defects in these very small features can be very difficult. Performing defect reviews can be very costly in terms of time and resources. Furthermore, due to the difficulty in detecting defects, many defects may not be detected during the defect review process. This can result in the integrated circuit functioning poorly or not functioning when processing of the wafer is completed. Summary of the invention

[0004] An embodiment of the present invention provides a method for detecting defects in a semiconductor wafer, comprising: taking a test image of the semiconductor wafer; generating a simulated integrated circuit layout by analyzing the test image; and identifying defects in the semiconductor wafer based on the simulated integrated circuit layout.

[0005] An embodiment of the present invention provides a method for detecting defects in a semiconductor wafer, comprising training a simulation layout generation system using a machine learning process to generate a simulated integrated circuit layout; providing a test image of the semiconductor wafer to the simulation layout generation system; generating a simulated integrated circuit layout using the simulation layout generation system; and comparing the simulated integrated circuit layout with a reference integrated circuit layout.

[0006] An embodiment of the present invention provides a semiconductor wafer defect detection system, comprising: a simulation layout generation system, configured to receive a test image of a semiconductor wafer and generate a simulation integrated circuit layout based on the test image; and a defect detection system, configured to compare the simulation integrated circuit layout with a reference integrated circuit layout and detect defects in the semiconductor wafer based on the difference between the simulation integrated circuit layout and the reference integrated circuit layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor wafer defect detection system according to one embodiment.

[0008] Figure 2 is a block diagram of a semiconductor wafer defect detection system according to one embodiment.

[0009] Figure 3 is a diagram of a semiconductor wafer according to one embodiment.

[0010] Figure 4 An image of a semiconductor wafer and a layout are shown according to one embodiment.

[0011] Figure 5 is a flow chart of a method for detecting defects in a semiconductor wafer according to one embodiment.

[0012] Figure 6 is a flow chart of a method for detecting defects in a semiconductor wafer according to one embodiment. DETAILED DESCRIPTION

[0013] In the following description, many thicknesses and materials are described for various layers and structures within the integrated circuit die. Specific dimensions and materials of various embodiments are given by way of example. Based on this disclosure, those skilled in the art will recognize that other dimensions and materials may be used in many cases without departing from the scope of this disclosure.

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter. Specific examples of components and arrangements are set forth below to simplify this description. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0015] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced without these specific details. In other cases, well-known structures associated with electronic components and fabrication techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0017] Unless the context requires otherwise, throughout the specification and following claims, the word "comprise" and variations thereof (eg, "comprises" and "comprising") are to be construed as having an open, inclusive sense, i.e., "including, but not limited to."

[0018] The use of ordinal numbers such as first, second, and third do not necessarily imply a ranked, sequential sense but may simply distinguish between multiple instances of an action or structure.

[0019] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification may not all refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0020] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise.

[0021] Embodiments of the present disclosure provide simpler, more efficient, and less expensive defect review of semiconductor wafers. Embodiments of the present disclosure capture images of the semiconductor wafer being reviewed. Embodiments of the present disclosure analyze the images and utilize a machine learning process to generate a simulated integrated circuit layout for the semiconductor wafer being reviewed based on the images. Embodiments of the present disclosure compare the simulated integrated circuit layout with a reference integrated circuit layout associated with a reference semiconductor wafer. Defects in the wafer being reviewed are easily and accurately identified by identifying the differences between the simulated integrated circuit layout and the reference integrated circuit layout. The defect review process is simple, efficient, and relatively inexpensive in terms of time and resources. Therefore, embodiments of the present disclosure form semiconductor wafers with fewer defects as defects in the process are identified and corrected.

[0022] Figure 11 is a block diagram of a semiconductor wafer defect review system 100 according to an embodiment. The semiconductor wafer defect review system 100 includes an imaging system 102, a simulation layout generation system 106, a defect locator 108, and a defect analyzer 110. The components of the semiconductor wafer defect review system 100 cooperate to identify and analyze defects in a semiconductor wafer 104.

[0023] In one embodiment, the imaging system 102 is configured to generate images of the semiconductor wafer 104. The imaging system 102 may capture images of the semiconductor wafer 104 between semiconductor processing steps. The images captured by the imaging system 102 may be used to identify defects in the semiconductor wafer 104.

[0024] The semiconductor wafer defect review system 100 may be part of a semiconductor processing system that performs a number of semiconductor processes on a semiconductor wafer 104. The semiconductor processes may include photolithography processes, etching processes, thin film deposition processes, planarization processes, doping processes, annealing processes, and other types of processes.

[0025] In one embodiment, after one or more of these processes have been performed, it may be beneficial to inspect the semiconductor wafer 104 for defects. This can help ensure that the one or more of the aforementioned processes have achieved their intended purpose. If defects are present, the process or parameters associated with the process may need to be adjusted to ensure that defects are not present in the future. If defects are not present, the process is proceeding normally.

[0026] In one example, a series of semiconductor processes form metal lines on a dielectric substrate. Thus, the semiconductor process may include forming a dielectric substrate on the semiconductor wafer 104 using a thin film deposition process, forming a metal layer on top of the dielectric substrate using a second thin film deposition process, and depositing a hard mask on the metal layer and patterning the hard mask. The semiconductor process may also include etching the metal layer in the presence of the patterned hard mask, thereby forming a metal line from the metal layer. The metal line has the pattern of the hard mask. The hard mask is then removed, leaving the metal line.

[0027] In this example, the pattern of metal lines is defined by a previously generated integrated circuit layout. One example of an integrated circuit layout is a simulated graphic database system (GDS) layout, but other types or formats of layouts may also be used. The integrated circuit layout defines a mask pattern of metal lines. After the integrated circuit layout has been generated using one or more dedicated software programs for generating layouts for semiconductor processing, a photolithography mask may be generated based on the layout. The integrated circuit layout generally has clear, distinct features. The semiconductor wafer defect viewing system 100 utilizes the properties of the layout mask to assist in identifying defects, as will be described in more detail below.

[0028] Continuing with the example of the metal lines, after the metal lines have been formed, the semiconductor wafer 104 is brought to the imaging system 102 to initiate the defect viewing process. The imaging system 102 captures a plurality of images of the semiconductor wafer 104. Each region of the semiconductor wafer 104 is captured into at least one of the images. Each region of the semiconductor wafer 104 may be captured in a plurality of images. The images may include images with different resolutions. For example, a particular region of the semiconductor wafer 104 may be imaged at a first resolution level. Then, various sub-regions of the region may be imaged at a second, higher resolution level to zoom in on the region of interest, as will be described in more detail below.

[0029] In one embodiment, the imaging system 102 passes the images to the simulated layout generation system 106. The simulated layout generation system 106 analyzes the images and generates a simulated integrated circuit layout for each image. In one embodiment, the simulated integrated circuit layout is a GDS layout. The simulated integrated circuit layout is a simulation of a layout having a pattern that will form the structure or feature captured in the image. The simulated integrated circuit layout can be used to identify defects in the semiconductor wafer 104.

[0030] Returning to the example in which metal lines have been formed on the semiconductor wafer 104, after the simulated layout generation system 106 has generated a simulated integrated circuit layout for each image, the simulated layout generation system 106 passes the simulated image to the defect locator 108. The defect locator 108 retrieves a reference integrated circuit layout for each simulated integrated circuit layout. The reference integrated circuit layout corresponds to the actual layout used to generate the features of the region of the semiconductor wafer 104.

[0031] After the defect locator 108 has retrieved the reference image for each simulated image, the defect locator 108 identifies defects in the image of the semiconductor wafer 104 by comparing the simulated integrated circuit layout with the corresponding reference integrated circuit layout. The area where the simulated integrated circuit layout is different from the reference integrated circuit layout corresponds to the area of ​​the defect. Therefore, the defect locator 108 can quickly identify the area of ​​the defect in the image by identifying the difference between the simulated integrated circuit layout and its corresponding reference integrated circuit layout.

[0032] Since the simulated integrated circuit layout and the reference integrated circuit layout have clear, distinct features, any differences between the simulated integrated circuit layout and its corresponding reference integrated circuit layout will be easily noticed in the comparison. Therefore, the defect locator 108 can quickly and reliably identify the area of ​​the defect by comparing the simulated integrated circuit layout with the reference integrated circuit layout.

[0033] In one embodiment, after the defect locator 108 identifies the area of ​​the defect, the image and information identifying the area of ​​the defect are passed to the defect analyzer 110. The defect analyzer 110 may focus or magnify the area of ​​the defect in the image generated by the imaging system 102. The defect analyzer 110 may enable a technician to quickly magnify and focus on the relevant area in the image to determine the nature of the defect and the possible cause of the defect. In one embodiment, after the defect locator 108 has identified the area of ​​the defect, the imaging system 102 may generate a higher resolution image of the area of ​​the defect.

[0034] In one embodiment, the imaging system 102 may include an electron microscope. The imaging system 102 generates electron microscope images of various regions of the semiconductor wafer 104. The electron microscope images may then be transmitted to the simulation layout generation system 106. Alternatively, the imaging system 102 may include other types of imaging systems. Without departing from the scope of the present disclosure, the other types of imaging systems may include optical imaging systems, atomic force microscope imaging systems, or other types of imaging systems.

[0035] Figure 2 is a block diagram of a portion of a defect review system 200 according to an embodiment. The system 200 includes a training set database 202, a deep learning unit 204, an image processing unit 206, a defect detection system 210, and a result database 212. The components of the defect review system 200 assist in detecting defects in semiconductor wafers.

[0036] In one embodiment, training set database 202 includes image database 214. Image database 214 stores multiple images of one or more semiconductor wafers after a particular stage of semiconductor processing. For example, if system 200 is used to detect defects after forming a metal line in metal 1, image database 214 may include images of various regions of the semiconductor wafer after forming the metal line in metal 1. The images of various regions of the semiconductor wafer are used in a machine learning process, as will be described in more detail below.

[0037] In one embodiment, the training set database 202 includes a layout database. The layout database includes a plurality of integrated circuit layouts. Each integrated circuit layout in the layout database 216 corresponds to a layout of a particular region or area of ​​a semiconductor wafer. More specifically, each layout corresponds to an area of ​​the semiconductor wafer captured in a corresponding image from the image database 214. Thus, each layout from the layout database 216 is linked to an image from the image database 214. Alternatively, multiple layouts may be associated with a single image, or multiple images may be associated with a single layout.

[0038] In one embodiment, images from the image database and layouts from the layout database 216 correspond to labeled training set data. The data items of the training set include images from the image database 214 and layouts from the layout database 216. The labeling identifies which layout is from the layout database 216 or which layouts correspond to each image from the image database 214.

[0039] The deep learning unit 204 performs a deep learning process using the training set data from the training set database 202. Specifically, the deep learning unit 204 undergoes a machine learning process that uses the training set to train the deep learning unit 204 to reproduce a layout based on an image of a semiconductor wafer. In other words, the deep learning unit uses the training set to learn how to generate a layout that matches a pattern in an image of a semiconductor wafer.

[0040] In one embodiment, the deep learning unit 204 trains an analysis model (e.g., a neural network). During the training process, the neural network receives images of semiconductor wafers from the image database 214 as input. During the training process, the neural network outputs a layout for each image based on a set of internal functions. The internal function is based on a weighted value associated with a neuron of each neural layer of the neural network. During training, the deep learning unit 204 compares each layout generated by the neural network with a layout for a portion of the wafer in the image. The deep learning unit 204 generates an error function indicating how closely the layout generated by the neural network matches the actual layout. The deep learning unit 204 then adjusts the internal function of the neural network. Since the neural network generates a layout based on the internal function, adjusting the internal function will result in different layouts being generated for the same image. Adjusting the internal function will cause the generated layout to generate a larger error function (worse match with the actual layout) or a smaller error function (better match with the actual layout). After adjusting the internal function of the neural network, the image is passed to the neural network again, and a layout is generated and compared with the actual layout. The deep learning unit 204 adjusts the internal function of the neural network again. This process is repeated over a very large number of iterations of tracking the error function and adjusting the internal functions of the neural network until a set of internal functions is found that forms a simulated layout that matches the actual layout.

[0041] At the beginning of the training process, the generated layout may not match the actual layout well. However, as the training process proceeds through multiple iterations of adjusting the internal functions of the neural network, the error function will become smaller and smaller until a set of internal functions is found that causes the generated layout to match the actual layout. The identification of a set of internal functions that causes the matching layout corresponds to the completion of the training process. Once the training process is complete, the neural network can be used to detect defects in the wafer.

[0042] In one embodiment, the deep learning unit 204 utilizes a convolutional neural network model. The convolutional neural network model includes multiple layers of neurons. Image data is input to the convolutional neural network in the form of a tensor. The first convolutional layer of neurons processes the image data according to the weighting function and parameters associated with the neurons of the first layer. Specifically, the first layer performs a convolution operation on the tensor. The result is a series of reduced-dimensional tensors. These reduced-dimensional tensors are then passed to the second convolutional neural layer. The second convolutional neural layer performs a convolution operation on the tensor received from the first convolutional neural layer. The tensor is finally passed to one or more fully connected layers. The fully connected layer classifies each area of ​​the image. The result of the classification is a GDS-type layout in which each area of ​​the image has been converted into a part of the layout. By splicing together the various parts of the layout output from the final fully connected layer, a layout corresponding to the image is generated. As described above, the training process trains the convolutional neural network to generate a layout that matches the actual layout used to generate the features captured in the image for each image by adjusting the function associated with each neural layer of the convolutional neural network. The deep learning unit 204 may include models or algorithms other than convolutional neural networks without departing from the scope of the present disclosure.

[0043] In one embodiment, after the deep learning unit 204 has trained the analysis model or algorithm, the analysis model or algorithm is imported into the image processing unit 206. The image processing unit 206 can utilize the model or algorithm generated by the deep learning unit 204 to generate a simulated integrated circuit layout.

[0044] In one embodiment, the image processing unit 206 receives the test image 208. The test image 208 corresponds to an image of the semiconductor wafer 104 captured by the imaging system 102, such as for Figure 1 The test image 208 is generated to determine whether there are defects in the semiconductor wafer 104 .

[0045] In one embodiment, the image processing unit 206 generates a corresponding simulated integrated circuit layout for each test image 208. The image processing unit 206 generates the simulated integrated circuit layout according to the algorithm or model generated by the deep learning unit 204. The simulated integrated circuit layout generated by the image processing unit 206 corresponds to the predicted layout that will form the features shown in the test image 208. The image processing unit 206 can generate the simulated integrated circuit layout for a large number of test images 208 received from the imaging system 102. The simulated integrated circuit layout is then transmitted to the defect detection system 210 and the result database 212.

[0046] In one embodiment, defect detection system 210 determines whether there are defects in semiconductor wafer 104. Defect detection system 210 determines whether there are defects by analyzing a simulated integrated circuit layout generated based on an image of semiconductor wafer 104. The simulated integrated circuit layout may provide an indication of the presence of defects in semiconductor wafer 104.

[0047] In one embodiment, defect detection system 210 identifies defects by comparing simulated integrated circuit layouts with reference integrated circuit layouts. Specifically, defect detection system 210 compares each simulated integrated circuit layout with a corresponding reference integrated circuit layout. If there are areas in the simulated integrated circuit layout that are different from the reference integrated circuit layout, this indicates that there are defects in semiconductor wafer 104 at locations corresponding to the different areas in the simulated integrated circuit layout.

[0048] In one embodiment, the defect detection system 210 compares the simulated integrated circuit layout to the reference integrated circuit layout by performing an image subtraction operation in which the simulated integrated circuit layout is subtracted from the reference integrated circuit layout, or vice versa. The result of the subtraction is a layout that highlights those areas where differences exist between the simulated integrated circuit layout and the reference integrated circuit layout. If the reference integrated circuit layout is the same as the simulated integrated circuit layout, the resulting layout will be blank. If the simulated integrated circuit layout is not the same as the reference integrated circuit layout, there will be indicators on the subtracted layout at locations corresponding to the locations where the simulated integrated circuit layout and the reference integrated circuit layout differ.

[0049] In one embodiment, the defect detection system 210 records the location of the defect. The defect detection system 210 can map the location of the defect as indicated on the subtracted image to a location on the semiconductor wafer 104. This is because the imaging system that captures the test images 208 records the location information for each test image 208. The location information indicates the area of ​​the semiconductor wafer 104 that is captured in each test image 208. This information is provided to the defect detection system 210. Since each simulated integrated circuit layout is based on the test image, the defect location indicated by the simulated integrated circuit layout, or the subtracted layout generated from the simulated integrated circuit layout and the reference integrated circuit layout, can be mapped to a location on the test image 208, which in turn is mapped to a location on the semiconductor wafer 104.

[0050] In one embodiment, after the defect location has been detected, the defect location information is passed to the defect analyzer 213. The defect analyzer 213 may receive the test image 208 and the defect location coordinates on the test image 208. The defect analyzer 213 may assist in analyzing the defects.

[0051] In one embodiment, the defect analyzer 213 zooms in on the location of the defect in the test image 208. The defect analyzer 213 may then show an enlarged view of the defect for the expert to review. One or more experts may determine the possible cause of the defect based on the analysis of the defect location presented by the defect analyzer 213.

[0052] In one embodiment, the defect analyzer 213 may utilize a defect analysis tool to analyze the defect location. The defect analysis tool may include analysis models and other software applications that may analyze various aspects of the test image. The defect analysis tool may provide an indication of the cause of the defect.

[0053] In one embodiment, after the defect detection system 210 has detected a defect, the imaging system 102 may automatically capture a new image of the defect location. The new image may include a high-resolution image of the defect location on the semiconductor wafer 104. The new high-resolution image may be provided to the defect analyzer 213 for review by an expert and / or software system.

[0054] In one embodiment, the result database 212 stores the simulated integrated circuit layout. After the image processing unit 206 generates the simulated integrated circuit layout, the simulated integrated circuit layout can be provided to the result database 212 for storage. In one embodiment, the defect detection system 210 can also provide defect location data, subtracted layout, and test image 208.

[0055] Figure 3 is a diagram of a semiconductor wafer 104 according to one embodiment. Figure 3 The illustrated diagram shows that the semiconductor wafer 104 is divided into a plurality of zones 302. The imaging system 102 can capture the test image 208 of each zone 302. As another option, the imaging system 102 can capture the test image 208 of only selected zones 302. In practice, the semiconductor wafer 104 may include more than one zone 302. Figure 3 Each test image 208 may capture an area less than 1 μm 2 The test image 208 may capture areas of other sizes without departing from the scope of the present disclosure.

[0056] Figure 4 A plurality of layouts and images for identifying defects in a semiconductor wafer 104 are shown according to one embodiment. Figure 4 Shown are test image 208, reference image 402, simulated integrated circuit layout 404, reference integrated circuit layout 406, and difference layout 408. The various images and layouts are used to detect defects in semiconductor wafer 104.

[0057] In one embodiment, the test image 208 is an image of the region 302 of the semiconductor wafer 104. The test image 208 may be taken after one or more semiconductor processes have been performed on the semiconductor wafer 104. The test image 208 may be an electron microscope image, an optical image, an x-ray scattering image, or another type of image.

[0058] In one embodiment, reference image 402 is an image of a reference semiconductor wafer. Reference image 402 corresponds to the same region of the reference semiconductor wafer as test image 208 taken of semiconductor wafer 104. In practice, the reference semiconductor wafer is known to have no defects. Therefore, reference image 402 does not contain defects. Instead, reference image 402 shows what the features of test image 208 should look like if formed correctly.

[0059] In one embodiment, the simulated integrated circuit layout 404 is performed by a graphics processing unit (eg, Figure 2 The image processing unit 206 shown in FIG. 1 generates an image based on the test image 208. Figure 2 As described above, the image processing unit 206 processes the test image 208 using a deep learning algorithm and generates a simulated integrated circuit layout 404 that will form features of the test image 208. Figure 4 As can be seen in FIG. 2 , the reference integrated circuit layout includes clear, sharply defined features. This contrasts with the test image 208 which has less distinct features.

[0060] Reference integrated circuit layout 406 is a layout used to generate features and reference image 402. A layout such as reference integrated circuit layout 406 is generated using a software program. The layout shows the location and shape of features to be formed on a semiconductor wafer. The layout is used to generate a photolithography mask for patterning features on a semiconductor wafer. Reference integrated circuit layout 406 shows a very small portion of the entire layout of features to be formed on a semiconductor wafer at a particular stage of processing. In one embodiment, reference integrated circuit layout 406 is a GDS layout, but other types of layouts may be utilized without departing from the scope of the present disclosure.

[0061] In one embodiment, a difference layout 408 is generated from simulated integrated circuit layout 404 and reference integrated circuit layout 406. Difference layout 408 corresponds to the difference between reference integrated circuit layout 406 and simulated integrated circuit layout 404. If a feature is present at a particular location in reference integrated circuit layout 406 but not in that location in simulated integrated circuit layout 404, the difference image will include the difference feature. In other embodiments, if a feature is not present at a particular location in reference integrated circuit layout 406 but is present in that location in simulated integrated circuit layout 404, the difference image will include the difference feature.

[0062] exist Figure 4 In the example shown, the difference layout 408 is blank at all locations except for the difference location 410. The difference location 410 is black, clearly indicating the difference area between the simulated integrated circuit layout 404 and the reference integrated circuit layout 406. The difference location 410 corresponds to the defect location 411 in the test image 208.

[0063] The generation of simulated integrated circuit layout 404 greatly assists in detecting defects in semiconductor wafer 104. Detecting defects based on a direct comparison between test image 208 and reference image 402 can be very difficult. This is because test image 208 and reference image 402 include a high level of detail, curved features, and slight differences in color or grayscale. Since small differences may exist throughout test image 208 and reference image 402, it is difficult to detect the effects. Simulated integrated circuit layout 404 and reference integrated circuit layout 406 have only binary coloration and sharp, clearly defined features. Differences between simulated integrated circuit layout 404 and reference integrated circuit layout 406 are very easy to detect.

[0064] Figure 5 is a flow chart of a method 500 for detecting defects in a semiconductor wafer according to one embodiment. At 502, the method 500 includes taking a test image of a semiconductor wafer. An example of a semiconductor wafer is Figure 3 A semiconductor wafer 104 is shown. An example of a test image is Figure 4 The test image 208 is shown. At 504, method 500 includes generating a simulated integrated circuit layout by analyzing the test image. An example of a simulated integrated circuit layout is Figure 4 The simulated integrated circuit layout 404 is shown. At 506, method 500 includes identifying defects in the semiconductor wafer based on the simulated integrated circuit layout.

[0065] Figure 6 is a flow chart of a method 600 for detecting defects in a semiconductor wafer according to one embodiment. At 602, the method 600 includes training a simulation layout generator using a machine learning process to generate a simulated integrated circuit layout. An example of a simulation layout generator is Figure 1 The simulation layout generator 106 is shown. At 604, the method 600 includes providing a test image of the semiconductor wafer to the simulation layout generation system. An example of a test image is Figure 4 The test image 208 is shown. At 606, method 600 includes generating a simulated integrated circuit layout using a simulated layout generation system. An example of a simulated integrated circuit layout is Figure 4The simulated integrated circuit layout 404 is shown. At 608, method 600 includes comparing the simulated integrated circuit layout to a reference integrated circuit layout.

[0066] An embodiment of a method for detecting defects in a semiconductor wafer includes capturing a test image of a semiconductor wafer. The method includes generating a simulated integrated circuit layout by analyzing the test image and identifying defects in the semiconductor wafer based on the simulated integrated circuit layout.

[0067] In a related embodiment, identifying defects in the semiconductor wafer includes comparing the simulated integrated circuit layout to a reference integrated circuit layout.

[0068] In a related embodiment, comparing the simulated integrated circuit layout to the reference integrated circuit layout includes generating a difference layout corresponding to a difference between the reference integrated circuit layout and the simulated integrated circuit layout.

[0069] In a related embodiment, identifying defects in the semiconductor wafer includes identifying locations of differences in the different layouts.

[0070] In a related embodiment, the reference integrated circuit layout is a layout used to generate a photolithography mask for semiconductor processing.

[0071] In a related embodiment, the method further comprises generating the simulated integrated circuit layout using an image processing system.

[0072] In a related embodiment, the method further includes training the image processing system using a machine learning process to generate a simulated integrated circuit layout based on the test image.

[0073] In a related embodiment, the machine learning process includes utilizing a labeled training set including training images and training layouts.

[0074] One embodiment of a method for detecting defects in a semiconductor wafer includes training a simulation layout generation system using a machine learning process to generate a simulated integrated circuit layout and providing a test image of a semiconductor wafer to the simulation layout generation system. The method includes generating a simulated integrated circuit layout using the simulation layout generation system and comparing the simulated integrated circuit layout with a reference integrated circuit layout.

[0075] In a related embodiment, the method further includes detecting defects in the semiconductor wafer based on differences between the simulated integrated circuit layout and the reference integrated circuit layout.

[0076] In a related embodiment, training the simulated layout generation system includes training the simulated layout generation system to generate a simulated integrated circuit layout that matches a training integrated circuit layout for a plurality of training images.

[0077] One embodiment of a semiconductor wafer defect detection system includes a simulation layout generation system configured to receive a test image of a semiconductor wafer and generate a simulated integrated circuit layout based on the test image. The system includes a defect detection system configured to compare the simulated integrated circuit layout with a reference integrated circuit layout and detect defects in the semiconductor wafer based on differences between the simulated integrated circuit layout and the reference integrated circuit layout.

[0078] In a related embodiment, the semiconductor wafer defect detection system further includes an imaging system configured to capture the test image by imaging the semiconductor wafer.

[0079] In related embodiments, the imaging system includes one or more of: an electron microscope; a bright-field optical imaging system; and a dark-field optical imaging system.

[0080] In a related embodiment, the simulated layout generation system includes a deep learning unit configured to learn an algorithm for generating a simulated integrated circuit layout based on a test image through one or more machine learning processes.

[0081] In a related embodiment, the semiconductor wafer defect detection system further includes an image processing unit configured to implement the algorithm.

[0082] In a related embodiment, the image processing unit is configured to process the test image and generate the simulated integrated circuit layout using the algorithm.

[0083] In a related embodiment, the simulation layout generation system includes a training set database, which includes training set data for training the deep learning unit.

[0084] In a related embodiment, the training set database includes: an image database including training images of the training set data; and a layout database including training layouts of the training set data.

[0085] In a related embodiment, the training images are images of one or more reference semiconductor wafers, wherein the training layouts are layouts associated with processing the one or more reference semiconductor wafers.

[0086] The various embodiments described above can be combined to provide further embodiments. If necessary, various aspects of the embodiments can be modified to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0087] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the above claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalent constructions to which the claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A method for detecting defects in a semiconductor wafer, comprising: taking a test image of the semiconductor wafer; generating a simulated integrated circuit layout by analyzing the test image; generating a reference image of a reference semiconductor wafer; generating a reference integrated circuit layout based on the reference image, wherein the reference integrated circuit layout is used to generate a layout of a photolithography mask for semiconductor processing; comparing the simulated integrated circuit layout to the reference integrated circuit layout; and Defects in the semiconductor wafer are identified based on a result of comparing the simulated integrated circuit layout with the reference integrated circuit layout.

2. The method of claim 1 , wherein comparing the simulated integrated circuit layout with the reference integrated circuit layout comprises: A difference layout corresponding to a difference between the reference integrated circuit layout and the simulated integrated circuit layout is generated.

3. The method of claim 2, wherein identifying defects in the semiconductor wafer comprises: A difference location in the difference layout is identified.

4. The method according to claim 1, further comprising: The simulated integrated circuit layout is generated using an image processing system.

5. The method according to claim 4, further comprising: The image processing system is trained using a machine learning process to generate simulated integrated circuit layouts based on test images.

6. The method of claim 5, wherein the machine learning process comprises utilizing a labeled training set comprising training images and training layouts.

7. A method for detecting defects in a semiconductor wafer, comprising: training a simulated layout generation system using a machine learning process to generate a simulated integrated circuit layout; providing a test image of the semiconductor wafer to the simulation layout generation system; Using the simulation layout generation system to generate a simulated integrated circuit layout; generating a reference image of a reference semiconductor wafer; generating a reference integrated circuit layout based on the reference image, wherein the reference integrated circuit layout is used to generate a layout of a photolithography mask for semiconductor processing; as well as The simulated integrated circuit layout is compared to a reference integrated circuit layout.

8. The method according to claim 7, further comprising: Defects in the semiconductor wafer are detected based on differences between the simulated integrated circuit layout and the reference integrated circuit layout.

9. The method according to claim 7, wherein training the simulation layout generation system comprises: The simulated layout generation system is trained to generate simulated integrated circuit layouts matching the training integrated circuit layouts for a plurality of training images.

10. A semiconductor wafer defect detection system, comprising: The simulation layout generation system is configured to: receiving a test image of a semiconductor wafer; generating a simulated integrated circuit layout based on the test image; receiving a reference image of a reference semiconductor wafer; and generating a reference integrated circuit layout based on the reference semiconductor wafer, wherein the reference integrated circuit layout is used to generate a layout of a photolithography mask for semiconductor processing; as well as A defect detection system is configured to compare the simulated integrated circuit layout with the reference integrated circuit layout and detect defects in the semiconductor wafer based on differences between the simulated integrated circuit layout and the reference integrated circuit layout. 11 . The semiconductor wafer defect detection system according to claim 10 , further comprising an imaging system configured to capture the test image by imaging the semiconductor wafer.

12. The semiconductor wafer defect detection system of claim 11, wherein the imaging system comprises one or more of: Electron microscopy; Bright field optical imaging system; and Dark-field optical imaging system.

13. The semiconductor wafer defect detection system according to claim 10, wherein the simulation layout generation system comprises a deep learning unit, and the deep learning unit is configured to learn an algorithm for generating a simulated integrated circuit layout based on a test image through one or more machine learning processes.

14. The semiconductor wafer defect detection system of claim 13, further comprising an image processing unit configured to implement the algorithm. 15 . The semiconductor wafer defect detection system according to claim 14 , wherein the image processing unit is configured to process the test image and generate the simulated integrated circuit layout using the algorithm. 16 . The semiconductor wafer defect detection system according to claim 15 , wherein the simulation layout generation system comprises a training set database, and the training set database comprises training set data for training the deep learning unit.

17. The semiconductor wafer defect detection system according to claim 16, wherein the training set database comprises: An image database, comprising training images of the training set data; as well as A layout database includes a training layout of the training set data.

18. The semiconductor wafer defect detection system of claim 17, wherein the training images are images of one or more reference semiconductor wafers, and wherein the training layouts are layouts associated with processing the one or more reference semiconductor wafers.

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