A reconfigurable power amplifier based on PIN switch and its design method

Abstract

The present invention discloses a reconfigurable power amplifier based on a PIN switch and a design method thereof, comprising an input port, an input matching circuit, a PIN switch, a gate bias circuit, a transistor, a drain bias circuit, an output matching circuit and an output port. The input end of the input matching network is connected to the power input end, and the output end is connected to the gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain bias circuit is connected in parallel with the drain, the drain of the transistor is connected to the input end of the output matching circuit, and the output end of the output matching circuit is used as the power output. The present invention adopts a PIN switch, which effectively reduces the actual operation difficulty during plate making and performance testing, proposes a new reconfigurable theory, improves the overall feasibility of the power amplifier, and also improves the performance to a certain extent.

Description

Technical Field

[0001] The invention relates to the field of radio frequency circuit design, and relates to a reconfigurable power amplifier based on a PIN switch and a design method thereof. Background Art

[0002] In the past 20 years, wireless communication has been invented, verified and developed rapidly. Today, it has become an indispensable tool for human society. Mobile phones, Bluetooth devices, wireless LAN devices, and satellite communication systems are all important applications of wireless communication and have been integrated into human daily life. As an important part of the wireless communication system, the power amplifier is the last link of antenna transmission in the uplink and the last link of antenna reception in the downlink. It must face the challenges of multi-band and multi-mode working environment. Reconfigurable power amplifiers can switch between different modes and frequency bands through the control of reconfigurable devices. Reconfigurable power amplifiers with simple structure and excellent performance can promote the better development of wireless communication systems. At present, there have been many reports on reconfigurable power amplifiers. In 2018, Kong Xiaoxiao designed a reconfigurable continuous Doherty power amplifier operating at 0.725GHz to 1.225GHz by using a comb filter at the output end. The test results show that the efficiency is greater than 35% and the gain is greater than 9dB. In general, the design of reconfigurable power amplifiers is relatively complex, the design of reconfigurable devices is difficult and has a great impact on the circuit, and the matching circuit structure of the reconfigurable power amplifier is relatively simple and the debugging of the reconfigurable power amplifier is relatively difficult.

[0003] In view of the above-mentioned technical problems, it is necessary to conduct research and improvement to provide a reconfigurable power amplifier based on a PIN switch and a design method thereof to solve the problems existing in the prior art. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a reconfigurable power amplifier based on a PIN switch and a design method thereof, which changes the circuit structure of the output matching circuit network by changing the working state of the PIN switch in the output matching circuit, thereby realizing a reconfigurable function and enabling the power amplifier to have good working performance in different modes and different frequency bands. In order to further improve the performance of the reconfigurable power amplifier, the input matching circuit also adopts the same design method.

[0005] In order to overcome the defects of the prior art, the present invention adopts the following technical solutions:

[0006] A reconfigurable power amplifier based on a PIN switch, comprising an input port, a reconfigurable input matching network, a gate bias network, a transistor, a PIN switch, a drain bias network, a reconfigurable output matching network and an output port;

[0007] The input end of the reconfigurable input matching network is adapted to and connected to the input port, the output end thereof is connected to the transistor gate, and the gate bias circuit is connected in parallel to the transistor gate;

[0008] The transistor drain is connected in parallel with the drain bias circuit, and the transistor drain is connected to the input end of the reconfigurable output matching network;

[0009] The reconfigurable input matching circuit includes a trunk microstrip line and a reconfigurable structure;

[0010] The trunk microstrip line is respectively connected to the input port, the transistor and the bias circuit; the trunk microstrip line is connected to a plurality of reconfigurable structures;

[0011] The reconfigurable structure is composed of a PIN switch and a microstrip line in series;

[0012] The output port is adapted to and connected to the reconfigurable output matching circuit.

[0013] The reconfigurable output matching network includes a reconfigurable structure consisting of a PIN switch and a microstrip line.

[0014] The number of the reconfigurable structures in the reconfigurable input matching and the reconfigurable output matching is 4 in total, and the reconfigurable structure can realize the switching between 1.75G and 2.6G.

[0015] The reconfigurable output matching network realizes frequency band switching by adding a reconfigurable structure composed of a PIN switch and a reconfigurable microstrip line, including a PIN switch 1, a PIN switch 2, a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6 and a seventh microstrip line TL7, wherein TL1, TL2, TL3, and TL4 are series microstrip lines, and TL5, TL6, and TL7 are parallel microstrip lines; the drain of the transistor is connected to the first microstrip line TL1, the other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the fifth microstrip line TL5, one end of the second microstrip line TL2 is connected to one end of the third microstrip line TL3 and one end of the PIN switch 1, the other end of the PIN switch 1 is connected to the sixth microstrip line TL6, and the third microstrip line TL4 is connected to the fifth microstrip line TL5. The other end of the strip line TL3 is connected to one end of the fourth microstrip line TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip line TL7; when the PIN switch 1 is closed and the PIN switch 2 is opened, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the sixth microstrip line TL6 together constitute a matching circuit, while the seventh microstrip line TL7 does not participate in the matching, thereby achieving output matching at 1.75 GHz; when the PIN switch 1 is opened and the PIN switch 2 is closed, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the seventh microstrip line TL7 together constitute a matching circuit, while the sixth microstrip line TL6 does not participate in the matching, thereby achieving output matching at 2.6 GHz.

[0016] The reconfigurable input matching circuit adopts the same structure as the reconfigurable output matching circuit;

[0017] The drain bias circuit provides power to the transistor while requiring the loss in the frequency band in which the reconfigurable power amplifier operates to be minimized. The drain bias circuit includes an eighth microstrip line TL8, a ninth microstrip line TL9, a tenth microstrip line TL10 and a DC blocking capacitor C1, wherein one end of the eighth microstrip line TL8 is connected to the transistor drain, the other end of the eighth microstrip line TL8 is connected to the ninth microstrip line TL9 and the tenth microstrip line TL10, the ninth microstrip line TL9 is a parallel open microstrip line, and the other end of the tenth microstrip line TL10 is connected to the drain power supply.

[0018] The gate bias circuit adopts the same circuit structure as the drain bias circuit.

[0019] The present invention also discloses a design method of a reconfigurable power amplifier based on a PIN switch, comprising the following steps:

[0020] Step S1: performing multiple load pulls and source pulls on the GaN HEMT CGH40010F transistor, and obtaining the optimal load impedance and optimal source impedance of the transistor at power added efficiency and maximum output power;

[0021] Step S2: adopting the design concept that a quarter-wavelength microstrip line can realize real impedance transformation to design a gate bias network and a drain bias network to ensure that the power amplifier has a stable DC power supply voltage, wherein three microstrip lines TL8, TL9, TL10 and a short-circuit capacitor C1 are adopted, wherein the microstrip lines TL8 and TL10 are series microstrip lines, and the microstrip line TL9 is a parallel microstrip line;

[0022] Step S3: designing a reconfigurable output matching circuit, optimizing the reconfigurable output matching structure by taking the optimal load impedance at different frequencies through the microstrip line and following the track on the Smith chart, and finding a suitable microstrip line electrical length and characteristic impedance;

[0023] The reconfigurable output matching circuit includes a PIN switch 1, a PIN switch 2, a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6 and a seventh microstrip line TL7, wherein the microstrip lines TL1, TL2, TL3 and TL4 are series microstrip lines, and TL5, TL6 and TL7 are parallel microstrip lines; the drain of the transistor is connected to one end of the first microstrip line TL1, the other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the fifth microstrip line TL5, the other end of the second microstrip line TL2 is connected to one end of the third microstrip line TL3 and one end of the PIN switch 1, and the other end of the PIN switch 1 is connected to the sixth microstrip line TL6. The other end of the third microstrip line TL3 is connected to one end of the fourth microstrip line TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip line TL7; when the PIN switch 1 is closed and the PIN switch 2 is opened, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the sixth microstrip line TL6 together constitute a matching circuit, and the seventh microstrip line TL7 does not participate in the matching; when the PIN switch 1 is opened and the PIN switch 2 is closed, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the seventh microstrip line TL7 together constitute a matching circuit, and the sixth microstrip line TL6 does not participate in the matching;

[0024] Step S4: design a reconfigurable structure, which is composed of a PIN switch and a reconfigurable branch. The output matching network is reconfigured by changing the switch state of the PIN switch in the reconfigurable structure. Since the electrical lengths and characteristic impedances of the microstrip lines TL1, TL2, TL3, TL4, and TL5 have been determined, the characteristic impedance and electrical length of the microstrip line TL6 are continuously adjusted at 1.75 GHz, so that the output impedance of the G point is exactly 50 ohms; similarly, at 2.6 GHz, the characteristic impedance and electrical length of the microstrip line TL7 are continuously adjusted, so that the output impedance of the G point is exactly 50 ohms;

[0025] Step S5: designing a reconfigurable input matching network, using the same design method as the output matching circuit, so that the reconfigurable power amplifier has better performance;

[0026] Step S6: Combine steps S1, S2, S3, S4, and S5 to build an overall circuit structure, and use ADS software to perform circuit simulation and optimization to ensure optimal performance.

[0027] As a further improvement scheme, the drain bias circuit includes an eighth microstrip line TL8, a ninth microstrip line TL9, a tenth microstrip line TL10 and a DC blocking capacitor C1, wherein one end of the eighth microstrip line TL8 is connected to the transistor drain, the other end of the eighth microstrip line TL8 is connected to the ninth microstrip line TL9 and the tenth microstrip line TL10, the ninth microstrip line TL9 is a parallel open microstrip line, and the other end of the tenth microstrip line TL10 is connected to the drain power supply.

[0028] Compared with the prior art, the present invention proposes a reconfigurable power amplifier based on a PIN switch for a traditional dual-band power amplifier. The reconfigurable function of the matching circuit is mainly achieved by changing the switching state of the PIN switch in the matching circuit. Different matching circuits are used at different frequencies so that good matching can be obtained at each frequency. Traditional dual-band power amplifiers either have a relatively simple structure but low efficiency, or use a complex structure to obtain higher efficiency. The reconfigurable power amplifier based on a PIN switch of the present invention solves this contradiction well, improves the efficiency of the power amplifier, and at the same time optimizes the bias circuit to a certain extent, further improving the overall performance of the power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a reconfigurable power amplifier based on a PIN switch of the present invention;

[0030] Figure 2 It is a schematic diagram of the bias circuit network topology structure of the present invention;

[0031] Figure 3a It is a schematic diagram of the structure of a conventional reconfigurable matching circuit;

[0032] Figure 3b is a schematic diagram of the structure of the optimized reconfigurable matching circuit;

[0033] Figure 4a It is a schematic diagram of the S parameter simulation result of the reconfigurable matching circuit of the present invention at f1;

[0034] Figure 4b It is a schematic diagram of the S parameter simulation result of the reconfigurable matching circuit of the present invention at f2;

[0035] Figure 5a It is a simulation result diagram of the output power, efficiency and gain of the reconfigurable power amplifier based on the PIN switch of the present invention at f1;

[0036] Figure 5b It is a simulation result diagram of the output power, efficiency and gain of the reconfigurable power amplifier based on PIN switch of the present invention at f1. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the specific implementation scheme of the present invention will be further described below in conjunction with examples and drawings:

[0038] At present, the design of reconfigurable power amplifiers has the following main defects: the design of reconfigurable devices is difficult and the non-ideality will have a certain impact on the circuit; the matching circuit structure of the reconfigurable power amplifier is relatively simple and difficult to implement; during the debugging process, the impact of changes in the matching circuit structure on the overall performance cannot be observed at the same time, so debugging is also more difficult.

[0039] In response to the above-mentioned problems, the applicant proposed a power amplifier based on a PIN switch and a design method thereof. The circuit structure of the output matching circuit network is changed by changing the working state of the PIN switch in the output matching circuit, thereby realizing a reconfigurable function, so that the power amplifier has good working performance in different modes and different frequency bands. In order to further improve the performance of the reconfigurable power amplifier, the input matching circuit also adopts the same design method.

[0040] See also Figure 1 , which is a schematic diagram of the structure of a reconfigurable power amplifier based on a PIN switch of the present invention, including a reconfigurable input matching network, a gate bias network, a transistor, a drain bias network and a reconfigurable output matching network, wherein,

[0041] The input end of the reconfigurable input matching network is adapted to and connected to the input port, the output end thereof is connected to the transistor gate, and the gate bias circuit is connected in parallel to the transistor gate;

[0042] The transistor drain is connected in parallel with the drain bias circuit, and the transistor drain is connected to the input end of the reconfigurable output matching network;

[0043] The reconfigurable input matching circuit includes a trunk microstrip line and a reconfigurable structure;

[0044] The trunk microstrip line is respectively connected to the input port, the transistor and the bias circuit; the trunk microstrip line is connected to a plurality of reconfigurable structures;

[0045] The reconfigurable structure is composed of a PIN switch and a microstrip line in series;

[0046] The output port is adapted to and connected to the reconfigurable output matching circuit.

[0047] See also Figure 2 , shown is the network topology of the drain bias circuit. The drain bias circuit supplies power to the transistor while requiring the loss to be minimized in the frequency band in which the reconfigurable power amplifier operates. The drain bias circuit includes an eighth microstrip line TL8, a ninth microstrip line TL9, a tenth microstrip line TL10 and a DC blocking capacitor C1, wherein one end of the eighth microstrip line TL8 is connected to the transistor drain, the other end of the eighth microstrip line TL8 is connected to the ninth microstrip line TL9 and the tenth microstrip line TL10, the ninth microstrip line TL9 is a parallel open microstrip line, and the other end of the tenth microstrip line TL10 is connected to the drain power supply.

[0048] The gate bias circuit adopts the same circuit structure as the drain bias circuit.

[0049] Furthermore, the calculation of the microstrip line parameters of the drain bias circuit is explained:

[0050] The two specific parameters of the microstrip line are the characteristic impedance Z n and electrical length θ n , where the characteristic impedance Z n is a free parameter, and the parameter to be sought is the electrical length θ n At the same time, for separate explanation, when the working frequency points of the working frequency band are f1 and f2, the corresponding electrical lengths and characteristic impedances are θ1 and θ2, Z1 and Z2, respectively, where n = f2 / f1.

[0051] The network topology of the drain bias circuit includes serial microstrip lines TL8 and TL10, parallel microstrip line TL10 and short-circuit capacitor C1, wherein the electrical length of TL8 and TL9 is 90°, the characteristic impedance is 50Ω, and the frequency is 2.6GHz, so the impedance of point B is 0 ohm at 2.6GHz, and the impedance of point C at 2.6GHz is infinite after the electrical length of 90° TL8, and no RF signal will pass through the bias circuit to damage the DC power supply, and the RF open circuit has not been realized at 1.75GHz, so the electrical length of TL10 needs to be calculated. Point A is connected to the ground by the short-circuit capacitor C1, so the impedance of point A is 0Ω,

[0052] The impedance from point A to point B is

[0053]

[0054] The impedance from the ninth microstrip line TL9 to point B is

[0055]

[0056] The impedance of point B at f1 is

[0057]

[0058] The impedance from point B to point C is

[0059]

[0060] To achieve RF open circuit, the impedance Zc of C must be infinite at 1.75GHz. A It is known that the characteristic impedance and electrical length of the eighth microstrip line TL8 and the ninth microstrip line TL9 are known, and the characteristic impedance of the tenth microstrip line TL10 is known, and the electrical length of the tenth microstrip line TL10 can be obtained by the above formula.

[0061] See also Figure 3a , shown is the network topology diagram of the matching structure of the traditional reconfigurable power amplifier. The matching networks of each frequency band required are designed in turn and integrated together through PIN switches to form a reconfigurable matching circuit. The matching circuits are directly approximated to be independent of each other and are basically unaffected by each other. The matching network is selected by switches to achieve normal operation in different modes and frequencies. Compared with other reconfigurable matching structures, the design method of this reconfigurable matching structure is relatively simple, but the disadvantages are also obvious. The frequency points that can be integrated in the same power amplifier are very limited. As the operating frequency of the power amplifier increases, the corresponding matching network increases accordingly, and the number of switches required will gradually increase, which will lead to a larger power amplifier size and higher cost.

[0062] See also Figure 3b, shown is a schematic diagram of the optimized reconfigurable output matching network topology structure, which realizes frequency band switching by adding a reconfigurable structure composed of a PIN switch and a reconfigurable microstrip line, including a PIN switch 1, a PIN switch 2, a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6 and a seventh microstrip line TL7, wherein the microstrip lines TL1, TL2, TL3, and TL4 are series microstrip lines, and TL5, TL6, and TL7 are parallel microstrip lines; the drain of the transistor is connected to the first microstrip line TL1, the other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the fifth microstrip line TL5, one end of the second microstrip line TL2 is connected to one end of the third microstrip line TL3 and one end of the PIN switch 1, and the other end of the PIN switch 1 is connected to the sixth microstrip line TL L6 is connected, the other end of the third microstrip line TL3 is connected to one end of the fourth microstrip line TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip line TL7; when the PIN switch 1 is closed and the PIN switch 2 is opened, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the sixth microstrip line TL6 together constitute a matching circuit, while the seventh microstrip line TL7 does not participate in the matching, and the output matching at 1.75GHz is achieved; when the PIN switch 1 is opened and the PIN switch 2 is closed, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the seventh microstrip line TL7 together constitute a matching circuit, while the sixth microstrip line TL6 does not participate in the matching, and the output matching at 2.6GHz is achieved. Compared with the traditional reconfigurable matching structure, the optimized reconfigurable output matching structure has a smaller circuit size, improved debugging possibilities, smaller losses, and a simpler structure.

[0063] Furthermore, the design and working principle of the reconfigurable matching network is further explained:

[0064] The specific parameters of the microstrip line are the electrical length θ n and characteristic impedance Z n In order to determine the specific parameters of each microstrip line, it is necessary to obtain the optimal fundamental impedance at the center frequencies f1 and f2 through load-pull technology, and the optimal fundamental impedance Z at the center frequencies of 1.75 GHz and 2.6 GHz are obtained respectively. f1 and Z f2 .

[0065] The impedance from point C through the first microstrip line TL1 to point D is

[0066]

[0067]

[0068] The impedance from the open point through the fifth microstrip line TL5 to point D is

[0069]

[0070]

[0071] So the total impedance at point D is

[0072]

[0073]

[0074] The impedance from point D through the second microstrip line TL2 to point E is

[0075]

[0076]

[0077] The impedance from the open point through the sixth microstrip line TL6 to point E is

[0078]

[0079] So the total impedance at point E at f1 is

[0080]

[0081] At f2, the sixth microstrip line TL6 does not participate in the matching, so the impedance of point E at f2 is

[0082] Z E (f2) = Z E1 (f2) (15)

[0083] The impedance from point E through the third microstrip line TL3 to point F is

[0084]

[0085]

[0086] The impedance from the open point through the seventh microstrip line TL7 to point F is

[0087]

[0088] At f1, the sixth microstrip line TL7 does not participate in the matching, so the impedance of point F at f1 is

[0089] Z F (f1) = Z F1 (f1) (19)

[0090] So the total impedance at point F at f2 is

[0091]

[0092] The impedance from point F through the fourth microstrip line TL4 to point G is

[0093]

[0094]

[0095] Transformed into real impedance through reconfigurable output matching network As the output impedance of the design. However, the switch is not an ideal device, so there will be a certain degree of mutual influence, so it needs to be tuned and corrected according to power and efficiency.

[0096] If the impedance of point G is 50 ohms at both frequencies, it means that a good match has been achieved between the transistor and the load.

[0097] The present invention is based on a design method of a reconfigurable power amplifier based on a PIN switch, which is implemented by the following steps:

[0098] Step S1: performing multiple load pulls and source pulls on the GaN HEMT CGH40010F transistor, and obtaining the optimal load impedance and optimal source impedance of the transistor at power added efficiency and maximum output power;

[0099] Step S2: The gate bias network and the drain bias network are designed by using the design concept that a quarter-wavelength microstrip line can realize real impedance transformation to ensure that the power amplifier has a stable DC supply voltage. However, a single quarter-wavelength line cannot realize RF open circuit in two frequency bands, so the bias circuit is optimized and three microstrip lines TL8, TL9, TL10 and a short-circuit capacitor C1 are used to form it, wherein the microstrip lines TL8 and TL10 are series microstrip lines, and the microstrip line TL9 is a parallel microstrip line, wherein the electrical lengths and characteristic impedances of the microstrip lines TL8, TL9, and TL10 are θ8, θ9, θ10, respectively. 10 and Z8, Z9, Z 10 In order to satisfy the RF open circuit at both 1.75 GHz and 2.6 GHz and prevent the RF signal from damaging the current source, the above equations (1), (2), and (3) need to be satisfied at the same time, which is equivalent to a quarter-wavelength line. The transmission matrix of the quarter-wavelength line is

[0100]

[0101] The characteristic parameters of the microstrip line are obtained by calculation;

[0102] Step S3: Design a reconfigurable output matching circuit, observe the trajectory of the optimal load impedance at different frequencies along the Smith chart after passing through the microstrip line, and use the optimized reconfigurable output matching structure to find the appropriate electrical length and characteristic impedance of the microstrip line. When the center frequency is f1, the output matching network is equivalent to being composed of series microstrip lines TL1, TL2, TL3, TL4 and parallel microstrip lines TL5 and TL6. When the center frequency is f2, the output matching network is equivalent to being composed of series microstrip lines TL1, TL2, TL3, TL4 and parallel microstrip lines TL5 and TL7, where the electrical length and characteristic impedance of the microstrip line TL1 are θ1 and Z1, and the impedance of point D after passing through the microstrip line TL1 is

[0103]

[0104]

[0105] Then substitute into the above equations (7) to (22). Due to the large amount of calculation, the characteristic parameters and electrical length of each microstrip line are calculated by Matlab, so that the final impedance at point G is close to the standard 50 ohms.

[0106] Step S4: Design a reconfigurable structure, which is composed of a PIN switch and a reconfigurable branch node. The reconfigurable output matching network realizes the reconstruction of the output matching network by changing the switching state of the PIN switch in the reconfigurable structure. After the electrical length θ and the characteristic impedance Z of the reconfigurable microstrip line have been determined for the matching circuit trunk, that is, the electrical length and characteristic impedance of the microstrip lines TL1, TL2, TL3, TL4, and TL5 have been determined, the characteristic impedance and electrical length of the microstrip line TL6 are continuously adjusted at 1.75 GHz so that the output impedance of point G is exactly 50 ohms; similarly, at 2.6 GHz, the characteristic impedance and electrical length of the microstrip line TL7 are continuously adjusted so that the output impedance of point G is exactly 50 ohms.

[0107] Step S5: designing a reconfigurable input matching network, using the same design method as the output matching circuit, so that the reconfigurable power amplifier has better performance;

[0108] Step S6: Combine steps S1, S2, S3, S4, and S5 to build an overall circuit structure, and use ADS software to perform circuit simulation and optimization to ensure optimal performance.

[0109] The technical effect of the present invention is further demonstrated through simulation experiments, wherein: Figure 4a It is a schematic diagram of the S parameter simulation result of the reconfigurable matching circuit of the present invention at f1; Figure 4b It is a schematic diagram of the S parameter simulation result of the reconfigurable matching circuit of the present invention at f2; Figure 5aIt is a simulation result diagram of the output power, efficiency and gain of the reconfigurable power amplifier based on the PIN switch of the present invention at f1; Figure 5b This is a simulation result diagram of the output power, efficiency and gain of the reconfigurable power amplifier based on PIN switch at f1 of the present invention. It can be seen from the simulation results that when the center frequency is 1.75GHz, the saturated output power is 41.63dbm, the gain is 11.63dB, and the drain efficiency is 69%. When the center frequency is 2.6GHz, the saturated output power is 40.48dbm, the gain is 10.48dB, and the drain efficiency is 65%. Compared with the performance of other dual-frequency power amplifiers, the drain efficiency is about 60%, and the output power is about 40dBm. It can be seen that the performance has been significantly improved, and the expected purpose has been basically achieved.

[0110] The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. It is obvious to those skilled in the art that various modifications to these embodiments can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A reconfigurable power amplifier based on a PIN switch, characterized in that: At least includes an equal input port, a reconfigurable input matching circuit, a gate bias circuit, a transistor, a reconfigurable output matching circuit, a drain bias circuit and an output port; wherein, The input end of the reconfigurable input matching network is adapted to and connected to the input port, the output end thereof is connected to the transistor gate, and the gate bias circuit is connected in parallel to the transistor gate; The transistor drain is connected in parallel with the drain bias circuit, and the transistor drain is connected to the input end of the output matching network; The reconfigurable input matching circuit comprises a trunk microstrip line and a reconfigurable structure, wherein the trunk microstrip line is used to connect the input port, the transistor and the bias circuit; the trunk microstrip line is connected to a plurality of reconfigurable structures; the reconfigurable structure is formed by connecting a PIN switch and a microstrip line in series; The output port is adapted to and connected to the output matching circuit; The reconfigurable output matching circuit includes a PIN switch 1, a PIN switch 2, a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6 and a seventh microstrip line TL7, wherein the microstrip lines TL1, TL2, TL3 and TL4 are series microstrip lines, and TL5, TL6 and TL7 are parallel microstrip lines; the drain of the transistor is connected to one end of the first microstrip line TL1, the other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the fifth microstrip line TL5, the other end of the second microstrip line TL2 is connected to one end of the third microstrip line TL3 and one end of the PIN switch 1, and the other end of the PIN switch 1 is connected to the sixth microstrip line TL6, The other end of the third microstrip line TL3 is connected to one end of the fourth microstrip line TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip line TL7; when the PIN switch 1 is closed and the PIN switch 2 is opened, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the sixth microstrip line TL6 together constitute a matching circuit, while the seventh microstrip line TL7 does not participate in the matching; when the PIN switch 1 is opened and the PIN switch 2 is closed, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the seventh microstrip line TL7 together constitute a matching circuit, while the sixth microstrip line TL6 does not participate in the matching; The drain bias circuit includes an eighth microstrip line TL8, a ninth microstrip line TL9, a tenth microstrip line TL10 and a DC blocking capacitor C1, wherein one end of the eighth microstrip line TL8 is connected to the transistor drain, the other end of the eighth microstrip line TL8 is connected to the ninth microstrip line TL9 and the tenth microstrip line TL10, the ninth microstrip line TL9 is a parallel open microstrip line, and the other end of the tenth microstrip line TL10 is connected to the drain power supply; The reconfigurable output matching circuit includes a reconfigurable structure; The reconfigurable structure can be combined and switched to achieve frequency band switching between 1.75G and 2.6G.

2. The reconfigurable power amplifier based on PIN switch according to claim 1, characterized in that: The gate bias circuit adopts the same circuit structure as the drain bias circuit.

3. A design method for a reconfigurable power amplifier based on a PIN switch, characterized in that: The steps include: Step S1: performing multiple load pulls and source pulls on the GaN HEMT CGH40010F transistor, and obtaining the optimal load impedance and optimal source impedance of the transistor at power added efficiency and maximum output power; Step S2: adopting the design concept that a quarter-wavelength microstrip line can realize real impedance transformation to design a gate bias network and a drain bias network to ensure that the power amplifier has a stable DC power supply voltage, wherein three microstrip lines TL8, TL9, TL10 and a short-circuit capacitor C1 are adopted, wherein the microstrip lines TL8 and TL10 are series microstrip lines, and the microstrip line TL9 is a parallel microstrip line; Step S3: designing a reconfigurable output matching circuit, optimizing the reconfigurable output matching structure by taking the optimal load impedance at different frequencies through the microstrip line and following the track on the Smith chart, and finding a suitable microstrip line electrical length and characteristic impedance; The reconfigurable output matching circuit includes a PIN switch 1, a PIN switch 2, a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth microstrip line TL4, a fifth microstrip line TL5, a sixth microstrip line TL6 and a seventh microstrip line TL7, wherein the microstrip lines TL1, TL2, TL3 and TL4 are series microstrip lines, and TL5, TL6 and TL7 are parallel microstrip lines; the drain of the transistor is connected to one end of the first microstrip line TL1, the other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the fifth microstrip line TL5, the other end of the second microstrip line TL2 is connected to one end of the third microstrip line TL3 and one end of the PIN switch 1, and the other end of the PIN switch 1 is connected to the sixth microstrip line TL6, The other end of the third microstrip line TL3 is connected to one end of the fourth microstrip line TL4 and one end of the PIN switch 2, and the other end of the PIN switch 2 is connected to the seventh microstrip line TL7; when the PIN switch 1 is closed and the PIN switch 2 is opened, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the sixth microstrip line TL6 together constitute a matching circuit, while the seventh microstrip line TL7 does not participate in the matching; when the PIN switch 1 is opened and the PIN switch 2 is closed, the first microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, the fourth microstrip line TL4, the fifth microstrip line TL5 and the seventh microstrip line TL7 together constitute a matching circuit, while the sixth microstrip line TL6 does not participate in the matching; Step S4: design a reconfigurable structure, which is composed of a PIN switch and a reconfigurable branch. The output matching network is reconfigured by changing the switch state of the PIN switch in the reconfigurable structure. Since the electrical lengths and characteristic impedances of the microstrip lines TL1, TL2, TL3, TL4, and TL5 have been determined, the characteristic impedance and electrical length of the microstrip line TL6 are continuously adjusted at 1.75 GHz, so that the output impedance of the G point is exactly 50 ohms; similarly, at 2.6 GHz, the characteristic impedance and electrical length of the microstrip line TL7 are continuously adjusted, so that the output impedance of the G point is exactly 50 ohms; Step S5: designing a reconfigurable input matching network, using the same design method as the output matching circuit, so that the reconfigurable power amplifier has better performance; Step S6: Combine steps S1, S2, S3, S4, and S5 to build an overall circuit structure, and use ADS software to perform circuit simulation and optimization to ensure optimal performance.

4. The design method of a reconfigurable power amplifier based on a PIN switch according to claim 3, characterized in that: The drain bias circuit includes an eighth microstrip line TL8, a ninth microstrip line TL9, a tenth microstrip line TL10 and a DC blocking capacitor C1, wherein one end of the eighth microstrip line TL8 is connected to the transistor drain, the other end of the eighth microstrip line TL8 is connected to the ninth microstrip line TL9 and the tenth microstrip line TL10, the ninth microstrip line TL9 is a parallel open microstrip line, and the other end of the tenth microstrip line TL10 is connected to the drain power supply.

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