In-die metrology method and system for process control

Abstract

Systems and methods for performing in-die metrology using a target design pattern are provided. These systems and methods include: selecting a target design pattern based on design data representing a design of an integrated circuit; providing design data indicative of the target design pattern to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data. The systems and methods may also include: causing a structure derived from the second design data to be printed on a wafer; using a charged particle beam tool to inspect the structure on the wafer; and identifying metrology data or process defects based on the inspection. In some embodiments, the systems and methods also include: adjusting the charged particle beam tool, the second design data, a scanner, or a lithographic device based on the identified metrology data or process defects.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 62 / 787,203, filed December 31, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments provided herein relate to in-die metrology methods and systems for process control, and more particularly to methods and systems for identifying and placing in-die metrology target areas to identify defects in semiconductor manufacturing and operating processes. Background Art

[0004] During the manufacture of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes such as scanning electron microscopes (SEMs) may be employed. As the physical size of IC components continues to shrink, the accuracy and yield of defect detection become increasingly important. However, the imaging resolution and throughput of inspection tools struggle to keep up with the shrinking feature sizes of IC components. Summary of the invention

[0005] In some embodiments of the present disclosure, systems and methods for in-die measurement using a target design pattern are provided. Systems and methods for in-die measurement using a target design pattern are provided. These systems and methods include: selecting a target design pattern based on design data representing a design of an integrated circuit; providing design data indicating the target design pattern so that design data derived from the target design pattern can be added to second design data, wherein the second design data is based on the first design data. The systems and methods may also include: causing a structure derived from the second design data to be printed on a wafer; using a charged particle beam tool to inspect the structure on the wafer; and identifying measurement data or process defects based on the inspection. In some embodiments, the systems and methods also include: causing the charged particle beam tool, the second design data, the scanner, or the lithography equipment to be adjusted based on the identified measurement data or process defects.

[0006] In some embodiments, the design data representing the design of the integrated circuit is represented as one of a Graphic Database System (GDS), Open Artifact System Interchange Standard (OASIS), and Caltech Intermediate Format (CIF) data file.

[0007] In some embodiments, the identified metrology data or process defect is at least one of edge placement error, overlay shift, contact hole size variation, and edge roughness.

[0008] In yet another embodiment, the system and method further include selecting a target design pattern from a design library based on the attributes associated with the target design pattern, wherein the design library includes design patterns and corresponding attributes.

[0009] In yet another embodiment, the system and method further include analyzing process window qualification data associated with one or more potential target design patterns, and based on the analysis results, selecting a target design pattern.

[0010] In other embodiments, the systems and methods include analyzing design data associated with a target design pattern, and based on the analysis results, selecting the target design pattern. In some of those embodiments, the analysis may be a process simulation. In other embodiments, the systems and methods further include selecting the target design pattern based on a similarity between the target design pattern and the design data representing the design of the integrated circuit.

[0011] In yet another embodiment, the design data derived from the target design pattern is added to the second design data at a specified location. In some embodiments, the specified location in the second design data is between components in the second design data.

[0012] In yet another embodiment, the first design data and the second design data represent different versions of layout design data of the integrated circuit.In yet another embodiment, the system and method further include a designated location in the second design layout, which may be located between components in the second design layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure.

[0014] Figure 2 is a schematic diagram illustrating an exemplary electron beam tool consistent with embodiments of the present disclosure, which may be Figure 1 Portions of an exemplary electron beam inspection system.

[0015] Figure 3A-3B is a block diagram illustrating an exemplary wafer consistent with embodiments of the present disclosure.

[0016] Figure 4 is a block diagram illustrating an exemplary wafer consistent with embodiments of the present disclosure.

[0017] Figure 5 is a block diagram illustrating an exemplary target structure consistent with embodiments of the present disclosure.

[0018] Figure 6 is a flow chart representing an exemplary method consistent with embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise indicated, the same reference numerals in different figures represent the same or similar elements. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the present invention. Instead, they are merely examples of devices, systems, and methods consistent with aspects related to the subject matter described in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the present disclosure is not limited thereto. Other types of charged particle beams may be similarly applied.

[0020] The increased computing power of electronic devices can be achieved by significantly increasing the packaging density of circuit components (such as transistors, capacitors, diodes, etc.) on IC chips while reducing the physical size of the devices. For example, the IC chip of a smart phone (which is the size of a thumbnail) can include more than 2 billion transistors, each of which is less than 1 / 1000 the size of a human hair. Therefore, it is not surprising that semiconductor IC manufacturing is a complex and time-consuming process with hundreds of individual steps. Even an error in one step may significantly affect the function of the final product. Even a "fatal defect" may cause device failure. The goal of the manufacturing process is to improve the overall yield of the process. For example, to achieve a 75% yield for a 50-step process, each individual step must have a yield greater than 99.4%, and if the yield of the individual step is 95%, the yield of the entire process will drop to 7%.

[0021] Although high process yields are desirable in IC chip manufacturing facilities, it is also necessary to maintain high wafer throughput, which is defined as the number of wafers processed per hour. High process yields and high wafer throughput may be affected by the presence of defects, especially when operators intervene to check for defects. Therefore, detection and identification of micron- and nano-scale defects by inspection tools (such as SEM) is critical to maintaining high yields and low costs.

[0022] As the size of integrated circuits continues to shrink, the ability of existing inspection systems to identify defects during the manufacturing process also decreases. In particular, optical inspection tools have many disadvantages. To assist in the inspection process, target design patterns are placed on the wafer to measure certain defects. However, due to the size required for optical inspection tools, these patterns are typically larger than 10 μm. 2 , is too large to be placed within the boundaries of the IC chip die. Due to this size, the target design pattern is usually placed on the scribe line (e.g., Figure 3BThe target design pattern is placed on or near the scribing lines 333 and 337 of the wafer, which are the spaces between IC chips on the wafer. However, placing the target design pattern on the scribing lines limits the effectiveness of the target design pattern. When the target design pattern is in the scribing lines, the defects in the target design pattern do not always accurately predict the defects in the chip die because they are too far away from the components of the chip. In addition, optical inspection tools limit the complexity that can be used for the target design pattern.

[0023] Unfortunately, current optical inspection tools using target design patterns and methods for selecting those target design patterns do not meet the need for continuous improvement in manufacturing processes. In order to achieve high throughput and high yield manufacturing processes, new methods are needed to reduce the size and effectiveness of target design patterns.

[0024] In IC chip manufacturing, defect identification can include the use of specially designed electronic structures placed on the wafer. During manufacturing, the target structure can be measured and compared to its original design to help measure the difference between the design of the electronic components on the wafer and the actual production results. Previous systems required the use of large test structures. These test structures were placed in the scribe lines because they were too large to be placed in individual dies without interfering with their ultimate operation. But by using charged particle beam inspection (e.g., electron beam inspection) and improved methods for selecting test structures, the in-die metrology system of the present disclosure can reduce the size of the target structure used to detect defects. Due to the reduced size, the manufacturing system can place the structure close to or in the middle of components of the actual electronic device, such as Figure 4 As shown. In addition, the increased accuracy of the embodiments disclosed herein can allow the use of target design patterns that better match the components of the actual tube core being manufactured. By including test patterns that match the tube core component components and by placing these patterns inside the tube core itself, the embodiments described herein provide better accuracy in measuring defects during manufacturing. The target design pattern inside the tube core ensures that the distance between the design pattern and the important components does not cause differences in the defects measured. In addition, selecting a target design pattern that matches the tube core components increases the chance that defects in the target design pattern will accurately predict defects in the matching tube core component.

[0025] In addition, the increased precision and accuracy of the embodiments described herein allow for use after development inspection ("ADI"). In ADI, a target design pattern can be developed on a silicon wafer and inspected prior to the remainder of the manufacturing process. Thus, corrections can be made prior to etching the actual die. This adjustment made prior to etching the die allows the silicon wafer to be used to produce the die even if defects are measured, which can increase production throughput and improve processing yield. In addition to ADI, the embodiments described herein can also be used with post-etch inspection ("AEI"). In AEI, the silicon wafer is inspected after etching the design on the wafer.

[0026] The increased precision and accuracy of the embodiments described herein may also allow target design patterns to be significantly more complex than other systems. For example, complex two-dimensional patterns may be used. These patterns may include, for example, contact holes and overlay structures, etc. Thus, the embodiments described herein may allow inspection of more advanced structures over typical systems that may be limited to simple one-dimensional patterns, such as simple lines.

[0027] In addition, after the target design pattern is used in manufacturing, the target design pattern and the measured results from their use can be stored in the design library to allow the target design pattern to be used for future manufacturing. The design library can be a database storing design patterns. The design pattern can be stored in a standard layout format (e.g., Graphic Database System (GDS), Caltech Intermediate Format (CIF), Open Source Graphics System Interchange Standard (OASIS), etc.). Together with the design pattern layout, the properties measured according to the previous use of the design pattern can be stored in the design library. Future microchip designers can use known and predictable results to identify the target design pattern that meets their needs by browsing the library.

[0028] IC manufacturing systems consistent with those disclosed herein may also utilize process window qualification ("PWQ"). PWQ involves analyzing structures made using a particular process to determine the process windows for the various structures that make up potential design patterns. Target design patterns may then be selected based on which target design patterns meet the requirements of a particular manufacturing process based on the process window requirements. By selecting target design patterns with smaller windows than the manufacturing requirements, the systems and methods disclosed herein may ensure that defects in the target design patterns may most likely correspond to defects in the die.

[0029] In addition, the shape and layout of the target design pattern can be determined using the analysis of the design file. The analysis can include process simulation and risk analysis. The process can also include any analysis that may be performed using an automated design tool and can include any analysis of the design layout to predict the behavior of the layout. The microchip designer can design the target design pattern and then use the automated design tool to run the simulation of the manufacturing pattern. The results of many simulation runs can be used to predict possible defect rates and process windows. By using these simulation tools, the target design pattern can be designed and implemented based on the simulation results without the need for data from a completed manufacturing run, which may be rare and expensive.

[0030] As used herein, unless otherwise specifically stated, the term "or" encompasses all possible combinations unless not feasible. For example, if it is stated that a database may include A or B, then unless otherwise specified or not feasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then unless otherwise specified or not feasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0031] Additional purposes and advantages of the disclosed embodiments will be partially set forth in the following description, and will partially become apparent from the description, or may be learned through the practice of the embodiments. The purposes and advantages of the disclosed embodiments may be achieved and obtained through the elements and combinations set forth in the present disclosure. However, the exemplary embodiments of the present disclosure do not necessarily need to achieve the exemplary purposes and advantages, and some embodiments may not achieve any of the purposes and advantages.

[0032] Reference now Figure 1 , Figure 1 An exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure is illustrated. The EBI system 100 can be used for imaging. Figure 1 As shown, the EBI system 100 includes a main chamber 101a, a load / lock chamber 102, an electron beam tool 104, and an equipment front end module (EFEM) 106. The electron beam tool 104 is located in the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include additional (multiple) loading ports. The first loading port 106a and the second loading port 106b receive a wafer front end opening box (FOUP) containing a wafer (e.g., a semiconductor wafer or a wafer made of other (multiple) materials) or a sample to be inspected (in this article, the wafer and the sample may be collectively referred to as "wafer"). A "batch" is a plurality of wafers that can be loaded for batch processing.

[0033] One or more robotic arms (not shown) in the EFEM 106 can transport the wafer to the load / lock chamber 102. The load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown) that removes gas molecules in the load / lock chamber 102 to reach a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafer from the load / lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules in the main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by the electron beam tool 104. The electron beam tool 104 can be a single beam system or a multi-beam system. The controller 109 is electronically connected to the electron beam tool 104. The controller 109 can be a computer configured to perform various controls of the EBI system 100. When the controller 109 is in Figure 1 While shown in FIG. 1 as being external to the structure including the main chamber 101 , the load / lock chamber 102 , and the EFEM 106 , it should be understood that the controller 109 may be part of the structure.

[0034] Figure 2 An imaging system 200 is illustrated according to an embodiment of the present disclosure. Figure 2 The electron beam tool 104 may be configured for use in the EBI system 100. Although Figure 2 The electron beam tool 104 is shown as a single beam inspection tool that can use only one primary electron beam to scan one location of the wafer 230 at a time, but the embodiments of the present disclosure are not limited thereto. For example, the electron beam tool 104 can also be a multi-beam inspection tool that uses multiple primary electron beam waves to scan multiple locations on the wafer 230 simultaneously.

[0035] The system 200 can be used to inspect a wafer 230 on a sample stage and includes an electron beam tool 104 as described above. The system 200 also includes an image processing system 199, which includes an image acquisition device 120, a storage device 130, and a controller 109. The image acquisition device 120 may include one or more processors or circuit systems, such as circuit systems of one or more processors or other circuit systems. For example, the image acquisition device 120 may include a computer, a server, a mainframe, a terminal, a personal computer, any kind of mobile computing device, etc., or a combination thereof. The image acquisition device 120 may be connected to a detector 244 of the electron beam tool 104 through a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, infrared (IR), Bluetooth, the Internet, a wireless network, radio, or a combination thereof. The image acquisition device 120 may receive a signal from the detector 244 and may construct an image. The image acquisition device 120 may thus acquire an image of the wafer 230. The image acquisition device 120 may also perform various post-processing functions, such as generating a contour, superimposing an indicator on the acquired image, etc. The image acquirer 120 may be configured to perform adjustments such as brightness and contrast on the acquired image. The storage 130 may be a storage medium such as a hard disk, cloud storage, random access memory (RAM), other types of computer-readable memory, etc. The storage 130 may be coupled to the image acquirer 120 and may be used to save the scanned raw image data as original images and save post-processed images. The image acquirer 120 and the storage 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage 130, and the controller 109 may be integrated together as a control unit.

[0036] In some embodiments, the image acquirer 120 can acquire one or more images of the sample based on the imaging signal received from the detector 244. The imaging signal can correspond to a scanning operation for conducting charged particle imaging. The acquired image can be a single scanned raw image including multiple imaging areas. The image can be stored in the storage 130. The image can be a raw image that can be divided into multiple areas. Each of the areas can include an imaging area containing a feature of the wafer 230.

[0037] Reference now Figure 3A and Figure 3B , Figure 3A and Figure 3B is a diagram of an exemplary wafer 310 consistent with an embodiment of the present disclosure. Figure 1 As discussed, wafer 310 may be, for example, a semiconductor wafer. Figure 3AAs shown, wafer 310 may include multiple dies 320. Die 320 may represent areas of the wafer reserved for specific dies or may represent dies that have been etched onto wafer 310. As understood by one of ordinary skill in the art, a semiconductor device may encompass the entirety represented by each of the dies 320 or some small amount of area of ​​each of the dies 320.

[0038] Figure 3B Included is enlargement 311, which shows an enlarged view of a subset of die 320, die 320A, 320B, 320C, and 320D. Although only die 320A, 320B, 320C, and 320D are shown in enlargement 311, it should be understood that there are additional die 320 surrounding these. Enlargement 311 shows the spaces between die 320A, 320B, 320C, and 320D. These spaces or demarcations between the die are called scribe lines and generally define where the wafer is cut to separate the die 320. As shown in enlargement 311, scribe line 333 passes horizontally through wafer 310, defining the boundaries between semiconductor devices 320A and 320C and semiconductor devices 320B and 320D. Scribe line 337 passes vertically through wafer 310, defining the boundaries between semiconductor devices 320A and 320B and die 320C and 320D. Because scribe lines 333 and 337 define where the wafer will be cut later, components of die 320 generally do not overlap scribe lines 333 and 337, and some space is generally placed between the scribe lines and the components of die 320. As will be discussed in more detail below, previous methods using target design patterns place the target design patterns in these scribe lines so they will not interfere with components of die 320.

[0039] Reference now Figure 4 , Figure 4 3 is an example diagram of a wafer 410. Wafer 410 may be the same wafer as wafer 310 of FIG. 3 or it may be a different wafer. Wafer 410 also includes die 420. Similar to die 320 of FIG. 3, die 420 may represent an etched device or an area on which a die may be etched in the future.

[0040] The die 420 may also include target design patterns 431 and 432. Figure 4 Only the target design patterns 431 and 432 of one of the dies 420 are identified, but it should be understood that Figure 4As indicated by the unidentified black frame within each die in die 420, target design patterns 431 and 432 may be placed in each die in die 420. In addition, target design patterns 431 and 432 may be the same target design pattern or different target design patterns. In addition, different die 420 may contain different target design patterns. Using different target design patterns on different die 420 may be advantageous for many reasons.

[0041] For example, in some embodiments, different dies 420 may include different semiconductor layouts. In these embodiments, the target design pattern selected based on the specific layout of each of semiconductor devices 420 may result in a different target design pattern for each of semiconductors 420. The ability to use different target design patterns based on the specific layout of each of semiconductors 420 may enable more accurate defect identification.

[0042] In some embodiments, different target design patterns may be used based on the location of a particular semiconductor device 420 on wafer 410. For example, dies 420 closer to the periphery of wafer 410 may exhibit different types of manufacturing defects than dies 420 near the center of wafer 410. Thus, target design patterns 431 and 432 may be selected to identify defects that may occur based on the physical location of each of semiconductor devices 420 on wafer 410.

[0043] like Figure 4 As further shown, target design patterns 431 and 432 are placed toward the center of die 420. Because embodiments consistent with the present disclosure utilize electron beam inspection technology, target design patterns 431 and 432 can be an order of magnitude smaller than previous systems. Due to the reduced size, target design patterns 431 and 432 can be placed between components of die 420. By placing the target design patterns closer to the actual components, the defects identified in the target design patterns can more accurately simulate potential defects in the components of die 420. As previously described, this increased accuracy can improve overall yield.

[0044] It should be further understood that in some embodiments, before the components of semiconductor 420 are etched onto wafer 420, target design patterns 431 and 432 are etched onto wafer 410. In these embodiments, sometimes referred to as post-development inspection ("ADI"), the target design patterns can be inspected, and based on the inspection or measured metrology data, adjustments can be made to the design and layout of the IC to account for the measured defects. In some embodiments, the design and layout, scanner, charged particle beam tool or other lithography equipment can be adjusted based on the results of the inspection. The electron beam tool can make adjustments or provide data to the manufacturer, controller or processor or other system attached to the manufacturing system for adjustment. Due to the small size that can be used with the target design patterns 431 and 432, more space on the wafer can be used for the components of the tube core 420 without overlapping with the target design patterns 431 or 432 and increasing the wafer yield.

[0045] The target design pattern can include electronic components of various shapes and sizes. Figure 5 Two exemplary target design patterns are shown, target design pattern 510 and target design pattern 520. Target design patterns 510 and 520 illustrate different shapes and arrangements of components. It should be understood that target design patterns 510 and 520 are merely exemplary, and that many different target design patterns are possible. It should also be understood that the target design patterns may vary in complexity, number, and arrangement of components. This variation may allow the target design pattern to more accurately match a particular die being manufactured (e.g., Figure 4 of tube core 420).

[0046] like Figure 5 As shown, target design pattern 510 may include two rectangular components, target design pattern components 513 and 515. Target design pattern components 513 and 515 may be offset from each other at an angle and may overlap. Target design pattern components 513 and 515 may occupy the same or different layers on a wafer. When used, inspection of a wafer containing target design pattern 510 may reveal changes in the angle or position at which target design pattern components 513 and 515 intersect or the length and width of target design pattern components 513 and 515.

[0047] Target design pattern 520 may include three components, rectangular target design pattern components 523 and 525 and circular target design pattern component 527. In this example, target design pattern components 523 and 525 overlap target design pattern component 527 but do not overlap each other. In addition, target design pattern components 523, 525, and 527 may occupy the same or different layers on a wafer. When used, inspection of a wafer containing target design pattern 520 may reveal changes in the relative positioning, amount of overlap, or other characteristics of target design pattern components 523, 525, and 527.

[0048] As previously discussed, it should be understood that target design patterns 510 and 520 are merely exemplary, and that many different target design patterns exist or can be created consistent with embodiments of the present disclosure. Furthermore, it should be understood that additional target design patterns can be more or less complex, vary in shape and size, and contain more or fewer components than those shown in target design patterns 510 and 520.

[0049] After the target design pattern 510 or 520 is etched into the wafer (eg, Figure 4 After the wafer 410 is formed, an imaging system (e.g., Figure 2 The imaging system 200) can inspect the target design pattern 510 to determine the amount of difference between the expected target design pattern 510 or 520 and the target design pattern 510 or 520 actually deposited on the wafer. The imaging system can also collect measurement data for the target design pattern. Based on the defects or measurement data, the imaging system can be adjusted to account for the measured differences. The measured differences and measurement data can be provided to the designer or design system and used to update the design or layout for the tube core. In some embodiments, the design and layout, scanner, charged particle beam tool or other lithography equipment can be adjusted based on the results of the inspection. The electron beam tool system can make adjustments or provide data to the manufacturer, a controller or processor attached to the manufacturing system, or other system for adjustment. As previously described, because embodiments consistent with the present disclosure can be used when depositing actual tube cores (for example, Figure 4 The target design pattern 510 or 520 is deposited before one or more layers of the die 410 are deposited, so defects can be identified and corrected without discarding the wafer.

[0050] The EBI system (e.g., EBI system 100) or a designer can select a target design pattern to include as part of the overall wafer design. The target design pattern can be stored in a target design pattern library. The library can include the target design pattern and all relevant characteristics of the target design pattern. The target design pattern can be selected based on their similarity to the components of the semiconductor device. In addition, by including previously measured values ​​associated with the target design pattern in the library, the target design pattern can be selected to meet specific process requirements.

[0051] In some embodiments, the target design pattern can be selected based on a process window qualification ("PWQ") analysis of the target design pattern. In the PWQ analysis, a wafer can be used with a focus and dose matrix associated with the wafer. The matrix can show the behavior of the target design pattern under different combinations of focus and exposure or dose during manufacturing. In addition, measurements of the line width of the target design pattern elements or key dimension statistics and total defect counts can be calculated. These results can be analyzed and the process window can be inferred from the measurement results. Target design patterns with loose process windows are less prone to errors. Therefore, the process window required for the manufacturing run can dictate which target design patterns should be selected. A target design pattern with a stricter process window than required by the manufacturing process can be selected to ensure that any defects in the target design pattern will be associated with defects in the die so that appropriate adjustments can be made to increase yield.

[0052] In some embodiments, the target design pattern can be selected based on simulation and risk analysis. In these embodiments, the target design pattern is designed and tested using automated design software. The process can, for example, generate a prediction model for edge placement error (EPE) distribution based on simulation. This will indicate the amount of errors that occur in the overlapping elements of the design relative to each other. A target design pattern with a higher EPE probability can be selected over a target design pattern with a lower EPE probability to ensure that any EPE in the layout will also likely appear in the target design pattern and can be corrected during inspection.

[0053] Based on one or more of the above considerations, embodiments consistent with the present disclosure may select an appropriate target design pattern to meet the requirements of a particular manufacturing process.

[0054] Reference now Figure 6 , Figure 6 FIG. 1 is a flow chart of an exemplary in-die measurement system consistent with an embodiment of the present disclosure. The controller may be programmed to implement Figure 6The controller may be coupled to the charged particle beam device. The controller may control the operation of the charged particle beam device. The controller may be configured to receive information collected from a detector of the charged particle beam device and may be configured to perform processing functions. For example, Figure 1 The controller 109 may be configured to perform Figure 6 all or part of the method.

[0055] In step S101, the method can start. At step S102, a controller or designer can select a target design pattern to include on a wafer. The target design pattern can be selected based on data from one or more of the hotspot library D101, PWQ analysis D102, or process simulation and risk analysis D103. Process simulation can include any analysis that may be performed using automated design tools, and can include any analysis of the design layout to predict the behavior of the layout. The results from these various data sources can be compared with the current manufacturing requirements and designs to select a target design pattern that can help ensure that one or more of these requirements are met and both are closely similar to the overall design.

[0056] After selecting the target design pattern, in step S103, the design data indicating the target design pattern can be provided for adding to the layout of the wafer. In some embodiments, the step of providing the design data indicating the target design pattern also includes providing the target design pattern or the data representing the target design pattern to the manufacturer. In these embodiments, for example, the manufacturer can receive the data representing the target design pattern and add the data to the design data for the integrated circuit. It should also be understood that providing the target design pattern or the data representing the target design pattern includes providing the data to the processor of the SEM or the manufacturer so that the data can be added to the design data for the integrated circuit. Adding data to the design data can be automatically performed by the processor or can be guided by a person using a design application (such as a computer-aided design ("CAD") application). The updated design can then be used to manufacture or produce an integrated circuit. These target design patterns can then be etched onto the wafer by selecting a system, process or equipment of the target design pattern or by a manufacturer receiving the design data.

[0057] Due to the electron beam inspection method used in accordance with the present disclosure, the target design pattern can be very small. For example, in some embodiments, the target design pattern can be as small as 1 μm. 2 Furthermore, due to their small size, the provided design data may include locations that enable target design patterns to be placed within the semiconductor design, rather than restricting the locations to, for example, within or near a scribe line.

[0058] In step S104, the system may cause the structure of the design layout to be printed on the wafer. In some embodiments, causing the structure of the design layout to be printed results from, for example, an instruction from a manufacturer to print the design layout with the added target design pattern. The design data is data representing the design layout of the integrated circuit. In some embodiments, the target design pattern is placed on the wafer before depositing the rest of the design.

[0059] In step S105, the printed target design pattern is inspected using a charged particle inspection tool (e.g., such as Figure 2 The inspection results are analyzed by a charged particle beam system (e.g., EBI system 200). In step S106, the inspection results are analyzed by a charged particle beam system (e.g., EBI system 200). The analysis can reveal defects from the manufacturing process, such as, for example, EPE, overlay shift, contact hole size and edge roughness, and additional measurement data. The analysis results for a specific target design pattern can be included in a hotspot library D101 for use in subsequent processes.

[0060] In step S107, the charged particle beam system or computer system can use the results of the analysis to cause adjustments to the layout or design of the die, or cause adjustments to the settings of the scanner or other lithography equipment used to pattern the die. In some embodiments, these adjustments can be made by the charged particle beam system. In other embodiments, the charged particle beam system can provide data about the adjustments to other systems or equipment (e.g., other lithography equipment, scanners, or controllers or processors attached to the equipment) to make adjustments. Because embodiments consistent with the present disclosure allow ADI, the layout adjustments provided in step S107 can occur before the semiconductor design is etched onto the wafer, and the scanner settings adjustments in step S107 can occur before the semiconductor design is patterned onto the wafer. In addition, the layer with defects can be de-processed (e.g., removed from the wafer), and the layer can be reprocessed and re-imaged by the scanner but with the adjusted scanner settings or design. Because the wafer can still be used for manufacturing in the adjusted system, the system can increase the yield by detecting and adjusting the layout or scanner settings for these defects at this stage.

[0061] The process may end in step S108.

[0062] In some embodiments, the detector can communicate with a controller that controls the charged particle beam system. The controller can instruct components of the charged particle beam system to perform various functions, such as controlling a charged particle source to generate a charged particle beam and controlling a deflector to scan the charged particle beam over a sample. The controller can also perform post-processing functions, brightness / contrast adjustment, image segmentation, image processing, generating contours, superimposing indicators on acquired images, etc. The controller can, for example, Figure 1The functions of the controller 109 and the image acquirer 120 are combined. In addition, the controller may include a Figure 1 The storage 130 of storage. Non-temporary computer readable medium can be provided, and storage is used for the processor execution of controller 109 to select target design pattern, charged particle beam inspection, analysis target design pattern result, based on analysis adjustment particle beam scanner or other functions and methods consistent with the present disclosure. Common forms of non-temporary medium include, for example, floppy disk (floppydisk), floppy disk (flexible disk), hard disk, solid state drive, magnetic tape or any other magnetic data storage medium, CD-ROM, any other optical data storage medium, any physical medium with pattern of hole, RAM, PROM and EPROM, FLASH-EPROM or any other flash memory, NVRAM, cache, register, any other memory chip or cassette tape and their networked versions.

[0063] The embodiments may be further described using the following terms:

[0064] 1. A method related to in-die metrology using a charged particle beam tool, the method comprising:

[0065] selecting a target design pattern based on first design data representing a design of the integrated circuit; and

[0066] Design data indicative of a target design pattern is provided to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data.

[0067] 2. The method of clause 1, wherein the first design data is represented as one of Graphic Database System (GDS), Open Artifact System Interchange Standard (OASIS), or Caltech Intermediate Format (CIF) data.

[0068] 3. The method according to any one of clauses 1 and 2, further comprising:

[0069] causing a structure derived from the second design data to be printed on a wafer;

[0070] Using charged particle beam tools to inspect structures on the wafer; and

[0071] Based on the inspection, measurement data or process defects are identified.

[0072] 4. The method of clause 3, further comprising causing the second design data to be adjusted based on the identified metrology data or process defects.

[0073] 5. The method of clause 3, further comprising causing the scanner to be adjusted based on the identified metrology data or process defects.

[0074] 6. The method of clause 3, further comprising causing the lithographic apparatus to be adjusted based on the identified metrology data or process defects.

[0075] 7. The method of any of clauses 3-6, wherein the identified metrology data or process defect is at least one of edge placement error, overlay shift, contact hole size variation, and edge roughness.

[0076] 8. The method according to any one of clauses 1 to 7, wherein selecting a target design pattern further comprises:

[0077] A target design pattern is selected from a design library based on attributes associated with the target design pattern, wherein the design library includes design patterns and corresponding attributes.

[0078] 9. The method according to any one of clauses 1 to 8, wherein selecting a target design pattern further comprises:

[0079] analyzing process window qualification data associated with one or more potential target design patterns; and

[0080] Based on the analysis results, a target design pattern is selected.

[0081] 10. The method according to any one of clauses 1 to 9, wherein selecting a target design pattern further comprises:

[0082] analyzing design data associated with a target design pattern; and

[0083] Based on the analysis results, a target design pattern is selected.

[0084] 11. The method of clause 10, wherein the analysis is a process simulation.

[0085] 12. The method according to any one of clauses 1 to 11, wherein selecting a target design pattern further comprises:

[0086] Based on the similarity between the target design pattern and the first design data, a target design pattern is selected.

[0087] 13. A method according to any of clauses 1-12, wherein the design data derived from the target design pattern is added to the second design data at a specified position.

[0088] 14. The method of clause 13, wherein the specified position in the second design data is between components in the second design data.

[0089] 15. A method according to any of clauses 1-14, wherein the first design data and the second design data represent different versions of layout design data of the integrated circuit.

[0090] 16. A system for in-die metrology, comprising:

[0091] Charged particle beam equipment, including detectors;

[0092] an image acquirer including circuitry that receives the detection signal from the detector and constructs an image including a target design pattern; and

[0093] A controller having at least one processor and a non-transitory computer readable medium including instructions that, when executed by the processor, cause the system to:

[0094] selecting a target design pattern based on first design data representing a design of the integrated circuit; and

[0095] Design data indicative of a target design pattern is provided to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data.

[0096] 17. The system of clause 16, wherein the first design data is represented as one of Graphic Database System (GDS), Open Artifact System Interchange Standard (OASIS), or Caltech Intermediate Format (CIF) data.

[0097] 18. A system according to any of clauses 16 and 17, wherein the instructions, when executed by the processor, further cause the system to:

[0098] causing a structure derived from the second design data to be printed on a wafer;

[0099] Using charged particle beam tools to inspect structures on the wafer; and

[0100] Based on the inspection, measurement data or process defects are identified.

[0101] 19. The system of clause 18, wherein the instructions, when executed by the processor, further cause the system to: cause the second design data to be adjusted based on the identified metrology data or process defect.

[0102] 20. The system of clause 18, wherein the instructions, when executed by the processor, further cause the system to: cause the scanner to be adjusted based on the identified metrology data or process defect.

[0103] 21. The system of clause 18, wherein the instructions, when executed by the processor, further cause the system to: cause the lithographic apparatus to be adjusted based on the identified metrology data or process defect.

[0104] 22. The system of any of clauses 18-21, wherein the identified process defect is at least one of edge placement error, overlay shift, contact hole size variation, and edge roughness.

[0105] 23. A system according to any of clauses 16-22, further comprising:

[0106] Memory;

[0107] A design library is stored in the memory, wherein the design library includes design patterns and corresponding attributes.

[0108] 24. A system according to any of clauses 16-24, wherein the instructions, when executed by the processor, further cause the system to:

[0109] analyzing process window qualification data associated with one or more potential target design patterns; and

[0110] Based on the analysis results, a target design pattern is selected.

[0111] 25. A system according to any of clauses 16-25, wherein the instructions, when executed by the processor, further cause the system to:

[0112] analyzing design data associated with a target design pattern; and

[0113] Based on the analysis results, a target design pattern is selected.

[0114] 26. The system of clause 25, wherein the analysis is a process simulation.

[0115] 27. The system of any of clauses 16-26, wherein the instructions, when executed by the processor, further cause the system to: select a target design pattern based on a similarity between the target design pattern and the first design data.

[0116] 28. A system according to any of clauses 16-27, wherein the design data derived from the target design pattern is added to the second design data at a specified location.

[0117] 29. The system of clause 28, wherein the specified position in the second design data is between components in the second design data.

[0118] 30. A system according to any of clauses 16-29, wherein the first design data and the second design data represent different versions of layout design data of the integrated circuit.

[0119] 31. A non-transitory computer readable medium storing a set of instructions executable by one or more processors of a system to cause the system to perform a method comprising:

[0120] selecting a target design pattern based on first design data representing a design of the integrated circuit; and

[0121] Design data indicative of a target design pattern is provided to enable design data derived from the target design pattern to be added to second design data, wherein the second design data is based on the first design data.

[0122] 32. The computer-readable medium of clause 31, wherein the first design data is represented as one of Graphic Database System (GDS), Open Artifact System Interchange Standard (OASIS), or Caltech Intermediate Format (CIF) data.

[0123] 33. A computer-readable medium according to any of clauses 31 and 32, wherein the set of instructions executable by one or more processors of the system causes the system to further perform:

[0124] causing a structure derived from the second design data to be printed on a wafer;

[0125] Using charged particle beam tools to inspect structures on the wafer; and

[0126] Based on the inspection, measurement data or process defects are identified.

[0127] 34. The computer-readable medium of clause 33, wherein the set of instructions executable by one or more processors of the system causes the system to further perform: causing the second design data to be adjusted based on the identified metrology data or process defect.

[0128] 35. The computer-readable medium of clause 33, wherein the set of instructions executable by one or more processors of the system causes the system to further perform: causing the scanner to be adjusted based on the identified metrology data or process defects.

[0129] 36. The computer-readable medium of clause 33, wherein the set of instructions executable by one or more processors of the system causes the system to further perform: causing the lithographic apparatus to be adjusted based on the identified metrology data or process defect.

[0130] 37. The computer-readable medium of any of clauses 33-36, wherein the identified metrology data or process defect is at least one of edge placement error, overlay shift, contact hole size variation, and edge roughness.

[0131] 38. A computer-readable medium according to any of clauses 31-37, wherein the set of instructions executable by one or more processors of the system causes the system to further perform:

[0132] A target design pattern is selected from a design library based on attributes associated with the target design pattern, wherein the design library includes design patterns and corresponding attributes.

[0133] 39. A computer-readable medium according to any of clauses 31-38, wherein the set of instructions executable by one or more processors of the system causes the system to further perform:

[0134] analyzing process window qualification data associated with one or more potential target design patterns; and

[0135] Based on the analysis results, a target design pattern is selected.

[0136] 40. A computer-readable medium according to any of clauses 31-39, wherein the set of instructions executable by one or more processors of the system causes the system to further perform:

[0137] analyzing design data associated with a target design pattern; and

[0138] Based on the analysis results, a target design pattern is selected.

[0139] 41. The computer-readable medium of clause 40, wherein the analysis is a process simulation.

[0140] 42. A computer-readable medium according to any of clauses 31-41, wherein the set of instructions executable by one or more processors of the system causes the system to further perform:

[0141] Based on the similarity between the target design pattern and the first design data, a target design pattern is selected.

[0142] 43. The computer-readable medium of any of clauses 31-42, wherein the design data derived from the target design pattern is added to the second design data at a specified location.

[0143] 44. The computer-readable medium of clause 43, wherein the specified location in the second design data is between components in the second design data.

[0144] 45. The computer-readable medium of any of clauses 31-44, wherein the first design data and the second design data represent different versions of layout design data of the integrated circuit.

[0145] The block diagram in the figure shows the architecture, function and operation of the possible implementation of the system, method and computer hardware / software product according to various exemplary embodiments of the present disclosure. In this regard, each frame in the schematic diagram can represent certain arithmetic or logic operations that can be implemented using hardware such as electronic circuits. The frame can also represent a module, segment or code portion including one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative implementations, the functions indicated in the frame may not occur in the order marked in the figure. For example, depending on the function involved, the two frames shown in succession can be performed or implemented substantially simultaneously, or the two frames can sometimes be performed in reverse order. Some frames can also be omitted.

[0146] It will also be understood that each block of the block diagrams and combinations of blocks can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0147] Although the present invention has been described in conjunction with various embodiments, other embodiments of the present invention will be apparent to those skilled in the art in view of the specification and practice of the invention disclosed herein. The specification and embodiments are to be considered exemplary only, with the true scope and spirit of the present invention being indicated by the appended claims.

Claims

1. A non-transitory computer readable medium storing a set of instructions, the set of instructions being executable by one or more processors of a system to cause the system to perform a method comprising: selecting a target design pattern based on first design data representing a design of the integrated circuit; and providing design data indicative of the target design pattern so that design data derived from the target design pattern can be added to second design data representing a layout design of the integrated circuit, wherein the second design data is based on the first design data, The first design data and the second design data relate to the position of the integrated circuit on the die and / or the size of the integrated circuit.

2. The computer-readable medium of claim 1, wherein the first design data is represented as one of Graphic Database System (GDS), Open Artifact System Interchange Standard (OASIS), or Caltech Intermediate Format (CIF) data.

3. The computer-readable medium of claim 1 , wherein the set of instructions executable by one or more processors of the system causes the system to further perform: inspecting the structure on the wafer using a charged particle beam tool after the structure derived from the second design data is printed on the wafer; and Based on the inspection, metrology or process defects are identified.

4. The computer-readable medium of claim 3, wherein the set of instructions executable by one or more processors of a system causes the system to further perform: causing the second design data to be adjusted based on the identified metrology data or process defects.

5. The computer readable medium of claim 3, wherein the identified metrology data or process defect is at least one of edge placement error, overlay shift, contact hole size variation, and edge roughness.

6. The computer-readable medium of claim 1 , wherein the set of instructions executable by one or more processors of a system causes the system to further perform: The target design pattern is selected from a design library based on attributes associated with the target design pattern, wherein the design library includes design patterns and corresponding attributes.

7. The computer-readable medium of claim 1, wherein the set of instructions executable by one or more processors of a system causes the system to further perform: analyzing process window qualification data associated with one or more potential target design patterns; and Based on the results of the analysis, the target design pattern is selected.

8. The computer-readable medium of claim 1, wherein the set of instructions executable by one or more processors of a system causes the system to further perform: analyzing design data associated with the target design pattern; and Based on the results of the analysis, the target design pattern is selected.

9. The computer-readable medium of claim 7, wherein the analysis comprises a process simulation.

10. The computer-readable medium of claim 1, wherein the set of instructions executable by one or more processors of a system causes the system to further perform: The target design pattern is selected based on a similarity between the target design pattern and the first design data.

11. The computer-readable medium of claim 1, wherein the design data derived from the target design pattern is added to the second design data at a specified position.

12. The computer-readable medium of claim 11, wherein the designated location in the second design data is between components in the second design data.

13. The computer-readable medium of claim 1, wherein the first design data and the second design data represent different versions of layout design data for the integrated circuit.

14. A system for in-die metrology, comprising: Charged particle beam equipment, including detectors; an image acquirer including circuitry that receives the detection signal from the detector and constructs an image including a target design pattern; as well as A controller having at least one processor and a non-transitory computer-readable medium including instructions that, when executed by the processor, cause the system to: selecting a target design pattern based on first design data representing a design of the integrated circuit; as well as providing design data indicative of the target design pattern so that design data derived from the target design pattern can be added to second design data representing a layout design of the integrated circuit, wherein the second design data is based on the first design data, The first design data and the second design data relate to the position of the integrated circuit on the die and / or the size of the integrated circuit.

15. The system of claim 14, wherein the instructions, when executed by the processor, further cause the system to: inspecting the structure on the wafer using a charged particle beam tool after the structure derived from the second design data is printed on the wafer; and A metrology data or process defect is identified based on the inspection.

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