Load drives and engine systems

Abstract

The present invention provides a load driving device, which can diagnose a fault of the output terminal before the charging voltage is stabilized in a structure in which a capacitor is connected to the output terminal of the load driving device driving an inductive load. The load driving device of the present invention has a capacitor connected between the load terminal and the ground terminal, and diagnoses whether the load terminal has a fault based on the current flowing between the internal power supply of the diagnostic circuit and the load terminal.

Description

Technical Field

[0001] The present invention relates to a load driving device that drives an inductive load constituted by a driving circuit having either a low-side driving circuit or a high-side driving circuit. Background Art

[0002] As one of the functions of in-vehicle mounted electronic control components, there is fuel injection control based on an injector. In order to improve the reliability of fuel injection control, in addition to a low-side driving circuit that drives the injector, a load driving device having a diagnostic circuit for diagnosing a failure at a load terminal is sometimes used.

[0003] The following Patent Document 1 describes a driving device for an electrical load. In this document, with the problem of "distinguishing and detecting an open-circuit failure and a ground short circuit of an electrical load when a driving switch unit is OFF in a low-side driving type electronic control device", the following technology is disclosed: "In an ECU10 having an N-channel MOSFET15 that energizes and drives a load L from the low side, between the power supply voltage VB and the output terminal 13 (the drain of FET15), and between the terminal 13 and the ground, resistors Ru and Rd are respectively provided, and the resistance values of the resistors Ru and Rd are set such that the voltage VO at the terminal 13 when FET15 is OFF becomes VB / 2 in the case of an open-circuit failure of the load L and becomes approximately VB in the normal state. Then, the comparator 21 and 22 compare the respective determination voltages Vth1 (>VB / 2) and Vth2 (<VB / 2) with the voltage VO. When FET15 is OFF, if "Vth1≥VO>Vth2", it is determined as an open-circuit failure, and if "Vth2≥VO", it is determined as a ground short circuit, and different fail-safe processes are performed during the detection of each of these failures." (Refer to the abstract).

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-347423 Summary of the Invention

[0007] Technical Problem to be Solved by the Invention

[0008] In-vehicle mounted electronic control components are required to have a function of detecting failures at each terminal. As detection targets, examples can include (a) normal, (b) Open-Load failure, (c) ground short circuit failure (hereinafter also referred to as Short-to-GND failure), (d) battery short circuit failure (hereinafter also referred to as Short-to-VB failure), etc.

[0009] On the other hand, the output terminal of the electronic control component is required to be resistant to noise or surge from outside the component, such as ESD (Electro-Static Discharge). For example, the above requirement can be achieved by connecting a capacitor between the output terminal of the component and the ground. However, in this case, since the charging current flows through the capacitor, it takes a certain amount of time until the charging voltage stabilizes.

[0010] As shown in Patent Document 1, in the method of judging an Open-Load fault or a Short-to-GND fault by comparing the output voltage VO with a judgment threshold, it is difficult to diagnose it until the charging voltage of the capacitor is stabilized. Since the capacitor is connected to the output terminal, the output voltage VO is also unstable until the charging voltage is stabilized.

[0011] The present invention has been made in view of the above problem and provides a load driving device that drives an inductive load and has a structure in which a capacitor is connected to an output terminal of the load driving device, and in which a failure of the output terminal can be diagnosed before a charging voltage is stabilized.

[0012] Technical solutions to solve problems

[0013] The load driving device of the present invention has a capacitor connected between a load terminal and a ground terminal, and diagnoses whether the load terminal has a fault based on a current flowing between an internal power supply of a diagnostic circuit and the load terminal.

[0014] Effects of the Invention

[0015] According to the load driving device of the present invention, in a structure in which a capacitor is connected between the load terminal and the ground terminal, by performing a diagnosis before the charging of the capacitor is completed, the state of the load terminal (normal, Open-Load fault, Short-to-GND fault) can be detected more accurately in a shorter time. The problems, structures and effects other than the above can be clarified through the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is an example of the overall structure of a conventional load driving circuit including a diagnostic circuit.

[0017] Figure 2 This is an example of a load driving circuit that diagnoses a fault in IC_OUT based on the voltage value of Vout.

[0018] Figure 3 This is a block diagram showing the configuration of the load driving device 100 according to the first embodiment.

[0019] Figure 4An example of the configuration of the first constant current source 211 and the current comparison circuit 213 is shown.

[0020] Figure 5 An example of the filter circuit 215 is shown.

[0021] Figure 6 Yes Description Figure 3 Flowchart of the process of diagnosing UNIT_OUT of the load driving device 100 shown in FIG.

[0022] Figure 7 is based on Figure 6 A correspondence table of the diagnostic results of the diagnostic process.

[0023] Figure 8 It is a timing diagram for explaining the behavior of signals in each load state.

[0024] Fig. 9 It is a block diagram showing the structure of a load driving device 100 according to the second embodiment.

[0025] Fig.10 An example of the configuration of the second constant current source 212 and the current comparison circuit 214 is shown.

[0026] Fig.11 A configuration example of the constant current source control circuit 217 according to the second embodiment is shown.

[0027] Fig.12 This is a flowchart illustrating the flow of diagnosing UNIT_OUT in the load driving device 100 according to the second embodiment.

[0028] Fig.13 is based on Fig.12 A correspondence table of the diagnostic results of the diagnostic process.

[0029] Fig.14 It is a timing diagram for explaining the behavior of signals in each load state.

[0030] Fig.15 It is a block diagram showing the structure of a load driving device 100 according to the third embodiment.

[0031] Fig.16 1 is a timing chart for explaining the operation of changing the constant currents Ierr and Ierm.

[0032] Fig.17 It is a block diagram showing the structure of a load driving device 100 according to a fourth embodiment.

[0033] Fig.18 This is a timing chart for explaining the operation of changing the filter time.

[0034] Fig.19This is a block diagram of the engine misfire diagnosis mechanism of the fifth embodiment.

[0035] Fig. 20 It is a block diagram showing the structure of a load driving device 100 according to the sixth embodiment.

[0036] Fig.21 It is a timing diagram for explaining the behavior of signals in each load state.

[0037] Fig. 22 It is a block diagram showing the structure of a load driving device 100 according to the seventh embodiment.

[0038] Fig.23 This is a timing diagram that explains the circuit operation when an open-load failure occurs in UNIT_OUT.

[0039] Fig.24 It is a block diagram showing the structure of a load driving device 100 according to the eighth embodiment.

[0040] Fig.25 This is a flowchart illustrating the flow of diagnosing UNIT_OUT in the load driving device 100 according to the eighth embodiment.

[0041] Fig.26 A table showing the correspondence between fault detection current and diagnosis results.

[0042] Fig. 27 It is a block diagram showing the structure of a load driving device 100 according to the eighth embodiment.

[0043] Fig.28 This is a flowchart illustrating the flow of diagnosing UNIT_OUT in the load driving device 100 according to the ninth embodiment.

[0044] Fig.29 A table showing the correspondence between fault detection current and diagnosis results.

[0045] Fig.30 Yes Description Fig.29 The operation timing diagram in the correspondence table when an open-load failure occurs in UNIT_OUT.

[0046] Fig.31 It is a block diagram showing the structure of a load driving device 100 according to the tenth embodiment.

[0047] Fig.32 This is a flowchart illustrating the flow of diagnosing UNIT_OUT in the load driving device 100 according to the tenth embodiment.

[0048] Fig.33 A table showing the correspondence between the fault detection current and output voltage and the diagnosis results.

[0049] Fig.34 This is a timing diagram for explaining the circuit operation when an open-load failure occurs in UNIT_OUT. DETAILED DESCRIPTION

[0050] <About the load driving device of the prior art>

[0051] Figure 1 This is an example of the overall structure of a load driving circuit of the prior art including a diagnostic circuit. The load driving device 100 has a driving circuit 2 for driving an injector 101. The driving circuit 2 includes a gate driving circuit 6, a diagnostic circuit 21, a low-side driving circuit 22, and a communication interface (I / F) 4. The gate driving circuit 6 outputs a driving signal Vgate corresponding to a driving command from a CPU (Central Processing Unit) 5 possessed by a microcontroller 3. The low-side driving circuit 22 is ON when the driving signal Vgate from the gate driving circuit 6 is at a High level, and is OFF when it is at a Low level. The diagnostic circuit 21 diagnoses UNIT_OUT, which is an output terminal of the component. The communication interface 4 performs data communication between the driving circuit 2 and the microcontroller 3. The diagnostic result is read out by the CPU 5 via the communication interface 4, and the CPU 5 implements control corresponding to the diagnostic result.

[0052] Figure 2 This is an example of a load driving circuit that diagnoses a fault of IC_OUT based on the voltage value of Vout. Here, a configuration example similar to that of Patent Document 1 is shown. The diagnostic circuit 21 has a voltage divider circuit 315 and voltage comparison circuits 311 and 312. The voltage divider circuit 315 applies the intermediate voltage VB / 2 obtained by dividing the first power supply voltage VB by the resistor R0 to IC_OUT, which is the output terminal of the driving circuit. The voltage comparison circuits 311 and 312 compare Vout with each diagnostic threshold. The voltage divider circuit 315 is configured as follows: the Vout potential of the low-side driving circuit 22 during the OFF period, (a) becomes the intermediate voltage VB / 2 when the connection with the injector 101 as the load becomes an open circuit (hereinafter referred to as an Open-Load fault), and (b) becomes the first power supply voltage VB in normal conditions. The voltage comparison circuits 311 and 312 compare Vout with the diagnostic threshold to perform fault diagnosis. Since the driving object of the driving circuit 2 is the injector 101, the load driving device 100 is a load driving device that drives an inductive load.

[0053] When the drive circuit 2 drives the injector 101, if there is an Open-Load fault at the output terminal UNIT_OUT of the load drive device 100, the injector 101 cannot inject fuel, resulting in a misfire fault, which may cause engine damage. To prevent engine damage, it is necessary to detect the fault and perform accurate control. In recent years, with the multi-stage injection control aimed at reducing exhaust emissions for the injector 101, the drive cycle of the low-side drive circuit 22 has become shorter, and it is necessary to judge the Open-Load fault and the Short-to-GND fault at a higher speed.

[0054] In Figure 2 it, in case (a) Vout < Vtgnd, it can be judged as a Short-to-GND fault; in case (b) Vtgnd < Vout < Vtopen, it can be judged as an Open-Load fault; in case (c) Vtopen < Vout, it can be judged as normal. The intermediate voltage VB / 2 is formed as a voltage value that satisfies Vtgnd < VB / 2 < Vtopen.

[0055] On the other hand, for the UNIT_OUT terminal mounted on a vehicle, tolerance to noise or surges outside the components such as from ESD is required. When the IC_OUT of the drive circuit 2 is connected to the UNIT_OUT of the load drive device 100, for the noise or surge protection of the drive circuit 2, a capacitor 1 is provided outside the drive circuit 2 and inside the load drive device 100. When the capacitor 1 is provided for ESD countermeasures, since the charging current flows according to a certain time constant, the responsiveness of the charging voltage of the capacitor 1 deteriorates, and it takes time until the charging voltage stabilizes.

[0056] In the method of judging the Open-Load fault and the Short-to-GND fault based on Vout during the OFF period of the low-side drive circuit 22, it is difficult to perform the diagnosis until the charging voltage stabilizes, and it is necessary to perform the diagnosis based on the voltage after the charging ends. However, in the multi-stage injection control with a short drive cycle, since the charging does not end within the drive cycle, it is difficult to perform the fault judgment.

[0057] <Embodiment 1>

[0058] In Embodiment 1 of the present invention, a description will be given of the structure and operation of a load driving device 100 that can detect whether the UNIT_OUT terminal is normal or faulty even when a capacitor 1 is connected between the output terminal and the ground terminal inside the load driving device 100 for interfering with noise or surge countermeasures. However, in this Embodiment 1, it is assumed that an Open-Load fault of the IC_OUT terminal can be ignored. Therefore, the Open-Load fault in this Embodiment 1 refers to an Open-Load fault occurring at the UNIT_OUT terminal.

[0059] Figure 3 It is a block diagram showing the structure of the load driving device 100 of this Embodiment 1. Figure 3 The shown load driving device 100 includes a capacitor 1, a low-side driving circuit 22, and a diagnostic circuit 21. The low-side driving circuit 22 and the capacitor 1 are connected in parallel between the output terminal and the ground terminal. The diagnostic circuit 21 includes a first constant current source 211, a current comparison circuit 213, a filter circuit 215, a constant current source control circuit 217, and an anti-backflow diode 210.

[0060] The first constant current source 211 conducts an Ierr current from the second power supply voltage VCC to the IC_OUT terminal. The current comparison circuit 213 monitors the driving current of the first constant current source 211. The filter circuit 215 takes the driving current detection signal DET_E, which is the output of the current comparison circuit 213, as an input.

[0061] The constant current source control circuit 217 outputs a constant current source control signal Ierr_con as a driving signal for the first constant current source 211. The anti-backflow diode 210 is connected between the second power supply voltage VCC and the first constant current source 211. The backflow prevention unit only needs to be arranged between VCC and IC_OUT. As an example, an anti-backflow diode 210 is provided between VCC and the first constant current source 211 in Figure 3 Here, as an example, an anti-backflow diode 210 is provided between VCC and the first constant current source 211.

[0062] When the detected driving current is greater than a threshold current Iref1 described later, the current comparison circuit 213 outputs a High level. For the first constant current source 211 to conduct a driving current Ierr from the second power supply voltage VCC to IC_OUT (output potential Vout), it is necessary to at least satisfy Vout < VCC (Equation 1). When this condition is satisfied, diagnosis based on the current comparison circuit 213 is implemented.

[0063] Figure 4The first constant current source 211 and the current comparison circuit 213 are shown as examples of their configurations. The first constant current source 211 is composed of an operational amplifier 231a, a resistor R1, an NMOS 232, and a PMOS 233. The first constant current source 211 takes Ierr_con as an input, and when Ierr_con is at a High level, an Ierr current corresponding to the Vref_err voltage flows. Through a current mirror composed of PMOS 233a, 233b, and 233c, Ierr_c1 and Ierr_c2, which are replica currents of the Ierr current, flow to the output terminal and the current comparison circuit 213, respectively.

[0064] Since the two inputs of the operational amplifier 231a are virtually short-circuited, Vnms, which is the source potential of the NMOS 232a, becomes the same potential as Vref_err, so Ierr can be expressed by Vref_err / R1. That is, Ierr can be adjusted depending on Vref_err. When Ierr_con is at a Low level, the PMOS 233f becomes ON, and no potential is generated at both ends of the PMOS 233a, so current does not flow.

[0065] The current comparison circuit 213 includes a PMOS 233, a resistor Rref, an operational amplifier 231b, and a reference power supply Vref1. Ierr_c2 is converted into a voltage by Rref and compared with Vref1 as a detection threshold. Vref1 is constituted as a voltage value when the Iref1 current flows through Rref. When Ierr_c2 is larger than Iref1, Verr becomes larger than Vref1, and the operational amplifier 231b makes DET_E as a fault detection signal High. When Ierr_c2 is smaller than Iref1, Verr becomes smaller than Vref1, and the operational amplifier 231b makes DET_E Low.

[0066] Figure 5 An example of the filter circuit 215 is shown. The filter circuit 215 is composed of a clock-based input synchronization unit 221 and a glitch filter 222. The filter circuit 215 receives DET_E, which is the output of the current comparison circuit 213, as an input signal. The filter circuit 215 is composed of a flip-flop 223, NOR 224, NAND 225, and AND 226, etc., which are operated by a clock, and outputs an Error signal.

[0067] The glitch filter outputs a High level only when the current and previous N samples are at a High level, and outputs a Low level only when the current and previous N samples are at a Low level. In other cases, the output does not change from the current value. Figure 5This is the case where N = 4. In order to remove asynchronous glitches or jitters in DET_E, the filter circuit 215 can remove glitches shorter than the filter time and pass signals longer than the filter time.

[0068] Figure 6 Yes Description Figure 3 1 is a flowchart of the process of diagnosing UNIT_OUT of the load driving device 100 shown in FIG. In this flowchart, when the low-side driving circuit 22 is switched from ON to OFF, each functional unit of the load driving device 100 is implemented. Figure 6 The following describes each step.

[0069] S1: The gate drive circuit 6 changes the drive signal Vgate of the low-side drive circuit 22 from the High level to the Low level according to the instruction from the CPU 5. As a result, the low-side drive circuit 22 changes from ON to OFF.

[0070] S2: The current comparison circuit 213 determines whether the drive current flowing through the first constant current source 211 is greater than or equal to Iref1 at a time point when the fault detection filtering time tfil1 has passed since the low-side drive circuit 22 was turned off. If a current greater than Iref1 is flowing, the process proceeds to S3, and if a current less than Iref1 is flowing, the process proceeds to S4.

[0071] S3: The current comparison circuit 213 sets the Error signal, which is a failure detection signal, to the High level, and ends the process.

[0072] S4: The current comparison circuit 213 sets the Error signal, which is a failure detection signal, to the Low level, and ends the process.

[0073] Figure 7 Time based on Figure 6 The corresponding table of the diagnostic results of the diagnostic process. If the low-side drive circuit 22 is OFF and the drive current Ierr flowing through the first constant current source 211 is greater than Iref1, it is diagnosed that UNIT_OUT has a fault. If the low-side drive circuit 22 is OFF and the drive current Ierr flowing through the first constant current source 211 is less than Iref1, it is diagnosed that UNIT_OUT is normal.

[0074] Figure 8 is a timing diagram that illustrates the behavior of signals in each load state. Figure 3 The circuit operation shown is when an Open-Load failure occurs in UNIT_OUT of the load driving device 100 .

[0075] In the case where an Open-Load fault occurs at UNIT_OUT, since there is no charge in capacitor 1 after the low-side drive circuit 22 becomes OFF (t0), the Vout potential is the ground potential, and Vgnd = Vout < VCC. Since this satisfies Equation 1, Ierr becomes equal to or greater than Iref1, and thus DET_E becomes High level. If DET_E remains High for a time longer than tfil1, a fault is determined. tfil1 is a time shorter than tchg_fin, which is the time required for the charging of the capacitor to be completed.

[0076] In the case where a Short-to-GND fault occurs at UNIT_OUT, Vout is connected to the ground potential Vgnd, and Vgnd = Vout < VCC. Since this satisfies Equation 1, Ierr becomes equal to or greater than Iref1, and thus DET_E becomes High level. If DET_E remains High for a time longer than tfil1, a fault is determined.

[0077] In the case of normal operation, Vout is connected to the first power supply voltage VB via a load, and VCC < Vout (= VB). Since this does not satisfy Equation 1, Ierr is less than Iref1, and thus DET_E becomes Low level. If DET_E remains Low for a time longer than tfil1, it is diagnosed as normal. The second power supply voltage VCC is a voltage smaller than the first power supply voltage VB.

[0078] <Embodiment 1: Summary>

[0079] In the load driving device 100 of this Embodiment 1, a capacitor 1 is connected between the output terminal UNIT_OUT and the ground terminal UNIT_GND of the load driving device 100 that drives an inductive load (injector 101). The diagnostic circuit 21 diagnoses UNIT_OUT using the drive current Ierr of the first constant current source 211 before the charging voltage of the capacitor 1 stabilizes. Thus, compared with the prior art, the state of the UNIT_OUT terminal can be detected more quickly and accurately, thereby improving the reliability.

[0080] <Embodiment 2>

[0081] In Embodiment 2 of the present invention, on the basis of the fault diagnosis of Embodiment 1, it is also diagnosed what kind of fault (fault mode) has occurred. That is, the structure and operation for detecting the state of the load (any one of normal, Open-Load fault, and Short-to-GND fault) will be described. However, the following will refer appropriately to Figures 3 to 8 Mainly, aspects that are different from Embodiment 1 will be described.

[0082] Fig. 9 This is a block diagram showing the structure of the load driving device 100 according to the second embodiment. Fig. 9 Based on the structure described in the first embodiment, the diagnostic circuit 21 shown in FIG. further includes a second constant current source 212, a current comparison circuit 214, and a filter circuit 216.

[0083] The second constant current source 212 allows a current Ierm to flow from the IC_OUT terminal to the ground. The current comparison circuit 214 monitors the driving current Ierm of the second constant current source 212. The filter circuit 216 takes the driving current detection signal DET_EM, which is the output of the current comparison circuit 214, as an input.

[0084] The constant current source control circuit 217 outputs not only Ierr_con for controlling the first constant current source 211 but also Ierr_con for controlling the second constant current source 212. In order for the second constant current source 212 to allow the driving current Ierm to flow from the IC_OUT to the ground, at least Vgnd < Vout (Equation 2) must be satisfied. When this condition is satisfied, diagnosis based on the current comparison circuit 214 is performed.

[0085] Fig.10 This shows a structural example of the second constant current source 212 and the current comparison circuit 214. The second constant current source 212 is composed of an operational amplifier 231c, a resistor R2, an NMOS 232, and a PMOS 233. The second constant current source 212 takes Ierm_con as an input. When Ierm_con is at a Low level, the NMOS 232f turns OFF, and a current Ierm corresponding to the Vref_erm voltage flows. Using the current mirror formed by the NMOSs 232b, 232c, and 232d, Ierm_c1 and Ierm_c2, which are replicas of Ierm, flow to the output terminal and the current comparison circuit 214.

[0086] Since the two inputs of the operational amplifier 231c are virtually short-circuited, the source potential Vnms of the NMOS 233d becomes the same potential as Vref_erm, so Ierm can be expressed as (VCC - Vref_erm) / R2. That is, Ierm can be adjusted depending on the potential of Vref_erm. When Ierm_con is at a High level, the NMOS 232f turns ON, no potential is generated across the NMOS 232b, and no current flows.

[0087] The current comparison circuit 214 includes an NMOS 232, a resistor Rref, an operational amplifier 231d, and a reference power supply Vref2. Ierm_c2 is converted into a voltage by Rref and compared with Vref2 as a detection threshold. Vref2 is a voltage value when a current of Iref2 flows through Rref. When Ierm_c2 is larger than Iref2, Verm becomes larger than Vref2, and the operational amplifier 231d makes DET_EM, which is a fault mode determination signal, High. When Ierm_c2 is smaller than Iref2, Verm becomes smaller than Vref2, and the operational amplifier 231d makes DET_EM Low.

[0088] Fig.11 The following is a structural example of the constant current source control circuit 217 of the second embodiment. The constant current source control circuit 217 takes the fault detection signal Error as input and outputs Ierr_con and Ierm_con. When the Error signal is Low and Vout is smaller than VCC, Ierr_con is set to a High level. When the Error signal becomes a High level, Ierr_con is set to a Low level, and Ierm_con is set to a High level via the buffer circuit 228, thereby switching the constant current source for driving from the first constant current source 211 to the second constant current source 212.

[0089] Fig.12 This is a flowchart for explaining the process of diagnosing UNIT_OUT by the load driving device 100 according to the second embodiment. Figure 6 There are modified steps in the diagnostic process of the first embodiment described in .

[0090] S3: The current comparison circuit 213 sets the Error signal, which is a failure detection signal, to the High level.

[0091] S5: Input Error signal to constant current source control circuit 217. Constant current source control circuit 217 turns OFF first constant current source 211 and turns ON second constant current source 212 by turning LOW Ierr_con controlling first constant current source 211 and HIGH Ierm_con controlling second constant current source 212.

[0092] S6: At the time point tfil2, which is the filtering time of the filter circuit 216, after the second constant current source 212 starts to be driven, the current comparison circuit 214 determines whether the driving current Ierm flowing through the second constant current source 212 is greater than Iref2. If a current greater than Iref2 is flowing, the process proceeds to S7, and if a current less than Iref2, the process proceeds to S8.

[0093] S7: The current comparison circuit 214 sets the Error Mode signal, which is a fault mode determination signal, to the High level, and ends the process.

[0094] S8: The current comparison circuit 214 sets the Error Mode signal to the Low level, and ends the process.

[0095] Fig.13 is a correspondence table of the diagnostic results of the diagnostic process based on Fig.12 If the low-side drive circuit 22 is OFF, and the drive current Ierr flowing through the first constant current source 211 is equal to or greater than Iref1 and the drive current Ierm flowing through the second constant current source 212 is less than Iref2, it can be diagnosed that a ground short fault has occurred in UNIT_OUT. If the low-side drive circuit 22 is OFF, and the drive current Ierr flowing through the first constant current source 211 is equal to or greater than Iref1 and the drive current Ierm flowing through the second constant current source 212 is equal to or greater than Iref2, it can be diagnosed that an open circuit fault has occurred in UNIT_OUT. If the low-side drive circuit 22 is OFF, and the drive current Ierr flowing through the first constant current source 211 is less than Iref1, it can be diagnosed that UNIT_OUT is normal.

[0096] Fig.14 is a timing chart showing the behavior of the signals in each load state. Here, the circuit operation in the case where an Open-Load fault has occurred in UNIT_OUT in Fig.12 is described.

[0097] Because the equation 1 is satisfied when an Open-Load fault has occurred in UNIT_OUT, the diagnostic circuit 21 outputs the Error signal at the High level. As a result, the constant current source control circuit 217 switches the diagnostic current from the fault detection current Ierr to the fault mode determination current Ierm. When an Open-Load fault has occurred in UNIT_OUT, Ierr charges the capacitor 1, and the potential of Vout after the time tfil1 is expressed as Vgnd < Vout (= Ierr × tfil1 / C1) using the capacitance value C1 of the capacitor 1. When the second constant current source 212 is driven after tfil1 has elapsed, the charge stored in the capacitor 1 discharges through the second constant current source 212, and only Ierm equal to or greater than Iref2 flows during the discharge time tdchg. Therefore, DET_EM becomes High level during this period. By setting tfil2 to be shorter than the tdchg of the capacitor 1, Ierm can be detected, so an Open-Load fault can be judged.

[0098] Since equation 1 is satisfied when a Short-to-GND fault occurs, the diagnostic circuit 21 outputs the Error signal at a High level. As a result, the constant current source control circuit 217 switches the diagnostic current from Ierr to Ierm. On the other hand, since UNIT_OUT is short-circuited to ground, equation 2 is not satisfied, and since the Ierm current becomes smaller than Iref2, DET_EM becomes a Low level. If DET_EM is at a Low level for a period of time longer than tfil2, it is determined to be a Short-to-GND fault.

[0099] <Implementation 2: Summary>

[0100] The load driving device 100 of the second embodiment is configured in accordance with the first embodiment, and further diagnoses a failure mode based on Ierm when a failure is detected based on Ierr.

[0101] Thus, similarly to the first embodiment, UNIT_OUT can be diagnosed at high speed, and its failure mode can be determined at high speed.

[0102] <Implementation Method 3>

[0103] In the third embodiment of the present invention, a configuration example in which the constant current source control circuit 217 controls the current values ​​of Ierr and Ierm is described. In this way, the most appropriate diagnostic current can be selected in accordance with the constraints of the capacitance value and the current consumption of the capacitor 1. Figures 9 to 14 , and mainly explains the changes relative to Implementation 2.

[0104] Fig.15 It is a block diagram showing the structure of a load driving device 100 according to the third embodiment. Fig.15 The diagnostic circuit 21 shown in FIG. 2 has drive current control circuits 411 and 412. The drive current control circuit 411 receives a constant current source control signal Ierr_con and a drive current control signal Vref_err as inputs, and controls the current value of Ierr based on them. The drive current control circuit 412 receives a constant current source control signal Ierm_con and a drive current control signal Vref_erm as inputs, and controls the current value of Ierm based on them.

[0105] The drive current control circuits 411 and 412 output a Low level when the output of the constant current source control circuit 217 is at a Low level, and flow Ierr and Ierm currents corresponding to the magnitude of the drive current control signal (Vref_err or Vref_erm) when the output is at a High level. Figure 4 The first constant current source 211 or Fig.10 According to these constant current sources, by controlling the voltages of Vref_err and Vref_erm, the magnitudes of Ierr and Ierm can be variably controlled.

[0106] Fig.16 This is a timing diagram for explaining the operation of changing the constant currents Ierr and Ierm. When Vref_err decreases from Verr to Verr', Ierr decreases from Ierr to Ierr' according to Vref_err / R1. When Vref_erm increases from Verm to Verm', Ierm decreases from Ierm to Ierm' according to (VCC-Vref_erm) / R2.

[0107] By changing the driving current of the constant current source in this way, the most appropriate current value of the diagnostic current can be selected according to the conditions, and the charging and discharging time to the capacitor 1 can be controlled. For example, if the capacitance value of the capacitor 1 is small, and the charging and discharging time is too short due to the magnitude of the diagnostic current, and an accurate diagnosis cannot be performed, the driving current can be reduced to extend the charging and discharging time, so that a correct diagnosis can be performed.

[0108] <Implementation Method 4>

[0109] In the fourth embodiment of the present invention, the structure and operation of the load driving device 100 capable of controlling the filtering time of the filter circuit will be described. Figures 9 to 14 , mainly explaining the changes relative to Implementation 2.

[0110] Fig.17 1 is a block diagram showing the structure of the load driving device 100 of the present embodiment 4. Here, an example in which the filter circuits 215 and 216 described in the embodiment 2 are replaced by filter circuits 413 and 414, respectively. The filter circuit 413 receives the drive current detection signal DET_E and the filter time control signal Verr_fi as input. The filter circuit 414 receives the drive current detection signal DET_EM and the filter time control signal Verm_fi as input. The filter circuits 413 and 414 can switch the filter time according to the digital output High / Low of the filter time control signal.

[0111] Fig.181 is a timing diagram for explaining the action of changing the filter time. When the digital value of Verr_fi changes from Low to High at time t4, the filter time of fault current detection is switched from tfil1 to tfil1'. When the digital value of Verm_fi changes from High to Low at time t4, the filter time of Ierm detection is switched from tfil2 to tfil2'. In the present embodiment 4, the filter circuit is constituted by a digital filter, and the filter time tfil1 and tfil2 are switched according to the digital signal, but it can also be constituted by an analog filter. In this case, the filter time is continuously variably controlled by the analog signal.

[0112] According to the fourth embodiment, an appropriate filtering time can be selected according to the conditions. For example, when the capacitance value of capacitor 1 is small and the charging and discharging time is shorter than the filtering time, by setting the filtering time so that it is shorter than the charging and discharging time, accurate diagnosis can be performed even if the capacitance value of capacitor 1 is small.

[0113] <Implementation method 5>

[0114] When a misfire occurs in an internal combustion engine, there is a possibility that the three-way catalyst may dissolve, etc., so rapid misfire diagnosis is required. In the fifth embodiment of the present invention, the structure of the misfire diagnosis mechanism of the internal combustion engine is described. By applying the load driving device 100 described in the second embodiment to the misfire diagnosis of the internal combustion engine, it is possible to perform fault detection faster than the conventional diagnosis method using the crank angle sensor.

[0115] Fig.19 This is a block diagram of the engine misfire diagnosis mechanism according to the fifth embodiment. Fig.19 The misfire diagnosis mechanism shown in the figure includes an internal combustion engine 102 and an engine control unit (ECU) 104. The internal combustion engine 102 has an injector 101 and a crank angle sensor 103. The ECU 104 has a load driving device 100. The crank angle sensor 103 outputs Drotate, which is data of the number of rotations per unit time (rotation speed) of the engine, to the ECU 104. When the value of Drotate decreases to less than a threshold value, the ECU 104 determines that it is a misfire (misfire). That is, the ECU 104 diagnoses a misfire after it occurs inside the engine.

[0116] On the other hand, the load driving device 100 described in the second embodiment can perform diagnosis during the driver OFF period before driving the injector, so it can diagnose the misfire in the internal combustion engine 102 before it occurs. Therefore, it is possible to perform fault diagnosis more quickly than the diagnosis method based on the crank angle sensor 103. In addition, by combining the diagnosis mechanism based on the crank angle sensor 103 of the prior art and the diagnosis mechanism based on the load driving device 100, a dual system for engine misfire diagnosis can be formed. Therefore, even if the diagnosis mechanism on one side cannot be diagnosed due to damage, etc., the diagnosis mechanism on the other side can be used for diagnosis, so the reliability can be improved.

[0117] In the above description, an example of using the load driving device 100 described in Embodiment 2 is described. This is because it is possible to determine a misfire when an open circuit fault occurs in UNIT_OUT, and it is desired to diagnose the fault mode. Therefore, if the fault mode can be diagnosed, the load driving device 100 of any embodiment including the embodiment described later can also be used.

[0118] Even when the load driving device 100 detects only the presence of a fault but cannot diagnose the fault mode, the fault mode can be diagnosed by analyzing the abnormal rotation behavior using the detection result based on the crank angle sensor 103. Therefore, in this case, the load driving device 100 of any embodiment after the first embodiment can also be used.

[0119] <Implementation Method 6>

[0120] In the sixth embodiment of the present invention, a configuration example of a load driving device 100 is described in which the low-side driving circuit 22 described in the first embodiment is replaced by a high-side driving circuit 23. In the sixth embodiment, it is described that in a configuration in which a capacitor 1 is connected between an output terminal and a ground terminal as in the first embodiment, the configuration and operation of the UNIT_OUT terminal can be diagnosed quickly and accurately. In the following description, reference is made to Figures 3 to 8 The following mainly describes the changes compared to Implementation Example 1.

[0121] Fig. 20 2 is a block diagram showing the structure of the load driving device 100 of the sixth embodiment. In the load driving device 100 of the sixth embodiment, the high-side driving circuit 23 is connected between the first power supply voltage VB and IC_OUT. The first constant current source 211 and the current comparison circuit 214 in the diagnostic circuit 21 can be, for example, Fig.10 The circuit structure shown is composed of: The first constant current source 211 is connected between IC_OUT and ground.

[0122] The first constant current source 211 needs to satisfy Equation 2 at least to drive the current Ierr from the output terminal of IC_OUT to the ground. In the case of normal operation, IC_OUT is connected to the ground potential via the load, and since Vgnd = Vout, the relationship of Equation 2 is not satisfied, so Ierr does not become Iref2 or more, and DET_E becomes Low level. If DET_E becomes Low level for a time of tfil2 or more, the diagnostic result is judged to be normal.

[0123] In the case where a VB short circuit fault occurs in UNIT_OUT, IC_OUT is connected to the first power supply voltage VB, and Vgnd < Vout (= VB). This satisfies Equation 2, Ierr becomes Iref2 or more, and DET_E becomes High level. If DET_E is High level for a time of tfil2 or more, it is judged as a fault.

[0124] Fig.21 It is a timing chart showing the behavior of signals in each load state. Fig. 20 In the case where an Open-Load fault occurs in UNIT_OUT of the load driving device shown, after the high-side drive circuit 23 becomes OFF, the capacitor 1 is charged with the charge of the VB level, so Vgnd < Vout (= VB), and Equation 2 is satisfied. Thus, Ierr becomes Iref2 or more. When DET_E becomes High level for a time of tfil or more, it is judged as a fault.

[0125] According to the sixth embodiment, in the structure of the load driving device 100 in which the low-side drive circuit 22 in the first embodiment is replaced with the high-side drive circuit 23, even when a capacitor 1 is connected between Vout and the ground, the UNIT_OUT terminal can be diagnosed quickly and accurately, and the reliability can be improved.

[0126] <Embodiment 7>

[0127] In the seventh embodiment of the present invention, a structural example for diagnosing the fault mode (any one of normal, Open-Load fault, VB short circuit fault) of the UNIT_OUT terminal in the structure described in the sixth embodiment is described. Hereinafter, referring to the sixth embodiment as appropriate, mainly the parts that are changed compared to the sixth embodiment will be described.

[0128] Fig. 22 A block diagram showing the structure of the load driving device 100 of the seventh embodiment. Fig. 22The diagnostic circuit 21 shown further includes a second constant current source 212, a current comparison circuit 214, and a filter circuit 216 on the basis of the structure described in Embodiment 6. Their structures are the same as those described in Embodiment 2, but the second constant current source 212 in this Embodiment 6 is connected between the second power supply voltage VCC and the output terminal, which is different from Embodiment 2.

[0129] For the first constant current source 211 to drive the current Ierr from the output terminal to the ground, at least Equation 2 needs to be satisfied. For the second constant current source 212 to drive the current Ierm from the second power supply voltage VCC to the output terminal, at least Equation 1 needs to be satisfied.

[0130] Fig. 22 When a VB short circuit fault occurs in UNIT_OUT of the load driving device 100 shown, since Equation 2 is satisfied, it is determined as a fault, and the diagnostic current is switched from Ierr to Ierm. At this time, since Equation 1 is not satisfied, when DET_EM remains Low for more than tfil2 time, the diagnostic result is determined as VB short circuit, and the diagnostic process ends.

[0131] Fig.23 is a timing chart illustrating the circuit operation when an Open-Load fault occurs in UNIT_OUT. The diagnostic process is the same as Fig.12 the same. Fig. 22 When an Open-Load fault occurs in UNIT_OUT of the load driving device 100 shown, since Equation 2 is satisfied, it is determined as a fault, and the diagnostic current is switched from Ierr to Ierm in the same way as the VB short circuit detection process.

[0132] When UNIT_OUT has an Open-Load fault, the charge stored in the capacitor 1 discharges when driving the first constant current source 211. Thus, the Vout potential after the tfil1 time elapses is expressed using the capacitance value C1 of the capacitor 1 as Vout(=VB - Ierr×tfil1 / C1) < VB. When driving the second constant current source 212 after the tfil1 time elapses, Ierm charges the capacitor 1. Since Ierm flows only during the period until the charging is completed, DET_EM becomes High during this period. By setting tfil2 shorter than the charging time tchg of the capacitor 1, Ierm can be detected, and an Open-Load fault can be determined.

[0133] According to Embodiment 7, based on the structure described in Embodiment 6, the state (normal, Open-Load fault, VB short circuit fault) of UNIT_OUT can be detected. Thereby, the reliability of the load driving device 100 can be improved.

[0134] <Implementation Method 8>

[0135] Fig.24 This is a block diagram showing the configuration of a load driving device 100 according to Embodiment 8 of the present invention. In Embodiment 8, a configuration and an operation example will be described assuming an Open-Load failure in IC_OUT that cannot be ignored. Fig.24 The structure shown is a structure that replaces the first constant current source 211 / current comparison circuit 213 / filter circuit 215 described in Embodiment 1 with a second constant current source 212 / current comparison circuit 214 / filter circuit 216. These have the same structure as that described in Embodiment 2.

[0136] The method described in Embodiment 1 Figure 3 In the circuit structure, since IC_OUT has not failed, the potential of UNIT_OUT is = VB in normal state, and Ierr does not flow as long as VB>VCC. When Ierr flows, the potential becomes VCC>UNIT_OUT (i.e., an open circuit failure or a short circuit failure to ground). Therefore, in Implementation 1, the normal state and the fault state can be distinguished based on the presence or absence of Ierr. In contrast, in this Implementation 8, there is a situation where IC_OUT fails. When IC_OUT is an open circuit failure or a short circuit failure, no current flows through capacitor 1, so the diagnostic current (equivalent to Ierr in Implementation 1) cannot flow. On the other hand, in this Implementation 8, since the diagnostic current flows in normal state, it is necessary to distinguish between normal state and abnormal state. That is, in this Implementation 8, unlike Implementation 1, it is necessary to use a circuit structure in which the diagnostic current flows in normal state. Therefore, in this Implementation 8, in order to ensure the path from VB to ground in normal state, a Fig.24 The circuit structure shown.

[0137] exist Fig.24 In the circuit structure, Ierm flows from VB to ground in normal conditions. If IC_OUT has an open circuit fault, Ierm cannot flow. Ierm cannot flow in the case of an open circuit fault at UNIT_OUT, a short circuit fault at UNIT_OUT to ground, or a short circuit fault at IC_OUT to ground. Therefore, according to Fig.24 With the circuit structure, even if IC_OUT may have an open circuit fault, the normal state and the fault state can be distinguished by the presence or absence of Ierm.

[0138] Fig.25 1 is a flowchart for explaining the process of diagnosing UNIT_OUT in the load driving device 100 according to the eighth embodiment. Figure 6The steps in which changes are made to the flowchart described in the previous section will be described below.

[0139] S2: After the filter time has passed since the low-side drive circuit 22 was turned off, the current comparison circuit 214 monitors whether the drive current flowing through the first constant current source 211 is greater than Iref2. If the current is greater than Iref2, the process proceeds to S4, and if it is less than Iref2, the process proceeds to S3.

[0140] Fig.26 This table shows the correspondence between the fault detection current and the diagnostic result. When an open-load fault occurs at the UNIT_OUT terminal, there is no charge in the capacitor 1 after the low-side drive circuit 22 becomes OFF, so the Vout potential is the ground potential, which does not satisfy equation 2. Therefore, Ierm is less than Iref2, and DET_E becomes a Low level. If DET_E continues to be a Low level for more than tfil2 time, it is judged as a fault.

[0141] exist Fig.26 According to the correspondence table, when an open-load fault occurs at the IC_OUT terminal, there is no path for current to flow from IC_OUT, so Ierm above Iref2 does not flow, and DET_E becomes a low level. If DET_E continues to be a low level for more than tfil2 time, it is judged as a fault.

[0142] According to the eighth embodiment, in the load driving device 100 of the first embodiment, even when the open-load failure of the IC_OUT terminal cannot be ignored, the state of UNIT_OUT (normal, failure (including the open-load failure of the IC_OUT terminal)) can be detected. Thus, the reliability of the load driving device 100 can be improved.

[0143] <Implementation Method 9>

[0144] Embodiment 9 of the present invention describes a configuration example of diagnosing a failure mode (normal, Open-Load failure, VB short-circuit failure) of the UNIT_OUT terminal in the configuration described in Embodiment 8. Hereinafter, the changes from Embodiment 8 will be described with reference to Embodiment 8 as appropriate.

[0145] Fig. 27 This is a block diagram showing the configuration of a load driving device 100 according to the eighth embodiment. Fig. 27 The diagnostic circuit 21 shown in the figure has, in addition to the structure described in the eighth embodiment, a first constant current source 211, a current comparison circuit 213, and a filter circuit 215. These structures are the same as those described in the first embodiment.

[0146] Fig.28 is a flowchart for explaining the process of diagnosing UNIT_OUT in the load driving device 100 according to the ninth embodiment. Fig.12 The steps in which changes are made to the flowchart described in the previous section will be described below.

[0147] S2: After tfil2 has passed since the low-side drive circuit 22 was OFF, the current comparison circuit 214 monitors whether the drive current flowing in the second constant current source 212 is greater than Iref2. When a current greater than Iref2 flows, it enters S4, and when a current less than Iref2 flows, it moves to S3. When Ierm is less than Iref2 (≈not flowing), some kind of failure occurs in UNIT_OUT or IC_OUT. This step has the significance of detecting this condition as the first stage.

[0148] S6: After tfil1 time has passed since the first constant current source 211 was driven, the current comparison circuit 213 monitors whether the driving current flowing through the first constant current source 211 is greater than Iref1. If the current is greater than Iref1, the process proceeds to S9, and if the current is less than Iref2, the process proceeds to S7.

[0149] S6: Supplement: (a) If UNIT_OUT is open, Ierr flows through capacitor 1, (b) If UNIT_OUT is short-circuited to ground, Ierr flows to ground, (c) If IC_OUT is short-circuited to ground, Ierr flows to ground. Therefore, in this step, if Ierr does not flow in S6 (S6: No), IC_OUT becomes open. Therefore, the significance of this step is to determine whether IC_OUT is open.

[0150] S9: Turn OFF the first constant current source 211 and turn ON the second constant current source 212.

[0151] S10: After tfil2 time has passed since the second constant current source 212 was driven in S9, the current comparison circuit 214 monitors whether the driving current flowing in the second constant current source 212 is greater than Iref2. If the current is greater than Iref2, the process proceeds to S11, and if the current is less than Iref2, the process proceeds to S8.

[0152] S10: Supplement: In this step, if Ierm flows (S10: Yes), UNIT_OUT is open and Ierm flows from capacitor 1. Therefore, in S11, the diagnosis result of this situation is output. In this step, if Ierm does not flow (S10: No), UNIT_OUT or IC_OUT is short-circuited to the ground. However, it cannot be distinguished which one is short-circuited to the ground.

[0153] Fig.29 This table shows the correspondence between the fault detection current and the diagnostic result. First, as a fault diagnosis, if Ierm is greater than Iref2, the diagnosis is normal. When Ierm is less than Iref2, the diagnostic current is switched from Ierm to Ierr, and the fault mode diagnosis is transferred. Ierr is further compared with Iref1 or Ierm with Iref2, and the fault mode is diagnosed based on the result.

[0154] Fig.30 Yes Description Fig.29 In the corresponding table, the timing diagram of the action in the case of an Open-Load fault at UNIT_OUT. In the case of an Open-Load fault at the UNIT_OUT terminal, there is no charge in the capacitor 1 after the low-side drive circuit 22 is OFF, so the Vout potential is the ground potential, which does not satisfy Formula 2. Therefore, Ierm is less than Iref2, and DET_E becomes a Low level. When DET_E is at a Low level for more than tfil2 time, it is judged as a fault. An Error signal is input to the constant current source control circuit 219, the current is switched from Ierm to Ierr, and the diagnosis based on the Ierr current is implemented.

[0155] In the case of an Open-Load failure of UNIT_OUT, since equation 1 is satisfied, an Ierr greater than Iref1 flows through capacitor 1, and DET_EM becomes a High level. If DET_EM continues to be a High level for more than tfil1 time, IC_OUT Open becomes Low, and it is determined that it is not an Open-Load failure of IC_OUT. Then, the IC_OUTOpen signal is input to the constant current source control circuit 219, and the driving current is switched from Ierr to Ierm, and a diagnosis based on Ierm is performed. Since a potential is generated in capacitor 1 by the charge charged to capacitor 1 by Ierr, equation 2 is satisfied, and therefore an Ierm greater than Iref2 flows through, and DET_EM becomes a High level. If DET_EM continues to be a High level for more than tfil2 time, it is determined that it is an Open-Load failure.

[0156] According to the ninth embodiment, even when the open-load failure of the IC_OUT terminal cannot be ignored in the load driving device 100 shown in the first embodiment, the state at the drive circuit terminal (normal, open-load failure of IC_OUT, open-load failure of UNIT_OUT, short-to-GND failure) can be determined. This can improve the reliability of the load driving device 100.

[0157] <Implementation Method 10>

[0158] In the second embodiment, a configuration example in which the fault mode is diagnosed using Ierm in addition to the fault diagnosis of the first embodiment is described. In the tenth embodiment of the present invention, a configuration example in which the fault mode is diagnosed using the potential Vout of the IC_OUT terminal instead of Ierm is described. Figures 3 to 8 , mainly explaining the changes compared to Implementation 1.

[0159] Fig.31 It is a block diagram showing the structure of the load driving device 100 according to the tenth embodiment.

[0160] Fig.31 The diagnostic circuit 21 shown in the figure has a voltage comparison circuit 316 and a filter circuit 317 in addition to the structure described in the first embodiment. The voltage comparison circuit 316 compares the potential Vout of the IC_OUT terminal with the fault mode detection threshold voltage Vterm. The filter circuit 317 takes the output voltage detection signal VDET_EM as the output of the voltage comparison circuit 316 as input. The filtering time of the filter circuit 317 is tfil2.

[0161] Fig.32 is a flowchart for explaining the process of diagnosing UNIT_OUT in the load driving device 100 according to the tenth embodiment. Figure 6 The steps in the flowchart described are described with modifications.

[0162] S3: The current comparison circuit 213 sets the fault detection signal, namely the Error signal, to the High level, and ends the process.

[0163] S5: The voltage comparison circuit 316 determines whether the potential of Vout is equal to or greater than Vterm at a time point tfil2 after the Error signal becomes High level. If it is equal to or greater than Vterm, the process proceeds to S6, and if it is less than Vterm, the process proceeds to S7.

[0164] S6: The filter circuit 317 makes the fault mode determination signal, namely the Error Mode signal, High level, and the processing ends.

[0165] S7: The filter circuit 317 sets the Error Mode signal to a Low level, and the process ends.

[0166] Fig.33It represents a correspondence table of the fault detection current, output voltage, and diagnostic results. If Ierr is less than Iref1, it is judged as normal. When Ierr is equal to or greater than Iref1, it is judged as a fault, and Vout is monitored. Vout is compared with Vterm, and the fault mode is diagnosed based on the result.

[0167] Fig.34 It is a timing diagram illustrating the circuit operation when an Open-Load fault occurs at UNIT_OUT. When an Open-Load fault occurs at UNIT_OUT, since Equation 1 is satisfied, it is judged as a fault. When UNIT_OUT has an Open-Load fault, Ierr charges capacitor 1, and the potential of Vout after time tfil1 is expressed as Vterm < Vout (= Ierr × tfil1 / C1) using the capacitance value C1 of capacitor 1. After time tfil1, when Vout is monitored by the voltage comparison circuit 316, since a potential equal to or higher than Vterm is detected, the output voltage detection signal VDET_EM becomes High level during this period. If VDET_EM continues to be High for tfil2 or more, it is judged as an Open-Load fault.

[0168] When a Short-to-GND fault occurs at UNIT_OUT, since Equation 1 is satisfied, it is judged as a fault. The voltage of Vout is monitored by the voltage comparison circuit 316 after time tfil1. When UNIT_OUT is shorted to the ground, no charge is applied to capacitor 1. Therefore, the potential of Vout after time tfil1 becomes Vout = Vgnd < Vterm, becoming smaller than Vterm. As a result, VDET_EM becomes Low level. If VDET_EM remains Low for tfil2 or more, it is judged as Short-to-GND.

[0169] According to Embodiment 10 of the present invention, by using Vout instead of Ierm, the diagnosis of UNIT_OUT can be performed at high speed in the same manner as in Embodiment 2, and its fault mode can be judged at high speed.

[0170] <Regarding a modification example of the present invention>

[0171] The present invention is not limited to the above-mentioned embodiments, and includes various modifications. For example, the above-mentioned embodiments are described in detail for easy understanding of the present invention, but are not limited to having all the structures described. In addition, a part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and the structure of other embodiments can be added to the decoupling strand of a certain embodiment. In addition, with respect to a part of the structure of each embodiment, other structures can also be added, deleted, or replaced. In addition, the control line or signal line indicates the part that is considered necessary for the description, and is not limited to indicating all the control lines or signal lines required on the product.

[0172] For example, in the configuration using the high-side drive circuit 23 described in Embodiments 6 to 7, it is also possible to adopt a configuration in which the drive current value described in Embodiment 3 is changed or a configuration in which the filter time described in Embodiment 4 is changed.

[0173] Description of Reference Numerals

[0174] 1: Capacitor

[0175] 2: Driving circuit

[0176] 3: Microcontroller

[0177] 4: Communication interface (I / F)

[0178] 5: CPU

[0179] 6: Gate drive circuit

[0180] 21: Diagnostic circuit

[0181] 22: Low-side drive circuit

[0182] 23: High-side drive circuit

[0183] 100: Load driving device

[0184] 101: Injector

[0185] 102: Internal combustion engine

[0186] 103: Crank angle sensor

[0187] 104: Engine Control Unit (ECU)

[0188] 210: Anti-reverse current diode

[0189] 211: The first constant current source

[0190] 212: Second constant current source

[0191] 213, 214: Current comparison circuit

[0192] 215, 216: Filter circuit

[0193] 217: Constant current source control circuit

[0194] 221: Input synchronization unit

[0195] 222: Glitch Filter

[0196] 223: Trigger

[0197] 224: NOR

[0198] 225: NAND

[0199] 226: AND

[0200] 227: NOT

[0201] 228: Buffer circuit

[0202] 231: Operational Amplifier

[0203] 232: NMOS

[0204] 233: PMOS

[0205] 311, 312: Voltage comparison circuit

[0206] 315: Voltage divider circuit

[0207] 316: Voltage Comparator Circuit

[0208] 317: Filter Circuit

[0209] 411, 412: Driving current control circuit

[0210] 413, 414: Filter circuit

[0211] VB: First power supply voltage

[0212] VCC: Second power supply voltage

[0213] Ierr_con, Ierm_con: constant current source control signal.

Claims

1. A load driving device, characterized in that: include: Low-side drivers for driving inductive loads; a gate drive circuit for performing drive control of the driver; An inter-terminal capacitor disposed between the ground terminal and the load terminal; and a diagnostic circuit for detecting whether the load terminal has a fault by using a current flowing between an internal power supply and an output terminal of the low-side driver when the driver is OFF, The diagnosis circuit determines whether the failure mode is an open circuit failure or a short circuit failure to ground by using a voltage value of the inter-terminal capacitor or a current value of a current flowing between an output terminal of the low-side driver and ground.

2. The load driving device according to claim 1, characterized in that: A diagnostic circuit is provided for determining whether the inductive load is short-circuited to ground or open-circuited based on a comparison result between a current value and a predetermined threshold current when a fault mode is determined by current.

3. The load driving device according to claim 1, wherein: The diagnostic circuit for detecting whether the load terminal has a fault comprises: a second power source providing a second voltage lower than a first voltage of the first power source connected to the inductive load; a first constant current source which receives the second voltage and outputs a first constant current to the load terminal; and The first comparison circuit outputs an error signal indicating that a fault has occurred at the load terminal when the first constant current is greater than a first determination threshold.

4. The load driving device according to claim 3, characterized in that: The load driving device further comprises a fault mode diagnosis circuit, which determines whether the fault is a short circuit to ground or an open circuit when a fault occurs at the load terminal. The failure mode diagnosis circuit comprises: a second constant current source connected between the load terminal and ground and outputting a second constant current; and A second comparison circuit outputs a diagnostic result indicating that the short-circuit fault to ground has occurred when the second constant current is less than a second judgment threshold, and outputs a diagnostic result indicating that the open-circuit fault has occurred when the second constant current is greater than the second judgment threshold.

5. The load driving device according to claim 1, wherein: The diagnostic circuit is configured to output the current between the internal power supply and the output terminal of the low-side driver, The load driving device further includes a control circuit that outputs a current control signal indicating the value of the current output by the diagnostic circuit. The diagnostic circuit outputs the current having a current value indicated by the current control signal.

6. The load driving device according to claim 1, wherein: The load driving device further comprises a diagnostic filter circuit, which outputs a diagnostic result indicating that a fault has occurred at the load terminal when the diagnostic circuit outputs a diagnostic result indicating that a fault has occurred at the load terminal for a period of time exceeding a prescribed period, and does not output a diagnostic result indicating that a fault has occurred at the load terminal when the diagnostic circuit outputs a diagnostic result indicating that a fault has occurred at the load terminal for a period of time less than the prescribed period. The diagnosis circuit outputs an output of the diagnosis filter circuit as a diagnosis result of the load terminal.

7. The load driving device according to claim 6, wherein: The load driving device further includes a control circuit that outputs a filter control signal indicating the specified time. The diagnostic filter circuit outputs a diagnostic result at the prescribed time indicated by the filter control signal.

8. The load driving device according to claim 1, wherein: The inter-terminal capacitor is connected between the output terminal of the low-side driver and the load terminal, The load driving device further comprises a second diagnostic circuit, which determines whether a fault occurs in the output terminal of the low-side driver. The second diagnostic circuit comprises: a second constant current source for flowing a second constant current between an output terminal of the low-side driver and ground; and The second comparison circuit outputs an error signal indicating that a failure has occurred in the output terminal of the low-side driver or the load terminal when the second constant current is less than a second judgment threshold.

9. The load driving device according to claim 8, characterized in that: The diagnostic circuit for detecting whether the load terminal has a fault comprises: a second power source providing a second voltage lower than a first voltage of the first power source connected to the inductive load; a first constant current source connected in series with the second constant current source and receiving supply of the second voltage to output a first constant current to the load terminal; and a first comparison circuit which compares the first constant current with a first judgment threshold to output an error signal indicating that a fault has occurred at the load terminal; The load driving device further comprises a control circuit, which turns the first constant current source and the second constant current source on or off respectively. The control circuit switches the second constant current source to OFF and turns the first constant current source to ON when the second constant current is less than the second judgment threshold when the first constant current source is OFF and the second constant current source is ON, When the first constant current is less than the first judgment threshold, the first comparison circuit outputs an error signal indicating that an open circuit fault has occurred at the output terminal of the low-side driver. The control circuit switches the first constant current source to OFF and turns the second constant current source to ON when the first constant current is greater than the first determination threshold value when the first constant current source is turned ON and the second constant current source is turned OFF, The second comparison circuit outputs an error signal indicating that an open circuit fault has occurred at the load terminal when the second constant current is greater than the second judgment threshold value when the first constant current source is switched OFF and the second constant current source is switched ON. When the second constant current is less than the second judgment threshold when the first constant current source is switched OFF and the second constant current source is switched ON, the second comparison circuit outputs an error signal indicating that a short circuit to ground has occurred at the output terminal of the low-side driver or the load terminal.

10. An engine system, characterized in that: include: a crank angle sensor that monitors the engine's speed; a misfire diagnosis mechanism for detecting misfire of the engine based on the value of the rotation speed detected by the crank angle sensor; and The load driving device according to claim 1, The load driving device drives an injector that ignites the engine as the inductive load.

Images