Electrical interconnection structure, electronic device and manufacturing method thereof

Abstract

The embodiment of the present invention provides an electrical interconnection structure, an electronic device and a manufacturing method thereof, which relates to the field of MEMS devices, and is used to provide a reliable electrical interconnection structure between the MEMS device and an external circuit while sealing and packaging the MEMS device. The electrical interconnection structure includes a bonding metal located on one side of a substrate, a first dielectric layer and a second dielectric layer located on a side of the bonding metal away from the substrate, the first dielectric layer includes a first through hole penetrating the first dielectric layer, and the first through hole exposes the bonding metal; the first through hole is filled with a first conductive material electrically connected to the bonding metal; the second dielectric layer includes a second through hole; the second through hole is filled with a second conductive material electrically connected to the first conductive material; the orthographic projection of the second conductive material filled in the second through hole on the plane where the substrate is located covers the orthographic projection of the first conductive material filled in the first through hole on the plane where the substrate is located.

Description

[Technical field]

[0001] The present invention relates to the technical field of electronic devices, and in particular to an electrical interconnection structure, an electronic device and a manufacturing method thereof. [Background technology]

[0002] Micro Electro-Mechanical Systems (MEMS) devices, such as gyroscopes, accelerometers, pressure sensors, gas sensors, etc., are gaining more and more attention. In order to drive MEMS devices and transmit output signals of MEMS devices, through holes filled with conductive materials are usually set in the insulating layer of the MEMS device to achieve interconnection of conductive structures. However, there are great risks when integrating the through hole setting process into the manufacturing process of MEMS devices. [Summary of the invention]

[0003] In view of this, an embodiment of the present invention provides an electrical interconnection structure, an electronic device and a manufacturing method thereof, which are used to provide a reliable electrical interconnection structure between a MEMS device and an external circuit while sealing and packaging the MEMS device.

[0004] On the one hand, an embodiment of the present invention provides an electrical interconnection structure, including:

[0005] Bonding metals;

[0006] A first dielectric layer is located on one side of the bonding metal; the first dielectric layer includes a first through hole penetrating the first dielectric layer, the first through hole exposing the bonding metal; the first through hole is filled with a first conductive material electrically connected to the bonding metal;

[0007] A second dielectric layer is located on a side of the first dielectric layer away from the bonding metal; the second dielectric layer includes a second through hole; the second through hole is filled with a second conductive material electrically connected to the first conductive material; the orthographic projection of the second conductive material filled in the second through hole on the plane where the bonding metal is located covers the orthographic projection of the first conductive material filled in the first through hole on the plane where the bonding metal is located.

[0008] In a possible implementation manner, a total height of the first through hole and the second through hole is greater than or equal to 9 μm.

[0009] In a possible implementation manner, both the first through hole and the second through hole are tapered through holes, and the angles between the side walls of the first through hole and the second through hole and the thickness direction of the electrical interconnection structure are between 0° and 20°.

[0010] In a possible implementation, the first conductive material includes tungsten or copper.

[0011] In a possible implementation manner, the aspect ratio of the first through hole is between 3:1 and 4:1.

[0012] In a possible implementation manner, the thickness of the cap oxide layer is 3.5 μm.

[0013] In a possible implementation manner, the thickness of the second dielectric layer is between 5.7 μm and 5.8 μm.

[0014] In a possible implementation, the second dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer which are stacked, wherein the first sub-dielectric layer is located between the second sub-dielectric layer and the first dielectric layer;

[0015] The thickness of the first sub-dielectric layer is between 0.2 μm and 0.3 μm.

[0016] In a possible implementation manner, the thickness of the second sub-dielectric layer is 5.5 μm.

[0017] In another aspect, an embodiment of the present invention provides an electronic device, including:

[0018] An electronic device, and the electrical interconnection structure described above, wherein the electrical interconnection structure is electrically connected to the electronic device.

[0019] In a possible implementation, the electronic device includes a MEMS device; the electronic device also includes a substrate, the MEMS device is located in a cavity on one side of the substrate, and the electrical interconnection structure is located on a side of the cavity away from the substrate.

[0020] In a possible implementation, the second dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer which are stacked, wherein the first sub-dielectric layer is located between the second sub-dielectric layer and the first dielectric layer;

[0021] The first dielectric layer and the first sub-dielectric layer include ventilation holes;

[0022] The second sub-dielectric layer fills the ventilation hole;

[0023] The orthographic projections of the second sub-dielectric layer filled in the ventilation hole and the first conductive material filled in the first through hole on the plane where the substrate is located do not overlap.

[0024] In another aspect, an embodiment of the present invention provides a method for manufacturing an electrical interconnection structure, comprising:

[0025] Forming bonding metals;

[0026] forming a first dielectric layer on one side of the bonding metal;

[0027] forming a first through hole penetrating the first dielectric layer in the first dielectric layer, wherein the first through hole exposes the bonding metal;

[0028] forming a first conductive material filling the first through hole, wherein the first conductive material is electrically connected to the bonding metal;

[0029] forming a second dielectric layer on a side of the first dielectric layer away from the bonding metal;

[0030] forming a second through hole in the second dielectric layer that penetrates the second dielectric layer,

[0031] forming a second conductive material filling the second through hole,

[0032] The orthographic projection of the second conductive material filled in the second through hole on the plane where the bonding metal is located covers the orthographic projection of the first conductive material filled in the first through hole on the plane where the bonding metal is located;

[0033] The second conductive material is electrically connected to the first conductive material.

[0034] In a possible implementation, the first conductive material includes tungsten or copper.

[0035] In a possible implementation, the first conductive material includes tungsten, and a method for forming the first conductive material filling the first through hole includes:

[0036] The first conductive material is formed by chemical vapor deposition of tungsten hexafluoride.

[0037] In another aspect, an embodiment of the present invention further provides a method for manufacturing an electronic device, comprising:

[0038] Make electronic devices;

[0039] The electrical interconnection structure is formed by the above method, and the electrical interconnection structure is electrically connected to the electronic device.

[0040] In a possible implementation, the electronic device includes a MEMS device; the second dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked together, wherein the first sub-dielectric layer is located between the second sub-dielectric layer and the first dielectric layer;

[0041] The method of manufacturing the electronic device and forming the electrical interconnection structure includes:

[0042] forming a sacrificial layer and a MEMS device on one side of the substrate;

[0043] forming a bonding metal on a side of the sacrificial layer away from the substrate;

[0044] forming a first dielectric layer on a side of the bonding metal away from the substrate;

[0045] forming a first through hole penetrating the first dielectric layer on the first dielectric layer, wherein the first through hole exposes the bonding metal;

[0046] forming a first conductive material filling the first through hole;

[0047] forming a first sub-dielectric layer on a side of the first dielectric layer away from the MEMS device;

[0048] forming a ventilation hole penetrating the first sub-dielectric layer and the first dielectric layer;

[0049] removing the sacrificial layer through the vent hole to form a cavity surrounding the MEMS device;

[0050] forming a second sub-dielectric layer on a side of the first sub-dielectric layer away from the substrate; the second sub-dielectric layer fills the ventilation hole;

[0051] forming a second through hole penetrating the first sub-dielectric layer and the second sub-dielectric layer;

[0052] forming a second conductive material filling the second through hole,

[0053] The orthographic projection of the second conductive material filled in the second through hole on the plane where the substrate is located covers the orthographic projection of the first conductive material filled in the first through hole on the plane where the substrate is located;

[0054] The second conductive material is electrically connected to the first conductive material.

[0055] In one possible implementation, the sacrificial layer is removed using any one or more of XeF2, SF6, fluorocarbons, ashing oxygen or ashing ozone, or a mixture of HF and CH3OH.

[0056] The electrical interconnection structure, electronic device and manufacturing method thereof provided by the embodiment of the present invention can adjust the total height of the through hole formed by the first through hole and the second through hole by adjusting the height of the first through hole and the second through hole, so that the total height of the through hole formed by the two can meet certain height requirements, for example, the total height of the two can be at least 9μm, and the ratio of the metal area to the thickness of the pull-up electrode can be increased. In addition, on the basis of increasing the height of the through hole, the embodiment of the present invention can also fill the through hole. When filling the first through hole and / or the second through hole, according to the aspect ratio of the first through hole and / or the second through hole, the first conductive material and / or the second conductive material filled in the first through hole and / or the second through hole can form a gap-free filling, or can form a gap filling. When a gap is formed in the first conductive material and / or the second conductive material, the gap is buried inside the first conductive material and / or the second conductive material to avoid affecting the electrical interconnection of the electrical interconnection structure with the external redistribution layer. Such a setting can avoid the local accumulation of materials including the first conductive material and the second conductive material inside the through hole. Moreover, the embodiment of the present invention is configured in this way, so that the first conductive material and bonding metal disposed below can be protected from the influence of etching. In addition, the embodiment of the present invention is configured in this way so that a plurality of first through holes can be disposed, and then a plurality of second through holes can be disposed. That is, the density of through holes including the first through holes and the second through holes can be changed. The MEMS device has excellent RF performance, and the yield of the MEMS device is increased.

Brief Description of the Drawings

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0059] Figure 2 is a schematic top view of a partial area of ​​a first mask plate;

[0060] Figure 3 is a schematic top view of a partial area of ​​a second mask plate;

[0061] Figure 4 Another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0062] Figure 5 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0063] Figure 6 is a schematic top view of a partial area of ​​a third mask plate;

[0064] Figure 7 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0065] Figure 8 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0066] Fig. 9 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0067] Fig.10 is a schematic top view of a partial area of ​​a fourth mask plate;

[0068] Fig.11 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0069] Fig.12 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0070] Fig.13 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0071] Fig.14 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0072] Fig.15 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0073] Fig.16 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0074] Fig.17 It is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process;

[0075] Fig.18 A cross-sectional schematic diagram of a MEMS device provided by an embodiment of the present invention;

[0076] Fig.19 A cross-sectional schematic diagram of another MEMS device provided by an embodiment of the present invention;

[0077] Fig. 20 A cross-sectional schematic diagram of another MEMS device provided by an embodiment of the present invention;

[0078] Fig.21 A cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention;

[0079] Fig. 22 Another cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention;

[0080] Fig.23 Another cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention;

[0081] Fig.24 Another cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention;

[0082] Fig.25 Another cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention;

[0083] Fig.26 Another cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention;

[0084] Fig. 27 Another cross-sectional schematic diagram of a MEMS device during the preparation process provided by an embodiment of the present invention.

[0085] It should be noted that these drawings and textual descriptions are not intended to limit the conceptual scope of the present invention in any way, but are intended to illustrate the concept of the present invention for those skilled in the art by referring to specific embodiments. [Specific implementation method]

[0086] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0087] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0088] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0089] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0090] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present application are described at the angles shown in the accompanying drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is connected to another element "upper" or "lower", it can not only be directly connected to another element "upper" or "lower", but also indirectly connected to another element "upper" or "lower" through an intermediate element.

[0091] It should be understood that although the terms first, second, etc. may be used to describe the through holes in the embodiments of the present invention, the through holes should not be limited to these terms. These terms are only used to distinguish through holes in different positions from each other. For example, without departing from the scope of the embodiments of the present invention, the first through hole may also be referred to as the second through hole, and similarly, the second through hole may also be referred to as the first through hole.

[0092] In the process of implementing the embodiments of the present invention, the inventors have found that currently, there are several methods for setting through holes for electrical interconnection in MEMS devices:

[0093] First method:

[0094] like Figure 1 As shown, Figure 1 It is a cross-sectional schematic diagram of a MEMS device in the related art during the preparation process. First, a first sacrificial layer 21', a MEMS device 3' and a second sacrificial layer 22' are sequentially formed on one side of a substrate 1'. Then, a first bonding metal 41' is formed on a side of the second sacrificial layer 22' away from the first sacrificial layer 21'. Then, a cap oxide layer 5' is formed on a side of the first bonding metal 41' away from the second sacrificial layer 22'.

[0095] After the cover oxide layer 5' is prepared, the cover oxide layer 5' is patterned. In the patterning process, the shape of the mask is selected as Figure 2 and Figure 3 As shown. Among them, Figure 2 The first mask plate 61' shown includes a plurality of openings with relatively small areas (eg Figure 2 Indicated by the white dot in the middle), Figure 3 The second mask plate 62 ′ shown includes an opening 620 ′ with a relatively large area.

[0096] Combination Figure 1 to Figure 4 As shown, Figure 4 Another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process, after forming the cover oxide layer 5', Figure 2 The first mask plate 61' shown is set corresponding to the first sacrificial layer 21' and the second sacrificial layer 22', and the second mask plate 62' is set corresponding to the first bonding metal 41'. The ventilation hole 51' penetrating the cover oxide layer 5' is formed in the cover oxide layer 5' by using the opening with a smaller area of ​​the first mask plate 61'. The ventilation hole 51' is used to etch the first sacrificial layer 21' and the second sacrificial layer 22' to form a cavity 7' at the location of the first sacrificial layer 21' and the second sacrificial layer 22' to release the MEMS device 3'. The through hole 52' penetrating the cover oxide layer 5' and exposing the first bonding metal 41' is formed in the cover oxide layer 5' by using the opening with a larger area of ​​the second mask plate 62'.

[0097] After removing the first sacrificial layer 21' and the second sacrificial layer 22' to form the cavity 7', Figure 5 As shown, Figure 5 FIG. 8 is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process; a sealing layer 8' is formed on the cover oxide layer 5'. Exemplarily, the sealing layer 8' can be formed of oxide or nitride to seal the vent 51' on the cover oxide layer 5'. Figure 5 As shown, after the sealing layer 8' is prepared, the through hole 52' is filled. Exemplarily, the preparation of the sealing layer 8' can adopt a conformal process, that is, after the sealing layer 8' is prepared, the surface of the sealing layer 8' will form a shape similar to the surface shape of the cap oxide layer 5'. Figure 5 As shown, the sealing layer 8 ′ has a recessed structure 80 ′ at a position corresponding to the through hole 52 ′.

[0098] After the sealing layer 8' is prepared, Figure 6 The third mask plate 63' shown is used to pattern the sealing layer 8' to expose the first bonding metal 41'. Optionally, the area of ​​the opening 630' of the third mask plate 63' can be slightly smaller than the area of ​​the opening 620' of the second mask plate 62', so that the area of ​​the through hole 81' formed in the sealing layer 8' is smaller than the surface area of ​​the recessed structure 80', so as to form a MEMS device as shown in FIG. Figure 7 In this process, if there is TiN on the surface of the first bonding metal 41', a TiN removal etching step can be added to remove the TiN. If the etching time of the above etching step is long enough, the TiN removal etching step can also be omitted.

[0099] Subsequently, the through hole 81' may be filled with a conductive material and a redistribution layer (RDL) may be fabricated to connect the first bonding metal 41' and the RDL so that the MEMS device is connected to an external circuit to drive the MEMS device and transmit the signal output by the MEMS device.

[0100] Optional, such as Figure 7 As shown, the recess structure 80 ′ and the through hole 81 ′ may have sidewalls that are almost perpendicular to the substrate.

[0101] For example, Figure 2 The first mask plate 61 ′ and Figure 3 The second mask plate 62' shown can be integrated into one. When forming the ventilation holes 51' and the through holes 52' in the cover oxide layer 5', reactive ion etching (hereinafter referred to as RIE) can be used. When using RIE, different desired etching depths can be determined by selecting the RIE hysteresis coefficient. For example, the etching speed of the area where the ventilation holes 51' corresponding to the smaller size in the cover oxide layer 5' are located can be made lower than the etching speed of the area where the through holes 52' corresponding to the larger size are located. That is, the etching of the area where the ventilation holes 51' are located has a certain hysteresis. The etching of the area where the through hole 52' is located does not experience hysteresis until the etching of the cover oxide layer 5' is completed when the through hole 52' contacts the first bonding metal 41' or is located near it.

[0102] With this method, when etching the cap oxide layer 5' to form the vent hole 51' and the through hole 52', the first bonding metal 41' has a risk of being over-etched.

[0103] Second method:

[0104] Still follow Figure 1 As shown, a first sacrificial layer 21 ′, a MEMS device 3 ′, a second sacrificial layer 22 ′, a first bonding metal 41 ′ and a cap oxide layer 5 ′ are prepared.

[0105] After the cap oxide layer 5' is prepared, Figure 2 and Figure 8 As shown, Figure 7 FIG. 1 is another cross-sectional schematic diagram of a MEMS device in the related art during the preparation process. Figure 2The first mask plate 61' shown is arranged corresponding to the first sacrificial layer 21' and the second sacrificial layer 22', and a ventilation hole 51' penetrating the cover oxide layer 5' is formed in the cover oxide layer 5' by using the opening with a smaller area of ​​the first mask plate 61'. The ventilation hole 51' is used to etch the first sacrificial layer 21' and the second sacrificial layer 22' to form a cavity 7' at the location of the first sacrificial layer 21' and the second sacrificial layer 22', and release the MEMS device 3'.

[0106] After removing the first sacrificial layer 21' and the second sacrificial layer 22' to form the cavity 7', Fig. 9 As shown, Fig. 9 Another cross-sectional view of a MEMS device in the related art during the preparation process is shown in FIG. 8 , where a sealing layer 8 ′ is formed on the cap oxide layer 5 ′. For example, the sealing layer 8 ′ may be formed of oxide or nitride to seal the vent hole 51 ′ on the cap oxide layer 5 ′.

[0107] After the sealing layer 8' is prepared, Fig.10 The fourth mask plate 64' shown is used to pattern the sealing layer 8' and the cover oxide layer 5' to form Fig.11 The through hole 82' having a conical shape is shown to penetrate the sealing layer 8' and the cap oxide layer 5' and expose the first bonding metal 41'. Optionally, the fourth mask plate 64' patterns the full-size bonding metal. The opening area of ​​the upper part of the through hole 82' is larger than the opening area of ​​the lower part, and the angle between the side wall of the through hole 82' and the thickness direction of the MEMS device is between 5° and 10°.

[0108] During the etching process of the sealing layer 8' and the cap oxide layer 5', if there is TiN on the surface of the first bonding metal 41', a TiN removal etching step can be added to remove the TiN. If the etching time of the above etching step is long enough, the TiN removal etching step can be omitted.

[0109] It can be seen that, by adopting this method, the through hole exposing the first bonding metal 41' can be formed by one etching step. However, by adopting this method, the depth of the through hole 82' cannot be designed to be larger. For example, if the through hole depth is to be greater than 9 μm, this method may not be achievable.

[0110] Third method:

[0111] Still follow Figure 1 As shown, a first sacrificial layer 21 ′, a MEMS device 3 ′, a second sacrificial layer 22 ′, a first bonding metal 41 ′ and a cap oxide layer 5 ′ are prepared.

[0112] After the cover oxide layer 5' is prepared, the same as the second method, combined with Figure 2 and Figure 8 As shown, Figure 2 The first mask plate 61' shown is arranged corresponding to the first sacrificial layer 21' and the second sacrificial layer 22', and a ventilation hole 51' penetrating the cover oxide layer 5' is formed in the cover oxide layer 5' by using the opening with a smaller area of ​​the first mask plate 61'. The ventilation hole 51' is used to etch the first sacrificial layer 21' and the second sacrificial layer 22' to form a cavity 7' at the location of the first sacrificial layer 21' and the second sacrificial layer 22', and release the MEMS device 3'.

[0113] After removing the first sacrificial layer 21' and the second sacrificial layer 22' to form the cavity 7', Fig. 9 As shown, a sealing layer 8' is formed on the cap oxide layer 5'. Exemplarily, the sealing layer 8' may be formed of oxide or nitride to seal the vent hole 51' on the cap oxide layer 5'.

[0114] After the sealing layer 8' is prepared, a fifth mask plate (not shown) is used to pattern the sealing layer 8' and the cover oxide layer 5' to form Fig.12 A through hole 83 ′ with a relatively small area is shown penetrating the sealing layer 8 ′ and the cap oxide layer 5 ′ and exposing the first bonding metal 41 ′.

[0115] After the through hole 83' is made, Fig.13 As shown, the second bonding metal 42' is continuously formed on the side of the sealing layer 8' away from the substrate 1', the second bonding metal 42' overlaps with the through hole 83', and the second bonding metal 42' is electrically connected to the first bonding metal 41' through the through hole 83'.

[0116] After the second bonding metal 42' is formed, Fig.14 As shown, an oxide layer 91', a passivation layer 92' and a photosensitive polyimide (PSPI) layer 93' are sequentially formed on the side of the second bonding metal 42' away from the substrate 1'. Then, the oxide layer 91', the passivation layer 92' and the PSPI layer 93' are etched using a fifth mask to form a through hole 90' ​​exposing the second bonding metal 42'. Subsequently, RDL can be further formed to electrically connect the second bonding metal 42' to the first bonding metal 41', so that the MEMS device is connected to an external circuit to drive the MEMS device and transmit the signal output by the MEMS device.

[0117] Optionally, the PSPI can be left on the wafer for bump plating.

[0118] With this method, if the vertical distance between the second bonding metal 42 ′ and the first bonding metal 41 ′ is about 9 μm, it is difficult to form a through hole 83 ′ with a width of about 1.25 μm.

[0119] Fourth method:

[0120] like Fig.15 As shown, first, a first sacrificial layer 21', a MEMS device 3' and a second sacrificial layer 22' are sequentially formed on one side of a substrate 1'. During this period, a third bonding metal 43' is formed between the formation of the MEMS device 3' and the second sacrificial layer 22', wherein the third bonding metal 43' is formed avoiding the first sacrificial layer 21' and the second sacrificial layer 22'. Then, a cap oxide layer 5' is formed on the side of the second sacrificial layer 22' away from the substrate 1'.

[0121] After the cover oxide layer 5' is prepared, the cover oxide layer 5' is patterned. In the patterning process, the shape of the mask is selected as Figure 2 and Figure 3 As shown. Among them, Figure 2 The first mask plate 61' shown includes a plurality of openings with relatively small areas (eg Figure 2 ), Figure 3 The second mask plate 62 ′ shown includes an opening 620 ′ with a relatively large area.

[0122] Continue to refer to Fig.15 After forming the cap oxide layer 5', Figure 2 The first mask plate 61' shown is set corresponding to the first sacrificial layer 21' and the second sacrificial layer 22', and the second mask plate 62' is set corresponding to the first bonding metal 41'. The ventilation hole 51' penetrating the cover oxide layer 5' is formed in the cover oxide layer 5' by using the opening with a smaller area of ​​the first mask plate 61'. The ventilation hole 51' is used to etch the first sacrificial layer 21' and the second sacrificial layer 22' to form a cavity 7' at the location of the first sacrificial layer 21' and the second sacrificial layer 22' to release the MEMS device 3'. The through hole 53' penetrating the cover oxide layer 5' and exposing the third bonding metal 43' is formed in the cover oxide layer 5' by using the opening with a larger area of ​​the second mask plate 62'.

[0123] After removing the first sacrificial layer 21' and the second sacrificial layer 22' to form the cavity 7', Fig.16 As shown, a sealing layer 8' is formed on the cap oxide layer 5'. Exemplarily, the sealing layer 8' can be formed of oxide or nitride to seal the vents on the cap oxide layer 5'. Fig.16 As shown, after the sealing layer 8' is prepared, the through hole 53' is filled. Exemplarily, the preparation of the sealing layer 8' can adopt a conformal process, that is, after the sealing layer 8' is prepared, the surface of the sealing layer 8' will form a shape similar to the surface shape of the cap oxide layer 5'. Fig.16As shown, the sealing layer 8 ′ has a recessed structure 801 ′ at a position corresponding to the through hole 52 ′.

[0124] After the sealing layer 8' is prepared, a sixth mask plate (not shown) is used to pattern the sealing layer 8' to form the following in the MEMS device: Fig.17 The step-shaped through hole shown in the figure exposes the third bonding metal 43'. In this process, if there is TiN on the surface of the third bonding metal 43', a TiN removal etching step can be added to remove the TiN. If the time of the above etching step is long enough, the TiN removal etching step can also be omitted. However, this method also has risks.

[0125] In view of this, an embodiment of the present invention provides an electrical interconnection structure and an electronic device, such as Fig.18 As shown, Fig.18 A cross-sectional schematic diagram of a MEMS device including an electrical interconnection structure is provided in an embodiment of the present invention, wherein the MEMS device includes a substrate 1, a cavity 8 located on one side of the substrate 1, and a MEMS device 3 is arranged in the cavity 8.

[0126] The electrical interconnection structure includes a bonding metal 4, a first dielectric layer 5, and a second dielectric layer. The second dielectric layer includes a first sub-dielectric layer 7 and a second sub-dielectric layer 9. The bonding metal 4 is located on the side of the cavity 8 away from the substrate, and the first dielectric layer 5 is located on the side of the bonding metal 4 away from the substrate. The first dielectric layer 5 includes a first through hole 50 penetrating the first dielectric layer 5, and the first through hole 50 exposes the bonding metal 4. The first through hole 50 is filled with a first conductive material 61 electrically connected to the bonding metal 4.

[0127] The first sub-dielectric layer 7 is located on the side of the first dielectric layer 5 away from the MEMS device 3. The first sub-dielectric layer 7 and the first dielectric layer 5 include ventilation holes 51; the etchant for etching the ventilation holes 51 does not overlap with the orthographic projection of the first conductive material 61 filled in the first through hole 50 on the plane where the substrate 1 is located, so that the ventilation holes 51 formed by the etchant do not overlap with the orthographic projection of the first conductive material 61 filled in the first through hole 50 on the plane where the substrate 1 is located. In the process of preparing the MEMS device, the ventilation holes 51 can be used to etch the sacrificial material to form a cavity 8 at the location of the sacrificial material to release the MEMS device 3. Exemplarily, any one of XeF2, SF6, fluorocarbons, ashing oxygen or ashing ozone, HF and CH3OH mixtures can be selected as an etchant to etch the sacrificial material. Among them, the selection of the etchant can be selected according to the material of the sacrificial layer. For example, when the sacrificial layer is a polymer, an oxygen ashing method or an ozone ashing method can be used.

[0128] The second sub-dielectric layer 9 is located on the side of the first sub-dielectric layer 7 away from the first dielectric layer 5, and the second sub-dielectric layer 9 is used to fill the above-mentioned ventilation hole 51 and seal the ventilation hole 51. The second sub-dielectric layer 9 filled in the ventilation hole 51 does not overlap with the first conductive material 61 filled in the first through hole 50 in the plane where the substrate 1 is located. The second sub-dielectric layer 9 and the first sub-dielectric layer 7 include a second through hole 90. The area of ​​the second through hole 90 is greater than the area of ​​the first through hole 50. The second through hole 90 is filled with a second conductive material 62 electrically connected to the first conductive material 61. The orthographic projection of the second conductive material 62 filled in the second through hole 90 in the plane where the substrate 1 is located covers the orthographic projection of the first conductive material 61 filled in the first through hole 50 in the plane where the substrate 1 is located. Exemplarily, an oxidized material can be selected to form the first dielectric layer 5 and the first sub-dielectric layer 7.

[0129] After the second conductive material 62 is prepared, a redistribution layer may be prepared above the second conductive material 62 to connect the MEMS device with an external circuit.

[0130] The electrical interconnect structure and MEMS device provided by the embodiment of the present invention can adjust the total height of the through hole formed by the first through hole 50 and the second through hole 90 by setting a stacked arrangement, so that the total height of the through hole formed by the two can meet certain height requirements. For example, the total height of the two can be at least 9μm, increasing the ratio of the metal area to the thickness of the pull-up electrode. Moreover, on the basis of increasing the height of the through hole, the embodiment of the present invention can also fill the through hole. When filling the first through hole 50 and / or the second through hole 90, according to the aspect ratio of the first through hole 50 and / or the second through hole 90, the first conductive material 61 and / or the second conductive material 62 filled in the first through hole 50 and / or the second through hole 90 can form the following: Fig.18 No gap filling as shown, or can be formed as Fig.19 and Fig. 20 As shown, there is a gap filling. When a gap is formed in the first conductive material and / or the second conductive material, the gap is buried inside the first conductive material and / or the second conductive material to avoid affecting the electrical interconnection between the electrical interconnection structure and the external redistribution layer. Such a configuration can prevent the materials including the first conductive material and the second conductive material from being locally accumulated inside the through hole. Moreover, the embodiment of the present invention is configured in this way to protect the first conductive material 61 and the bonding metal 4 disposed below from being affected by etching. In addition, the embodiment of the present invention is configured in this way to set a plurality of first through holes and then set a plurality of second through holes. That is, the density of the through holes including the first through holes and the second through holes can be changed. The MEMS device has excellent RF performance and the yield of the MEMS device is improved.

[0131] Optionally, the first through hole 50 and the second through hole 90 may both be tapered through holes, that is, the side walls of the first through hole 50 and the second through hole 90 form a certain angle with the thickness direction of the MEMS device, and the angle may be between 0° and 20°, for example. The angle may be within a conformal range and may be subsequently filled with a conductive material. Alternatively, the side walls of the first through hole 50 and the second through hole 90 may also be set to be perpendicular to the substrate.

[0132] Optionally, the first conductive material 61 includes tungsten or copper.

[0133] For example, when a material including tungsten is selected as the first conductive material 61, it can be made by chemically depositing (Chemical Vapor Deposited, hereinafter referred to as CVD) tungsten hexafluoride WF6. After the deposition is completed, W-polishing (CPW) can be used to flatten its surface, which is convenient for the subsequent preparation of the second conductive material 62 and improves the contact performance between the first conductive material 61 and the second conductive material 62.

[0134] Optionally, the shape of the orthographic projection of the first conductive material filled in the first through hole 50 and the second conductive material filled in the second through hole 90 on the plane where the substrate 1 is located may be circular or polygonal, and this is not limited in the embodiment of the present invention. For example, when etching to form the first through hole 50 and the second through hole 90, a mask having a hexagonal opening close to a circular shape may be used, and the shape of the orthographic projection of the first conductive material filled in the first through hole 50 and the second conductive material filled in the second through hole 90 on the plane where the substrate 1 is located is designed to be a hexagon, so as to minimize the mass of the conductive material required for subsequent filling.

[0135] Optionally, the aspect ratio of the first through hole 50 can be adjusted according to different application scenarios. For example, the aspect ratio of the first through hole 50 can be set to 3:1 or 4:1 to completely fill the first through hole with a conductive material, thereby avoiding the situation in which a gap is generated in the first conductive material due to setting the aspect ratio of the first through hole 50 too large. The height of the first through hole 50 is the thickness of the first dielectric layer 5. Exemplarily, the thickness of the first dielectric layer 5 can also be adjusted according to different application scenarios. Exemplarily, the thickness of the first dielectric layer 5 can be set between 3μm and 5μm. For example, the height of the first dielectric layer 5 can be set to 3.5μm.

[0136] Exemplarily, during the sacrificial layer release etching process, the thickness of the first sub-dielectric layer 7 can be adjusted to compensate for the etching rate required in the release etching process. For example, the thickness of the first sub-dielectric layer 7 can be set between 0.2 μm and 0.3 μm. The provision of the first sub-dielectric layer 7 can protect tungsten from the influence of etchants such as XeF2 during the etching step. Moreover, if the first dielectric layer 5 is lost during the W-polishing (CPW) process, the provision of the first sub-dielectric layer 7 can also compensate for the loss of the first dielectric layer 5.

[0137] Optionally, the thickness of the second sub-dielectric layer 9 may be set according to the mechanical integrity and strength required by the electronic device. For example, the thickness of the second sub-dielectric layer 9 may be set to 5.5 μm.

[0138] Optionally, the sum of the heights of the first through hole and the second through hole may be adjusted according to different applications of the electronic device. For example, the sum of the heights of the first through hole and the second through hole may be set to be greater than or equal to 9 μm.

[0139] In making Fig.18 The MEMS device shown, when combined with Figure 21 to Figure 27 As shown, an embodiment of the present invention provides a method for manufacturing an electrical interconnection structure and an electronic device, the manufacturing method comprising:

[0140] Step S1: Fig.21 As shown, first, a sacrificial layer and an electronic device are formed on one side of a substrate 1. Exemplarily, the sacrificial layer may include multiple layers. The electronic device may be a MEMS device. Specifically, as Fig.19 As shown, a first sacrificial layer 21, a MEMS device 3, and a second sacrificial layer 22 are sequentially formed on one side of a substrate 1. Then, a bonding metal 4 is formed on a side of the second sacrificial layer 22 away from the first sacrificial layer 21. Then, a first dielectric layer 5 is formed on a side of the bonding metal 4 away from the second sacrificial layer 22. The materials of the first sacrificial layer 21 and the second sacrificial layer 22 can be selected from amorphous silicon (aSi), amorphous germanium (aGe), or polymers such as PVDF, PET, etc.

[0141] Step S2: After the first dielectric layer 5 is prepared, the first dielectric layer 5 is patterned. Fig. 22 As shown, a first through hole 50 penetrating the first dielectric layer 5 is formed on the first dielectric layer 5, and the first through hole 50 exposes the bonding metal 4. Exemplarily, the first through hole 50 may be formed by etching.

[0142] Step S3: Fig.23 As shown, a first conductive material 61 is formed to fill the first through hole 50. Optionally, WF 6 filling the first through hole 50 may be formed by CVD.

[0143] Step S4: Fig.24 As shown, a first sub-dielectric layer 7 is formed on a side of the first dielectric layer 5 away from the MEMS device 3. Optionally, the thickness of the first sub-dielectric layer 7 may be between 0.2 μm and 0.3 μm.

[0144] Step S5: Fig.25 As shown, a vent 51 is formed that penetrates the first sub-dielectric layer 7 and the first dielectric layer 5. Wherein, the orthographic projection of the etchant for etching the vent 51 on the plane where the substrate 1 is located does not overlap with the orthographic projection of the first conductive material filled in the first through hole 50 on the plane where the substrate 1 is located. After the vent 51 is made, the first sacrificial layer 21 and the second sacrificial layer 22 are removed through the vent 51 to form a cavity 8 surrounding the MEMS device 3. Exemplarily, any one of XeF2, ashing oxygen or ashing ozone, or SF6 or fluorocarbon or a mixture of HF and CH3OH can be selected as an etchant. Wherein, the selection of the etchant can be selected according to the material of the sacrificial layer. For example, when the sacrificial layer is a polymer, an oxygen ashing method or an ozone ashing method can be used. If the materials of the first sacrificial layer 21 and the second sacrificial layer 22 are different, a sequential or mixed release process can be used. For example, chemical, physical, and vapor-based isotropic etching chemicals can be selected for etching.

[0145] Step 6: Fig.26 As shown, after the cavity 8 is formed, a second sub-dielectric layer 9 is formed on the side of the first sub-dielectric layer 7 away from the substrate 1. The second sub-dielectric layer 9 fills the ventilation holes 51. Optionally, the thickness of the second sub-dielectric layer 9 can be set to 5.5 μm.

[0146] Step 7: Fig. 27 As shown, a second through hole 90 penetrating the second sub-dielectric layer 9 and the first sub-dielectric layer 7 is formed, and the area of ​​the second through hole 90 is greater than that of the first through hole 50 .

[0147] Step S8: Fig.18 As shown, a second conductive material 62 is formed to fill the second through hole 90, and the second conductive material 62 is electrically connected to the first conductive material 61. The orthographic projection of the second conductive material 62 filled in the second through hole 90 on the plane where the substrate 1 is located covers the orthographic projection of the first conductive material 51 filled in the first through hole 50 on the plane where the substrate 1 is located.

[0148] After the second conductive material 62 is prepared, a redistribution layer may be prepared above the second conductive material 62 to connect the MEMS device with an external circuit.

[0149] The method for manufacturing a MEMS device provided in an embodiment of the present invention can adjust the total height of the through hole formed by the first through hole 50 and the second through hole 90 by setting a stacked arrangement, so that the total height of the through hole formed by the two can meet certain height requirements. For example, the total height of the two can be at least 9μm, increasing the ratio of the metal area to the thickness of the pull-up electrode. Moreover, on the basis of increasing the height of the through hole, the embodiment of the present invention can also fill the through hole. When filling the first through hole 50 and / or the second through hole 90, according to the aspect ratio of the first through hole 50 and / or the second through hole 90, the first conductive material 61 and / or the second conductive material 62 filled in the first through hole 50 and / or the second through hole 90 can be formed as follows: Fig.18 No gap filling as shown, or can be formed as Fig.19 and Fig. 20 As shown, there is a gap filling. When a gap is formed in the first conductive material and / or the second conductive material, the gap is buried inside the first conductive material and / or the second conductive material to avoid affecting the electrical interconnection between the electrical interconnection structure and the external redistribution layer. Such a configuration can prevent the materials including the first conductive material and the second conductive material from being locally accumulated inside the through hole. Moreover, the embodiment of the present invention is configured in this way to protect the first conductive material 61 and the bonding metal 4 disposed below from being affected by etching. In addition, the embodiment of the present invention is configured in this way to set a plurality of first through holes and then set a plurality of second through holes. That is, the density of the through holes including the first through holes and the second through holes can be changed. The MEMS device has excellent RF performance and the yield of the MEMS device is improved.

[0150] Exemplarily, the MEMS device 3 may be a capacitor.

[0151] Optionally, in an embodiment of the present invention, the MEMS device 3 may be a motion sensor (such as a gyroscope or an accelerometer), an RF MEMS device (such as an RF switch, a resonator or a filter), a MEMS magnetometer, an optical MEMS device (such as a MEMS micromirror), a MEMS oscillator, a MEMS microphone, a piezoelectric device, a thermal phase switch, a magnetic MEMS and / or any other MEMS type device, which is not limited in the embodiment of the present invention.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An electrical interconnection structure for providing an electronic device with an electrical connection to an external circuit, wherein the electronic device is located inside an electronic device and includes a MEMS device; the electronic device includes a substrate, the MEMS device is located in a cavity on one side of the substrate, and the electrical interconnection structure is located on a side of the cavity away from the substrate; the electronic device also includes a sacrificial layer deposited on the substrate, and the cavity is formed in the sacrificial layer; characterized in that The electrical interconnection structure comprises: A bonding metal located on a side of the sacrificial layer away from the substrate; an orthographic projection of the bonding metal onto the substrate does not overlap with the cavity; A first dielectric layer is located on one side of the bonding metal; the first dielectric layer includes a first through hole penetrating the first dielectric layer, the first through hole exposing the bonding metal; the first through hole is filled with a first conductive material electrically connected to the bonding metal; A second dielectric layer is located on a side of the first dielectric layer away from the bonding metal; the second dielectric layer includes a second through hole; the second through hole is filled with a second conductive material electrically connected to the first conductive material; the orthographic projection of the second conductive material filled in the second through hole on the plane where the bonding metal is located covers the orthographic projection of the first conductive material filled in the first through hole on the plane where the bonding metal is located; a gap is also formed in the first conductive material and / or the second conductive material, and the gap is buried inside the first conductive material and / or the second conductive material.

2. The electrical interconnection structure according to claim 1, characterized in that: A total height of the first through hole and the second through hole is greater than or equal to 9 μm.

3. The electrical interconnection structure according to claim 1, characterized in that: The first through hole and the second through hole are both tapered through holes, and the angles between the side walls of the first through hole and the second through hole and the thickness direction of the electrical interconnection structure are between 0° and 20°.

4. The electrical interconnection structure according to claim 1, characterized in that: The first conductive material includes tungsten or copper.

5. The electrical interconnection structure according to claim 1, characterized in that: The aspect ratio of the first through hole is between 3:1 and 4:

1.

6. The electrical interconnection structure according to claim 1, characterized in that: The thickness of the first dielectric layer is 3.5 μm.

7. The electrical interconnection structure according to claim 1, characterized in that: The thickness of the second dielectric layer is between 5.7 μm and 5.8 μm.

8. The electrical interconnection structure according to claim 7, characterized in that: The second dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer which are stacked, wherein the first sub-dielectric layer is located between the second sub-dielectric layer and the first dielectric layer; The thickness of the first sub-dielectric layer is between 0.2 μm and 0.3 μm.

9. The electrical interconnection structure according to claim 8, characterized in that: The thickness of the second sub-dielectric layer is 5.5 μm.

10. The electrical interconnection structure according to claim 1, characterized in that: The second dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer which are stacked, wherein the first sub-dielectric layer is located between the second sub-dielectric layer and the first dielectric layer; The first dielectric layer and the first sub-dielectric layer include ventilation holes; The second sub-dielectric layer fills the ventilation hole; The orthographic projections of the second sub-dielectric layer filled in the ventilation hole and the first conductive material filled in the first through hole on the plane where the substrate is located do not overlap.

11. A method for manufacturing an electronic device, the electronic device comprising an electronic device and an electrical interconnection structure according to any one of claims 1 to 10, characterized in that: The electronic device comprises a MEMS device; the second dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer which are stacked, wherein the first sub-dielectric layer is located between the second sub-dielectric layer and the first dielectric layer; The method of manufacturing the electronic device and forming the electrical interconnection structure includes: forming a sacrificial layer and a MEMS device on one side of the substrate; forming a bonding metal on a side of the sacrificial layer away from the substrate; forming a first dielectric layer on a side of the bonding metal away from the substrate; forming a first through hole penetrating the first dielectric layer in the first dielectric layer, wherein the first through hole exposes the bonding metal; forming a first conductive material filling the first through hole; forming a first sub-dielectric layer on a side of the first dielectric layer away from the MEMS device; forming a ventilation hole penetrating the first sub-dielectric layer and the first dielectric layer; removing the sacrificial layer through the vent hole to form a cavity surrounding the MEMS device; forming a second sub-dielectric layer on a side of the first sub-dielectric layer away from the substrate; the second sub-dielectric layer fills the ventilation hole; forming a second through hole penetrating the first sub-dielectric layer and the second sub-dielectric layer; A second conductive material is formed to fill the second through hole, wherein the orthographic projection of the second conductive material filled in the second through hole on the plane where the substrate is located covers the orthographic projection of the first conductive material filled in the first through hole on the plane where the substrate is located; the second conductive material is electrically connected to the first conductive material; and gaps are further formed in the first conductive material and / or the second conductive material, wherein the gaps are buried inside the first conductive material and / or the second conductive material.

12. The manufacturing method according to claim 11, characterized in that: The sacrificial layer is removed by using any one or more of XeF2, SF6, fluorocarbons, ashing oxygen or ashing ozone, or a mixture of HF and CH3OH.

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