Controlled curvature correction in high-accuracy thermal sensors

Abstract

Embodiments of the present disclosure relate to controlled curvature correction in a high-accuracy thermal sensor. A circuit device generates base-to-emitter voltages of two BJTs biased at different current densities, base-to-emitter voltages of BJTs biased so that the base-to-emitter voltages are complementary to absolute temperature and have curvature nonlinearity across temperature, and base-to-emitter voltages of two BJTs biased by a constant current that is independent of temperature and a current that is proportional to absolute temperature. A sampling circuit samples these voltages and provides the voltages to the input of a loop filter. The filter output is quantized to produce a bit stream. The sampling circuit: when the received bit of the bit stream is zero, causes the integration of Vbe1-Vbe2 to produce a voltage proportional to absolute temperature; when the received bit of the bit stream is one, causes the integration of Vbe2_c-Vbe_Vbe1_c to produce a negative voltage complementary to absolute temperature without nonlinearity across temperature.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 968,539, filed on January 31, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of temperature sensing circuits, and in particular to a temperature sensing circuit that utilizes a sigma-delta based analog-to-digital converter to generate a highly accurate temperature value, based on which the temperature of an integrated circuit chip in which the temperature sensing circuit is placed can be determined. Background Art

[0004] Systems on a chip (SOCs) are used in mobile devices such as smartphones and tablets, as well as in several embedded systems. Some existing SOCs are capable of temperature-aware task scheduling and self-calibration with respect to temperature to help reduce power consumption. To enable this functionality, such SOCs include an on-chip temperature sensor integrated with other components of the SOC.

[0005] A voltage proportional to absolute temperature Vptat can be generated as the difference between the base-emitter junction voltages of two bipolar junction transistors biased at different current densities. Mathematically, this can be expressed as: Vptat = ΔVbe = Vbe1 - Vbe2. This voltage Vptat, which is proportional to absolute temperature, is relatively error-free because the errors in Vbe1 and Vbe2 due to the lack of ideal performance of the transistors cancel each other out.

[0006] The relationship between Vptat and temperature can be expressed mathematically as Where T is the temperature in Kelvin, k is the Boltzmann constant, q is the magnitude of the electron charge, and p is the ratio of the current densities of the bipolar junction transistors used to generate Vptat. The analog-to-digital converter (ADC) digitizes Vptat relative to a reference voltage Vref and, therefore, outputs a ratio μ that can be calculated as This ratio can be appropriately scaled to produce a digital temperature reading in the desired units, for example: Where A and B are constants.

[0007] The accuracy of this temperature reading depends primarily on the temperature independence of the reference voltage Vref. To achieve temperature independence, the reference voltage Vref is usually generated as the sum of a voltage proportional to the absolute temperature Vptat and a voltage complementary to the absolute temperature Vctat, as in Figure 1AAs can be seen in , this would ideally produce a reference voltage that is truly temperature independent.

[0008] A voltage complementary to the absolute temperature Vctat is generated as the base-emitter junction voltage Vbe of the bipolar junction transistor. However, due to the lack of ideal performance of the transistor, errors are introduced. Mathematically, the real-world Vbe generated can be expressed as: Vbe = Vbe0-λT+C(T), where Vbe0 is the value of Vbe at 0°K, λ is the slope of Vbe0 decay with temperature, and C(T) is a nonlinear quantity.

[0009] The slope λ is process dependent and, therefore, introduces inaccuracies in Vbe. Figure 1B The sampling spread of Vbe values ​​caused by different values ​​of slope λ can be seen in Figure 1B It can be noted in , that the inaccuracy introduced into Vbe by the slope λ is linear. Since the inaccuracy is linear, this can be easily corrected via calibration.

[0010] As stated, C(T) is a nonlinear quantity and is responsible for the nonlinear curvature that exists in Vctat across temperature. C(T) can be mathematically expressed as:

[0011]

[0012] where k is the Boltzmann constant, q is the magnitude of the electron charge, n is typically 4 for silicon, T is the temperature in Kelvin, and m is the exponential proportionality of the bias current to T (Ibias∝T m ), and Tr is the reference temperature.

[0013] Can be Figure 1C It can be seen from the nonlinear inaccuracy introduced by C(T) in Vbe that Figure 1C In , Vbe curves across temperature (e.g., has a nonlinear slope). Figure 1D As can be seen in Figure 1, since Vref is calculated as Vctat + Vptat, it should be kept in mind that Vctat = Vbe. This is because Vptat is relatively error-free and the curvature of Vctat produces a temperature-dependent curvature in Vref. is used to calculate the output temperature, so it can be understood that the curvature of Vref produces a nonlinear error in the output temperature, such as Figure 1E As shown in .

[0014] Attempts have been made to correct this error and generate a truly temperature-independent reference voltage. For example, a first prior art design is disclosed in "Curvature-compensated BiCMOS bandgap with 1-V supply voltage" by P. Malcovati, F. Maloberti, C. Fiocchi, and M. Pruzzi, IEEE Journal of Solid-State Circuits, Vol. 36, July 2001, pp. 1076-01081 (incorporated by reference). However, this design utilizes an operational amplifier to add the compensation voltage, and the offset of the operational amplifier itself introduces errors into the compensation voltage. A second prior art design is disclosed in "A single-trim CMOS bandgap reference with a 3σ inaccuracy of 0.15% from 40C to 125C" by G. Ce, C. Zhang, G. Hoogezand, and K. Makinwa, 2010 IEEE International Solid-State Circuits Conference Technical Paper Abstracts (ISSCC), February 2010, pages 78-79. However, this design suffers from similar drawbacks as the first prior art design discussed above.

[0015] Thus, attempts to date to correct for non-linearities in Vctat (and hence Vref) across temperature have been insufficient to properly eliminate the non-linearities, and further developments are needed. In particular, a design is desired that is capable of adding a highly accurate compensation voltage, for example by using sigma-delta modulation. Summary of the invention

[0016] A temperature sensing circuit including a voltage generating circuit device is disclosed herein. The voltage generating circuit device includes: a first bipolar junction transistor and a second bipolar junction transistor having coupled collectors and bases and biased at different current densities; a third bipolar junction transistor having a collector coupled to its base, the third bipolar junction transistor biased by a calibration current and having a base-emitter voltage, the base-emitter voltage being a voltage complementary to absolute temperature, the voltage complementary to absolute temperature having a curved nonlinearity across temperature; and a fourth bipolar junction transistor and a fifth bipolar junction transistor having coupled collectors and bases, the fifth bipolar junction transistor biased by a constant current independent of temperature, the fourth bipolar junction transistor biased by a current proportional to absolute temperature. The temperature sensing circuit also includes: a switched capacitor circuit configured to selectively sample the voltage generated by the voltage generating circuit device and provide the sampled voltage to the input of an integrator; and a quantization circuit configured to quantize the output of the integrator to generate a bit stream. The switched capacitor circuit cooperates with the integrator under the control of the bit stream to: cause the integration of the difference between the base-emitter voltage of the first bipolar junction transistor and the base-emitter voltage of the second bipolar junction transistor when the latest bit of the bit stream is a logic zero, thereby generating a voltage proportional to the absolute temperature; and, cause the integration of the difference between the base-emitter voltage of the fourth bipolar junction transistor and the sum of the voltage complementary to the absolute temperature and the base-emitter voltage of the fifth bipolar junction transistor when the latest bit of the bit stream is a logic one, thereby generating a negative voltage complementary to the absolute temperature, which has negligible nonlinearity across temperature. The temperature sensing circuit also includes: a low-pass filter and an extractor, which are configured to filter and extract the bit stream generated by the quantization circuit to generate a voltage indicating the temperature of the chip in which the temperature sensing circuit is placed.

[0017] The switched capacitor circuit may further include: a first variable capacitor for sampling and holding the base-emitter voltage of the fourth bipolar junction transistor, the first variable capacitor comprising parallel capacitors of the same capacitance being γ; a second variable capacitor for sampling and holding the base-emitter voltage of the fifth bipolar junction transistor, the second variable capacitor comprising parallel capacitors of the same capacitance being γ; wherein γ is selected so that the integral of the difference between the sum of the base-emitter voltage of the fourth bipolar junction transistor and the voltage complementary to the absolute temperature and the base-emitter voltage of the fifth bipolar junction transistor is During this period, the nonlinearity of the curvature over the temperature of the voltage complementary to the absolute temperature is offset; a third variable capacitor for sampling and holding the base-emitter voltage of the first bipolar junction transistor, the third variable capacitor comprising a number of parallel capacitors of the same capacitance being α; a first fixed capacitor for sampling and holding grounding; a second fixed capacitor for sampling and holding the base-emitter voltage of the third bipolar junction transistor; and a fourth variable capacitor for sampling and holding the base-emitter voltage of the second bipolar junction transistor, the fourth variable capacitor comprising a number of parallel capacitors of the same capacitance being α.

[0018] The switched capacitor circuit may further include: a first switch having a first node coupled to a base-emitter voltage of a fourth bipolar junction transistor, wherein the first switch operates in response to a third control signal; a second switch having a first node and a second node, the first node of the second switch being coupled to the second node of the first switch, the second node of the second switch being coupled to the first node of the first variable capacitor, wherein the second switch operates in response to the first control signal; a third switch having a first node and a second node, the first node of the third switch being coupled to the second node of the first variable capacitor, the second node of the third switch being coupled to the non-inverting input of the integrator, wherein the third switch operates in response to the second control signal; A fourth switch having a first node and a second node, the first node of the fourth switch being coupled to the second node of the first switch, the second node of the fourth switch being coupled to a common mode voltage, wherein the fourth switch operates in response to a fourth control signal; a fifth switch having a first node and a second node, the first node of the fifth switch being coupled to the first node of the first variable capacitor, the second node of the fifth switch being coupled to the common mode voltage, wherein the fifth switch operates in response to the second control signal; and a sixth switch having a first node and a second node, the first node of the sixth switch being coupled to the second node of the first variable capacitor, the second node of the sixth switch being coupled to the common mode voltage, wherein the sixth switch operates in response to the first control signal.

[0019] The switched capacitor circuit may further include: a seventh switch having a first node coupled to the base-emitter voltage of the first bipolar junction transistor, wherein the seventh switch operates in response to a fourth control signal; an eighth switch having a first node and a second node, the first node of the eighth switch being coupled to the second node of the seventh switch, the second node of the eighth switch being coupled to the first node of the third variable capacitor, wherein the eighth switch operates in response to the first control signal; a ninth switch having a first node and a second node, the first node of the ninth switch being coupled to the second node of the third variable capacitor, the second node of the ninth switch being coupled to the non-inverting input of the integrator, wherein the ninth switch operates in response to the second control signal; and a tenth switch, a tenth switch having a first node and a second node, the first node of the tenth switch being coupled to the second node of the seventh switch, the second node of the tenth switch being coupled to a common mode voltage, wherein the tenth switch operates in response to a third control signal; an eleventh switch having a first node and a second node, the first node of the eleventh switch being coupled to the first node of the third variable capacitor, the second node of the eleventh switch being coupled to the common mode voltage, wherein the eleventh switch operates in response to the second control signal; and a twelfth switch having a first node and a second node, the first node of the twelfth switch being coupled to the second node of the third variable capacitor, the second node of the twelfth switch being coupled to the common mode voltage, wherein the twelfth switch operates in response to the first control signal.

[0020] The switched capacitor circuit may further include: a thirteenth switch having a first node coupled to ground, wherein the thirteenth switch operates in response to a third control signal; a fourteenth switch having a first node and a second node, the first node of the fourteenth switch being coupled to the second node of the thirteenth switch, the second node of the fourteenth switch being coupled to the first node of the first fixed capacitor, wherein the fourteenth switch operates in response to the first control signal; a fifteenth switch having a first node and a second node, the first node of the fifteenth switch being coupled to the second node of the first fixed capacitor, the second node of the fifteenth switch being coupled to the non-inverting terminal of the non-inverting input of the integrator, wherein the fifteenth switch operates in response to the second control signal; a sixteenth switch having a first node and a second node, the first node of the fifteenth switch being coupled to the second node of the first fixed capacitor, the second node of the fifteenth switch being coupled to the non-inverting terminal of the non-inverting input of the integrator, wherein the fifteenth switch operates in response to the second control signal; A sixteenth switch having a first node and a second node, the first node of the sixteenth switch being coupled to the second node of the thirteenth switch, the second node of the sixteenth switch being coupled to the common mode voltage, wherein the sixteenth switch operates in response to a fourth control signal; a seventeenth switch having a first node and a second node, the first node of the seventeenth switch being coupled to the first node of the first fixed capacitor, the second node of the seventeenth switch being coupled to the common mode voltage, wherein the seventeenth switch operates in response to the second control signal; and an eighteenth switch having a first node and a second node, the first node of the eighteenth switch being coupled to the second node of the first fixed capacitor, the second node of the eighteenth switch being coupled to the common mode voltage, wherein the eighteenth switch operates in response to the first control signal.

[0021] The switched capacitor circuit may further include: a nineteenth switch having a first node coupled to the base-emitter voltage of the third bipolar junction transistor, wherein the nineteenth switch operates in response to the third control signal; a twentieth switch having a first node and a second node, the first node of the twentieth switch being coupled to the second node of the nineteenth switch, the second node of the twentieth switch being coupled to the first node of the second fixed capacitor, wherein the twentieth switch operates in response to the first control signal; a twenty-first switch having a first node and a second node, the first node of the twenty-first switch being coupled to the second node of the second fixed capacitor, the second node of the twenty-first switch being coupled to the inverting input of the integrator, wherein the twenty-first switch operates in response to the second control signal; and a twenty-second switch , having a first node and a second node, the first node of a twenty-second switch is coupled to the second node of the nineteenth switch, and the second node of the twenty-second switch is coupled to the common mode voltage, wherein the twenty-second switch operates in response to a fourth control signal; a twenty-third switch, having a first node and a second node, the first node of the twenty-third switch is coupled to the first node of the second fixed capacitor, and the second node of the twenty-third switch is coupled to the common mode voltage, wherein the twenty-third switch operates in response to the second control signal; and, a twenty-fourth switch, having a first node and a second node, the first node of the twenty-fourth switch is coupled to the second node of the second fixed capacitor, and the second node of the twenty-fourth switch is coupled to the common mode voltage, wherein the twenty-fourth switch operates in response to the first control signal.

[0022] The switched capacitor circuit may further include: a twenty-fifth switch having a first node coupled to the base-emitter voltage of the second bipolar junction transistor, wherein the twenty-fifth switch operates in response to a fourth control signal; a twenty-sixth switch having a first node and a second node, the first node of the twenty-sixth switch being coupled to the second node of the twenty-fifth switch, and the second node of the twenty-sixth switch being coupled to the first node of the fourth variable capacitor, wherein the twenty-sixth switch operates in response to the first control signal; a twenty-seventh switch having a first node and a second node, the first node of the twenty-seventh switch being coupled to the second node of the fourth variable capacitor, and the second node of the twenty-seventh switch being coupled to the inverting input of the integrator, wherein the twenty-seventh switch operates in response to the second control signal; an eighteenth switch having a first node and a second node, the first node of a twenty-eighth switch being coupled to the second node of a twenty-fifth switch, the second node of the twenty-eighth switch being coupled to a common mode voltage, wherein the twenty-eighth switch operates in response to a third control signal; a twenty-ninth switch having a first node and a second node, the first node of the twenty-ninth switch being coupled to the first node of a fourth variable capacitor, the second node of the twenty-ninth switch being coupled to the common mode voltage, wherein the twenty-ninth switch operates in response to the second control signal; and a thirtieth switch having a first node and a second node, the first node of the thirtieth switch being coupled to the second node of the fourth variable capacitor, the second node of the thirtieth switch being coupled to the common mode voltage, wherein the thirtieth switch operates in response to the first control signal.

[0023] The switched capacitor circuit may further include: a thirty-first switch having a first node coupled to the base-emitter voltage of the fifth bipolar junction transistor, wherein the thirty-first switch operates in response to the third control signal; a thirty-second switch having a first node and a second node, the first node of the thirty-second switch being coupled to the second node of the thirty-first switch, the second node of the thirty-second switch being coupled to the first node of the second variable capacitor, wherein the thirty-second switch operates in response to the first control signal; a thirty-third switch having a first node and a second node, the first node of the thirty-third switch being coupled to the second node of the second variable capacitor, the second node of the thirty-third switch being coupled to the non-inverting input of the integrator, wherein the thirty-third switch operates in response to the second control signal; a fourth switch having a first node and a second node, the first node of a thirty-fourth switch being coupled to the second node of a thirty-first switch, the second node of the thirty-fourth switch being coupled to a common mode voltage, wherein the thirty-fourth switch operates in response to a fourth control signal; a thirty-fifth switch having a first node and a second node, the first node of the thirty-fifth switch being coupled to the first node of a second variable capacitor, the second node of the thirty-fifth switch being coupled to a common mode voltage, wherein the thirty-fifth switch operates in response to a second control signal; and a thirty-sixth switch having a first node and a second node, the first node of the thirty-sixth switch being coupled to the second node of the second variable capacitor, the second node of the thirty-sixth switch being coupled to a common mode voltage, wherein the thirty-sixth switch operates in response to the first control signal.

[0024] The temperature sensor may also include: a control signal generator configured to: assert the first control signal and the fourth control signal, and de-assert the second control signal and the third control signal in a sampling phase when the latest bit of the bit stream is a logic zero; and, in an integration phase, assert the second control signal and simultaneously de-assert the first control signal, the third control signal, and the fourth control signal.

[0025] The control signal generator can also be configured to: assert the first control signal and the third control signal, and de-assert the second control signal and the fourth control signal in the sampling phase when the latest bit of the bit stream is logic one; and assert the second control signal, and de-assert the first control signal, the third control signal, and the fourth control signal in the integration phase.

[0026] A temperature sensing circuit is also disclosed herein, comprising: a switched capacitor circuit configured to selectively sample a voltage generated by a voltage generating circuit device and provide the sampled voltage to an input of an integrator; and a quantization circuit configured to quantize the output of the integrator to generate a bit stream; wherein under the control of the bit stream, the switched capacitor circuit cooperates with the integrator to cause integration of a first voltage, or causes a correction voltage to be added to a second voltage to generate a corrected voltage, and the corrected voltage is then integrated according to the latest bit of the bit stream.

[0027] The switched capacitor circuit may include: a first variable capacitance for sampling and holding a first component of the correction voltage, the first variable capacitance comprising a number γ of parallel capacitors of the same capacitance; and a second variable capacitance for sampling and holding a second component of the correction voltage, the second variable capacitance comprising γ parallel capacitors of the same capacitance. γ may be selected so that nonlinearity in the second voltage is offset during generation of the corrected voltage and integration of the corrected voltage.

[0028] The switched capacitor circuit may also include: a third variable capacitor for sampling and holding the first component of the first voltage, the third variable capacitor comprising a number α of parallel capacitors of the same capacitance; and a fourth variable capacitor for sampling and holding the second component of the first voltage, the fourth variable capacitor comprising a number α of parallel capacitors of the same capacitance.

[0029] The switched capacitor may cause integration of a first voltage when a latest bit of the bit stream is a first value and cause integration of a corrected voltage when a latest bit of the bit stream of a second voltage is a second value.

[0030] The first value may be a logical zero and the second value may be a logical one. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A is a graph showing generation of a temperature-independent reference voltage (Vref) in a prior art temperature sensor by summing a voltage proportional to absolute temperature (Vptat) and a voltage complementary to absolute temperature (Vctat).

[0032] Figure 1B is a graph showing how the slope of the voltage at the base-emitter junction of a bipolar junction transistor used to generate Vctat (also referred to as Vbe) across temperature is process dependent (varies from transistor to transistor due to process variations).

[0033] Figure 1C is a graph showing the curvature of the voltage complementary to absolute temperature across temperature that exists due to the lack of ideality of a bipolar junction transistor that generates a voltage complementary to absolute temperature.

[0034] Figure 1D is a graph showing the curvature of a graph of a temperature-independent reference voltage across temperature, which results from the curvature of a voltage complementary to absolute temperature.

[0035] Figure 1E is a graph showing the error in the temperature output produced by a prior art temperature sensor, the error being caused by the curvature of a reference voltage that is independent of temperature.

[0036] Figure 2 is a detailed schematic diagram of an on-chip temperature sensor utilizing a sigma-delta analog-to-digital converter according to the present disclosure.

[0037] Figure 3A shows the operation in the sampling phase when the previous output bit of the generated bit stream is a logic 1. Figure 2 design.

[0038] Figure 3B shows that when the previously output bit of the generated bit stream is a logic 1, the operation in the integration phase Figure 2 design.

[0039] Figure 3C shows the operation in the sampling phase when the previously output bit of the generated bit stream is a logic 0. Figure 2 design.

[0040] Figure 3D shows the operation in the integration phase when the previously output bit of the generated bit stream is a logic 0. Figure 2 design.

[0041] Figure 4 is a diagram showing the bits of the previously output bit stream generated during the sampling phase and the integration phase to generate FIG. 3A to FIG. 3C The operating status shown in Figure 2 A timing diagram of the timing of the switch control signal. DETAILED DESCRIPTION

[0042] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the examples shown, but is in accordance with the broadest scope of the principles and features disclosed or suggested herein.

[0043] In general, the temperature sensor circuit disclosed herein generates a first base-emitter junction voltage (Vbe1) of a first bipolar junction transistor biased at a first current density (I), a second base-emitter junction voltage (Vbe2) of a second bipolar junction transistor whose base and collector are coupled to the base and collector of the first bipolar junction transistor and biased at a second current density (pI), and a third base-emitter junction voltage (Vbe) of a third bipolar junction transistor biased at a calibration current (Ical) and having a nonlinear curvature that exists across temperature.

[0044] In addition, the temperature sensor circuit generates a first corrected base-emitter junction voltage (Vbe1_c) of a fourth bipolar junction transistor biased by a temperature-independent constant current (Iconst) and a second corrected base-emitter junction voltage (Vbe2_c) of a fifth bipolar junction transistor whose base and collector are coupled to the base and collector of the fourth bipolar junction transistor and is biased by a current proportional to the absolute temperature (Iptat).

[0045] The switched capacitor sigma-delta modulation (SDM) analog-to-digital converter (ADC) samples its input voltage and converts it into a digital bit stream (1 and 0) by using a loop filter based on a switched capacitor integrator block. The order of the loop filter depends on the number of integrators used. The output of the loop filter is then processed by a quantizer to produce a bit stream. The bit stream is used to apply appropriate feedback to complete the negative feedback loop. In the input sampling circuit of the first integrator, a reference voltage is sampled and subtracted from the sampled input voltage based on the previously generated bits of the bit stream. The complete loop encodes the bit stream in the time domain in this way: an appropriate digital decimation filter can generate a digital code corresponding to an accurate representation of the ratio of the input voltage to the reference voltage from the bit stream.

[0046] In the thermal sensor disclosed herein, the input sampling circuit of the SDM-based ADC can be used to sample an input voltage, which is a voltage proportional to absolute temperature (Vptat), according to Vbe1 and Vbe2. The input sampling circuit of the SDM can also generate a temperature-independent reference voltage (Vref) in an equivalent manner by sampling Vptat together with a corrected voltage complementary to absolute temperature (Vctat_c) by adding Vbe and the difference between Vbe1_c and Vbe2_c. The corrected voltage Vctat_c complementary to absolute temperature has a negligible nonlinear curvature across temperature, as does the reference voltage Vref generated by adding Vbe and the difference between Vbe1_c and Vbe2_c.

[0047] By using a suitable ratio of sampling capacitors, any scaling required to compensate for Vptat and Vctat_c can be included. For thermal sensors using sigma-delta modulation, the input voltage Vptat of the ADC is used, and both Vptat and Vctat_c are used as references. Using the principle of sigma-delta modulation, Vptat can be sampled as an input voltage, which is subtracted from a sampling reference voltage associated with the bit stream. Therefore, depending on whether the previously generated bit of the bit stream is 0 or 1, the sampled voltage can be Vptat or (Vptat-Vref). The sampled voltage can be further integrated and processed in a loop filter to generate a bit stream. The bit stream generated by the quantizer is used to operate the switches of the switched capacitor circuit in a suitable manner to achieve sampling and integration of Vptat and Vref in a manner that produces a sigma-delta encoded bit stream, which, after filtering and decimation within a given time window, represents a digital code that can be appropriately scaled to produce a digital temperature reading in the desired unit.

[0048] Reference now Figure 2 The structure of the temperature sensor circuit 5 is described in detail, and thereafter, reference will be made to FIG. 3A to FIG. 3D The operation of the temperature sensor circuit 5 is described.

[0049] A. Structure of temperature sensor circuit

[0050] The temperature sensor circuit 5 is arranged to include a sigma-delta modulation analog-to-digital converter (ADC). The temperature sensor circuit 5 includes an analog voltage generation circuit 10, a switched capacitor input sampling circuit 20 having an input receiving a voltage generated by the analog voltage generation circuit 10 and an output coupled to a non-inverting terminal and an inverting terminal of a first integrator 40. The first integrator 40 has an output coupled to an input of a second integrator 50, which in turn has an output coupled to an input of a quantization circuit 60. The quantization circuit 60 generates a bit stream, which is fed to a control signal generator 70, and the bit stream is low-pass filtered and extracted by a circuit 65. The control signal generator 70 generates control signals Φ1, Φ2, Φ3 and Φ4 in response to the logic states of the bits of the bit stream, wherein the control signals control the switch actuation of various switches of the switched capacitor input sampling circuit 20. The low-pass filtering and extraction circuit 65 generates an output code, which can be used to calculate the temperature of the chip in which the temperature sensor circuit 5 is integrated in the desired unit.

[0051] In detail, the analog voltage generating circuit 10 includes bipolar junction PNP transistors QP1 and QP2, the collectors and bases of which are connected to ground. The emitter of QP2 is connected to the current source 11 to receive the current I, and the emitter of QP1 is connected to the current source 12 to receive the current pI (which means that the magnitude of the current pI is equal to the magnitude of the current I, with a scaling factor of p). A voltage Vbe1 is generated at the emitter of the transistor QP1, which is the voltage of the base-emitter junction of the transistor QP1. Similarly, a voltage Vbe2 is generated at the emitter of the transistor QP2, which is the voltage of the base-emitter junction of the transistor QP2.

[0052] The analog voltage generating circuit 10 also includes a PNP transistor QP3, whose collector and base are connected to ground, and whose emitter is connected to a current source 13 to receive a calibration current Ical (calibrated to exclude the influence of a process-related parameter λ). A voltage Vbe is generated at the emitter of the transistor QP3, which is the voltage of the base-emitter junction of the transistor QP3. The voltage Vbe is complementary to the absolute temperature and can therefore be referred to as Vctat. As explained and understood by those skilled in the art, due to the non-ideal performance of the PNP transistor QP3, the voltage Vctat has a non-linear curvature that exists with temperature changes.

[0053] The signal generating circuit 10 also includes PNP transistors QP4 and QP5, whose collectors and bases are connected to ground. The emitter of transistor QP4 is connected to a current source 14 to receive a current Iptat that is proportional to absolute temperature, and the emitter of transistor QP5 is connected to a current source 15 to receive a current Iconst that is constant with respect to temperature. The voltage Vbe1_c is the voltage of the base-emitter junction of transistor QP5 and is referred to herein as "Vbe1 corrected", and the voltage Vbe2_c is the voltage of the base-emitter junction of transistor QP4 and is referred to herein as "Vbe2 corrected". As will be explained below, a voltage equal to Vbe2_c-Vbe1_c is a nonlinear compensation voltage Vnl that has a nonlinear curvature across temperature that has the same properties as the curvature present in the voltage Vctat.

[0054] The switched capacitor input sampling circuit 20 includes: a switch S1 (closed when the control signal Φ3 is logic high, otherwise open) to selectively connect the voltage Vbe2_c to the first node of the switch S2 (closed when the control signal Φ1 is logic high, otherwise open). A first node of an adjustable capacitor γCs1 (where the adjustable capacitor can be formed, for example, by γ parallel capacitors each having a capacitance of Cs1, where the number γ is settable) is connected to the second node of the switch S2. A switch S3 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the second node of the adjustable capacitor γCs1 to the non-inverting terminal of the first integrator 40. A switch S4 (closed when the control signal Φ4 is logic high, otherwise open) selectively connects the first node of the switch S2 to the common mode voltage Vcm. Switch S5 (closed when control signal Φ2 is logic high, otherwise open) selectively connects a first node of the adjustable capacitor γCs1 to the common-mode voltage Vcm, and switch S6 (closed when control signal Φ1 is logic high, otherwise open) selectively connects a second node of the adjustable capacitor γCs1 to the common-mode voltage Vcm.

[0055] The switched capacitor input sampling circuit 20 includes: a switch S7 (closed when the control signal Φ4 is high, otherwise open) to selectively connect the voltage Vbe1 to the first node of a switch S8 (closed when the control signal Φ1 is high, otherwise open). A first node of an adjustable capacitor αCs1 (where the adjustable capacitor can be formed, for example, by α parallel capacitors each having a capacitance of Cs1, where the number α is settable) is connected to the second node of the switch S8. A switch S9 (closed when the control signal Φ2 is high, otherwise open) selectively connects the second node of the adjustable capacitor αCs1 to the non-inverting terminal of the first integrator 40. A switch S10 (closed when the control signal Φ3 is high, otherwise open) selectively connects the first node of the switch S8 to the common mode voltage Vcm. A switch S11 (closed when the control signal Φ2 is high, otherwise open) selectively connects the first node of the adjustable capacitor αCs1 to the common mode voltage Vcm. The switch S12 (closed when the control signal Φ1 is high, otherwise open) selectively connects the second node of the adjustable capacitor αCs1 to the common mode voltage Vcm.

[0056] The switched capacitor input sampling circuit 20 includes a switch S13 (closed when the control signal Φ3 is logic high, otherwise open) to selectively connect the ground to the first node of the switch S14 (closed when the control signal Φ1 is logic high, otherwise open). The second node of the switch S14 is connected to the first node of the capacitor Cs1. The switch S15 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the second node of the capacitor Cs1 to the non-inverting input of the first integrator 40. The switch S16 (closed when the control signal Φ4 is logic high, otherwise open) selectively connects the first node of the switch S14 to the common mode voltage Vcm. The switch S17 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the first node of the capacitor Cs1 to the common mode voltage Vcm, and the switch S18 (closed when the control signal Φ1 is logic high, otherwise open) selectively connects the second node of the capacitor Cs2 to the common mode voltage Vcm.

[0057] The switch S19 (closed when the control signal Φ3 is logic high, otherwise open) selectively connects the voltage Vbe to the first node of the switch S20 (closed when the control signal Φ1 is logic high, otherwise open). The second node of the switch S20 is connected to the first node of the capacitor Cs2. The switch S21 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the second node of the capacitor Cs2 to the inverting terminal of the first integrator 40. The switch S22 (closed when the control signal Φ4 is logic high, otherwise open) selectively connects the first node of the switch S20 to the common mode voltage Vcm. The switch S23 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the first node of the capacitor Cs2 to the common mode voltage Vcm. The switch S24 (closed when the control signal Φ1 is logic high, otherwise open) selectively connects the second node of the capacitor Cs2 to the common mode voltage Vcm.

[0058] The switch S25 (closed when the control signal Φ4 is logic high, otherwise open) selectively connects the voltage Vbe2 to the first node of the switch S26 (closed when the control signal Φ1 is logic high, otherwise open). The second node of the switch S26 is connected to the first node of the adjustable capacitance αCs2 (where the adjustable capacitance can be, for example, formed by α parallel capacitors each having a capacitance of Cs2, where the number α is settable). The second node of the adjustable capacitance αCs2 is selectively connected to the inverting terminal of the first integrator by the switch S27 (closed when the control signal Φ2 is logic high, otherwise open). The switch S28 (closed when the control signal Φ3 is logic high, otherwise open) selectively connects the first node of the switch S26 to the common mode voltage Vcm. The switch S29 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the first node of the adjustable capacitance αCs2 to the common mode voltage. The switch S30 (closed when the control signal Φ1 is logic high, otherwise open) selectively connects the second node of the adjustable capacitor αCs2 to the common mode voltage.

[0059] The switch S31 (closed when the control signal Φ3 is logic high, otherwise open) selectively connects the voltage Vbe1_c to the first node of the switch S32 (closed when the control signal Φ1 is logic high, otherwise open). The second node of the switch S32 is connected to the first node of the adjustable capacitance γCs2 (wherein the adjustable capacitance can be formed, for example, by γ parallel capacitors each having a capacitance of Cs2, where the number γ is settable). The second node of the adjustable capacitance γCs2 is selectively connected to the inverting terminal of the first integrator 40 by the switch S33 (closed when the control signal Φ2 is logic high, otherwise open). The switch S34 (closed when the control signal Φ4 is logic high, otherwise open) selectively connects the first node of the switch S32 to the common mode voltage Vcm. The switch S35 (closed when the control signal Φ2 is logic high, otherwise open) selectively connects the first node of the adjustable capacitance γCs2 to the common mode voltage Vcm. The switch S36 (closed when the control signal Φ1 is logic high, otherwise open) selectively connects the second node of the adjustable capacitor γCs2 to the common mode voltage Vcm.

[0060] The first integrator 40 is constituted by an amplifier 41 having a first integrating capacitor Ci1 connected between its non-inverting input and its non-inverting output and a second integrating capacitor Ci2 connected between its inverting input and its inverting output. The second integrator 50 has inputs coupled to the non-inverting output and the inverting output of the amplifier 41, and has an output coupled to the input of the quantization circuit 60. The quantization circuit 60 has an output (providing a bit stream) coupled to a low-pass filtering and extraction circuit 65 and a control signal generator 70. As stated, the low-pass filtering and extraction circuit 65 provides an output code, and the output digital code is used to determine the temperature of the chip in which the temperature sensor circuit 5 is integrated. In addition, as also stated, the control signal generator 70 generates new control signals Φ1, Φ2, Φ3, Φ4 according to the latest received bits of the bit stream.

[0061] B. Function of temperature sensor circuit

[0062] First, the theory on which the operation of the temperature sensor circuit 5 is based is described.

[0063] The voltage generated by the operation of transistors QP1 and QP2 and sampling circuit 20 and first integrator 40 equal to α*(Vbe1−Vbe2) is proportional to absolute temperature and may be referred to as Vptat or α*ΔVbe. The value of α is set by adjustable capacitors αCs1 and αCs2 in sampling circuit 20.

[0064] The voltage Vbe generated by transistor QP3 is complementary to absolute temperature and may be referred to as Vctat. Vbe may be mathematically represented as Vbe=Vbe0-λT+C(T), where Vbe0 is the value of Vbe at 0°K, λ is the decay slope of Vbe0 across temperature, and C(T) is a nonlinear quantity. The term C(T) is responsible for the nonlinear curvature present in Vbe over temperature. C(T) may be mathematically represented as where k is the Boltzmann constant, q is the magnitude of the electron charge, n is typically 4 for silicon, T is the temperature in Kelvin, and m is the exponential proportionality of the bias current to T (Ibias∝T m ), and Tr is the reference temperature.

[0065] The voltage Vbe1_c-Vbe2_c generated by the operation of the transistors QP4 and QP5 and the sampling circuit 20 may be referred to as a nonlinear correction voltage Vnl and may be mathematically expressed as where k is the Boltzmann constant, q is the magnitude of the electron charge, T is the temperature in Kelvin, Tr is the reference temperature, Vconst is a constant voltage relative to the temperature, and λ bias is the multiplication constant in the bias current generation.

[0066] Note that both voltages Vbe and Vnl have the same The term is responsible for the non-ideal behavior of the transistors generating the voltages Vbe and Vnl across temperature due to the natural logarithm term. By scaling the voltage Vnl by γ=n-m (where n and m here have the same values ​​as n and m in the C(T) term of Vbe, and where the value of γ is set by the adjustable capacitors γCs1 and γCs2 in the sampling circuit 20), when the voltage γVnl is added to the voltage Vbe, the non-linearity in the C(T) term of Vbe is reduced by The terms have opposite polarity and advantageously cancel.

[0067] This means that by adding voltage γVnl to voltage Vbe, a corrected voltage Vbe_c=γ(Vbe1_c−Vbe2_c)+Vbe complementary to absolute temperature can be produced which has an almost negligible amount of curvature in the graph of its value across temperature.

[0068] By adding the voltage Vbe_c to the voltage α*ΔVbe, a temperature-independent reference voltage Vref can be produced that has an almost negligible amount of curvature in the graph of its value across temperature variations.

[0069] The goal of the temperature sensor circuit 5 is to produce a digital code that represents α*ΔVbe sampled relative to Vref within a given time window, or in other words, the ratio μ=α*ΔVbe / Vref that can be used in the equation "Temperature=A*μ+B" (where A and B are constants that are chosen so that the temperature is expressed in desired unit values ​​(such as degrees Celsius)).

[0070] To this end, when the most recently generated value of the bit stream (produced by the quantization circuit 60) is a logic zero, it is desired that the sigma-delta modulation analog-to-digital converter samples the voltage α*ΔVbe, and when the most recently generated value of the bit stream is a logic one, it is desired that the sigma-delta modulation analog-to-digital converter samples the voltage α*ΔVbe-Vref.

[0071] As explained above, the voltage Vref = αΔVbe + Vbe_c. Therefore, expanding the expression α*ΔVbe-Vref yields αΔVbe-αΔVbe-Vbe_c, which simplifies to -Vbe_c. Therefore, when the bit stream is a logical one and Vin-Vref is to be sampled, only -Vbe_c needs to be sampled.

[0072] Now, refer to FIG. 3A to FIG. 3D as well as Figure 4The operation of the temperature sensor circuit is described in detail in the timing diagram of FIG. Upon receiving each pulse of the clock signal CLK, the control signal generator 70 generates new values ​​of the control signals Φ1, Φ2, Φ3 and Φ4 based on the logic value of the most recently received bit of the bit stream generated by the quantization circuit 60. The control signals Φ1, Φ2, Φ3 and Φ4 are generated so as to complete the sampling phase when the clock signal CLK is logic high and to complete the integration phase when the clock signal CLK is logic low.

[0073] Figure 3A , the case where the most recently generated bit of the bit stream received by the control signal generator 70 is a logic one. In this case, Figure 4 As shown in , when the clock signal CLK changes to logic high and the bit stream is logic one, the control signal generator 70 causes the control signals Φ1 and Φ3 to change to logic high and remain logic high until the clock signal CLK changes to logic low, and maintains the control signals Φ2 and Φ4 to logic low, thereby starting the sampling phase.

[0074] exist Figure 3A The sampling phase is shown in Figure 3A It can be seen that: switches S1, S2 and S6 are closed to sample the voltage Vbe2_c of the reference common-mode voltage Vcm across the adjustable capacitor γCs1, thereby charging the adjustable capacitor γCs1 to γ*(Vbe2_c-Vcm); switches S13, S14 and S18 are closed to sample the ground voltage GND of the reference common-mode voltage Vcm across the capacitor Cs1, thereby charging the capacitor Cs1 to GND-Vcm; switches S19, S20 and S24 are closed to sample the voltage Vbe of the reference common-mode voltage Vcm across the capacitor Cs2, thereby charging the capacitor Cs2 to Vbe-Vcm; and switches S31, S32 and S36 are closed to sample the voltage Vbe1_c of the reference common-mode voltage Vcm across the adjustable capacitor γCs2, thereby charging the adjustable capacitor γCs2 to γ*(Vbe1_c-Vcm). In addition, in order to maintain the capacitive load on the first integrator 40 to be uniform during the sampling phase and the integration phase: switches S10, S8 and S12 are closed to sample the common-mode voltage Vcm referenced to itself across the adjustable capacitor αCs1, thereby maintaining the adjustable capacitor αCs1 at 0V; and switches S28, S26 and S30 are closed to sample the common-mode voltage Vcm referenced to itself across the adjustable capacitor αCs2, thereby maintaining the adjustable capacitor αCs2 at 0V.

[0075] Then, if Figure 4As shown in , when the clock signal CLK transitions to logic low, the control signal generator 70 then transitions the control signals Φ1 and Φ3 to logic low, transitions the control signal Φ2 to logic high, and maintains the control signal Φ4 to logic low, thereby starting the integration phase. Figure 3B The integration phase is shown in Figure 3B It can be seen that: switches S2 and S3 are closed to add the voltage γVcm to the voltage γ*(Vbe2_c-Vcm) stored across the adjustable capacitor γCs1, thereby applying γ*Vbe2_c to the non-inverting terminal of the first integrator 40; switches S17 and S15 are closed to add the voltage Vcm to the voltage GND-Vcm stored across the capacitor Cs1, thereby applying 0V to the non-inverting terminal of the first integrator 40; switches S23 and S21 are closed to add the voltage Vcm to the voltage Vbe-Vcm stored across the capacitor Cs2, thereby applying the voltage Vbe to the inverting terminal of the first integrator 40; and switches S35 and S33 are closed to add the voltage γVcm to the voltage γ*(Vbe1_c-Vcm) stored across the adjustable capacitor γCs2, thereby applying the voltage γ*Vbe1_c to the inverting terminal of the first integrator 40.

[0076] In addition, in order to maintain the capacitive load on the first integrator 40 to be uniform across the sampling phase and the integration phase: switches S11 and S9 are closed to add αVcm to the 0V stored across the adjustable capacitor αCs1, thereby applying αVcm to the non-inverting terminal of the first integrator 40; and switches S29 and S27 are closed to add αVcm to the 0V stored across the adjustable capacitor αCs2, thereby applying αVcm to the inverting terminal of the first integrator 40.

[0077] Summing the voltages applied to the non-inverting terminal of the first integrator 40 produces a voltage γ*Vbe2_c+αVcm, while summing the voltages applied to the inverting terminal of the first integrator 40 produces a voltage Vbe+γ*Vbe1_c+αVcm. Therefore, the result of the integration performed by the first integrator 40 is a voltage γVbe2_c-γVbe1_c-Vbe, assuming that the first integrator 40 has a unity gain.

[0078] As stated above, when the bit stream is 1, it is desirable to sample the voltage -Vbe_c. Since we know that the voltage Vbe_c = γ(Vbe1_c - Vbe2_c) + Vbe = γVbe1_c - γVbe2_c + Vbe, this means that the voltage -Vbe_c will be equal to the voltage -γVbe1_c + γVbe2_c - Vbe. Rearranged, this means that the voltage -Vbe_c will be equal to the voltage Vbe2_c - γVbe1_c - Vbe, which, as shown directly above, is given by Figure 3B The first integrator 40 in FIG.

[0079] Thus, when the bit stream is 1, the first integrator 40 integrates the voltage -Vbe_c as needed. The second integrator 50 performs another integration of the voltage -Vbe_c, which is then quantized to generate the next bit of the bit stream by the quantization circuit 60. This next bit of the bit stream will be used by the control signal generator 70 to generate new values ​​for the control signals Φ1, Φ2, Φ3, and Φ4. In addition, the bit stream passes through the circuit 65, which performs low-pass filtering and decimation to produce an output digital code (wherein the ratio of 1 to 0 within a given time window represents the desired output μ, which can be used to calculate the temperature of the chip in which the temperature sensor circuit 5 is integrated).

[0080] Now assume that the next bit generated by quantization circuit 60 is a logic 0. In this case, Figure 4 As shown in , when the clock signal CLK changes to logic high and the bit stream is logic zero, the control signal generator 70 causes the control signals Φ1 and Φ4 to change to logic high and remain logic high until the clock signal CLK changes to logic low, while maintaining the control signals Φ2 and Φ3 at logic low, thereby starting the sampling phase. Figure 3C The sampling phase is shown in Figure 3C It can be seen that: switches S7, S8 and S12 are closed to sample the voltage Vbe1 of the reference common-mode voltage Vcm across the adjustable capacitor αCs1, thereby charging the adjustable capacitor αCs1 to the voltage α*(Vbe1-Vcm); and switches S25, S26 and S30 are closed to sample the voltage Vbe2 of the reference common-mode voltage Vcm across the adjustable capacitor αCs2, thereby charging the adjustable capacitor αCs2 to the voltage α*(Vbe2-Vcm).

[0081] In addition, in order to maintain the capacitive load on the first integrator 40 uniform across the sampling phase and the integration phase: switches S4, S2 and S6 are closed to sample the common-mode voltage Vcm referenced to itself across the adjustable capacitor γCs1, thereby maintaining the adjustable capacitor γCs1 at 0V; switches S16, S14 and S18 are closed to sample the common-mode voltage Vcm referenced to itself across the capacitor Cs1, thereby maintaining the capacitor Cs1 at 0V; switches S22, S20 and S24 are closed to sample the common-mode voltage Vcm referenced to itself across the capacitor Cs2, thereby maintaining the capacitor Cs2 at 0V; and switches S34, S32 and S36 are closed to sample the common-mode voltage referenced to itself across the adjustable capacitor γCs2, thereby maintaining the adjustable capacitor γCs2 at 0V.

[0082] Then, if Figure 4As shown in , when the clock signal CLK transitions to logic low, the control signal generator 70 then transitions the control signals Φ1 and Φ4 to logic low, transitions the control signal Φ2 to logic high, and maintains the control signal Φ3 to logic low, thereby starting the integration phase. Figure 3D The integration phase is shown in Figure 3D It can be seen that: switches S11 and S9 are closed to add the voltage αVcm to the α*(Vbe1-Vcm) stored across the adjustable capacitor αCs1, thereby applying the voltage αVbe1 to the non-inverting terminal of the first integrator 40; and switches S29 and S27 are closed to add the voltage αVcm to the voltage α*(Vbe2-Vcm) stored across the adjustable capacitor αCs2, thereby applying the voltage αVbe2 to the inverting terminal of the first integrator 40.

[0083] In addition, in order to maintain the capacitive load on the first integrator 40 to be uniform across the sampling phase and the integration phase: switches S5 and S3 are closed to add γVcm to the 0V stored across the adjustable capacitor γCs1, thereby applying the voltage γVcm to the non-inverting terminal of the first integrator 40; switches S17 and S15 are closed to add Vcm to the 0V stored across the capacitor Cs1, thereby applying the voltage Vcm to the non-inverting terminal of the first integrator 40; switches S23 and S21 are closed to add Vcm to the 0V stored across the capacitor Cs2, thereby applying the voltage Vcm to the inverting terminal of the first integrator 40; and switches S35 and S33 are closed to add γVcm to the 0V stored across the adjustable capacitor γCs2, thereby applying the voltage γVcm to the inverting terminal of the first integrator 40.

[0084] Summing the voltages applied to the non-inverting terminal of the first integrator 40 produces a voltage αVbe1+γVcm+Vcm, while summing the voltages applied to the inverting terminal of the first integrator 40 produces a voltage αVbe2+γVcm+Vcm. Therefore, the result of the integration performed by the first integrator 40 is a voltage αVbe1-αVbe2, assuming that the first integrator 40 has a unity gain.

[0085] As stated above, when the bit stream is 0, it is desirable to sample the voltage αΔVbe=αVbe1-αVbe2, which, as directly shown above, is given by Figure 3D The result of the integration performed by the first integrator 40 in .

[0086] Thus, it can be seen that when the bit stream is 0, the first integrator 40 integrates the voltage αΔVbe as required. The second integrator 50 performs another integration of the voltage αΔVbe, which is then quantized to generate the next bit of the bit stream through the quantization circuit 60. This next bit of the bit stream will be used by the control signal generator 70 to generate new values ​​of the control signals Φ1, Φ2, Φ3, and Φ4. In addition, the bit stream passes through the low-pass filtering and extraction circuit 65, which performs low-pass filtering and extraction to produce an output digital code (wherein, within a given time window, the ratio of 1 to 0 represents the desired output μ, which can be used to calculate the temperature of the chip in which the temperature sensor circuit 5 is integrated).

[0087] By using adjustable capacitors γCs1 and γCs2, the compensation voltage γVnl can be adjusted so that it has the same nonlinear component as the voltage Vbe, thereby allowing the nonlinear component of the voltage Vbe to be properly corrected. It should be noted that this embodiment lacks the use of an operational amplifier to generate the compensation voltage γVnl or other circuit devices that introduce their own nonlinearity. In addition, by using adjustable capacitors αCs1 and αCs2, the voltage ΔVbe can be appropriately scaled, but there is no need to use an operational amplifier to generate the voltage αΔVbe.

[0088] Although the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments may be conceived without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure shall be limited solely by the appended claims.

Claims

1. A temperature sensing circuit, comprising: A voltage generating circuit device comprising: a first bipolar junction transistor and a second bipolar junction transistor having coupled collectors and bases and biased at different current densities; a third bipolar junction transistor having a collector coupled to its base, the third bipolar junction transistor being biased by a calibration current and having a base-emitter voltage, the base-emitter voltage of the third bipolar junction transistor being a complementary to absolute temperature voltage having a curved nonlinearity across temperature; and a fourth bipolar junction transistor and a fifth bipolar junction transistor having coupled collectors and bases, the fifth bipolar junction transistor being biased by a constant current that is independent of temperature and the fourth bipolar junction transistor being biased by a current that is proportional to absolute temperature; a switched capacitor circuit configured to selectively sample a voltage produced by the voltage generating circuit arrangement and provide the sampled voltage to an input of an integrator; a quantization circuit configured to quantize the output of the integrator to generate a bit stream; wherein the switched capacitor circuit cooperates with the integrator under the control of the bit stream to perform the following steps: When the most recent bit of the bit stream is a logic zero, causing integration of a difference between a base-emitter voltage of the first bipolar junction transistor and a base-emitter voltage of the second bipolar junction transistor to produce a voltage proportional to absolute temperature; and causing, when the most recent bit of the bit stream is a logic one, an integration of a difference between a base-emitter voltage of the fourth bipolar junction transistor and a sum of the complementary to absolute temperature voltage and a base-emitter voltage of the fifth bipolar junction transistor to produce a negative complementary to absolute temperature voltage having negligible nonlinearity across temperature; and A low pass filter and decimator are configured to filter and decimate the bit stream generated by the quantization circuit to generate a voltage indicative of the temperature of the chip in which the temperature sensing circuit is placed.

2. The temperature sensing circuit of claim 1 , wherein the switched capacitor circuit comprises: a first variable capacitor, used for sampling and holding the base-emitter voltage of the fourth bipolar junction transistor, the first variable capacitor being composed of parallel capacitors having the same capacitance and the number of the capacitors being γ; and a second variable capacitor, for sampling and holding the base-emitter voltage of the fifth bipolar junction transistor, the second variable capacitor being composed of γ parallel capacitors of the same capacitance; wherein γ is selected so that the nonlinearity of the bending of the voltage complementary to the absolute temperature across temperature is canceled during integration of the difference between the base-emitter voltage of the fourth bipolar junction transistor and the sum of the voltage complementary to the absolute temperature and the base-emitter voltage of the fifth bipolar junction transistor.

3. The temperature sensing circuit of claim 2, wherein the switched capacitor circuit further comprises: a third variable capacitor, used for sampling and holding the base-emitter voltage of the first bipolar junction transistor, wherein the third variable capacitor is composed of parallel capacitors having the same capacitance and the number of the capacitors being α; A first fixed capacitor for sampling and holding ground; a second fixed capacitor, for sampling and holding a base-emitter voltage of the third bipolar junction transistor; and A fourth variable capacitor is used to sample and hold the base-emitter voltage of the second bipolar junction transistor, wherein the fourth variable capacitor is composed of α parallel capacitors of the same capacitance.

4. The temperature sensing circuit of claim 3, wherein the switched capacitor circuit further comprises: a first switch having a first node coupled to a base-emitter voltage of the fourth bipolar junction transistor, wherein the first switch operates in response to a third control signal; a second switch having a first node and a second node, the first node of the second switch being coupled to the second node of the first switch, the second node of the second switch being coupled to the first node of the first variable capacitor, wherein the second switch operates in response to a first control signal; a third switch having a first node and a second node, the first node of the third switch being coupled to the second node of the first variable capacitor, the second node of the third switch being coupled to the non-inverting input of the integrator, wherein the third switch operates in response to a second control signal; a fourth switch having a first node and a second node, the first node of the fourth switch being coupled to the second node of the first switch, the second node of the fourth switch being coupled to a common mode voltage, wherein the fourth switch operates in response to a fourth control signal; a fifth switch having a first node and a second node, the first node of the fifth switch being coupled to the first node of the first variable capacitor, the second node of the fifth switch being coupled to the common mode voltage, wherein the fifth switch operates in response to the second control signal; as well as A sixth switch has a first node and a second node, the first node of the sixth switch is coupled to the second node of the first variable capacitor, the second node of the sixth switch is coupled to the common mode voltage, wherein the sixth switch operates in response to the first control signal.

5. The temperature sensing circuit of claim 4, wherein the switched capacitor circuit further comprises: a seventh switch having a first node coupled to a base-emitter voltage of the first bipolar junction transistor, wherein the seventh switch operates in response to the fourth control signal; an eighth switch having a first node and a second node, the first node of the eighth switch being coupled to the second node of the seventh switch, the second node of the eighth switch being coupled to the first node of the third variable capacitor, wherein the eighth switch operates in response to the first control signal; a ninth switch having a first node and a second node, the first node of the ninth switch being coupled to the second node of the third variable capacitor, the second node of the ninth switch being coupled to the non-inverting input of the integrator, wherein the ninth switch operates in response to the second control signal; a tenth switch having a first node and a second node, the first node of the tenth switch being coupled to the second node of the seventh switch, the second node of the tenth switch being coupled to the common mode voltage, wherein the tenth switch operates in response to the third control signal; an eleventh switch having a first node and a second node, the first node of the eleventh switch being coupled to the first node of the third variable capacitor, the second node of the eleventh switch being coupled to the common mode voltage, wherein the eleventh switch operates in response to the second control signal; as well as A twelfth switch has a first node and a second node, the first node of the twelfth switch is coupled to the second node of the third variable capacitor, the second node of the twelfth switch is coupled to the common mode voltage, and the twelfth switch operates in response to the first control signal.

6. The temperature sensing circuit of claim 5, wherein the switched capacitor circuit further comprises: a thirteenth switch having a first node coupled to ground, wherein the thirteenth switch operates in response to the third control signal; a fourteenth switch having a first node and a second node, the first node of the fourteenth switch being coupled to the second node of the thirteenth switch, the second node of the fourteenth switch being coupled to the first node of the first fixed capacitor, wherein the fourteenth switch operates in response to the first control signal; a fifteenth switch having a first node and a second node, the first node of the fifteenth switch being coupled to the second node of the first fixed capacitor, the second node of the fifteenth switch being coupled to the non-inverting input of the integrator, wherein the fifteenth switch operates in response to the second control signal; a sixteenth switch having a first node and a second node, the first node of the sixteenth switch being coupled to the second node of the thirteenth switch, the second node of the sixteenth switch being coupled to the common mode voltage, wherein the sixteenth switch operates in response to the fourth control signal; a seventeenth switch having a first node and a second node, the first node of the seventeenth switch being coupled to the first node of the first fixed capacitor, the second node of the seventeenth switch being coupled to the common mode voltage, wherein the seventeenth switch operates in response to the second control signal; as well as An eighteenth switch has a first node and a second node, the first node of the eighteenth switch is coupled to the second node of the first fixed capacitor, the second node of the eighteenth switch is coupled to the common mode voltage, and the eighteenth switch operates in response to the first control signal.

7. The temperature sensing circuit of claim 6, wherein the switched capacitor circuit further comprises: a nineteenth switch having a first node coupled to a base-emitter voltage of the third bipolar junction transistor, wherein the nineteenth switch operates in response to the third control signal; a twentieth switch having a first node and a second node, the first node of the twentieth switch being coupled to the second node of the nineteenth switch, the second node of the twentieth switch being coupled to the first node of the second fixed capacitor, wherein the twentieth switch operates in response to the first control signal; a twenty-first switch having a first node and a second node, the first node of the twenty-first switch being coupled to the second node of the second fixed capacitor, the second node of the twenty-first switch being coupled to the inverting input of the integrator, wherein the twenty-first switch operates in response to the second control signal; a twenty-second switch having a first node and a second node, the first node of the twenty-second switch being coupled to the second node of the nineteenth switch, the second node of the twenty-second switch being coupled to the common mode voltage, wherein the twenty-second switch operates in response to the fourth control signal; a twenty-third switch having a first node and a second node, the first node of the twenty-third switch being coupled to the first node of the second fixed capacitor, the second node of the twenty-third switch being coupled to the common mode voltage, wherein the twenty-third switch operates in response to the second control signal; as well as A twenty-fourth switch has a first node and a second node, the first node of the twenty-fourth switch is coupled to the second node of the second fixed capacitor, the second node of the twenty-fourth switch is coupled to the common mode voltage, wherein the twenty-fourth switch operates in response to the first control signal.

8. The temperature sensing circuit of claim 7, wherein the switched capacitor circuit further comprises: a twenty-fifth switch having a first node coupled to a base-emitter voltage of the second bipolar junction transistor, wherein the twenty-fifth switch operates in response to the fourth control signal; a twenty-sixth switch having a first node and a second node, the first node of the twenty-sixth switch being coupled to the second node of the twenty-fifth switch, the second node of the twenty-sixth switch being coupled to the first node of the fourth variable capacitor, wherein the twenty-sixth switch operates in response to the first control signal; a twenty-seventh switch having a first node and a second node, the first node of the twenty-seventh switch being coupled to the second node of the fourth variable capacitor, the second node of the twenty-seventh switch being coupled to the inverting input of the integrator, wherein the twenty-seventh switch operates in response to the second control signal; a twenty-eighth switch having a first node and a second node, the first node of the twenty-eighth switch being coupled to the second node of the twenty-fifth switch, the second node of the twenty-eighth switch being coupled to the common mode voltage, wherein the twenty-eighth switch operates in response to the third control signal; a twenty-ninth switch having a first node and a second node, the first node of the twenty-ninth switch being coupled to the first node of the fourth variable capacitor, the second node of the twenty-ninth switch being coupled to the common mode voltage, wherein the twenty-ninth switch operates in response to the second control signal; as well as A thirtieth switch having a first node and a second node, wherein the first node of the thirtieth switch is coupled to the second node of the fourth variable capacitor, and the second node of the thirtieth switch is coupled to the common mode voltage, wherein the thirtieth switch operates in response to the first control signal.

9. The temperature sensing circuit of claim 8, wherein the switched capacitor circuit further comprises: a thirty-first switch having a first node coupled to a base-emitter voltage of the fifth bipolar junction transistor, wherein the thirty-first switch operates in response to the third control signal; a thirty-second switch having a first node and a second node, the first node of the thirty-second switch being coupled to the second node of the thirty-first switch, the second node of the thirty-second switch being coupled to the first node of the second variable capacitor, wherein the thirty-second switch operates in response to the first control signal; a thirty-third switch having a first node and a second node, the first node of the thirty-third switch being coupled to the second node of the second variable capacitor, the second node of the thirty-third switch being coupled to the non-inverting input of the integrator, wherein the thirty-third switch operates in response to the second control signal; a thirty-fourth switch having a first node and a second node, the first node of the thirty-fourth switch being coupled to the second node of the thirty-first switch, the second node of the thirty-fourth switch being coupled to the common mode voltage, wherein the thirty-fourth switch operates in response to the fourth control signal; a thirty-fifth switch having a first node and a second node, the first node of the thirty-fifth switch being coupled to the first node of the second variable capacitor, the second node of the thirty-fifth switch being coupled to the common mode voltage, wherein the thirty-fifth switch operates in response to the second control signal; as well as A thirty-sixth switch has a first node and a second node, the first node of the thirty-sixth switch is coupled to the second node of the second variable capacitor, the second node of the thirty-sixth switch is coupled to the common mode voltage, and the thirty-sixth switch operates in response to the first control signal.

10. The temperature sensing circuit according to claim 9, further comprising: A control signal generator configured to, when the most recent bit in the bit stream is a logic zero: In a sampling phase, asserting the first control signal and the fourth control signal, and deasserting the second control signal and the third control signal; as well as During the integration phase, the second control signal is asserted while the first control signal, the third control signal, and the fourth control signal are de-asserted.

11. The temperature sensing circuit of claim 10 , wherein the control signal generator is further configured to: In a sampling phase, asserting the first control signal and the third control signal while deasserting the second control signal and the fourth control signal; and During the integration phase, the second control signal is asserted while the first control signal, the third control signal, and the fourth control signal are de-asserted.

12. A temperature sensing circuit, comprising: A voltage generating circuit device comprising: a first bipolar junction transistor and a second bipolar junction transistor having coupled collectors and bases and biased at different current densities; a third bipolar junction transistor having a collector coupled to its base, the third bipolar junction transistor being biased by a calibration current and having a base-emitter voltage, the base-emitter voltage of the third bipolar junction transistor being a complementary to absolute temperature voltage having a curved nonlinearity across temperature; and a fourth bipolar junction transistor and a fifth bipolar junction transistor having coupled collectors and bases, the fifth bipolar junction transistor being biased by a constant current that is independent of temperature and the fourth bipolar junction transistor being biased by a current that is proportional to absolute temperature; a switched capacitor circuit configured to selectively sample a voltage produced by the voltage generating circuitry and provide the sampled voltage to an input of an integrator; and a quantization circuit configured to quantize the output of the integrator to generate a bit stream; Wherein the switched capacitor circuit cooperates with the integrator under the control of the bit stream to cause the integration of the difference between the base-emitter voltage of the first bipolar junction transistor and the base-emitter voltage of the second bipolar junction transistor, thereby generating a voltage proportional to the absolute temperature, or to cause the integration of the difference between the base-emitter voltage of the fourth bipolar junction transistor and the sum of the voltage complementary to the absolute temperature and the base-emitter voltage of the fifth bipolar junction transistor, thereby generating a negative voltage complementary to the absolute temperature, the negative voltage having negligible nonlinearity across temperature.

13. The temperature sensing circuit of claim 12, wherein the switched capacitor circuit comprises: a first variable capacitor, used for sampling and holding the base-emitter voltage of the fourth bipolar junction transistor, wherein the first variable capacitor is composed of parallel capacitors with the same capacitance being γ in number; a second variable capacitor, for sampling and holding the base-emitter voltage of the fifth bipolar junction transistor, the second variable capacitor being composed of γ parallel capacitors of the same capacitance; wherein γ is selected so that the nonlinearity of the curvature of the complementary to absolute temperature voltage across temperature is cancelled during integration of the difference between the base-emitter voltage of the fourth bipolar junction transistor and the sum of the complementary to absolute temperature voltage and the base-emitter voltage of the fifth bipolar junction transistor; a third variable capacitor, used for sampling and holding the base-emitter voltage of the first bipolar junction transistor, wherein the third variable capacitor is composed of parallel capacitors having the same capacitance and the number of the capacitors being α; A first fixed capacitor for sampling and holding ground; a second fixed capacitor, for sampling and holding a base-emitter voltage of the third bipolar junction transistor; and A fourth variable capacitor is used to sample and hold the base-emitter voltage of the second bipolar junction transistor, wherein the fourth variable capacitor is composed of α parallel capacitors of the same capacitance.

14. A sigma-delta modulation analog-to-digital converter, comprising: a voltage generating circuit arrangement configured to generate a voltage proportional to absolute temperature, an uncorrected voltage complementary to absolute temperature, and a correction voltage based on at least a calibration current, a temperature-independent constant current, and a current proportional to absolute temperature, wherein the correction voltage when added to the uncorrected voltage complementary to absolute temperature produces a corrected voltage complementary to absolute temperature, the corrected voltage having negligible nonlinearity across temperature; a switched capacitor circuit configured to selectively sample a voltage produced by the voltage generating circuit arrangement and provide the sampled voltage to an input of an integrator; a quantization circuit configured to quantize the output of the integrator to generate a bit stream; wherein the switched capacitor circuit cooperates with the integrator under the control of the bit stream so that the integrator integrates the voltage proportional to absolute temperature or adds the correction voltage to the uncorrected voltage complementary to absolute temperature to generate the corrected voltage complementary to absolute temperature, and then integrates the corrected voltage complementary to absolute temperature according to the latest bit of the bit stream; as well as A low pass filter and decimator configured to filter and decimate the bit stream produced by the quantization circuit to produce a voltage indicative of the temperature of a chip in which the sigma-delta modulated analog-to-digital converter is placed.

15. The sigma-delta modulation analog-to-digital converter of claim 14, wherein the switched capacitor cooperates with the integrator under control of the bit stream to: causing the integrator to integrate the voltage proportional to absolute temperature when the latest bit of the bit stream is a first value; and When the newest bit of the bit stream is a second value, the correction voltage is added to the complementary to absolute temperature uncorrected voltage to generate the complementary to absolute temperature corrected voltage, and then the complementary to absolute temperature corrected voltage is integrated.

16. The sigma-delta modulation analog-to-digital converter of claim 15, wherein the first value is a logical zero and the second value is a logical one.

17. A method for a temperature sensing circuit, comprising: Generates a voltage proportional to absolute temperature; generating an uncorrected voltage complementary to absolute temperature based on at least the calibration current; generating a correction voltage based on at least a current proportional to absolute temperature and a temperature-independent constant current; selectively sampling the proportional to absolute temperature voltage, the complementary to absolute temperature uncorrected voltage, and the corrected voltage, and providing the sampled voltages to an input of an integrator; quantizing the output of the integrator to generate a bit stream; causing the integrator to integrate the voltage proportional to the absolute temperature, or causing the integrator to add the correction voltage to the uncorrected voltage complementary to the absolute temperature to generate the corrected voltage complementary to the absolute temperature, and then integrating the corrected voltage complementary to the absolute temperature according to the latest bit of the bit stream; as well as The bit stream is filtered and decimated to produce a voltage indicative of the temperature of the chip into which the temperature sensing circuit is placed.

18. The method of claim 17, wherein when the latest bit of the bit stream is a first value, the integrator is caused to integrate the voltage proportional to the absolute temperature, and when the latest bit of the bit stream is a second value, the integrator is caused to add the correction voltage to the uncorrected voltage complementary to the absolute temperature to generate the corrected voltage complementary to the absolute temperature, and then integrate the corrected voltage complementary to the absolute temperature.

19. The method of claim 18, wherein the first value is a logical zero and the second value is a logical one.

20. The method of claim 17, wherein the correction voltage, when added to the complementary to absolute temperature uncorrected voltage, produces the complementary to absolute temperature corrected voltage having negligible nonlinearity across temperature.

21. A temperature sensing circuit, comprising: a switched capacitor circuit configured to selectively sample a voltage produced by the voltage generating circuit arrangement and provide the sampled voltage to an input of the integrator; as well as a quantization circuit configured to quantize the output of the integrator to generate a bit stream; wherein the switched capacitor circuit cooperates with the integrator under control of the bit stream to cause integration of a first voltage or to cause a correction voltage to be added to a second voltage to produce a corrected voltage, which is then integrated according to the most recent bit of the bit stream; The switched capacitor circuit comprises: a first variable capacitor for sampling and holding a first component of the correction voltage, the first component of the correction voltage being generated based on a current proportional to absolute temperature; a second variable capacitor for sampling and holding a second component of the correction voltage, the second component of the correction voltage being generated based on a temperature-independent constant current; and An additional capacitor is used to sample and hold a voltage complementary to absolute temperature, the voltage complementary to absolute temperature being generated based on the calibration current.

22. The temperature sensing circuit of claim 21 , wherein the switched capacitor circuit comprises: The first variable capacitor is composed of parallel capacitors with the same capacitance being γ in number; as well as The second variable capacitor is composed of γ parallel capacitors of the same capacitance; wherein γ is selected such that non-linearities in the second voltage are cancelled during generation of the corrected voltage and integration of the corrected voltage.

23. The temperature sensing circuit of claim 22, wherein the switched capacitor circuit further comprises: a third variable capacitor, used for sampling and holding the first component of the first voltage, wherein the third variable capacitor is composed of parallel capacitors having the same capacitance and the number of the capacitors being α; as well as A fourth variable capacitor is used to sample and hold the second component of the first voltage, wherein the fourth variable capacitor is composed of α parallel capacitors of the same capacitance.

24. The temperature sensing circuit of claim 21, wherein the switched capacitor causes integration of the first voltage when the most recent bit of the bit stream is a first value, and causes integration of the corrected voltage when the most recent bit of the bit stream of the second voltage is a second value.

25. The temperature sensing circuit of claim 24, wherein the first value is a logical zero and the second value is a logical one.

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