A new gate drive circuit

Abstract

The invention discloses a novel gate driving circuit, which belongs to the field of integrated circuits, and includes a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate and a NAND gate, an AND gate and a control logic circuit; the first input end of the AND gate is connected to the output end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the AND gate is connected to the gate of the NMOS tube M3; the first input end of the NAND gate is connected to the input end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the NAND gate is connected to the gate of the PMOS tube M2; the source of the PMOS tube M2 is connected to the positive input end of the comparator I0, and the drain is connected to the gate of the NMOS tube M5. The invention can selectively adjust the driving capability and reduce the conduction loss.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a novel gate drive circuit. Background Art

[0002] In various applications based on switching operations, efficiency is closely related to the loss of switching devices. The power loss of switching elements is mainly composed of "switching loss" and "conduction loss". "Switching loss" is related to the switching speed, that is, it refers to the loss of the switching element "from on state to off state" or "from off state to on state"; "conduction loss" refers to the loss caused by "the impedance of the switch when it is powered on" and "the current flowing through the switch".

[0003] like Figure 1 The half-bridge switch shown drives an inductive load circuit. The power loss of the switch when switching between the on and off states is shown in Figure 2 (a) and Figure 2 (b). Generally speaking, the way to reduce switching loss is to increase the switching speed. That is, to reduce power loss by reducing Tr and Tf. However, the switching operation changes the current flow path, and due to the presence of parasitic parameters in the wiring, it often causes high-frequency resonance (ringing). Reducing Tr and Tf by increasing the driving capability can increase the rate of change of current (di / dt), thereby increasing the amplitude of the ringing. This not only "increases the stress of the switching element", but also "leads to electromagnetic wave emission, affecting the operation of the peripheral circuit, and high-frequency emission causes energy loss".

[0004] Therefore, it is necessary to reduce the influence of parasitic parameters by optimizing the current flow path. However, there are often certain limitations in reducing parasitic parameters, so there are also certain limitations in improving the driving capability. This limited driving capability also affects the conduction loss. This is because the time required for the switch to be fully turned on or off also depends on the driving capability. Generally speaking, the switch has a threshold voltage for entering the on state from the off state. That is, when the voltage (control voltage) amplitude of the control switch-related node is greater than the threshold voltage, current may flow through the switch, and as the voltage amplitude increases, the on-resistance of the switch decreases. Therefore, until the switch control voltage is high enough, the value of the on-resistance of the switch is higher than the expected value, so that the conduction loss is also high. Summary of the invention

[0005] The object of the present invention is to provide a novel gate driving circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a novel gate drive circuit, including a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate, a NAND gate, an AND gate and a control logic circuit;

[0007] The first input terminal of the AND gate is connected to the output terminal of the NOT gate, the second input terminal is connected to the output terminal of the comparator I0, and the output terminal of the AND gate is connected to the gate of the NMOS tube M3;

[0008] The first input end of the NAND gate is connected to the input end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the NAND gate is connected to the gate of the PMOS tube M2;

[0009] The source of the PMOS tube M2 is connected to the positive input terminal of the comparator I0, and the drain is connected to the gate of the NMOS tube M5;

[0010] The drain of the NMOS tube M3 is connected to the gate of the NMOS tube M5, and the source is connected to the source terminal SOURCE;

[0011] The drain of the NMOS tube M5 is connected to the negative input terminal of the comparator I0, and the source terminal is connected to the source terminal SOURCE.

[0012] Optionally, the gate of the PMOS transistor M0 and the gate of the NMOS transistor M1 are both connected to a control logic circuit.

[0013] Optionally, the source of the PMOS tube M0 is connected to the positive input terminal of the comparator I0.

[0014] Optionally, the drain of the PMOS tube M0 is connected to the gate of the NMOS tube M5 , and the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M5 .

[0015] Optionally, the comparator I0 includes an NMOS tube M6, a resistor R0 and a trigger I1;

[0016] The source terminal of the NMOS tube M6 is connected to the resistor R0, the drain terminal is connected to the drain of the NMOS tube M5, and the gate is connected to the source of the PMOS tube M2;

[0017] The input end of the trigger I1 is connected to the source of the NMOS tube M6, and the output end serves as the output end of the comparator I0.

[0018] The novel gate drive circuit provided by the present invention includes a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate and a NAND gate, an AND gate and a control logic circuit; the first input end of the AND gate is connected to the output end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the AND gate is connected to the gate of the NMOS tube M3; the first input end of the NAND gate is connected to the input end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the NAND gate is connected to the gate of the PMOS tube M2; the source of the PMOS tube M2 is connected to the positive input end of the comparator I0, and the drain is connected to the gate of the NMOS tube M5. The present invention can selectively adjust the driving capability and reduce the conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the circuit structure of a half-bridge switch driving an inductive load;

[0020] FIG2 (a) and FIG2 (b) are schematic diagrams of power loss when the switch is switched between the on state and the off state;

[0021] Figure 3 It is a schematic diagram of the structure of a novel gate drive circuit provided by the present invention;

[0022] Figure 4 It is a schematic diagram of the structure of a novel gate drive circuit provided by the present invention;

[0023] FIG5(a) and FIG5(b) are schematic diagrams showing how to reduce conduction loss without changing Tr / Tf. DETAILED DESCRIPTION

[0024] The following is a further detailed description of a novel gate drive circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] Embodiment 1

[0026] The present invention provides a novel gate drive circuit, the structure of which is as follows: Figure 3 As shown, it includes a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate and a NAND gate, an AND gate and a control logic circuit; the first input end of the AND gate is connected to the output end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the AND gate is connected to the gate of the NMOS tube M3; the first input end of the NAND gate is connected to the input end of the NOT gate, the second input end is connected to the output end of the comparator I0, and the output end of the NAND gate is connected to the gate of the PMOS tube M2; the source of the PMOS tube M2 is connected to the positive input of the comparator I0 The drain of the NMOS tube M3 is connected to the gate of the NMOS tube M5, and the source is connected to the source terminal SOURCE; the drain of the NMOS tube M5 is connected to the negative input terminal of the comparator I0, and the source terminal is connected to the source terminal SOURCE; the gate of the PMOS tube M0 and the gate of the NMOS tube M1 are both connected to the control logic circuit; the source of the PMOS tube M0 is connected to the positive input terminal of the comparator I0; the drain of the PMOS tube M0 is connected to the gate of the NMOS tube M5, and the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M5.

[0027] Further, such as Figure 4As shown, the comparator I0 includes an NMOS tube M6, a resistor R0 and a trigger I1; the source terminal of the NMOS tube M6 is connected to the resistor R0, the drain terminal is connected to the drain of the NMOS tube M5, and the gate is connected to the source of the PMOS tube M2; the input terminal of the trigger I1 is connected to the source of the NMOS tube M6, and the output terminal serves as the output terminal of the comparator I0.

[0028] The source voltage of NMOS tube M6 follows the drain voltage of NMOS tube M5 and is clamped (within the allowable input voltage range of trigger I1). That is, through NMOS tube M6, the voltage of the drain of NMOS tube M5 is sensed to the source of NMOS tube M6. The voltage of the source of NMOS tube M6 is compared with the trigger voltage of trigger I1 (the trigger voltage is between "M5 source voltage" and "V_DRV"). Although the trigger voltage of trigger I1 is different from the "voltage of V_DRV", it does not matter. Since the trigger voltage is related to the "V_DRV voltage", the switching transition is usually very fast and the response time of trigger I1 is quite short, so the Vcomp voltage reflects Figure 3 The comparator I0 compares the "V_DRV voltage" and the "M5 drain voltage". Figure 3 The novel gate drive circuit selectively adjusts the drive capability to reduce conduction loss, as shown in Figure 5(a) and Figure 5(b).

[0029] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A novel gate drive circuit, characterized in that: It includes a comparator I0, a PMOS tube M0, a PMOS tube M2, an NMOS tube M1, an NMOS tube M3, an NMOS tube M5, a NOT gate, a NAND gate, an AND gate and a control logic circuit; The first input terminal of the AND gate is connected to the output terminal of the NOT gate, the second input terminal is connected to the output terminal of the comparator I0, and the output terminal of the AND gate is connected to the gate of the NMOS tube M3; The first input terminal of the NAND gate is connected to the input terminal of the NOT gate, the second input terminal is connected to the output terminal of the comparator I0, and the output terminal of the NAND gate is connected to the gate of the PMOS tube M2; the input terminal of the NOT gate is connected to the voltage DRV_IN; The source of the PMOS tube M2 is connected to the positive input terminal of the comparator I0, and the drain is connected to the gate of the NMOS tube M5; The drain of the NMOS tube M3 is connected to the gate of the NMOS tube M5, and the source is connected to the source terminal SOURCE; The drain of the NMOS tube M5 is connected to the negative input terminal of the comparator I0, and the source terminal is connected to the source terminal SOURCE; The gate of the PMOS tube M0 and the gate of the NMOS tube M1 are both connected to a control logic circuit; the control logic circuit is connected to a voltage DRV_IN; The source of the PMOS tube M0 is connected to the positive input terminal of the comparator I0; The drain of the PMOS tube M0 is connected to the gate of the NMOS tube M5, the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M5, and the source of the NMOS tube M1 is connected to the source terminal SOURCE; The comparator I0 has a positive input terminal connected to a voltage V_DRV, a negative input terminal connected to a drain terminal DRAIN, and an output terminal outputting a voltage Vcomp.

2. The novel gate drive circuit according to claim 1, characterized in that: The comparator I0 includes an NMOS tube M6, a resistor R0 and a trigger I1; The source terminal of the NMOS tube M6 is connected to the resistor R0, the drain terminal is connected to the drain of the NMOS tube M5, and the gate is connected to the source of the PMOS tube M2; The input end of the trigger I1 is connected to the source of the NMOS tube M6, and the output end serves as the output end of the comparator I0.

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