Data processing method based on random numbers, random number generation method and device

Abstract

The present disclosure relates to a data processing method based on random numbers, a random number generation method and a device, wherein the device includes a control module, wherein the control module includes: an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used to store the calculation instructions associated with the artificial neural network operation; the instruction processing unit is used to parse the calculation instructions to obtain multiple operation instructions; the storage queue unit is used to store an instruction queue, which includes: multiple operation instructions or calculation instructions to be executed in the order of the queue. Through the above method, the present disclosure can improve the operation efficiency of related products when performing operations on neural network models.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method based on random numbers, a random number generation method and a device. Background Art

[0002] In the field of artificial intelligence technology, neural network algorithms are a very popular machine learning algorithm recently, and have achieved very good results in various fields, such as image recognition, speech recognition, natural language processing, etc. With the development of neural network algorithms, the complexity of the algorithms is getting higher and higher. In order to improve the recognition, the scale of the model is also gradually increasing. Using GPU and CPU to process these large-scale models takes a lot of computing time and consumes a lot of power. Summary of the invention

[0003] Based on this, the present disclosure proposes a technical solution of a data processing method based on random numbers, a random number generation method and a device.

[0004] According to one aspect of the present disclosure, a random number-based data processing method is provided, which is applied to a first processor, and includes: before executing a target operator that uses a random number for data processing, determining whether a flag bit corresponding to the target operator is in a first state, wherein the first state is used to indicate that a target random number is stored in a random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on a second processor; when the flag bit is in the first state, using the target random number obtained from the random number address to perform data processing operations on the target operator.

[0005] According to one aspect of the present disclosure, a random number generation method is provided, the method being applied to a second processor, the second processor including at least one random number generation operator, the method comprising: executing each random number generation operator in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and a flag bit; for any random number generation operator, storing the random number generated by the random number generation operator in the random number address corresponding to the random number generation operator; and determining the state of the flag bit corresponding to the random number generation operator as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available.

[0006] According to one aspect of the present disclosure, a data processing device based on random numbers is provided, and the device is applied to a first processor, and the device includes: a first determination module, used to determine whether a flag bit corresponding to the target operator is in a first state before executing a target operator that uses a random number for data processing, wherein the first state is used to indicate that a target random number is stored in a random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on a second processor; a data processing module, used to perform data processing operations of the target operator using the target random number obtained from the random number address when the flag bit is in the first state.

[0007] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above-mentioned random number-based data processing method.

[0008] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above-mentioned random number-based data processing method is implemented.

[0009] According to one aspect of the present disclosure, a random number generating device is provided, the device is applied to a second processor, the second processor includes at least one random number generating operator, the device includes: a generating module, used to execute each random number generating operator in sequence, to generate a random number corresponding to each random number generating operator, wherein each random number generating operator has a corresponding random number address and a flag bit; a storing module, used to store, for any random number generating operator, the random number generated by the random number generating operator in the random number address corresponding to the random number generating operator; a determining module, used to determine the state of the flag bit corresponding to the random number generating operator as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generating operator and the random number is available.

[0010] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above-mentioned random number generation method.

[0011] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above-mentioned random number generation method is implemented.

[0012] For the first processor, before executing a target operator that uses a random number for data processing, determine whether a flag bit corresponding to the target operator is in a first state for indicating that a target random number is stored in a random number address corresponding to the flag bit and that the target random number is available, and the target random number is generated by a random number generation operator on the second processor. When the flag bit is in the first state, the target random number obtained from the random number address is used to perform data processing operations of the target operator, so that data processing operations based on random numbers can be performed without performing random number generation operations in the first processor, thereby saving computing time and reducing energy consumption.

[0013] For a second processor including at least one random number generation operator, each random number generation operator is executed in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and a flag bit. For any random number generation operator, the random number generated by the random number generation operator is stored in the random number address corresponding to the random number generation operator, and the state of the flag bit corresponding to the random number generation operator is determined as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available, so that the second processor can perform the random number generation operation alone, saving computing time and reducing energy consumption.

[0014] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0016] Figure 1 A schematic diagram showing a processor of a random number-based data processing method according to an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram showing a flow chart of a random number-based data processing method according to an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram showing operators in a first processor and a second processor according to an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram showing a flow chart of a random number generation method according to an embodiment of the present disclosure;

[0020] Figure 5 A structural block diagram showing a random number-based data processing device according to an embodiment of the present disclosure;

[0021] Figure 6 A structural block diagram showing a random number generating device according to an embodiment of the present disclosure;

[0022] Figure 7 A structural block diagram of a board according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] It should be understood that the terms "first" and "second" and the like in the claims, specifications and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0025] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0026] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0027] The data processing method based on random numbers according to the embodiment of the present disclosure can be applied to a processor, which can be a general-purpose processor, such as a central processing unit (CPU), or an artificial intelligence processor (IPU) for performing artificial intelligence operations. Artificial intelligence operations may include machine learning operations, brain-like operations, etc. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor may, for example, include a graphics processing unit (GPU), a neural network processing unit (NPU), a digital signal processing unit (DSP), and a field-programmable gate array (FPGA) chip or a combination thereof. The present disclosure does not limit the specific type of the processor.

[0028] In a possible implementation, the processor mentioned in the present disclosure may include multiple processing units, each of which may independently run various assigned tasks, such as convolution operation tasks, pooling tasks, or fully connected tasks, etc. The present disclosure does not limit the processing units and the tasks run by the processing units.

[0029] Figure 1 A schematic diagram of a processor of a data processing method based on random numbers according to an embodiment of the present disclosure is shown. Figure 1 As shown, the processor 100 includes a plurality of processing units 101 and a storage unit 102. The plurality of processing units 101 are used to execute instruction sequences, and the storage unit 102 is used to store data, and may include a random access memory (RAM) and a register file. The plurality of processing units 101 in the processor 100 may share part of the storage space, such as sharing part of the RAM storage space and the register file, or may have their own storage space at the same time.

[0030] Figure 2 A flow chart of a random number-based data processing method according to an embodiment of the present disclosure is shown. The method is applied to a first processor, such as Figure 2 As shown, the method may include:

[0031] In step S21: before executing the target operator that uses random numbers for data processing, determine whether the flag bit corresponding to the target operator is in a first state, wherein the first state is used to indicate that a target random number is stored in the random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on the second processor.

[0032] In step S22: when the flag bit is in the first state, the target random number obtained from the random number address is used to perform a data processing operation of the target operator.

[0033] In one possible implementation, the first processor is an artificial intelligence processor.

[0034] For example, the first processor may be a machine learning processing chip MLU. It should be noted that, in addition to being an MLU, the first processor may also be other types of artificial intelligence processors, which is not specifically limited in the present disclosure.

[0035] In practical applications, when performing data processing operations based on random numbers in the first processor, it is also necessary to perform random number generation operations in the first processor to generate the required random numbers, which makes the data processing model complex and takes a lot of computing time. According to the data processing method based on random numbers disclosed in the present invention, the random number generation operation is separated from the first processor and executed in the second processor, and the interaction between the first processor and the second processor is realized by using shared memory (for example, DDR, HBM), so that the data processing operations based on random numbers and the random number generation operations can be performed in parallel in the first processor and the second processor, thereby saving computing time and reducing energy consumption.

[0036] In a possible implementation, the method further includes: allocating a corresponding random number address and a flag bit to each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

[0037] Figure 3 A schematic diagram showing operators in the first processor and the second processor of an embodiment of the present disclosure is shown. Figure 3 As shown, the second processor includes a random number generator 1 and a random number generator 2, and the first processor allocates a random number address 1 and a flag bit 1 in the shared memory to the random number generator 1, and allocates a random number address 2 and a flag bit 2 in the shared memory to the random number generator 2. Figure 3As shown, the first processor includes operators 1 to 8, wherein operator 3 is a target operator (hereinafter referred to as target operator 3) for data processing using a random number generated by a random number generator operator 1, and there is a corresponding relationship between target operator 3 and random number address 1 and flag bit 1; operator 7 in the first processor is a target operator (hereinafter referred to as target operator 7) for data processing using a random number generated by a random number generator operator 2, and there is a corresponding relationship between target operator 7 and random number address 2 and flag bit 2. The number of random number generator operators in the second processor can be set according to actual conditions (for example, the number of target operators in the first processor), and the present disclosure does not specifically limit this.

[0038] In a possible implementation, the method further includes: initializing a flag bit corresponding to each random number generation operator to a second state, wherein, for any random number generation operator, the flag bit corresponding to the random number generation operator is in the second state to indicate that no random number is stored in the random number address corresponding to the random number generation operator, or that the random number stored in the random number address corresponding to the random number generation operator is unavailable.

[0039] Still with the above Figure 3 For example, during the initialization process, that is, when neither the first processor nor the second processor performs any data processing, the flag bit 1 corresponding to the random number generator 1 is initialized to the second state, which is used to indicate that no random number is stored in the random number address 1 or the random number stored in the random number address 1 is unavailable; the flag bit 2 corresponding to the random number generator 2 is initialized to the second state, which is used to indicate that no random number is stored in the random number address 2 or the random number stored in the random number address 1 is unavailable. For example, the first state can be represented by 1, and the second state can be represented by 0. In addition to being represented by 0 / 1, the first state and the second state can also be represented by other representations, which are not specifically limited in the present disclosure.

[0040] In a possible implementation, the method further includes: determining a corresponding random number type and a random seed for each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

[0041] Still with the above Figure 3 For example, during the initialization process, that is, when neither the first processor nor the second processor performs any data processing, the corresponding random number type and random seed are determined for random number generator 1, and the corresponding random number type and random seed are determined for random number generator 2. The random number type and random seed corresponding to any random number generator are determined according to the data processing requirements of the target operator corresponding to the random number generator.

[0042] In one possible implementation, the preceding operator of the target operator is a synchronization operator; before executing the target operator that uses a random number to perform data processing, determining whether a flag bit corresponding to the target operator is in a first state includes: polling whether the flag bit is in the first state according to the synchronization operator.

[0043] Still with the above Figure 3 For example, Figure 3 As shown, the preamble operator 2 of the target operator 3 is a synchronization operator (hereinafter referred to as synchronization operator 2), and the preamble operator 6 of the target operator 7 is a synchronization operator (hereinafter referred to as synchronization operator 6). When executing the preamble operator 3, according to the preamble operator 3, the flag bit 1 corresponding to the target operator 3 is polled until it is determined that the flag bit 1 is in the first state. The flag bit 1 in the first state indicates that the target random number required to be used by the target operator 3 is stored in the random number address 1 and the target random number is available, and then the target operator 3 is executed downward, and the target random number is obtained from the random number address 1 to perform the data processing operation of the target operator 3; when executing the preamble operator 6, according to the preamble operator 6, the flag bit 2 corresponding to the target operator 7 is polled until it is determined that the flag bit 2 is in the first state. The flag bit 2 in the first state indicates that the target random number required to be used by the target operator 7 is stored in the random number address 2 and the target random number is available, and then the target operator 7 is executed downward, and the target random number is obtained from the random number address 2 to perform the data processing operation of the target operator 7.

[0044] In a possible implementation, the method further includes: after obtaining the target random number according to the random number address, updating the state of the flag bit to a second state, wherein the second state is used to indicate that the target random number is not stored in the random number address, or that the target random number stored in the random number address is unavailable.

[0045] Still with the above Figure 3 For example, after the target operator 3 obtains the target random number from the random number address 1 to execute the data processing operation of the target operator 3, the state of the flag bit 1 is updated to the second state to indicate that the target random number is not stored in the random number address 1 or the target random number stored in the random number address 1 is unavailable; after the target operator 7 obtains the target random number from the random number address 2 to execute the data processing operation of the target operator 7, the state of the flag bit 2 is updated to the second state to indicate that the target random number is not stored in the random number address 2 or the target random number stored in the random number address 2 is unavailable.

[0046] For the first processor, before executing a target operator that uses a random number for data processing, determine whether a flag bit corresponding to the target operator is in a first state for indicating that a target random number is stored in a random number address corresponding to the flag bit and that the target random number is available, and the target random number is generated by a random number generation operator on the second processor. When the flag bit is in the first state, the target random number obtained from the random number address is used to perform data processing operations of the target operator, so that data processing operations based on random numbers can be performed without performing random number generation operations in the first processor, thereby saving computing time and reducing energy consumption.

[0047] Figure 4 The flowchart of the random number generation method of the embodiment of the present disclosure is shown. The method is applied to the second processor, and the second processor includes at least one random number generation operator, such as Figure 4 As shown, the method may include:

[0048] In step S41: each random number generation operator is executed in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and flag bit.

[0049] In step S42: for any random number generation operator, the random number generated by the random number generation operator is stored in the random number address corresponding to the random number generation operator.

[0050] In step S43: the state of the flag bit corresponding to the random number generation operator is determined to be a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available.

[0051] In a possible implementation, the second processor is an ARM processor.

[0052] It should be noted that, in addition to ARM, the second processor may also be other processors capable of executing a random number generation operator, and the present disclosure does not make any specific limitation on this.

[0053] Still with the above Figure 3For example, the first processor allocates the corresponding random number address 1 and flag bit 1 in the shared memory to the random number generator 1, and allocates the corresponding random number address 2 and flag bit 2 in the shared memory to the random number generator 2, and during the initialization process, both flag bit 1 and flag bit 2 are initialized to the second state, and the corresponding random number type and random seed are determined for the random number generator 1 and the random number generator 2. Each random number generator is executed in sequence in the second processor. Execute the random number generator 1, and store the random number generated by the random number generator 1 in the random number address 1, and update the state of the flag bit 1 to the first state; execute the random number generator 2, and store the random number generated by the random number generator 2 in the random number address 2, and update the state of the flag bit 2 to the first state. Among them, the random number generator has only output and no input, and can form a fusion operator together with other operators.

[0054] For a second processor including at least one random number generation operator, each random number generation operator is executed in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and a flag bit. For any random number generation operator, the random number generated by the random number generation operator is stored in the random number address corresponding to the random number generation operator, and the state of the flag bit corresponding to the random number generation operator is determined as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available, so that the second processor can perform the random number generation operation alone, saving computing time and reducing energy consumption.

[0055] Figure 5 FIG. 2 is a block diagram showing a random number-based data processing device according to an embodiment of the present disclosure. Figure 5 The device 50 shown is applied to a first processor, and the device 50 includes:

[0056] A first determination module 51 is used to determine whether a flag bit corresponding to the target operator is in a first state before executing the target operator that uses the random number for data processing, wherein the first state is used to indicate that a target random number is stored in the random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on the second processor;

[0057] The data processing module 52 is used to perform a data processing operation of a target operator using a target random number obtained from the random number address when the flag bit is in the first state.

[0058] In a possible implementation, the preceding operator of the target operator is a synchronization operator;

[0059] The first determining module 51 is specifically used for:

[0060] According to the synchronization operator, the flag bit is polled to determine whether it is in the first state.

[0061] In a possible implementation, the device 50 further includes:

[0062] A state update module is used to update the state of the flag bit to a second state after obtaining the target random number according to the random number address, wherein the second state is used to indicate that the target random number is not stored in the random number address, or that the target random number stored in the random number address is unavailable.

[0063] In a possible implementation, the device 50 further includes:

[0064] The allocation module is used to allocate corresponding random number addresses and flag bits to each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

[0065] In a possible implementation, the device 50 further includes:

[0066] An initialization module is used to initialize the flag bits corresponding to each random number generation operator to a second state, wherein, for any random number generation operator, the flag bit corresponding to the random number generation operator is in the second state to indicate that no random number is stored in the random number address corresponding to the random number generation operator, or that the random number stored in the random number address corresponding to the random number generation operator is unavailable.

[0067] In a possible implementation, the device 50 further includes:

[0068] The second determination module is used to determine the corresponding random number type and random seed for each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

[0069] In one possible implementation, the first processor is an artificial intelligence processor.

[0070] The random number-based data processing device 50 provided by the present disclosure can achieve Figure 2 The various steps in the method embodiment shown achieve the same technical effect and will not be described again here to avoid repetition.

[0071] Figure 6 FIG. 2 is a block diagram showing a random number generating device according to an embodiment of the present disclosure. Figure 6 The device 60 shown is applied to a second processor, and the second processor includes at least one random number generation operator. The device 60 includes:

[0072] A generating module 61, used to execute each random number generating operator in sequence to generate a random number corresponding to each random number generating operator, wherein each random number generating operator has a corresponding random number address and flag bit;

[0073] The storage module 62 is used for storing, for any random number generation operator, the random number generated by the random number generation operator in the random number address corresponding to the random number generation operator;

[0074] The determination module 63 is used to determine the state of the flag bit corresponding to the random number generation operator as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available.

[0075] The random number generating device 60 provided by the present disclosure can achieve Figure 4 The various steps in the method embodiment shown achieve the same technical effect and will not be described again here to avoid repetition.

[0076] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present disclosure can also be implemented in other ways. For example, the division of units / modules described in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0077] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present disclosure may be integrated into one unit / module, or each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0078] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. If not otherwise specified, the processor may be any appropriate hardware processor, such as a CPU, a GPU, an FPGA, a DSP, an ASIC, etc. If not otherwise specified, the storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access memory DRAM (Dynamic Random Access Memory), a static random access memory SRAM (Static Random-Access Memory), an enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc.

[0079] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0080] In a possible implementation, an artificial intelligence chip is also disclosed, which includes the above-mentioned random number-based data processing device and / or random number generation device.

[0081] In a possible implementation, a board is also disclosed, which includes a storage device, an interface device, a control device and an artificial intelligence chip; wherein the artificial intelligence chip is connected to the storage device, the control device and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the artificial intelligence chip and an external device; the control device is used to monitor the status of the artificial intelligence chip.

[0082] Figure 7 1 shows a structural block diagram of a board in an embodiment of the present disclosure. Figure 7 As shown, in addition to the artificial intelligence chip 71, the board may also include other supporting components, including but not limited to: a storage device 72, an interface device 73 and a control device 74;

[0083] The memory device 72 is connected to the artificial intelligence chip 71 via a bus for storing data. The memory device 72 may include multiple groups of memory cells 721. Each group of memory cells 721 is connected to the artificial intelligence chip 72 via a bus. It is understood that each group of memory cells 721 may be DDR SDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

[0084] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device 72 may include 4 groups of storage units 721. Each group of storage units 721 may include multiple DDR4 particles (chips). In one embodiment, the artificial intelligence chip 71 may include 4 72-bit DDR4 controllers, 64 bits of the above 72-bit DDR4 controllers are used to transmit data, and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units 721, the theoretical bandwidth of data transmission can reach 25600MB / s.

[0085] In one embodiment, each group of storage units 721 includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is provided in the artificial intelligence chip to control the data transmission and data storage of each of the storage units.

[0086] The interface device is electrically connected to the artificial intelligence chip. The interface device is used to realize data transmission between the artificial intelligence chip 71 and an external device (such as a server or a computer). For example, in one embodiment, the interface device 73 can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB / s. In another embodiment, the interface device 73 can also be other interfaces. The present disclosure does not limit the specific forms of expression of the above-mentioned other interfaces. The interface unit 721 can realize the switching function. In addition, the calculation results of the artificial intelligence chip 71 are still transmitted back to the external device (such as a server) by the interface device 73.

[0087] The control device 74 is electrically connected to the artificial intelligence chip 71. The control device 74 is used to monitor the state of the artificial intelligence chip 71. Specifically, the artificial intelligence chip 71 and the control device 74 can be electrically connected through an SPI interface. The control device 74 may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the artificial intelligence chip 71 may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the artificial intelligence chip 71 can be in different working states such as multi-load and light load. The control device 74 can realize the regulation of the working state of multiple processing chips, multiple processing and / or multiple processing circuits in the artificial intelligence chip 71.

[0088] In a possible implementation, an electronic device is disclosed, which includes the above-mentioned artificial intelligence chip. The electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a means of transportation, a household appliance, and / or a medical device. The means of transportation include an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical device includes an MRI, an ultrasound machine, and / or an electrocardiograph.

[0089] The present disclosure also provides a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above-mentioned random number-based data processing method and / or random number generation method are implemented. The computer-readable storage medium may be a non-volatile computer-readable storage medium.

[0090] An embodiment of the present disclosure also proposes an electronic device, comprising: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above-mentioned random number-based data processing method and / or random number generation method.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The foregoing content can be better understood in accordance with the following terms:

[0093] Clause A1, a data processing method based on random numbers, the method being applied to a first processor, the method comprising:

[0094] Before executing a target operator that uses a random number for data processing, determining whether a flag bit corresponding to the target operator is in a first state, wherein the first state is used to indicate that a target random number is stored in a random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on the second processor;

[0095] When the flag bit is in the first state, a data processing operation of the target operator is performed using the target random number obtained from the random number address.

[0096] Clause A2, according to the method described in clause A1, the predecessor operator of the target operator is a synchronization operator;

[0097] Before executing a target operator that uses a random number to perform data processing, determining whether a flag bit corresponding to the target operator is in a first state includes:

[0098] According to the synchronization operator, poll whether the flag bit is in the first state.

[0099] Clause A3. The method according to clause A1, further comprising:

[0100] After obtaining the target random number according to the random number address, the state of the flag bit is updated to a second state, wherein the second state is used to indicate that the target random number is not stored in the random number address, or that the target random number stored in the random number address is unavailable.

[0101] Clause A4. The method according to clause A1, further comprising:

[0102] A corresponding random number address and a flag bit are allocated to each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

[0103] Clause A5. The method according to clause A4, further comprising:

[0104] The flag bit corresponding to each random number generation operator is initialized to a second state, wherein, for any random number generation operator, the flag bit corresponding to the random number generation operator is in the second state to indicate that no random number is stored in the random number address corresponding to the random number generation operator, or that the random number stored in the random number address corresponding to the random number generation operator is unavailable.

[0105] Clause A6. A method according to clause A1, further comprising:

[0106] Determine a corresponding random number type and a random seed for each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

[0107] Item A7, according to the method described in any one of Items A1 to A6, the first processor is an artificial intelligence processor.

[0108] Clause A8, a method for generating a random number, the method being applied to a second processor, the second processor including at least one random number generation operator, the method comprising:

[0109] Execute each random number generation operator in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and flag bit;

[0110] For any random number generation operator, the random number generated by the random number generation operator is stored in the random number address corresponding to the random number generation operator;

[0111] The state of the flag bit corresponding to the random number generation operator is determined to be a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available.

[0112] Item A9, according to the method described in Item A8, the second processor is an ARM processor.

[0113] Clause A10, a data processing device based on random numbers, the device being applied to a first processor, the device comprising:

[0114] a first determination module, configured to determine whether a flag bit corresponding to the target operator is in a first state before executing the target operator that uses the random number for data processing, wherein the first state is used to indicate that a target random number is stored in the random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on the second processor;

[0115] A data processing module is used to perform a data processing operation of the target operator using the target random number obtained from the random number address when the flag bit is in the first state.

[0116] Item A11. An electronic device comprising:

[0117] processor;

[0118] a memory for storing processor-executable instructions;

[0119] The processor is configured to call instructions stored in the memory to execute the method described in any one of clauses A1 to A7.

[0120] Item A12, a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method described in any one of Items A1 to A7.

[0121] Clause A13, a random number generation device, the device being applied to a second processor, the second processor including at least one random number generation operator, the device comprising:

[0122] A generation module, used to execute each random number generation operator in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and flag bit;

[0123] A storage module, used for storing, for any random number generation operator, a random number generated by the random number generation operator in a random number address corresponding to the random number generation operator;

[0124] A determination module is used to determine the state of the flag bit corresponding to the random number generation operator as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available.

[0125] Item A14. An electronic device comprising:

[0126] processor;

[0127] a memory for storing processor-executable instructions;

[0128] Wherein, the processor is configured to call the instructions stored in the memory to execute the method described in clause A8 or A9.

[0129] Item A15, a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method described in Item A8 or A9.

[0130] The embodiments of the present disclosure are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present disclosure. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present disclosure, the specific implementation methods and the scope of application of the present disclosure, all belong to the scope of protection of the present disclosure. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A data processing method based on random numbers, characterized in that: The method is applied to a first processor, and the method includes: Before executing a target operator that uses a random number for data processing, determining whether a flag bit corresponding to the target operator is in a first state, wherein the first state is used to indicate that a target random number is stored in a random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on the second processor; When the flag bit is in the first state, using the target random number obtained from the random number address to perform a data processing operation of the target operator; After obtaining the target random number according to the random number address, the state of the flag bit is updated to a second state, wherein the second state is used to indicate that the target random number is not stored in the random number address, or that the target random number stored in the random number address is unavailable.

2. The method according to claim 1, characterized in that The preceding operator of the target operator is a synchronization operator; Before executing a target operator that uses a random number to perform data processing, determining whether a flag bit corresponding to the target operator is in a first state includes: According to the synchronization operator, poll whether the flag bit is in the first state.

3. The method according to claim 1, characterized in that The method further comprises: A corresponding random number address and a flag bit are allocated to each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

4. The method according to claim 3, characterized in that The method further comprises: The flag bit corresponding to each random number generation operator is initialized to a second state, wherein, for any random number generation operator, the flag bit corresponding to the random number generation operator is in the second state to indicate that no random number is stored in the random number address corresponding to the random number generation operator, or that the random number stored in the random number address corresponding to the random number generation operator is unavailable.

5. The method according to claim 1, characterized in that The method further comprises: Determine a corresponding random number type and a random seed for each random number generation operator on the second processor, wherein the second processor includes at least one random number generation operator.

6. The method according to any one of claims 1 to 5, characterized in that The first processor is an artificial intelligence processor.

7. A random number generation method, characterized in that: The method is applied to a second processor, the second processor includes at least one random number generation operator, and the method includes: Execute each random number generation operator in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and flag bit; For any random number generation operator, the random number generated by the random number generation operator is stored in the random number address corresponding to the random number generation operator; Determine the state of the flag bit corresponding to the random number generation operator as a first state, wherein the first state is used to indicate that a random number is stored in the random number address corresponding to the random number generation operator and the random number is available; For any random number generation operator, after the first processor obtains the random number according to the random number address corresponding to the random number generation operator, the state of the flag bit corresponding to the random number generation operator is updated to a second state, wherein the second state is used to indicate that no random number is stored in the random number address corresponding to the random number generation operator, or that the random number stored in the random number address corresponding to the random number generation operator is unavailable.

8. The method according to claim 7, characterized in that The second processor is an ARM processor.

9. A data processing device based on random numbers, characterized in that: The device is applied to a first processor, and the device includes: a first determination module, configured to determine whether a flag bit corresponding to the target operator is in a first state before executing the target operator that uses the random number for data processing, wherein the first state is used to indicate that a target random number is stored in the random number address corresponding to the flag bit and the target random number is available, and the target random number is generated by a random number generation operator on the second processor; a data processing module, configured to, when the flag bit is in the first state, use the target random number obtained from the random number address to perform a data processing operation of the target operator; A state update module is used to update the state of the flag bit to a second state after obtaining the target random number according to the random number address, wherein the second state is used to indicate that the target random number is not stored in the random number address, or that the target random number stored in the random number address is unavailable.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 6.

11. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

12. A random number generating device, characterized in that: The device is applied to a second processor, the second processor includes at least one random number generation operator, and the device includes: A generation module, used to execute each random number generation operator in sequence to generate a random number corresponding to each random number generation operator, wherein each random number generation operator has a corresponding random number address and flag bit; A storage module, used for storing, for any random number generation operator, a random number generated by the random number generation operator in a random number address corresponding to the random number generation operator; A determination module, configured to determine a state of a flag bit corresponding to the random number generation operator as a first state, wherein the first state is used to indicate that a random number is stored in a random number address corresponding to the random number generation operator and the random number is available; A state update module is used to update the state of a flag bit corresponding to any random number generation operator to a second state after a first processor obtains the random number according to the random number address corresponding to the random number generation operator, wherein the second state is used to indicate that no random number is stored in the random number address corresponding to the random number generation operator, or that the random number stored in the random number address corresponding to the random number generation operator is unavailable.

13. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method of claim 7 or 8.

14. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to claim 7 or 8 is implemented.

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