Generate synchronous digital circuits from source code constructs mapped to circuit implementations

Abstract

A multithreaded imperative programming language includes language constructs that map to circuit implementations. The constructs include conditional statements that enable threads in a pipeline to wait for a specified condition to occur, identify the beginning and end of a portion of source code instructions to be executed atomically, or indicate a read-modify-write memory operation to be executed atomically. Source code including one or more constructs that map to circuit implementations can be compiled to generate a circuit description. For example, using a hardware description language (HDL), the circuit description can be expressed. The circuit description can in turn be used to generate a synchronous digital circuit including a circuit implementation. For example, an HDL can be utilized to generate an FPGA image or bitstream that can be utilized to program an FPGA including a circuit implementation associated with the language construct.

Description

Background Art

[0001] A hardware description language ("HDL") is a modeling language used by hardware engineers to describe the structure and behavior of electronic circuits, most of which are typically digital logic circuits. Examples of HDLs include Very High Speed ​​Integrated Circuit ("VHSIC") HDL and VERILOG.

[0002] HDL typically requires many lines of code to simulate digital logic circuits. Creating this code is very time-consuming, even for hardware engineers who are very familiar with HDL. In addition, the more lines of code there are in a design, the more likely it is that the design will include errors or perform poorly.

[0003] Furthermore, because HDLs typically utilize a programming paradigm different from imperative programming languages, software engineers who are not very familiar with HDLs typically have difficulty utilizing these languages. As a result, electronic circuits created by software engineers and generated from HDLs may also include errors or perform poorly.

[0004] Presented herein are responses to these and other technical challenges made by the present disclosure. Summary of the invention

[0005] The disclosed technology is a technology for generating synchronous digital circuits ("SDCs") from source code constructs that map efficiently to circuit implementations. Through implementation of the disclosed technology, hardware engineers can achieve significant productivity gains by reducing the number of HDL code lines required to implement some types of SDCs, and by eliminating entire classes of common design errors, without sacrificing performance. For software engineers with some or no experience designing SDCs with HDL, the disclosed technology provides a familiar programming paradigm that can be used to quickly and easily generate high-performance circuit designs. Through implementation of the disclosed subject matter, other technical advantages not specifically mentioned herein may also be achieved.

[0006] To achieve the technical advantages briefly mentioned above, program source code is generated and stored in a multithreaded imperative programming language. The disclosed language is imperative because program statements are executed sequentially, and multithreaded because multiple execution threads can be executed in parallel. A thread refers to a collection of local variables. When the local variables are processed by the hardware circuit, the thread is executed.

[0007] The threads described herein are similar to, but different from, software threads. Whereas software threads maintain a call stack containing local variables and execute code in memory, threads described herein are collections of local variables that move around in hardware circuits. Whereas software threads have locations in executable code determined by instruction pointers, the disclosed threads have physical locations on the SDC at a given point in time. Furthermore, the language constructs described herein map to circuit implementations that guarantee thread order (i.e., threads will exit the circuit implementation in the order they were entered).

[0008] The multithreaded imperative programming language disclosed herein includes language constructs (or "constructs") that map to circuit implementations. A language construct is a syntactically permitted portion of a program that can be formed from one or more lexical tokens. The circuit implementation can be implemented as an SDC in a field programmable gate array ("FPGA"), a gate array, an application specific integrated circuit ("ASIC"), or other type of suitable device. Another hardware component, such as a network interface card ("NIC"), can be configured with an FPGA, a gate array, or an ASIC to achieve the desired functionality.

[0009] In one configuration, a construct includes a conditional statement that enables a thread in a pipeline to wait for a specified condition to occur. For example, the condition might be expressed as "wait_for(x>global_variable)". In this configuration, the construct maps to a circuit implementation that includes a hardware pipeline (or "pipeline") that implements the functionality defined by the source code instructions before the conditional statement. The circuit implementation also includes a second hardware pipeline that implements the functionality defined by the source code instructions after the conditional statement. The first hardware pipeline outputs to a queue. The second pipeline takes its input from the queue.

[0010] In this configuration, the second hardware pipeline processes the value from the queue only when the condition defined by the conditional statement is evaluated to be true (e.g., in the example above when x>global_variable). In some configurations, the condition in the second pipeline is evaluated by comparing the value obtained in the queue with a value stored in a register or another type of on-chip memory (such as, static random access memory ("SRAM")). For example, the value stored in the register can be generated by the third pipeline. The value in the queue (e.g., x in the example given above) corresponds to a local variable.

[0011] In another configuration, the construct identifies the beginning and end of a portion of source code instructions to be executed atomically. As used herein, the terms "atomically" and "atomic" refer to a circuit implementation that allows only one thread to be executed at a time. In this configuration, the circuit implementation includes a single hardware pipeline stage for implementing instructions to be executed atomically. The single hardware pipeline stage executes in a single clock cycle. The single hardware pipeline stage can receive inputs from one or more input registers and output values ​​to one or more output registers. The construct implements thread synchronization by mapping to a circuit implementation that allows only one thread to be in an atomic region at a time.

[0012] In another configuration, a construct indicates a read-modify-write memory operation to be performed atomically. The construct implements thread synchronization by mapping to a circuit implementation of the read-modify-write operation that is synchronized with the on-chip memory execution. This ensures that problems with read-write-modify operations are avoided without performance degradation.

[0013] In this configuration, the circuit implementation includes a memory and at least one first hardware pipeline stage. The first hardware pipeline stage can load a value from the on-chip memory. The first hardware pipeline stage provides a value read from the memory to a second pipeline stage.

[0014] The second hardware pipeline stage compares the memory address of the loaded value to one or more addresses associated with the most recent (e.g., previous) memory store operation. If the addresses match, the value loaded from the most recent memory is discarded, and the value stored in the register during the most recent store operation is modified as described below. If the addresses do not match, the value loaded from memory by the most recent load operation is then modified as described below.

[0015] The second hardware pipeline stage performs a user-specified calculation on the most recently loaded value or the value from a previous store operation to produce a modified value. The operations specified by the read-modify-write construct can be arbitrarily complex. For example, and without limitation, if the construct specifies an operation of the form "memory[x] = (memory[x] + y) * 2", then the "+y" and "*2" instructions occur atomically in the same pipeline stage that modifies the value if the load address matches the load address for the most recent store.

[0016] The second pipeline stage stores the modified value in a register for use during the next read-modify-write operation. The second pipeline stage also stores the address in a register, also for use during the next read-modify-write operation.

[0017] The one or more third hardware pipeline stages follow the second hardware pipeline stage. The one or more third hardware pipeline stages are configured to receive the modified value from the second pipeline stage and store the value at a memory address in the on-chip memory.

[0018] Once the program source code has been defined with a construct that maps to a circuit implementation, the source code (including the construct) can be compiled to generate a circuit description. For example, the circuit description can be expressed using an HDL. The circuit description can in turn be used to generate an SDC including a circuit implementation. For example, the HDL can be used to generate an FPGA image or bitstream including the circuit implementation defined by the construct. The FPGA image or bitstream can in turn be utilized to program an FPGA including the circuit implementation.

[0019] As briefly discussed above, the implementation of the technology disclosed in this article enables hardware engineers and software engineers to easily and quickly generate some good and reliable SDC implementations using programming constructs mapped to SDC implementations. Other technical effects not explicitly identified in this article can also be implemented by the disclosed technology implementation.

[0020] It should be understood that the above subject matter can be implemented as a computer-controlled apparatus, a computer-implemented method, a computing device, or an article of manufacture such as a product of a computer-readable medium. These and various other features will be apparent by reading the following detailed description and viewing the associated drawings.

[0021] This summary is provided to introduce in simplified form a brief description of some aspects of the disclosed technology that will be further described in the following specific implementations. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended that this summary be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that address any or all of the disadvantages mentioned in any part of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a computational architecture diagram illustrating aspects of a system disclosed herein for generating a synchronous digital circuit based on program source code including programming constructs mapped to the synchronous digital circuit;

[0023] Figure 2 is a hardware architecture diagram showing aspects of an illustrative example synchronous digital circuit including several hardware pipelines, each having a plurality of pipeline stages, and computational units that may be defined and implemented using the disclosed techniques;

[0024] Figure 3is a hardware architecture diagram showing aspects of a language construct mapped to circuit implementation for enabling threads in a pipeline to wait for a specified condition to occur;

[0025] Figure 4 is a hardware architecture diagram showing aspects of language constructs mapped to circuit implementations for atomically implementing source code instructions in hardware;

[0026] Figure 5 is a hardware architecture diagram illustrating aspects of a language construct mapped to a circuit implementation for atomically performing read-modify-write storage operations;

[0027] Figure 6 is a flow chart showing a routine for constructing a synchronous digital circuit, a reference circuit, and a circuit implementation from source code that is efficiently mapped to the circuit implementation. Figure 1-Figure 5 aspects of the operation of the described technology;

[0028] Figure 7 is a computer architecture diagram showing an illustrative computer hardware and software architecture for a computing device that may implement aspects of the techniques presented herein; and

[0029] Figure 8 is a network diagram illustrating a distributed computing environment in which aspects of the disclosed technology may be implemented. DETAILED DESCRIPTION

[0030] The following detailed description refers to techniques for generating SDC from source code constructs that map efficiently to circuit implementations. As briefly discussed, implementation of the techniques disclosed herein enables the creation of high-performance and reliable SDC implementations using programming constructs in iterative multithreaded programming languages ​​that map efficiently to SDC implementations. Other technical advantages not specifically mentioned herein may also be achieved through implementation of the disclosed subject matter.

[0031] Although the subject matter described herein is presented in the general context of a computing system executing a compiler, the compiler is configured to compile source code language constructs that are mapped to circuit implementations. Those skilled in the art will recognize that other implementations may be performed in conjunction with other types of computing systems and modules. Those skilled in the art will also appreciate that the subject matter described herein may be practiced using other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, computing or processing systems embedded in devices (such as wearable computing devices, automobiles, home automation, etc.), minicomputers, mainframe computers, etc.

[0032] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and which are shown by way of illustration of specific configurations or examples. Referring now to the drawings, in which like numerals represent like elements throughout the several views, aspects of various techniques for generating SDCs from source code constructs that efficiently map to circuit implementations will be described.

[0033] Figure 1 1 is a computational architecture diagram showing aspects of an illustrative system 100 disclosed herein for defining and generating a synchronous digital circuit ("SDC") 112 based on a program source code 102 that includes programming constructs that map to the SDC 112. The SDC may be implemented by a gate array, a field programmable gate array ("FPGA"), an application specific integrated circuit ("ASIC"), and other types of circuit devices. Although the disclosed subject matter is primarily described in the context of an SDC 112 implemented in an FPGA, it should be understood that the techniques disclosed herein may be utilized to define an SDC 112 implemented using other types of devices.

[0034] like Figure 1 As shown, the illustrative system 100 includes a compiler 104 that compiles program source code 102 to generate hardware description language ("HDL") code or a low-level representation of a circuit (such as a netlist). As briefly discussed above, HDL is a modeling language used by hardware engineers to describe the structure and behavior of electronic circuits, most of which are typically digital logic circuits. Examples of HDLs include VHSIC HDL and VERILOG.

[0035] As will be described in detail below, the program source code 102 is expressed using a multithreaded imperative programming language designed to target the SDC 112. The disclosed language provides many features of languages ​​such as 'C' and 'JAVA', such as function calls, for-loops, arithmetic operators, and conditional statements. However, the disclosed language includes constructs that map directly to the underlying SDC 112 hardware implementation. This enables both hardware and software engineers to reason about performance and be effective in optimizing their designs. As described above, this can also make software engineers familiar with the language and save hardware engineers from dealing with various types of errors that occur when coding in HDL.

[0036] The disclosed multithreaded imperative programming language is imperative because program statements are executed sequentially, and is multithreaded because multiple execution threads can be executed in parallel. As described above, a thread is a collection of local variables. The thread is executed when the hardware circuit processes the local variables.

[0037] The threads described herein are similar to, but different from, software threads. While software threads maintain a call stack containing local variables and execute code in memory, threads described herein are collections of local variables that are moved through hardware circuits. While software threads have locations in executable code determined by instruction pointers, the disclosed threads have physical locations on the SDC at a given point in time. An SDC can execute hundreds, thousands, or even millions of threads, and SDC execution can be pipelined, i.e., different threads can be executed simultaneously in different stages of the circuit.

[0038] As will be described in more detail below, language constructs may be defined in program source code 102 that is mapped to a circuit implementation. A language construct is a syntactically permitted portion of a program that may be formed from one or more lexical tokens. The language constructs described herein are mapped to a circuit implementation that guarantees thread ordering (i.e., threads will exit the circuit implementation in the same order as they entered).

[0039] As will be described in more detail below, the circuit implementation generated by the construction disclosed herein can be implemented as an SDC in an FPGA, a gate array, an ASIC, or another type of suitable device. Another hardware component such as a NIC can be configured with an FPGA, a gate array, or an ASIC to achieve the desired functionality.

[0040] like Figure 1 As shown, a compiler 104 can compile a program source code 102 including one or more of the language constructs disclosed herein into a circuit description, in this example, HDL code 106. The HDL code 106 can be provided to an HDL synthesis tool 108, which in turn can generate a bitstream 110 that can be utilized to program an SDC 112, such as, for example, on an FPGA. When targeting an ASIC, the HDL code 106 can be provided to an ASIC manufacturer for production in a factory.

[0041] Figure 2 1 is a hardware architecture diagram showing aspects of an illustrative example SDC 112, which includes several hardware pipelines 200A-200C (or "pipelines") that can be defined and implemented using the disclosed techniques. Each hardware pipeline has a plurality of pipeline stages, and each pipeline stage has a computational unit. Figure 2 As shown, program source code 102 may be compiled into a pipeline 200A-200C of a hardware computing unit.

[0042] The pipelines 200A-200C may be connected by a first-in-first-out ("FIFO") queue (also referred to herein as "FIFOs" or "queues"). The pipelines 200A-200C implement functionality defined by the program source code 102. FIFOs store data values, provide inputs to the pipelines, and store outputs generated by the pipelines. For example, the SDC 112 includes a pipeline 200A that feeds its output to FIFO 202A. Pipeline 200B, in turn, takes its input from FIFO 202A and provides its output to FIFO 202B. Pipeline 200C takes its input from FIFO 202B.

[0043] In some configurations, the pipeline implements circuitry that determines when to retrieve the next value(s) from the FIFO. For example, a policy may require that the input FIFO (e.g., FIFO 202A in the case of pipeline 200B) is not empty and the output FIFO (e.g., FIFO 202B) is not full before retrieving a value from the input FIFO (e.g., FIFO 202A) for processing.

[0044] like Figure 2 As shown, the pipeline can be composed of one or more pipeline stages 206A-206B. Execution is pipelined by executing different threads in different stages of the pipeline simultaneously. The results of a stage can be stored in a register and provided to the next stage for the duration of the next clock cycle.

[0045] Each pipeline stage may include one or more computational units 208B such as an adder 208A and a lookup table ("LUT") 208B. In the illustrated example, the adder 208A may perform basic operations such as addition, subtraction, and multiplication. The computational units may also implement Boolean operators (e.g., "OR," "NOR," "XOR," etc.) or other custom logic provided by the SDC manufacturer.

[0046] The computational unit may also be implemented by a user programmable lookup table 208B. The illustrated LUT 208B depicts a two-input truth table that maps two input bits to a single output bit. The LUT 208B may be configured to support different numbers of input bits. To generate more complex output values, such as characters or 8-bit integers, multiple LUTs 208B may be used, each connected to a different bit of the input variable.

[0047] A computational unit may temporarily store a result in a register (or "flip-flop"). The contents of such a register may be provided to other computational units in the same or different pipelines. A register may capture a value at the input when the connected digital clock transitions from 0 to 1, and provide that value at the output until the end of the next clock cycle (i.e., until the clock transitions from 0 to 1 again). A register may also include an enable line. If the enable line is set to false, the register will not perform the above operations, maintaining the current output value over multiple clock cycles.

[0048] It should be understood that for the purposes of this discussion, Figure 2 The pipeline architecture shown in has been simplified. The programming language constructs described herein may be utilized to implement a more complex SDC 112 having more than Figure 2 More components shown.

[0049] Figure 3 300 is a hardware architecture diagram showing aspects of a language construct that is mapped to a circuit implementation 300 for enabling threads in a pipeline to wait for a specified condition to occur. In this configuration, the language construct defines a conditional statement 304 that requires a thread in a pipeline to wait for a specified condition to occur. The conditional statement 304 in the program source code 102 may be expressed as "wait_for(x>global_variable)", for example, where "x>global_variable" is the condition that the pipeline must wait for. Other forms of syntax may be used in other configurations.

[0050] In this configuration, the language construct maps to a circuit implementation 300 that includes a hardware pipeline 200A that implements functionality defined by instructions 302A in the source code 102 that precedes the conditional statement 304. The circuit implementation 300 in this configuration also includes a second hardware pipeline 200B that implements functionality specified by instructions 302B in the source code 102 that follows the conditional statement 304. The first hardware pipeline outputs 200A values ​​306A to the queue 202A. The second pipeline 200B obtains input values ​​306A from the queue 202A.

[0051] In operation, the second hardware pipeline 200B processes the value 306A from the queue 202A only when it evaluates the condition defined by the conditional statement 304 in the program source code 102 to be true (e.g., when x>global_variable in the example above). In some configurations, the specified condition is evaluated in the second pipeline 200B by comparing the value 306A obtained from the queue 202A with the value 306B stored in the register 204A. For example, the value 306B stored in the register 204A is generated by the third pipeline 200C. The value 306B corresponds to the global variable in the program source code 102 (e.g., x in the example given above).

[0052] Figure 4 4 is a hardware architecture diagram showing aspects of a language construct 402 that is mapped to a circuit implementation 400 for atomically implementing source code instructions in hardware; as discussed above, the terms "atomically" and "atomic" refer to a circuit implementation that allows only one thread to be executed at a time. Atomic operations are also completed in a single step (e.g., clock cycle) relative to other operations.

[0053] In this configuration, construct 402 identifies the beginning and end of a sequence of instructions in source code 102 that will be atomically executed in hardware. For example, construct 402 may be expressed as "atomic {}" where curly braces encompass instructions 302C that will be atomically executed in hardware. Other forms of syntax may be used in other configurations. This construct implements thread synchronization by mapping to a circuit implementation that allows only one thread to be in an atomic region at a time.

[0054] The construction 402 is mapped to a circuit implementation 400 that includes a single hardware pipeline stage 206A for implementing the instruction 302C to be executed atomically. The single hardware pipeline stage 206A executes in a single clock cycle. Figure 4 As shown, a single hardware pipeline stage 206A may receive input from register 204C and output a value to another register 204D.

[0055] Figure 5 5 is a hardware architecture diagram showing aspects of a language construct 502 mapped to a circuit implementation 500 for atomically performing read-modify-write storage operations; the construct 500 may define an arbitrarily complex set of instructions for modifying a specified variable during a read-modify-write operation. As discussed above, the construct 502 implements thread synchronization by mapping to a circuit implementation 500 for performing read-modify-write operations synchronized with on-chip memory. This ensures that problems due to read-write-modify operations performed for unsynchronized threads are avoided without performance degradation.

[0056] In this configuration, the circuit implementation 500 includes a memory 504 and one or more first hardware pipeline stages 206B. In the illustrative example, the first hardware pipeline stage 206B loads a value 506 from the on-chip memory 504. The value 506 is loaded from an address 503 of the memory 504. The first hardware pipeline stage 206B provides the value 506 read from the memory 504 to the second pipeline stage 206C.

[0057] The second hardware pipeline stage compares address 503 to one or more addresses 505 associated with a most recent (e.g., previous) memory operation. If the addresses match, the value 506 loaded from the most recent memory 504 is discarded and the value 507 stored in register 204E during the most recent memory operation is modified as described below. If the addresses do not match, the value 506 loaded from memory 504 is then modified as described below.

[0058] The second hardware pipeline stage 206C performs a user-specified calculation on the value 506 or the value 507 from a previous store operation to generate a modified value 508. The operations specified by the read-modify-write construct can be arbitrarily complex. For example, and without limitation, if construct 502 specifies an operation of the form "memory[x] = (memory[x] + y) * 2", then the "+y" and "*2" instructions atomically occur in the same pipeline stage 206C that modifies the value 506 if the load address 503 matches the load address for the most recent store.

[0059] The second pipeline stage 206C stores the modified value 508 in register 204E for use during the next read-modify-write operation. The second pipeline stage 206C also stores the address 503 in register 204F, also for use during the next read-modify-write operation.

[0060] The one or more third hardware pipeline stages 206D follow the second hardware pipeline stage 206C. The one or more third hardware pipeline stages are configured to receive the modified value 508 from the second pipeline stage 206C and store the value 508 in the on-chip memory 504 at the memory address 503 .

[0061] As described above, once the program source code 102 has been defined and stored with constructs that map to circuit implementations (such as those discussed above), the source code 102 (including the constructs) can be compiled to generate a circuit description, such as the HDL code 106 described above. The circuit description can in turn be used to generate an SDC 112 that includes the described circuit implementation. For example, the HDL code 106 generated by the compiler 104 from the program source code 102 can be utilized to generate an FPGA that includes the circuit implementation defined by the language constructs.

[0062] Figure 6 is a flow chart showing a routine 600 for generating a synchronous digital circuit, a reference circuit, and a source code construct from an efficient mapping to a circuit implementation according to one implementation example disclosed herein. Figure 1-Figure 5 It should be understood that the description herein of the operation of the technology described herein is not limited to the following aspects. Figure 6 The logical operations of the and other figures may be implemented (1) as a sequence of computer-implemented acts or program modules running on a computing device and / or (2) as interconnected machine logic circuits or circuit modules within a computing device.

[0063] The specific implementation of the technology disclosed herein is a matter of choice depending on the performance and other requirements of the computing device. Therefore, the logical operations described herein are referred to as states, operations, structural devices, actions or modules in different ways. These states, operations, structural devices, actions and modules can be implemented with hardware, software, firmware, special digital logic, and any combination thereof. It should be understood that more or less operations than those shown in the figure and described herein can be performed. These operations can also be performed in an order different from those described herein.

[0064] Routine 600 begins at operation 602, where program source code 102 including language constructs mapped to circuit implementations is defined and stored. As described above, for example, a construct may be specified to map to circuit implementation 300 for enabling a thread in a pipeline to wait for a specified condition to occur (e.g., Figure 3 ), mapped to a circuit implementation 400 for atomically implementing source code instructions in hardware (e.g., Figure 4 ), or mapped to a circuit implementation 500 for atomically performing read-modify-write storage operations (e.g., Figure 5 ). Other types of constructs that map to other types of circuit implementations may be defined in other configurations.

[0065] Beginning with operation 602, the routine 600 proceeds to operation 604, where the compiler 104 compiles the program source code 102 (including language constructs that map to circuit implementations) into a circuit description. As described above, the circuit description may be expressed as HDL code 106.

[0066] From operation 604, the routine proceeds to operation 606, where the circuit description (eg, HDL code) is used to generate SDL 112, which includes the circuit implementation defined by the circuit description 106. The routine 600 then proceeds from operation 606 to operation 608, where it ends.

[0067] Figure 7is a computer architecture diagram showing an illustrative computer hardware and software architecture for a computing device that can implement aspects of the techniques presented herein. Specifically, Figure 7 The architecture illustrated in the may be used to implement a server computer, a mobile phone, an e-reader, a smart phone, a desktop computer, an AR / VR device, a tablet computer, a laptop computer, or another type of computing device.

[0068] Figure 7 The illustrated computer 700 includes a central processing unit 702 ("CPU"), a system memory 704 including a random access memory 706 ("RAM") and a read-only memory 708 ("ROM"), and a system bus 710 that couples the memory 704 to the CPU 702. A basic input / output system ("BIOS" or "firmware") containing the basic routines that help transfer information between components within the computer 900, such as during startup, may be stored in the ROM 708. The computer 700 also includes a mass storage device 712 for storing an operating system 722, application programs, and other types of programs, such as the compiler 104 and the HDL synthesis tool 108. The mass storage device 712 may also be configured to store other types of programs and data.

[0069] The mass storage device 712 is connected to the CPU 702 through a mass storage controller (not shown) connected to the bus 710. The mass storage device 712 and its associated computer-readable media provide non-volatile memory for the computer 700. Although the description of computer-readable media contained herein refers to a mass storage device, such as a hard disk, a CD-ROM drive, a DVD-ROM drive, or a USB memory key, it should be understood by those skilled in the art that computer-readable media can be any available computer storage media or communication media that can be accessed by the computer 700.

[0070] Communication media includes computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and includes any delivery medium. The term "modulated data signal" refers to a signal that has one or more of its characteristics changed or set in some way to encode the information in the signal. By way of example and not limitation, communication media include wired media such as a wired network or a direct wired connection, and wireless media such as acoustic, radio frequency, infrared and other wireless media. Combinations of any of the above should also be included within the scope of computer readable media.

[0071] By way of example and not limitation, computer storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. For example, computer storage media include, but are not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other solid-state memory technology, CD-ROM, digital versatile disks ("DVD"), HD-DVD, Blu-ray or other optical storage, cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by the computer 700. For purposes of the claims, the term "computer storage media" as used herein, and its corresponding variations, does not include waves or signals themselves or communications media.

[0072] According to various configurations, the computer 700 can operate in a networked environment using a logical connection to a remote computer via a network such as a network 720. The computer 700 can be connected to the network 720 via a network interface unit 716 connected to the bus 710. It should be understood that the network interface unit 716 can also be utilized to connect to other types of networks and remote computer systems. The computer 700 may also include an input / output controller 718 for receiving and processing input from a plurality of other devices, including a keyboard, a mouse, a touch input, an electronic stylus ( Figure 7 Similarly, the input / output controller 718 can send data to a display screen or other type of output device (also not shown). Figure 7 ) provides an output.

[0073] It should be understood that the software components described herein, when loaded into the CPU 702 and executed, can transform the CPU 702 and the entire computer 700 from a general-purpose computing device to a special-purpose computing device, which is customized to support the functionality presented herein. The CPU 702 can be composed of any number of transistors or other discrete circuit elements, which can take any number of states individually or collectively. More specifically, in response to the executable instructions contained in the software modules disclosed herein, the CPU 702 can operate as a finite state machine. These computer executable instructions can transform the CPU 702 by specifying how the CPU 702 switches between states, thereby transforming the transistors or other discrete hardware elements that constitute the CPU 702.

[0074] Encoding the software modules presented herein can also transform the physical structure of the computer-readable medium presented herein. In different implementations of this specification, the specific transformation of the physical structure depends on various factors. Examples of these factors include, but are not limited to, the technology used to implement the computer-readable medium, whether the computer-readable medium is characterized as a main memory or an auxiliary memory, etc. For example, if the computer-readable medium is implemented as a semiconductor-based memory, the software disclosed herein can be encoded on the computer-readable medium by transforming the physical state of the semiconductor memory. For example, the software can transform the state of the transistors, capacitors, or other discrete circuit elements that constitute the semiconductor memory. The software can also transform the physical state of these components in order to store data thereon.

[0075] As another example, the computer readable medium disclosed herein can be implemented using magnetic or optical technology. In this implementation, when the software is encoded in a magnetic or optical medium, the software presented herein can transform the physical state of the magnetic or optical medium. These transformations can include changing the magnetic properties of a specific location in a given magnetic medium. These transformations can also include changing the physical characteristics or properties of a specific location in a given optical medium to change the optical properties of these locations. Without departing from the scope and spirit of this specification, other transformations of physical media are possible, and the aforementioned examples are provided only for the convenience of this discussion.

[0076] In view of the above, it should be understood that many types of physical transformations occur in the computer 700 in order to store and execute the software components presented herein. It should also be understood that Figure 7 The architecture of the computer 700 shown, or a similar architecture, may be utilized to implement other types of computing devices, including handheld computers, video game devices, embedded computer systems, such as smart phones, tablet computers, and other types of computing devices known to those skilled in the art. It is also contemplated that the computer 700 may not include Figure 7 All components shown may include Figure 7 Other components not explicitly shown may be used in conjunction with Figure 7 Completely different architecture as shown.

[0077] Figure 8 8 is a network diagram illustrating a distributed network computing environment 800 in which aspects of the disclosed technology may be implemented according to various implementation examples presented herein. Figure 8As shown, one or more server computers 800A may be interconnected with multiple client computing devices via a communication network 720 (which may be any one or a combination of a fixed line or wireless LAN, WAN, intranet, extranet, peer-to-peer network, virtual private network, Internet, Bluetooth communication network, dedicated low voltage communication network, or other communication networks), such as, but not limited to, tablet computers 800B, game controllers 800C, smart watches 800D, phones 800E, such as smart phones, personal computers 800F, and AR / VR devices 800G.

[0078] In a network environment where the communication network 720 is the Internet, for example, the server computer 800A can be a dedicated server computer that is operable to process and transmit data to and from the client computing devices 800B-800G via any one of a number of known protocols, such as the Hypertext Transfer Protocol (“HTTP”), the File Transfer Protocol (“FTP”), or the Simple Object Access Protocol (“SOAP”). In addition, the networked computing environment 800 can utilize various data security protocols, such as the Secure Sockets Layer (“SSL”) or the Pretty Good Privacy Protocol (“PGP”). Each of the client computing devices 800B-800G can be equipped with an operating system that is operable to support one or more computing applications or terminal sessions, such as a web browser ( Figure 8 ), or other graphical user interfaces ( Figure 8 Not shown), or a mobile desktop environment ( Figure 8 ), to gain access to server computer 800A.

[0079] The server computer 800A can be communicatively coupled to other computing environments ( Figure 8 ) and receives data about participating user interactions / resource networks. In illustrative operation, a user ( Figure 8 ) can interact with computing applications running on client computing devices 800B-800G to obtain required data and / or execute other computing applications.

[0080] Data and / or computing applications may be stored on one or more servers 800A and communicated to collaborating users via client computing devices 800B-800G over the example communication network 720. Figure 8 The client computing devices 800B-800G and the server computer 800A may request access to specific data and applications that reside in whole or in part in the server computer 800A. Such data may be transferred between the client computing devices 800B-800G and the server computer 800A for processing and storage.

[0081] Server 800A can host computing applications, processes and applets for data and application generation, authentication, encryption, communication, and can communicate with other server computing environments ( Figure 8 Not shown), third-party service providers ( Figure 8 (not shown), network attached storage ("NAS"), and storage area network ("SAN") work together to enable application / data processing.

[0082] It should be understood that Figure 7 The illustrative computing architecture shown in Figure 8 The illustrative distributed network computing environment shown has been simplified for ease of discussion. It should be understood that the computing architecture and distributed network computing environment may include and utilize many more components, devices, software programs, network devices, and other components not specifically described herein.

[0083] The disclosure presented herein also includes the subject matter set forth in the following clauses:

[0084] Clause 1. A computer-implemented method comprising: storing source code expressed in a multithreaded imperative programming language, the source code comprising constructs, the constructs being mapped to circuit implementations, the constructs comprising conditional statements, and wherein the circuit implementation comprises: a first hardware pipeline implementing a first instruction before the conditional statement, the first hardware pipeline having an output connected to a queue, a second hardware pipeline implementing a second instruction after the conditional statement, the second hardware pipeline having an input connected to the queue, and wherein the second hardware pipeline processes a value from the queue only when the conditional statement is evaluated to be true; compiling the constructs into a circuit description; and generating a synchronous digital circuit based on the circuit description, the synchronous digital circuit comprising the circuit implementation.

[0085] Clause 2. The computer-implemented method of clause 1, wherein the conditional statement is evaluated by comparing a value from the queue to a value stored in a register.

[0086] Clause 3. The computer-implemented method of any of Clauses 1 to 2, wherein the value in the register is generated by a third hardware pipeline.

[0087] Clause 4. The computer-implemented method of any of Clauses 1 to 3, wherein the value from the queue comprises a local variable.

[0088] Clause 5. The computer-implemented method of any of Clauses 1 to 4, wherein the value stored in the register comprises a global variable.

[0089] Clause 6. The computer-implemented method of any of Clauses 1 to 5, wherein the synchronous digital circuit is implemented in a field programmable gate array (FPGA), a gate array, or an application specific integrated circuit (ASIC).

[0090] Clause 7. The computer-implemented method of any of clauses 1 to 6, wherein the network interface card (NIC) is configured with an FPGA, a gate array, or an ASIC.

[0091] Clause 8. A computer-implemented method comprising: storing source code expressed in a multithreaded imperative programming language, the source code comprising constructs, the constructs mapping to circuit implementations, the constructs comprising multiple instructions to be executed atomically, and wherein the circuit implementation comprises a single hardware pipeline stage for implementing the multiple instructions, the single hardware pipeline stage being configured for execution in a single clock cycle; compiling the constructs into a circuit description; and based on the circuit description, generating a synchronous digital circuit, the synchronous digital circuit comprising the circuit implementation.

[0092] Clause 9. The computer-implemented method of clause 8, wherein the circuit implementation further comprises: a first register for outputting a value to a single hardware pipeline stage.

[0093] Clause 10. The computer-implemented method of any of Clauses 8 to 9, wherein the circuit implementation further comprises: a second register for receiving a value output by the single hardware pipeline stage.

[0094] Clause 11. The computer-implemented method of any of Clauses 8 to 10, wherein the construct identifies a beginning of the plurality of instructions and an end of the plurality of instructions.

[0095] Clause 12. The computer-implemented method of any of clauses 8 to 11, wherein the synchronous digital circuit is implemented in a field programmable gate array (FPGA), a gate array, or an application specific integrated circuit (ASIC).

[0096] Clause 13. The computer-implemented method of any of clauses 8 to 12, wherein the network interface card (NIC) is configured with an FPGA, a gate array, or an ASIC.

[0097] Clause 14. The computer-implemented method of any of Clauses 8 to 13, wherein the circuit description comprises hardware description language (HDL) code.

[0098] Clause 15. A computer-implemented method comprising: storing source code expressed in a multithreaded imperative programming language, the source code comprising constructs, the constructs mapping to a circuit implementation, the constructs comprising indications that memory read-modify-write operations are to be performed atomically, and wherein the circuit implementation comprises: a memory, one or more first hardware pipeline stages for loading a first value stored at a memory address of the memory, a second hardware pipeline stage following the one or more first hardware pipeline stages for: comparing the memory address to a memory address associated with a previous memory operation, if the memory address and the memory address associated with the previous memory operation are the same, modifying a second value stored in a register by the previous memory operation to generate a modified value, and if the memory address and the memory address associated with the previous memory operation are not the same, modifying the first value to generate the modified value, and one or more third hardware pipeline stages following the second hardware pipeline stage for storing the modified value at the memory address; compiling the constructs into a circuit description; and generating a synchronous digital circuit based on the circuit description, the synchronous digital circuit comprising the circuit implementation.

[0099] Clause 16. The computer-implemented method of Clause 15, wherein the second hardware pipeline stage is further configured to store the modified value in a register and store the memory address of the first value in a second register.

[0100] Clause 17. The computer-implemented method of any of Clauses 15 to 16, wherein the second hardware pipeline stage is further for storing a memory address and a value associated with a previous store operation in a register.

[0101] Clause 18. The computer-implemented method of any of Clauses 15 to 17, wherein the synchronous digital circuit is implemented in a field programmable gate array (FPGA), a gate array, or an application specific integrated circuit (ASIC).

[0102] Clause 19. The computer-implemented method of any of clauses 15 to 18, wherein the network interface card (NIC) is configured with an FPGA, a gate array, or an ASIC.

[0103] Clause 20. The computer-implemented method of any one of Clauses 15 to 19, wherein the circuit description comprises hardware description language (HDL) code.

[0104] Based on the foregoing, it should be understood that techniques for constructing and generating SDCs from source code that is efficiently mapped to circuit implementations have been disclosed herein. Although the subject matter presented herein is described in the language of computer structural features, methods and transformation actions, specific computing machines, and computer-readable media, it should be understood that the subject matter set forth in the appended claims is not necessarily limited to the specific features, actions, or media described herein. Instead, these specific features, actions, and media are disclosed as example forms of implementing the claimed subject matter.

[0105] The above subject matter is provided by way of illustration only and should not be construed as limiting. Various modifications and changes may be made to the inventive subject matter described herein without following the illustrated and described example configurations and applications, and without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A computer-implemented method for constructing a synchronous digital circuit (SDC), comprising: storing source code expressed in a multithreaded imperative programming language, the source code comprising constructs, the constructs mapping to circuit implementations, the constructs comprising conditional statements, and wherein the circuit implementations comprise: a first hardware pipeline, the first hardware pipeline implementing a first functionality defined by a first instruction, the first instruction preceding the conditional statement in the source code, the first hardware pipeline having an output connected to a queue, and a second hardware pipeline that implements a second functionality defined by a second instruction and based on the output of the first hardware pipeline, the second instruction being located after the conditional statement in the source code, the second hardware pipeline having an input connected to the queue, the queue being connected to the output of the first hardware pipeline, and wherein the second hardware pipeline processes a value received by the queue from the first hardware pipeline only if the conditional statement evaluates to true; compiling the construction into an output circuit description in a hardware description language HDL; and A synchronous digital circuit is generated based on the circuit description, the synchronous digital circuit including the circuit implementation. 2 . The computer-implemented method of claim 1 , wherein the conditional statement is evaluated by comparing the value from the queue to a value stored in a register.

3. The computer-implemented method of claim 2, wherein the value stored in the register is generated by a third hardware pipeline. The computer-implemented method of claim 3 , wherein the value from the queue comprises a local variable.

5. The computer-implemented method of claim 4, wherein the value stored in the register comprises a global variable.

6. The computer-implemented method of claim 1, wherein the synchronous digital circuit is implemented in a field programmable gate array (FPGA), a gate array, or an application specific integrated circuit (ASIC).

7. The computer-implemented method of claim 6, wherein a network interface card (NIC) is configured with the FPGA, the gate array, or the ASIC.

8. The computer-implemented method of claim 1, wherein the circuit implementation guarantees thread ordering including a plurality of threads that enter the circuit implementation in a particular order and exit the circuit implementation in the particular order.

9. A computing system comprising: one or more processing units; as well as A computer-readable storage medium having stored thereon computer-executable instructions that, when executed by the one or more processing units, cause the computing system to: storing source code expressed in a multithreaded imperative programming language, the source code comprising constructs, the constructs mapping to circuit implementations, the constructs comprising conditional statements, and wherein the circuit implementations comprise: a first hardware pipeline, the first hardware pipeline implementing a first functionality defined by a first instruction, the first instruction preceding the conditional statement in the source code, the first hardware pipeline having an output connected to a queue, and a second hardware pipeline that implements a second functionality defined by a second instruction and based on the output of the first hardware pipeline, the second instruction being located after the conditional statement in the source code, the second hardware pipeline having an input connected to the queue, the queue being connected to the output of the first hardware pipeline, and wherein the second hardware pipeline processes a value received by the queue from the first hardware pipeline only if the conditional statement evaluates to true; compiling the construction into an output circuit description in a hardware description language HDL; as well as A synchronous digital circuit is generated based on the circuit description, the synchronous digital circuit including the circuit implementation.

10. The computing system of claim 9, wherein the conditional statement is evaluated by comparing the value from the queue to a value stored in a register.

11. The computing system of claim 10, wherein the value stored in the register is generated by a third hardware pipeline.

12. The computing system of claim 11, wherein the value from the queue comprises a local variable.

13. The computing system of claim 12, wherein the value stored in the register comprises a global variable.

14. The computing system of claim 9, wherein the synchronous digital circuit is implemented in a field programmable gate array (FPGA), a gate array, or an application specific integrated circuit (ASIC).

15. The computing system of claim 14, wherein a network interface card (NIC) is configured with the FPGA, the gate array, or the ASIC.

16. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by one or more processing units, cause a computing system to: storing source code expressed in a multithreaded imperative programming language, the source code comprising constructs, the constructs mapping to circuit implementations, the constructs comprising conditional statements, and wherein the circuit implementations comprise: a first hardware pipeline, the first hardware pipeline implementing a first functionality defined by a first instruction, the first instruction preceding the conditional statement in the source code, the first hardware pipeline having an output connected to a queue, and a second hardware pipeline that implements a second functionality defined by a second instruction and based on the output of the first hardware pipeline, the second instruction being located after the conditional statement in the source code, the second hardware pipeline having an input connected to the queue, the queue being connected to the output of the first hardware pipeline, and wherein the second hardware pipeline processes a value received by the queue from the first hardware pipeline only if the conditional statement evaluates to true; compiling the construction into an output circuit description in a hardware description language HDL; as well as A synchronous digital circuit is generated based on the circuit description, the synchronous digital circuit including the circuit implementation.

17. The computer-readable storage medium of claim 16, wherein the conditional statement is evaluated by comparing the value from the queue to a value stored in a register.

18. The computer-readable storage medium of claim 17, wherein the value stored in the register is generated by a third hardware pipeline.

19. The computer-readable storage medium of claim 18, wherein the value from the queue comprises a local variable.

20. The computer-readable storage medium of claim 19, wherein the value stored in the register comprises a global variable.

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