Digital circuit monitoring equipment

Abstract

Embodiments of the present disclosure relate to a digital circuit monitoring device. A ring oscillator includes a chain of logic components. A storage element is associated with each logic component and is configured to store the state of the output of the logic component associated with the storage element. A first circuit counts the state transitions of the output of a given chain of logic components. A second circuit synchronizes each storage with a clock signal. A third circuit determines the number of logic components traversed by the state transitions between two edges of the clock signal. The determination is made based on the counted number of state transitions and the stored state of the output.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from French Patent Application No. 2002212, filed on March 5, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits, and more particularly to integrated electronic circuits. The present disclosure more particularly relates to a digital circuit monitoring device. Background Art

[0004] Known digital or sequential circuits include storage devices or sequential elements, usually synchronous flip-flops that are synchronized with a clock signal. Such digital circuits also include combinatorial paths formed by multiple logical or combinational components, i.e., components that do not have a storage function. Each combinatorial path couples the output of one flip-flop to the input of another flip-flop. The clock signal controls the timing or sequence of the storage through the flip-flops.

[0005] In order for such digital circuits to operate as intended, the propagation or transmission time of a signal in each combinatorial path of the circuit should be shorter than a predetermined duration minus a time margin. Depending on the combinatorial path considered, the predetermined duration corresponds to the duration of a period or cycle of the clock signal, or to the duration of multiple periods of the clock signal. The time margin is usually equal to the signal settling duration t hd Keep the signal for a duration of t su Determine the duration t hd and t su , so that if the signal delivered to the data input of the flip-flop is before the edge of the clock signal that causes the storage su and the entire duration t after the edge hd is in a stable state, the storage of the trigger is performed as expected.

[0006] The combinatorial path of a digital circuit with the longest propagation time is often called the critical path.

[0007] Due to manufacturing dispersion of digital circuits, aging of digital circuits, and / or operating conditions of digital circuits (such as changes in the temperature of the circuits and / or the supply voltage of the circuits), the propagation time in the combinational paths of the circuits can vary. In particular, when the propagation time of a signal in one of the combinational paths of the circuit (usually the critical path) increases, the propagation time can exceed a predetermined duration minus a time margin, which results in a failure of the circuit. A failure of the circuit can also be caused by a decrease in the propagation time of a signal in one of the combinational paths of the circuit.

[0008] In order to prevent such failures, one or more monitoring devices of the digital circuit can be provided, the digital circuit and the monitoring device are preferably implemented in the same integrated circuit. Such a time drift monitoring device can obtain information related to changes in the propagation delay of the conversion or signal through a logic component. This information is then used to determine or estimate whether the propagation time in the combination path of the monitored circuit (particularly in the critical path) changes, for example, whether the propagation time in one of the combination paths of the circuit can be longer than the predetermined duration of the combination path under consideration minus the time margin. When this is affirmative, compensation can be achieved, for example, by adjusting the frequency of the clock signal, the power supply voltage of the integrated circuit, and / or the bias voltage of the transistors of the integrated circuit to avoid failure of the circuit.

[0009] There is a need to overcome all or some of the above-mentioned disadvantages of known monitoring devices. Summary of the invention

[0010] Embodiments overcome all or part of the above-mentioned disadvantages of known monitoring devices.

[0011] Embodiments provide a monitoring device that is sensitive to frequency variations of a clock signal of a digital circuit that it monitors.

[0012] Embodiments provide a monitoring device capable of providing information about the variation of propagation delay of a logic component within a clock cycle.

[0013] Embodiments provide a monitoring device capable of providing information about variations in propagation delay of a logic component during any number of cycles of a clock signal.

[0014] Embodiments provide a monitoring device capable of providing information about variations in propagation delay of a logic component that is more accurate than information provided by known monitoring devices such as those described above.

[0015] Thus, an embodiment provides a device comprising: a ring oscillator comprising a chain of logic components; an assembly of storage elements, each storage element being associated with a different logic component of the chain and configured to store the state of the output of the logic component associated with the storage element; a first circuit configured to count the state transitions of the output of a given logic component of the chain; a second circuit configured to synchronize each storage using a clock signal; and a third circuit configured to determine the number of logic components of the chain that are traversed by state transitions between two edges of the clock signal based on the number of counted state transitions and the stored state of the output.

[0016] According to an embodiment, the third circuit is configured to determine the number of times the state transitions completely traverse the chain between the two edges based on the number of counted state transitions.

[0017] According to an embodiment, the third circuit is configured to determine a position of the state transition in the chain during an edge of a clock signal based on a state of the output stored during the edge.

[0018] According to an embodiment, the third circuit is configured to determine the number of logic components traversed by the state transition between the two edges of the clock signal based on the number of times the transition between the two edges traverses the entire oscillator, based on the position of the transition in the chain during the last of the two edges, and possibly based on the position of the transition in the chain during the first of the two edges.

[0019] According to an embodiment, each logical component of the chain is associated with a storage element of the assembly.

[0020] According to an embodiment, the storage element is a latch.

[0021] According to an embodiment, each latch has an input coupled, preferably connected, to an output of the logic component having said latch associated therewith.

[0022] According to an embodiment, the first circuit comprises an input connected to an output of a latch, the input of the latch being coupled (preferably connected) to an output of said given logic component.

[0023] According to an embodiment, the device comprises another component of storage elements, each associated with a different logical part of the chain and configured to store the output state of the logical part, the component and the other components being preferably configured such that each logical part associated with a storage element of the component is associated with a storage element of the other component.

[0024] According to an embodiment, the second circuit is configured so that when the latch of the other component is in a latched state, the latch of the component is in a transparent state; and when the latch of the other component is in a transparent state, the latch of the component is in a latched state. Preferably, the second circuit is preferably configured so that the latch switches between the latched state and the transparent state when the latch changes in each cycle of the continuous cycle of the clock signal.

[0025] According to an embodiment, the first circuit is configured to count transitions from the first state to the second state and transitions from the second state to the first state.

[0026] According to an embodiment, the second circuit is configured to synchronize each storage with an active edge, preferably a rising edge.

[0027] According to an embodiment, one of the logic components of the chain, preferably the given logic component, is configured to prevent the propagation of oscillations in the oscillator when the control signal is in a first state, and to allow the propagation of oscillations when the control signal is in a second state, and the second circuit is preferably configured to pass the control signal in the second state between the two edges.

[0028] An embodiment provides an integrated circuit comprising a device such as described and a first digital circuit configured to be sequenced by the clock signal.

[0029] An embodiment provides a method comprising the following steps: counting, by a first circuit, state transitions of outputs of logic components of a given ring oscillator comprising a chain of logic components; storing the states of the outputs of the logic components of the chain in a component of storage elements, each storage element being associated with a different logic component; synchronizing the storage element with a clock signal using a second circuit; and determining, by a third circuit, the number of logic components traversed by the state transitions between two edges of the clock signal based on the number of counted state transitions and the stored states of the outputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above features and advantages and other features and advantages will be described in detail below in the description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0031] Figure 1 An embodiment of a monitoring device is shown very schematically;

[0032] Figure 2 shows a diagram according to the implementation mode Figure 1 Timing diagram of signal changes of the device;

[0033] Figure 3 Another embodiment of a monitoring device is shown very schematically;

[0034] Figure 4 shows a diagram according to the implementation mode Figure 3 Timing diagram of signal changes of the device;

[0035] Figure 5 A further embodiment of a monitoring device is shown very schematically; and

[0036] Figure 6 shows a diagram according to the implementation mode Figure 5 Timing diagram of the signal changes of the device. DETAILED DESCRIPTION

[0037] In the various figures, similar features are designated by similar reference numerals. In particular, the same structural and / or functional features may have the same reference numerals in the various embodiments, and may be arranged with the same structure, size, and material properties.

[0038] For the sake of clarity, only the steps and elements that are useful for understanding the embodiments described herein are detailed and described. In particular, known uses of information related to propagation times of logical components delivered by a monitoring device, said device delivering information compatible with such known uses, and in particular using known compensations that can be implemented based on this information to avoid malfunctions of the monitored digital device are not described in detail. Furthermore, known digital circuits that can be monitored by the monitoring device are not described, said monitoring device being compatible with such known digital circuits.

[0039] Unless otherwise stated, when referring to two elements being connected together, this means being directly connected without any intervening elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or coupled via one or more other elements.

[0040] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or relative position qualifiers (such as terms "above", "below", "high", "low", etc.), or direction qualifiers (such as "horizontal", "vertical", etc.), reference is made to the direction shown in the figure.

[0041] Unless otherwise specified, "about," "approximately," "substantially," and "approximately" mean within 10%, preferably within 5%.

[0042] Figure 1 An embodiment of a monitoring device 1 is shown very schematically.

[0043] The device 1 comprises a ring oscillator 3. The oscillator 3 comprises a chain of N logical components Ci (C1, C2, C3, C4, C5), i being an integer ranging from 1 to N. The components Ci of the chain are connected in series one after another, with the last component in the chain, i.e. Figure 1 Component C5 in the example has Figure 1 Output O5 in the example, output O5 is connected to the input of the first component C1 of the chain. In other words, this chain is looped back on itself, or closed. The number N of components Ci and the type of each component Ci are determined so that when the oscillator 3 is operating or activated, the output Oi of each component Ci oscillates between two states (high and low) at a frequency determined by the propagation or transmission time of the signal through the component Ci.

[0044] For example, all components Ci of a chain are identical, such as Figure 1 In other examples, the chain includes at least two different components Ci, such as inverters, AND gates, OR gates, or NAND gates, etc. Providing a plurality of different components can enable obtaining information about variations in the transmission times of the different components, which transmission times differ due to manufacturing dispersion, aging, and / or modifications of operating conditions.

[0045] exist Figure 1 In the example of , all components Ci are inverters. In this case, the chain includes an odd number N of inverters. Figure 1 In the example, N is equal to 5.

[0046] exist Figure 1 In the example of FIG. 3 , although the number N of components Ci is equal to 5, in practice, the oscillator 3 may include any number N of components Ci greater than two, for example N greater than 10, preferably greater than 50, or even greater than 100.

[0047] The device 1 further comprises a set of storage elements Mj, j being an integer in the range from 1 to K, K being less than or equal to N. The term storage element Mj here refers to a storage element Mj that is synchronized with a synchronization signal. Such a synchronous storage element Mj is configured to store a high or low state of its data input synchronously with the edge or level of the synchronization signal, the stored state being available at an output M[j] of the storage element and being maintained at a stable value throughout the storage process. Flip-flops and latches are examples of synchronous storage elements.

[0048] Preferably, the storage elements Mj are identical to one another. Furthermore, storage by an element Mj is performed simultaneously in all elements Mj, synchronized by means of a signal sync.

[0049] Each element Mj is associated with a different logic component Ci from the oscillator 3. Each element Mj is configured to store a high or low state of the output Oi of the logic component Mi with which it is associated and to deliver the stored state on an output M[j].

[0050] According to an embodiment, Figure 1 As shown in , the number K of elements Mj is equal to the number N of logical components Ci. In other words, each component Ci is associated with a different element Mj. Figure 1 In the example of FIG. 4 , components C1 , C2 , C3 , C4 , and C5 are associated with corresponding elements M1 , M2 , M3 , M4 , and M5 .

[0051] The device 1 comprises a circuit 5, which is configured to deliver a signal sync from a clock signal clk. More specifically, the circuit 5 is configured to deliver the signal sync so that each storage in the element Mj is synchronized with an edge of the signal clk, preferably an active edge of the signal clk (e.g., a rising edge of the signal clk). In other words, the circuit 5 is configured to synchronize each storage into the element Mj with the signal clk.

[0052] Signal clk is preferably a clock signal delivered to a digital circuit (not shown) monitored by the device 1, storage in a flip-flop of the monitored digital circuit being effected during an active edge of the clock signal (eg, a rising edge of signal clk).

[0053] According to an embodiment, the element Mj is a latch. When the signal sync is in a first state (e.g., a low state), each element Mj is called transparent, and each state switch of its data input is copied to its output. When the signal sync is in a second state (e.g., a high state), each element Mj is called a latch, and despite the state switch of its possible data input, the state of its output is maintained. The state of the data input of the latch is stored when the signal sync switches from the first state to the second state, and as long as the signal sync is in the second state, the value M[j] of the output of the latch represents the stored state and the output value M[j].

[0054] The device 1 comprises a circuit 7 configured to count the state transitions of an output Oi of a given logic component Ci of the oscillator 3. In other words, the circuit 7 is configured to count the transitions of the output Oi from a high state to a low state and / or the transitions of the output Oi from a low state to a high state. Preferably, the circuit 7 is configured to count the transitions of the output Oi from a high state to a low state and from a low state to a high state. The circuit 7 comprises an input coupled or connected to the output Oi. The circuit 7 delivers an output signal c-out representing the number of transitions counted.

[0055] In this example, the circuit 7 is configured to count the transitions of the output O4 of the component C4. Furthermore, in this example, the circuit 7 has an input connected to the output O4 of the logic component C4.

[0056] The device 1 comprises a circuit 9. The circuit 9 is configured to determine the number of logic components Ci of the oscillator 3 traversed by a state transition between two edges of the clock signal clk. For this purpose, the circuit 9 receives a signal c-out representing the number of state transitions counted by the circuit 7. The circuit 9 further receives an output M[j] of the storage element Mj, i.e. the stored state of the output Oi of the logic component Ci. In other words, the circuit 9 receives a binary signal M[1, ..., K] on K bits, corresponding to the concatenation of the K outputs M[j] of the storage element Mj. For example, in Figure 1 Where K is equal to 5, the signal M[1, ..., 5] includes 5 bits, which are respectively equal to M[1], M[2], M[3], M[4] and M[5].

[0057] The circuit 9 is configured to determine the number of times the state transitions have completely passed through the chain of components Ci of the oscillator 3 based on the signal c-out and the number of state transitions represented by the signal c-out. For example, the signal c-out represents a first number n1 during the first of the two edges, and a second number n2 during the last of the two edges, indicating that there have been n1-n1-1 transitions passed at the level of the output O4 between the two edges. In other words, considering that, for example, components C5 and C4 are respectively the first and last components of the chain of components Ci, the transitions have run n2-n1-1 times through the chain of components C5, C1, C2, C3, C4 in the order C5, C1, C2, C3, C4.

[0058] Furthermore, the circuit 9 is configured to determine the position of the state transition in the chain of the oscillator 3 during an edge of the clock signal corresponding to the memory stored in the element Mj, based on the signal M[1, ..., 5] representing the state of the output Oi stored during this edge. Figure 1 In the embodiment, all elements Ci are inverters, and after the edge of signal clk causes storage in element Mj, if signal M[1, ..., 5] is equal to "10010", this means that at the time of storage, the input of component C3 is in the same state as its output O3 (for example, a low state), so that the transition or oscillation propagated through oscillator 3 is at the level of the input of component C3, or in other words, at the level of the output O2 of component C2.

[0059] More specifically, based on the signals c-out and M[1, ..., 5], the circuit 9 is able to determine the position of the transition during the first of the two edges of the signal clk, the number of full strokes of the transition between the two edges of the signal clk through the oscillator 3, and the position of the transition during the last of the two edges of the signal clk. The circuit 9 is further configured to determine, based on the above information, which components Ci have been traversed by the transition between the two edges of the signal clk, and how many times each of these components has been traversed by the transition between the two edges of the signal clk. In other words, the circuit 9 is able to determine the number of components traversed by the transition between the two edges of the signal clk.

[0060] According to an embodiment, the two edges of the clock signal clk each correspond to a storage into an element Mj. In this embodiment, the position of the transition during the first of the two edges is determined, for example, from the signal M[1, ..., K] and, more specifically, by the value of the signal M[1, ..., K] stored from the first edge. For example, in Figure 1 The situation in.

[0061] According to another embodiment, for example, Figure 4 As further described in detail in , the oscillator 3 is controlled by a control signal and is configured such that oscillations do not propagate in the oscillator 3 when the control signal is in a first state, and oscillations propagate in the oscillator 3 when the control signal is in a second state. In such an embodiment, switching the control signal from its first state to its second state is equivalent to causing a state transition at the output Oi of a given component Ci, which then propagates in the oscillator 3, causing oscillations of the output Oi. Thus, by providing the control signal during an edge of the signal clk to switch from the first state to the second state, the position of the transition during this first edge is known, even if this edge does not necessarily correspond to storage by the element Mj.

[0062] Figure 2 shows the implementation mode according to Figure 1 More specifically, Figure 2 The changes of signals clk, sync, M[1, ..., K] and c-out are shown. Figure 2 For example:

[0063] The number N of components Ci is equal to 5;

[0064] The number K of storage elements Mj is equal to 5;

[0065] All components Ci are inverters;

[0066] All components Mj are latches, configured to be transparent when the signal sync is in a high state, and to be latched when the signal sync is in a low state;

[0067] Circuit 7 is configured to count all state transitions at output O4 of component C4; and

[0068] The circuit 5 is configured to switch the state of the signal sync at each active edge (here a rising edge) of the signal clk.

[0069] At time t0 at the start of the timing diagram, signal clk is in the low state, signal sync is in the high state, signal M[1, ..., 5] follows output Oi due to the fact that latch Mj is transparent, and signal c-out indicates that 10 transitions have been counted on output O4.

[0070] At the next time t1, corresponding to the rising edge of the signal clk, the signal sync switches from its high state to its low state. The latch Mj then switches to the latched state, and the state of the output Oi at time t1 is stored, and the value or state of the signal M[1, ..., 5] from time t1 represents the stored state of the output Oi at time t1. In this example, starting from time t1, the signal M[1, ..., 5] has the value "01101", which indicates that at time t1, the transition propagated in the oscillator 3 is located at the level of the output O2 of the component C2. From time t1 to the next increment of the value of the signal c-out (time t2 after time t1 - the transition on the output O4), the transition passes through the components C3 and C4 in this order.

[0071] At time t1 , signal c-out indicates that 11 transitions have been counted. For example, the value of signal c-out at time t1 is stored by circuit 9 .

[0072] At time t3 after time t2, and corresponding to the next rising edge of signal clk, signal sync is switched to a high state, and latch Mj is then switched to a transparent state. The value of signal M[1, ..., 5] from time t3 then no longer represents the state of output Oi at time t1.

[0073] At the next time t4, corresponding to the next rising edge of signal clk, the signal is switched to its low state. Latch Mj is then switched to the latched state and the state of the output Oi at time t4 is stored, and the value or state of the signal M[1, ..., 5] from time t4 represents the stored state of the output Oi at time t4. In this example, from time t12, the signal M[1, ..., 5] has a value of "01001", which indicates that at time t4, the conversion propagated in the oscillator 3 is located at the level of the output O3 of component C3. Therefore, starting from the last increment of signal c-out (time t5 before time t4 - conversion on output O4), the conversion has passed through components C5, C1, C2 and C3 in the order of C5, C1, C2 and C3.

[0074] Furthermore, at time t4, signal c-out indicates that 19 transitions have been counted. For example, the value of signal c-out at time t4 is stored by circuit 9. Thus, starting from time t1, the transitions propagating in oscillator 3 have passed through the chain of components C5, C1, C2, C3 and C4 19-11-1=7 times in sequence.

[0075] Circuit 9 thus infers that, between times t1 and t4, the transition has passed through component C1 zero times between times t1 and t2, seven times between times t2 and t5, and once between times t5 and t4, for a total of eight times between times t1 and t4. Similarly, circuit 9 determines that, between times t1 and t4, the transition has passed through component C2 eight times, component C3 nine times, component C4 eight times, and component C5 eight times.

[0076] In this example, all components Ci are identical and between times t1 and t4, the transition has passed through 41 identical components Ci in series. For example, it can be inferred from this information that the average propagation delay of the transition in component Ci is equal to 2×T / 41, T being the duration of a cycle or period of the clock signal clk.

[0077] The above calculation is actually carried out by the circuit 9 only through the signal c-out and the values ​​at the times t1 and t4, and through the values ​​of the signal M[1, ..., 5] representing the state of the output Oi stored at the times t1 and t4.

[0078] According to another example, the input of circuit 7 is connected to the output M[j] of element Mj, the input of element Mj is connected to the output Oi, wherein circuit 7 counts state transitions. For example, the input of circuit 7 is connected to the output M[4]. In this case, reference Figure 2In the timing diagram of , the circuit 7 counts the state transitions on the output O4 only when the latch M4 is transparent, that is, for example, between the times t3 and t4. In addition, since the values ​​of the signals M[1, ..., 5] are taken from these corresponding times, the positions of the transitions in the oscillator 3 at the times t3 and t4 are known, which makes it possible to determine the number of components Ci traversed by the transitions between the times t3 and t4. The connection of the inputs of the circuit 7 to the outputs M[j] of the latches Mj makes the states of the signals M[1, ..., 5] and c-out stable between the same times, or in other words, the states of these signals are stored at the same time. This makes it possible to avoid that the circuit 7 has not yet counted the transitions when the signals M[1, ..., 5] are stored and indicate that the transitions are at the level of the output Oi where the circuit 7 counts the transitions. In practice, this can lead to errors with respect to the number of components Ci traversed by the transitions determined by the signals c-out and M[1, ..., 5].

[0079] Here, an example is described in which the oscillator 3 does not include a device capable of blocking or allowing the propagation of a transition or oscillation in the oscillator 3 under the control of a control signal. In another example, the oscillator 3 includes a device configured to prevent the propagation of an oscillation through one of the components Ci when the control signal is in a first state, and to allow the propagation of the oscillation through the component Ci when the control signal is in a second state. When the propagation of an oscillation through the component Ci is blocked, this means that the state transition that causes the oscillation is located at the input of the component Ci, and therefore its position is known.

[0080] An example where the element Mj is a latch has been described. Consider another example where the element Mj is a D flip-flop configured to replicate the state of its data input on its corresponding output during an active edge (e.g., rising edge) of a synchronization signal it receives, and to maintain the state of its corresponding output until the next active edge of the signal. For example, the signal clk can be considered to be a synchronization signal of the flip-flop Mj. Figure 2 Taking the timing diagram of as an example, the value or state of the signal M[1, ..., 5] between time t1 and t3, between time t3 and t4, and between time t4 and the next active edge of the signal clk represents the state of the output Oi at the corresponding time t1, t3 and t4. Therefore, based on the value of the signal M[1, ..., 5] and the signal c-out at time t1, t3 and t4, the circuit 9 can determine the number of components Ci passed through by the state transition between time t1 and t3, between time t3 and t4, and / or between time t1 and t4.

[0081] More generally, depending on the type of storage elements Mj (flip-flops or latches), and on the synchronization signals delivered to these elements by the circuit 5, the device 1, and more specifically its circuit 9, is configured to determine how many components Ci are traversed by transitions between two consecutive active edges of the signal clk and / or between two non-consecutive active edges of the signal clk (i.e. two active edges separated from each other by at least one other active edge).

[0082] Although this is not shown in the figure, it does not have Figure 2 In the described example, it is not detailed, but the circuit 9 may include a storage circuit, for example, a register, ordered by the signal clk or the signal sync, and configured to store the state of the signal M[1, ..., 5] and the state of the signal c-out. Based on the functional indication given above, it is within the capabilities of a person skilled in the art to provide such a storage device or circuit in the circuit 9 and to implement the circuit 9.

[0083] Based on the number of elements Ci traversed by a transition between two edges of the signal clk, i.e., the number of times each element Ci is traversed by a transition between two edges of the signal clk, information about the digital circuit being monitored can be determined. For example, when all components Ci are identical, the average propagation time of the transition between two edges through the component Ci can be determined. The average delay is then used, for example, to extrapolate the propagation time of the signal in the combinatorial paths of the monitored circuit to verify whether the propagation time in each combinatorial path is effectively shorter than or equal to a predetermined duration associated with the path minus a time margin t hd +t su , i.e., verifying whether the monitored circuit is operating as expected. If not, compensation can be implemented to prevent malfunction of the monitored circuit.

[0084] Instead of using the device 1, it is also possible to envisage using a device comprising only a ring oscillator, ie a monitoring device which does not include the storage element Mj. The frequency of the oscillator will then indicate the average propagation time in the components forming the oscillator chain.

[0085] However, such a device is not sensitive to changes in the signal clk. Therefore, if the period T of the signal clk decreases relative to a nominal value defined, for example, in the circuit design, this may not be detected by such a device, although such a decrease in the period T of the signal clk may cause a malfunction of the monitored digital circuit.

[0086] In addition to using the device 1, it is also possible to design a monitoring device using what is currently called a tunable replica circuit or TRC. Such a device comprises a replica of the combinatorial path of the monitored circuit, which replica can be programmable. Such a device further comprises a time-to-digital converter or TDC synchronized with the signal clk. In such a device, state transitions synchronized with the active edge of the signal clk are delivered at the input of the replica of the combinatorial circuit, and the TDC converter delivers a digital signal representing the propagation time of the transition in the replica of the combinatorial path at the next active edge of the signal clk.

[0087] However, a TRC type monitoring device only operates if the propagation time of the transitions in the replicated combined path is within the range of a minimum propagation time and a maximum propagation time determined by the TDC converter.

[0088] Furthermore, TRC-type monitoring devices typically include circuitry that introduces a propagation delay between the output of the replica-combinatorial path and the input of the TDC converter so that, under nominal manufacturing and operating conditions, the propagation time of a transition in the replica-combinatorial path is substantially in the middle of a range defined by the maximum and minimum propagation times that can be measured by the TDC converter. Since variations in the propagation delay in the replica-combinatorial path and variations in the propagation delay in the delay circuit are typically different, this can lead to measurement errors.

[0089] The disadvantages of the two monitoring devices mentioned above (ring oscillator and TRC type device) are not present in device 1.

[0090] Figure 3 A further embodiment of a monitoring device 1 is shown very schematically. More specifically, Figure 3 Shows the combination Figure 1 and Figure 2 The specific embodiments of the general embodiment of the device 1 described herein are described in detail only. Figure 1 Device 1 and Figure 3 The difference between the devices 1.

[0091] exist Figure 3 In an embodiment of the invention, the oscillator 3 comprises means, in this example a component C1, configured to prevent oscillations in the oscillator 3 when the control signal is in a first state and to allow said oscillations when the control signal is in a second state. The control signal is obtained from the signal clk so that the control signal is in the second state between two edges of the signal clk between which the device 1 determines how many elements Ci have been traversed by the transition. Preferably, the control signal is delivered by the circuit 5.

[0092] In this example, the control signal is the signal sync, the component C1 is a NOR gate, and the other components Ci are inverters. Thus, the low state of the signal sync blocks the transmission of the transition between the input and output of the component C1, and the high state of the signal sync allows such transmission.

[0093] Preferably, if Figure 3 As shown in , when the oscillator 3 comprises a component C1 capable of interrupting or allowing the propagation of transitions in the oscillator 3 , the circuit 7 is configured to count the transitions at the output O1 of this component C1 . Figure 3 In the example of FIG. 7 , the input of circuit 7 is connected to the output M[1] of element M1.

[0094] exist Figure 3 In the example of , element Mj is a latch, and an embodiment of circuit 7 is shown. In this embodiment, circuit 7 includes a counter C that transmits a signal C-out, and each time the input of counter C receives a rising edge of signal x-out, the number of transitions counted by counter C increases by one unit. Circuit 7 further includes a component or logic gate 11 configured to transmit signal x-out. In this example, if latch Mj is transparent, signal x-out has a rising edge each time output O1 switches from a low state to a high state and each time the output switches from a high state to a low state. In this example, element 11 is an exclusive OR gate having one of its inputs connected to output M[1] and the other input connected to output M[j] of another element Mj, in this example output M[3] of element M3.

[0095] For example, where components C2, C3, C4 and C5 are not all inverters, it is within the capabilities of those skilled in the art to provide connections for component 11 other than those described herein as examples and / or where component 11 is not an XOR gate.

[0096] Figure 3 An embodiment of a circuit 5 is shown. The circuit 5 comprises a flip-flop M synchronized by the rising edge of the signal clk, having a data input receiving the signal mes and an output delivering the signal sync. When the signal sync is in a high (respectively, low) state, the signal mes can select or determine the number of cycles of the signal clk. This enables the selection of two active edges of the signal clk between which the device 1 determines the number of components Ci traversed by the transition.

[0097] It is within the capabilities of those skilled in the art to provide other methods of implementing the circuit 5. For example, in the case where the state of the signal sync is switched at each rising edge of the signal clk, the circuit 5 can be implemented with a frequency divider configured to pass the signal sync at a frequency twice lower than the frequency of the signal clk.

[0098] Figure 4 shows the implementation mode according to Figure 3 More specifically, Figure 4 The changes of signals mes, clk, sync, M[1, ..., 5] and c-out are shown. Figure 4 For example:

[0099] The number N of components Ci is equal to 5;

[0100] The number K of storage elements Mj is equal to 5;

[0101] Component C1 is a NOR gate as described above, and all other components Ci are inverters;

[0102] All components Mj are latches, configured to be transparent when the signal sync is in the high state, and to be latched when the signal sync is in the low state;

[0103] Circuit 7 Figure 3 are implemented and connected as shown; and

[0104] The circuit 5 is configured to switch the state of the signal sync at each rising edge of the signal clk.

[0105] At time t10 at the start of the timing diagram, signal mes is in a high state, signal clk is in a low state, signal sync is in a low state, latch Mj is in a locked state, and signal c-out is in a storage state, in this example, signal c-out indicating that 14 conversions have been counted. In addition, due to the fact that signal sync is in a low state, output O1 is necessarily in a high state. As a result, outputs O2, O3, O4 and O5 are in low, high, low and high states, respectively, signal x-out is in a low state, and the propagation of oscillations through oscillator 3 is blocked at the input level of component C1.

[0106] At the next time t11 corresponding to the next rising edge of the signal clk, due to the fact that the signal mes is in the high state, the signal sync switches to the high state and the latch switches to the transparent state. Switching the signal sync to the high state further causes the output O1 to be switched to the low state, and the oscillator 3 starts to oscillate. This switching of the output O1 to the low state is sent to the output M[1] of the latch M1, while the high state of the output O3 is sent to the output M[3] of the latch M3. As a result, the signal x-out switches to the high state. The signal c-out, which has a value of 14 at the time t11, then increases by one unit due to the rising edge of the signal x-out shortly after the time t11.

[0107] At the next time t13 corresponding to the next rising edge of the signal clk, due to the fact that the signal mes was switched to the low state between the time t11 and t12 and then maintained in the low state until the time t12, the signal sync is switched to the low state and the Mj switch is latched to the latched state. The state of the output Oi at the time t12 is then stored, and the value of the signal M[1, ..., 5] from the time t12 represents the stored state of the output Oi at the time t12. In this example, from the time t12, the signal M[1, ..., 5] has the value "01001", which indicates that at the time t12, the transition propagated in the oscillator 3 is located at the level of the output O3 of the component C3. In addition, switching the latch Mj to the latched state causes the value of the signal c-out at the time t12 to also be stored at the value 19, where the value 19 indicates that between the time t11 and t12, the circuit 7 counted 19-14=5 state transitions on the output O1. Furthermore, switching the signal sync to the low state at time t1 causes the oscillation in the oscillator 3 to stop.

[0108] Thus, the values ​​of the signals c-out at times t11 and t12 are known, the state of the output Oi at time t11 is known due to the low state of the signal sync at time t11, which indicates that the state transition propagating in the oscillator 3 is blocked at the output O5 of the component C5, and the state of the output Oi at time t12 is known via the stored value of the signal M[1, ..., 5] from time t12, which indicates that the state transition propagating in the oscillator 3 is located at the output O3 of the component C3 at time t12. The circuit 9 is then able to determine that between times t11 and t12, the state transition first passed through the component C1, then passed through the chain of components C2, C3, C4, C5 and C1 19-14-1=4 times, in the order of components C2, C3, C4, C5 and C1, and finally passed through components C2 and C3. In other words, between times t11 and t12, the state transition propagating through the oscillator 3 has passed through 1+4×5+2=23 components Ci. More specifically, the conversion passes through 5th order component C1, 5th order component C2, 5th order component C3, 4th order component C4, and 4th order component C5.

[0109] In this embodiment, the oscillator 3 comprises a logic component C1 making it possible to interrupt or allow the propagation of a transition in the oscillator 3, by means of the signal M[1, ..., 5], it being useless to store the state of the output Oi at the time t11. In fact, the position of the transition at the time t11 is imposed by the component C1 and the signal sync.

[0110] According to an embodiment, before each switching of the signal sync to the state in which the latch Mj is transparent, the counter C of the circuit 7 is reset. For example, such a reset of the counter C is controlled by the switching of the signal mes from a low state to a high state occurring during the period of the signal clk before the time t11. In this case, the storage of the signal c-out by the circuit 9 at the time t11 is useless.

[0111] Still according to this embodiment, circuit 9 can advantageously be implemented by simple logic and arithmetic units not including a storage function, and by a combinatorial circuit configured to transform signal M[1, ..., 5] into a value n3 corresponding to the number of components Ci traversed by the transformation resulting from the last increment of signal c-out and the transformation of time t12 when signal M[1, ..., 5] is stored. Figure 4 Taking the example of , and considering the case where the counter C is initialized with the value n1=0 before time t11, the signal c-out will be at the value n2=5 at time t12, and the value n3 will be equal to 2. The circuit 9 will then determine that the number of components Ci passed through between times t11 and t12 is equal to N*(n2-1)+n3+1=23, the increment of 1 corresponding to the passing of a transition in component C1 after time t11.

[0112] Figure 5 A further embodiment of a monitoring device 1 is shown very schematically. More specifically, Figure 5 Shows the combination Figure 1 and Figure 2 The specific embodiments of the general embodiment of the device 1 described herein are described in detail only. Figure 1 Device 1 and Figure 5 The difference between the devices 1.

[0113] exist Figure 5 In an embodiment of the invention, in addition to the component of storage elements Mj, the device 1 comprises another component of storage elements M'q, q being an integer in the range of 1 to K, K' being less than or equal to N, preferably equal to K. Each storage element M'q is configured to synchronously store a high or low state of its data input with the edge or level of a synchronization signal sync' obtained from the signal clk, the stored state being available at the output M'[q] of the storage element and remaining at a stable value throughout the storage period. Preferably, the storage elements M'q are identical to each other and to the element Mj.

[0114] The storage elements Mj and M'q here are latches. In addition, the circuit 5 transmits the synchronization signal sync to the element Mj and transmits the synchronization signal sync' to the element M'q. The signals sync and sync' make the latch M'q latched when the latch Mj is transparent, and vice versa, when the latch Mj is latched, the latch M'q is transparent.

[0115] Preferably, there are as many elements Mj as elements M'q, and for each element Mj associated with a component Ci, a corresponding element M'q is associated with the component Ci. In other words, the two elements Mj and M'q associated with the same component Ci are configured to synchronously store the output state Oi of the component Ci using the corresponding signals sync and sync'.

[0116] The circuit 9 receives the output signal M[j] of the latch Mj and the output signal M'[q] of the latch Mq. For example, the signals M'[q], M[j] and c-out enable the circuit 9 to determine at each cycle of the signal clk how many components Ci are switched through during that cycle. In other words, this makes it possible to avoid the presence of a cycle between two active edges of the signal clk, in which the device does not determine the number of components Ci that are crossed by the transition between the two active edges.

[0117] Figure 5 An embodiment of a circuit 5 is shown. In this embodiment, the circuit 5 comprises a flip-flop M synchronized with the rising edge of the signal clk. The data input of the flip-flop M receives the signal mes, and the output of the flip-flop M delivers the signal sync. Furthermore, the signal sync' here corresponds to the logical complement of the signal sync, i.e., when the signal sync is in the high state, the signal sync' is in the low state, and vice versa. In this example, the signal sync' is obtained at the output of an inverter 12, which has its input receiving the signal sync. In another example, the flip-flop M comprises two outputs that deliver the sync and sync' signals, respectively.

[0118] Those skilled in the art can provide other methods of implementing the circuit 5 .

[0119] In this embodiment, the circuit 7 is configured to count the transitions on the output O1 of the element C1. More specifically, in this example, the circuit 7 has an input connected to the output of the latch M1 so as to be able to count the state transitions on the output O1 when the latch M1 is in the transparent state, and the circuit 7 has another input connected to the output of the latch M'1 so as to be able to count the state transitions on the output O1 when the latch M'1 is in the transparent state. In another example not shown, the circuit 7 is directly connected to the output O1.

[0120] Figure 5 An embodiment of a circuit 7 is shown. The circuit 7 comprises a counter C delivering a signal c-out, the number of transitions counted by the counter C increasing by one unit each time the input of the counter C receives a rising edge of the signal mux. The circuit 7 further comprises a component or logic gate 13 configured to deliver a signal x1 with a rising edge each time the output O1 switches from a low state to a high state and each time the output switches from a high state to a low state (if the latch Mj is transparent). In this example, the component 13 is an XOR gate having its input connected to the output M[1] and having its other input connected to the output M[j] of another element Mj, in this example the output M[3] of the element M3. Similarly, the circuit 7 further comprises a component or logic gate 15 configured to deliver a signal x2 with a rising edge each time the output O1 switches from a low state to a high state and each time the output switches from a high state to a low state (if the latch M'q is transparent). In this example, component 15 is an XOR gate having its input connected to output M'[1] and having its other input connected to output M'[q] of another element M'q, in this example, output M'[q] of element M'3. Circuit 7 comprises component 17 configured such that signal mux is signal x1 when latch Mj is transparent and signal mux is signal x2 when latch M'q is transparent. Component 17 is, for example, a multiplexer comprising two inputs receiving respective signals x1 and x2, a control input receiving a signal sync or sync' and an output passing signal mux.

[0121] A person skilled in the art will be able to provide other ways of implementing component 7 and / or other ways of coupling component 7 to one or more outputs Oi.

[0122] Figure 6 shows a diagram according to the implementation mode Figure 5 More specifically, Figure 6 The changes of signals clk, mes, sync, M[1, ..., 5], sync', M'[1, ..., 5] and c-out are shown, and the signal M'[1, ..., 5] corresponds to the concatenation of the outputs in the order of M'[1], M'[2], M'[3], M'[4] and M'[5]. Figure 6 The example considered is circuits 5 and 7 as Figure 5 As shown and connected, the circuit 5 delivers a signal sync that switches at each active edge of the signal clk (in this example at each rising edge).

[0123] At time t20 at the beginning of the timing diagram, the signals clk, mes and sync are in the low state and the signal sync' is in the high state. The latches Mj and M'q are thus latched and transparent, respectively. Figure 6 Not shown in , but the counter C then receives the signal x2.

[0124] Before the next time t21 corresponding to the next rising edge of signal clk, signal mes is switched to a high state. Therefore, at time t21, signals sync and sync' are switched to a high state and a low state, respectively, and latches Mj and M'q are switched to a transparent state and a latched state, respectively. The state of output Oi at time t21 is stored, and the value or state of signal M'[1, ..., 5] from time t21 represents the stored state of output Oi at time t21. In this example, from time t21, signal M'[1, ..., 5] has a value of "00101", which indicates that at time t21, the transition propagated in oscillator 3 is located at the level of output O5 of component C5.

[0125] Furthermore, at time t21, signal c-out is at value 32, and although this Figure 6 It is not shown in FIG, but the counter c receives the signal x1 from time t21.

[0126] Before the next time t22 corresponding to the next rising edge of signal clk, signal mes is switched to a low state. Therefore, at time t22, signals sync and sync' are switched to a low state and a high state respectively, and latches Mj and M'q are switched to a latched state and a transparent state respectively. The state of the output Oi at time t22 is stored, and the value or state of the signal M[1, ..., 5] from time t22 represents the stored state of the output Oi at time t22. In this example, from time t22, signal M[1, ..., 5] has a value "01001", which indicates that at time t22, the conversion propagated in oscillator 3 is located at the level of the output O3 of component C3.

[0127] Furthermore, at time t22, signal c-out is at value 37, and although this Figure 6 Not shown, but counter c receives signal x2 from time t22.

[0128] Before the next time t23 corresponding to the next rising edge of signal clk, signal mes is switched to a high state. Therefore, at time t23, signals sync and sync' are switched to a high state and a low state, respectively, and latches Mj and M'q are switched to a transparent state and a latched state, respectively. The state of output Oi at time t23 is stored, and the value or state of signal M'[1, ..., 5] from time t23 represents the stored state of output Oi at time t23. In this example, from time t23, signal M'[1, ..., 5] has a value of "11010", which indicates that at time t23, the conversion propagated in oscillator 3 is located at the level of output O5 of component C5.

[0129] Furthermore, at time t23, signal c-out is at value 42, and although this Figure 6 It is not shown in FIG. 1 , but the counter c receives the signal x1 from time t23 .

[0130] Before the next time t24 corresponding to the next rising edge of signal clk, signal mes is switched to a low state. Therefore, at time t24, signals sync and sync' are switched to a low state and a high state respectively, and latches Mj and M'q are switched to a latched state and a transparent state respectively. The state of the output Oi at time t24 is stored, and the value or state of the signal M[1, ..., 5] from time t24 represents the stored state of the output Oi at time t24. In this example, from time t24, signal M[1, ..., 5] has a value "01011", which indicates that at time t23, the conversion propagated in oscillator 3 is located at the level of the output O4 of component C4.

[0131] Furthermore, at time t24, signal c-out is at value 48, and although this Figure 6 Not shown in FIG, but counter c receives signal x2 from time t24.

[0132] According to an embodiment, based on the value of the signal c-out and the position of the transitions in the oscillator 3 at each of the times t21, t22, t23 and t24, the circuit 9 is able to determine (similarly to the previous description of Figure 2 and Figure 4 As described), the number of components Ci traversed by the transitions between time t21 and t22, between time t22 and t23, and between time t23 and t24, that is, the number of components Ci traversed at each cycle of the signal clk.

[0133] For example, this enables to obtain for each period of the signal clk an average value of the propagation delays in the components Ci, which average value is then sensitive to fast changes in operating conditions, ie for example changes in the supply voltage, the duration of which is shorter than a period of the signal clk.

[0134] According to another embodiment, based on the same value of the signal c-out and the position of the transition in the oscillator 3 at each of the times t21, t22, t23 and t24, the circuit 9 is able to determine the number of components Ci traversed by the transition between two edges of the signal clk, the edge being selected between the edges occurring at the times t21, t22, t23 and t24.

[0135] For example, this enables an average value of the propagation delay in the component Ci to be obtained over a plurality of periods of the signal clk, which average value is less sensitive to rapid changes in operating conditions and thus more sensitive to slow changes in operating conditions (eg due to aging).

[0136] The above two embodiments can be used in combination.

[0137] The embodiment in which each component Ci is associated with at least one storage element has been described above in conjunction with Figures 1 to 6 In the embodiment of the invention, the at least one storage element is configured to store the state of the output Oi of the component Ci during the active edge of the signal clk. In an alternative embodiment, only certain components Ci are associated with such storage elements. In this variant, the position of the transition in the oscillator 3 is then determined less accurately, whereby the determination of the number of components Ci traversed by the transition between two edges of the signal clk is less accurate.

[0138] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and that other variations will readily occur to those skilled in the art. In particular, it is within the capabilities of those skilled in the art to provide other implementations of the ring oscillator 3, circuit 5, circuit 7, and / or circuit 9, provided that:

[0139] The device 1 comprises an assembly of synchronous memory elements configured to store the state of at least some of the outputs of the components Ci forming the oscillator 3;

[0140] The circuit 5 is configured to synchronize storage in such a storage element with the edges of the clock signal clk;

[0141] The circuit 7 is configured to count the state transitions occurring at the output Oi of one of the components Ci; and

[0142] The circuit 9 is configured to determine the number of components Ci traversed by a state transition propagating between two edges of the clock signal in the oscillator 3 based on the counted number of state transitions delivered by the circuit 7 and the stored state of the output delivered by the storage element. For example, a person skilled in the art is able to provide the ring oscillator to include a (possibly programmable) copy of the combinatorial path of the monitored circuit and / or one or more programmable logic components.

[0143] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, within the capabilities of a person skilled in the art, circuit 9 can be implemented by providing a storage circuit (such as a register) to store synchronously with the signal clk, the signal sync and / or the signal sync', the signal M[1, ..., K], M[1, ..., K'] and / or c-out. For example, referring to Figure 6 As an example, it is within the capabilities of a technician in this field to provide a storage device configured to store the signal c-out at each rising edge of the signal clk (time t21, t23, t24, etc.).

[0144] Such changes, modifications and improvements are intended to be part of the present invention and are intended to be within the spirit and scope of the present invention. Therefore, the above description is intended to be exemplary only and is not intended to be limiting. The present invention is limited only to the contents defined in the following claims and their equivalents.

Claims

1. An electronic device, comprising: A ring oscillator including a chain of logic components; a first assembly of storage elements, wherein each storage element is associated with a different logic component of the chain and is configured to store a state of an output of the logic component associated with the storage element; a first circuit configured to count a number of state transitions of an output of a given logic component of the chain; a second circuit configured to synchronize each of the stores of the state using a clock signal; as well as a third circuit configured to determine a number of the logic components of the chain traversed by a state transition between two edges of the clock signal, wherein the determined number of logic components is based on the counted number of the state transitions and a stored state of the output from the first component; wherein one of the logic components of the chain is configured to prevent propagation of oscillations in the oscillator in response to a control signal in a first state and to allow propagation of the oscillations in response to the control signal in a second state; and The second circuit is configured to generate the control signal and pass the control signal in the second state between the two edges of the clock signal. 2 . The electronic device according to claim 1 , wherein the one of the logic components of the chain is the given logic component. 3 . The electronic device of claim 1 , wherein the third circuit is further configured to determine a number of times the state transition between the two edges completely traverses the chain, wherein the determination of the number of times is based on the counted number of state transitions.

4. The electronic device of claim 1 , wherein the third circuit is further configured to determine a position of the state transition in the chain during an edge of the clock signal, wherein the position is determined based on a state of the output stored during the edge. 5 . The electronic device of claim 4 , wherein the third circuit is further configured to determine a number of times the state transition between the two edges completely traverses the chain, wherein the determination of the number of times is based on the counted number of state transitions.

6. An electronic device according to claim 5, wherein the third circuit is further configured to determine the number of logic components traversed by the state transition between the two edges of the clock signal based on the number of times the transition between the two edges passes through the entire oscillator and the position of the transition in the chain during the last of the two edges.

7. An electronic device according to claim 6, wherein the third circuit is configured to determine the number of logic components traversed by the state transition between the two edges of the clock signal further based on the position of the transition in the chain during the first of the two edges.

8. The electronic device of claim 1, wherein each logic component of the chain is associated with a storage element of the first component.

9. The electronic device of claim 1, wherein the storage element is a latch.

10. The electronic device of claim 9, wherein each of the latches has an input coupled to receive the output of the logic component associated with the latch.

11. The electronic device of claim 10, wherein the first circuit comprises an input connected to an output of the latch, the input of the latch being coupled to the output of the given logic component.

12. The electronic device according to claim 1 further comprises a second component of storage elements, wherein each storage element of the second component is associated with a different logic component of the chain and is configured to store the state of the output of the logic component, and the first component and the second component are configured so that each logic component associated with a storage element of the first component is further associated with a storage element of the second component.

13. An electronic device according to claim 12, wherein the second circuit is configured so that when the storage element of the second component is in a latched state, the storage element of the first component is in a transparent state, and so that when the storage element of the second component is in a transparent state, the storage element of the first component is in a latched state, and the second circuit is configured so that the storage element switches between the latched state and the transparent state when each cycle of the continuous cycle of the clock signal changes.

14. The electronic device of claim 1, wherein the first circuit is configured to count transitions from a first state to a second state and from the second state to the first state.

15. The electronic device of claim 1, wherein the second circuit is configured to synchronize each storage with an active edge of the clock signal.

16. An electronic device, comprising: A ring oscillator including a chain of logic components; a first assembly of first storage elements, wherein each first storage element is associated with a different logic component of the chain and is configured to store a state of an output of the logic component associated with the storage element; a second assembly of second storage elements, wherein each second storage element is associated with a different logic component of the chain and is configured to store a state of an output of the logic component, the first assembly and the second assembly being configured such that each logic component associated with one first storage element of the first assembly is further associated with one second storage element of the second assembly; a first circuit configured to count a number of state transitions of a logical combination of outputs of at least two logic components of the chain; a second circuit configured to synchronize each of the stores of the state using a clock signal; as well as A third circuit is configured to determine the number of logic components of the chain traversed by state transitions between two edges of the clock signal, wherein the determined number of logic components is based on the counted number of state transitions and the stored states of the outputs in the first component and the second component. 17 . The electronic device of claim 16 , wherein the third circuit is further configured to determine a number of times the state transition between the two edges completely traverses the chain, wherein the determination of the number of times is based on the counted number of state transitions.

18. The electronic device of claim 16, wherein the third circuit is further configured to determine a position of the state transition in the chain during an edge of the clock signal, wherein the position is determined based on a state of the output stored during the edge.

19. The electronic device of claim 18, wherein the third circuit is further configured to determine a number of times the state transition between the two edges completely traverses the chain, wherein the determination of the number of times is based on the number of counted state transitions.

20. An electronic device according to claim 19, wherein the third circuit is further configured to determine the number of logic components traversed by the state transition between the two edges of the clock signal based on the number of times the transition between the two edges passes through the entire oscillator and the position of the transition in the chain during the last of the two edges.

21. An electronic device according to claim 20, wherein the third circuit is configured to determine the number of the logic components traversed by the state transition between the two edges of the clock signal further based on the position of the transition in the chain during the first of the two edges.

22. The electronic device of claim 16, wherein each logic component of the chain is associated with a storage element of the first component.

23. The electronic device of claim 16, wherein the storage element is a latch.

24. The electronic device of claim 23, wherein each of the latches has an input coupled to receive the output of the logic component associated with the latch.

25. The electronic device of claim 24, wherein the first circuit comprises an input connected to an output of the latch, the input of the latch being coupled to the output of a given logic component.

26. An electronic device according to claim 16, wherein the second circuit is configured so that when the storage element of the second component is in a latched state, the storage element of the first component is in a transparent state, and so that when the storage element of the second component is in a transparent state, the storage element of the first component is in a latched state, and the second circuit is configured so that the storage element switches between the latched state and the transparent state when each cycle of the continuous cycle of the clock signal changes.

27. The electronic device of claim 16, wherein the first circuit is configured to count transitions from a first state to a second state and from the second state to the first state.

28. The electronic device of claim 16, wherein the second circuit is configured to synchronize each storage with an active edge of the clock signal.

29. An electronic device according to claim 16, wherein one of the logic components of the chain is configured to prevent the propagation of oscillations in the oscillator in response to a control signal in a first state, and to allow the propagation of the oscillations in response to the control signal in a second state; and wherein the second circuit is configured to generate the control signal and pass the control signal in the second state between the two edges.

30. The electronic device of claim 29, wherein the one of the logic components of the chain is a given logic component.

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