A fan-out packaging method and a fan-out packaging device

Abstract

The present application discloses a fan-out packaging method and a fan-out packaging device, the fan-out packaging method comprising: providing a chip, the chip comprising a first surface and a second surface disposed opposite to each other, wherein the first surface comprises a functional area and a non-functional area, the non-functional area is disposed around the periphery of the functional area, and the non-functional area is provided with an annular retaining wall, the retaining wall is disposed around the periphery of the functional area; the first surface of the chip is fixed on a carrier having an adhesive layer, and the retaining wall is embedded in the adhesive layer; a plastic sealing layer is formed on one side of the chip provided with the adhesive layer, the plastic sealing layer covers the second surface and side of the chip; and the adhesive layer and the carrier are removed. In the above manner, the present application can reduce the risk of glue overflow in the chip and effectively improve the yield of the chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging method and a fan-out packaging device. Background Art

[0002] With the development trend of ultra-large-scale integrated circuits, the market demand for small, high-density, and thin-packaged microelectronic products is also increasing. Among them, fan-out packaging technology has quickly become a hot spot in semiconductor advanced packaging technology with its advantages of miniaturization, low cost, and high density.

[0003] Fan-out packaging usually includes a process of sealing and molding to ensure the sealing performance of the chip. The existing sealing and molding process is to fix the chip body with the die attached on the carrier glue layer, and then inject the glue to form a plastic sealing layer to seal the chip.

[0004] The inventors of the present application have discovered during long-term research that existing fan-out packaging devices have the risk of mold overflow during the production process of the chip plastic sealing layer. Since the chip and the carrier glue layer cannot fit tightly, glue overflow is likely to occur, and the grains in the chip are contaminated by the colloid, resulting in a decrease in chip yield and affecting solderability and electrical quality. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a fan-out packaging method and a fan-out packaging device, which can reduce the risk of glue overflow in chip grains and effectively improve the chip yield.

[0006] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a fan-out packaging method, comprising: providing a chip, the chip comprising a first surface and a second surface arranged back to back, wherein the first surface comprises a functional area and a non-functional area, the non-functional area is arranged around the periphery of the functional area, and the non-functional area is provided with an annular retaining wall, and the retaining wall is arranged around the periphery of the functional area; the first surface of the chip is fixed on a carrier provided with a glue layer, and the retaining wall is embedded in the glue layer; a plastic sealing layer is formed on one side of the glue layer where the chip is provided, and the plastic sealing layer covers the second surface and side surfaces of the chip; and the glue layer and the carrier are removed.

[0007] Wherein, the retaining wall is made of metal, and the step of providing the chip includes: forming the retaining wall by electroplating on the non-functional area.

[0008] Wherein, the step of forming the retaining wall by electroplating in the non-functional area includes: forming a first annular sub-retaining wall in the non-functional area; forming a second annular sub-retaining wall on the side of the first sub-retaining wall away from the first surface, wherein the first sub-retaining wall and the second sub-retaining wall form the retaining wall, and the width of the second sub-retaining wall is smaller than the width of the first sub-retaining wall.

[0009] Wherein, after the step of removing the adhesive layer and the carrier plate, the method further includes: removing the retaining wall.

[0010] The step of removing the retaining wall comprises: covering the first surface of the chip with an insulating layer, with the retaining wall exposed from the insulating layer; etching away the retaining wall; and forming a first opening at a pad position of the insulating layer corresponding to the functional area.

[0011] Among them, after the step of removing the glue layer and the carrier, it also includes: forming a first dielectric layer on the first surface, the first dielectric layer covering the retaining wall; forming a second opening at the position of the first dielectric layer corresponding to the pad of the functional area; forming a rewiring layer on the first dielectric layer, the rewiring layer filling the second opening to be electrically connected to the pad.

[0012] Among them, after the step of forming a rewiring layer on the first dielectric layer and the rewiring layer filling the second opening to be electrically connected to the pad, it also includes: forming a second dielectric layer on the side of the rewiring layer away from the chip, and the second dielectric layer is provided with a third opening on the side corresponding to the rewiring layer; planting a solder ball in the third opening, and the solder ball is electrically connected to the metal rewiring layer.

[0013] To solve the above technical problems, another technical solution adopted in the present application is: to provide a fan-out packaging device, comprising: a chip, comprising a first surface and a second surface, wherein the first surface comprises a functional area and a non-functional area, and the non-functional area is arranged around the periphery of the functional area; a retaining wall, which is annular and arranged around the periphery of the functional area; a plastic encapsulation layer, covering the second surface and the side surface of the chip, and one side surface of the plastic encapsulation layer is flush with the first surface, and the retaining wall is exposed from the plastic encapsulation layer.

[0014] Wherein, the height of the retaining wall is 10-50 microns.

[0015] Among them, the fan-out packaging device also includes: a solder pad, which is located on the first surface of the chip; a first dielectric layer, which is located on the side of the plastic packaging layer close to the first surface, and a second opening is arranged corresponding to the position of the solder pad; a rewiring layer, which is located on the side of the first dielectric layer away from the chip, and is electrically connected to the solder pad; a second dielectric layer, which is located on the side of the rewiring layer away from the chip, and a third opening is arranged corresponding to the side of the rewiring layer; a solder ball, which is located in the third opening and is electrically connected to the rewiring layer.

[0016] Different from the prior art, the beneficial effects of the present application are: the fan-out packaging method provided by the present application includes, before the step of forming the plastic sealing layer, pre-setting an annular retaining wall around the non-functional area of ​​the first surface of the chip, and using the annular retaining wall higher than the first surface of the chip to block the colloid that overflows from the plastic sealing layer during the plastic sealing process, thereby reducing the risk of contamination of grains in the functional area of ​​the chip, effectively improving the yield of the chip, ensuring the subsequent weldability of the chip and the quality of the overall product, and significantly improving the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 It is a flow chart of an implementation method of a fan-out packaging method of the present application;

[0019] Figure 2 yes Figure 1 Steps S101 to S104 correspond to a structural schematic diagram of an implementation method;

[0020] Figure 3 yes Figure 1 A schematic flow chart of an implementation method of step S101;

[0021] Figure 4 yes Figure 3 Steps S201 and S202 correspond to a schematic structural diagram of an implementation method;

[0022] Figure 5 yes Figure 1 A schematic diagram of a flow chart of an implementation method after step S104;

[0023] Figure 6 yes Figure 1 A schematic diagram of a flow chart of another implementation method after step S104;

[0024] Figure 7 It is a structural schematic diagram of an implementation scheme of a fan-out packaging device of the present application;

[0025] Figure 8 yes Figure 6 A flowchart of an implementation method after step S403 is shown in FIG. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] See also Figure 1 and Figure 2 , Figure 1 is a flow chart of an implementation method of a fan-out packaging method of the present application, Figure 2 yes Figure 1 Steps S101 to S104 correspond to a schematic diagram of a structure of an embodiment. The packaging method includes:

[0028] S101: Provide a chip 10, the chip 10 includes a first surface 101 and a second surface 102 arranged opposite to each other, wherein the first surface 101 includes a functional area 1011 and a non-functional area 1012, the non-functional area 1012 is arranged around the periphery of the functional area 1011, and the non-functional area 1012 is provided with an annular retaining wall 20, and the retaining wall 20 is arranged around the periphery of the functional area 1011.

[0029] For details, please refer to Figure 2 (a) and Figure 2 (b), where Figure 2 (a) is a front view corresponding to the structure of chip 10, Figure 2 (b) is a top view of the chip 10 structure. The chip 10 is a silicon substrate, a germanium substrate, etc., and its first surface 101 is the front side of the chip 10, and the second surface 102 is the back side of the chip 10. A pad 103 is formed on the front side of the chip 10, and the pad 103 is arranged on one side of the first surface 101 and is located inside the functional area 1011. In this embodiment, Figure 2 In (b), in the top view projection direction, the functional area 1011 corresponds to a circle, and the non-functional area 1012 corresponds to other areas of the first surface 101 excluding the functional area 1011. Of course, in other embodiments, the top view projection shape of the functional area 1011 can also be a rectangle, square, etc., as long as the function of the chip 10 can be realized, and no specific limitation is made here.

[0030] In one embodiment, the material of the retaining wall 20 is metal, and the step S101 further comprises electroplating the retaining wall 20 in the non-functional area 1012. Figure 2 (b), a closed retaining wall 20 structure is formed in the non-functional area 1012 by using the RDL (rewiring) process, and the retaining wall 20 formed in the surrounding form a rectangle in the top view projection direction, and the four sides of the rectangle are the retaining wall 20. Of course, in other embodiments, the shape formed by the retaining wall 20 in the top view projection direction can also be a circle, an ellipse, or other irregular shapes, as long as the retaining wall 20 is surrounded and arranged in the non-functional area 1012. In addition, the retaining wall 20 can also be formed by other materials or other processes, as long as it can play the role of protecting the internal functional area 1011, which is not specifically limited here.

[0031] In yet another embodiment, see Figure 3 and Figure 4 , Figure 3 yes Figure 1 Step S101 in the figure corresponds to a flowchart of an implementation method. Figure 4 yes Figure 3 The structural diagram of an implementation method corresponding to step S201-step S202 in FIG. The above step S101 includes:

[0032] S201: forming a first annular sub-retaining wall 201 in the non-functional area 1012 .

[0033] Specifically, see Figure 4 (a) and Figure 4 (b) where Figure 4 (a) is a front view of the chip 10 structure, Figure 4 (b) is a top view of the chip 10. The first sub-wall 201 can be made of metal and formed in the non-functional area 1012 by using the RDL process.

[0034] S202: forming an annular second sub-retaining wall 202 on the side of the first sub-retaining wall 201 away from the first surface 101 , wherein the first sub-retaining wall 201 and the second sub-retaining wall 202 form a retaining wall 20 , and a width m of the second sub-retaining wall 202 is smaller than a width M of the first sub-retaining wall 201 .

[0035] Specifically, see Figure 4 (c) and Figure 4 (d) where Figure 4 (c) is a front view of the chip 10 structure, Figure 4(d) is a top view of the chip 10 structure. The second sub-retaining wall 202 can also be made of metal and is formed on the first sub-retaining wall 201 using the RDL process. The width m of the second sub-retaining wall 202 is smaller than the width M of the first sub-retaining wall 201. At this time, the first sub-retaining wall 201 and the second sub-retaining wall 202 are stacked up and down to form the overall structure of the retaining wall 20. The retaining wall 20 is in a "convex" shape in the projection direction of the main view.

[0036] Through the above implementation, the contact area between the retaining wall 20 and the non-functional area 1012 can be increased, providing technical support for the subsequent bonding and fixing of the chip 10 and the adhesive layer, and effectively improving the bonding force between the retaining wall 20 and the adhesive layer.

[0037] S102 : The first surface of the chip 10 is fixed on a carrier 40 having an adhesive layer 30 , and the retaining wall 20 is embedded in the adhesive layer 30 .

[0038] Specifically, see Figure 2 (c), in this embodiment, the material of the carrier 40 can be glass, silicon or metal. The adhesive layer 30 disposed above the carrier 40 can be a temporary bonding adhesive or a double-sided adhesive. The chip 10 adheres to the adhesive layer 30 to achieve a preliminary fixation with the carrier 40, and the retaining wall 20 sinks into the adhesive layer 30. The adhesive force between the retaining wall 20 and the adhesive layer 30 again ensures that the position of the chip 10 and the carrier 40 remains relatively fixed.

[0039] S103 : forming a plastic encapsulation layer 50 on the side of the adhesive layer 30 where the chip 10 is disposed, and the plastic encapsulation layer 50 covers the second surface 102 and the side surface (not shown) of the chip 10 .

[0040] Specifically, see Figure 2 (d) The material of the plastic layer 50 can be epoxy resin, etc. The second surface 102 of the chip 10, that is, the back and all the side areas are covered by the plastic layer 50. After this step, the fan-out package device can achieve the effect of five-sided coating.

[0041] S104: removing the glue layer 30 and the carrier plate 40.

[0042] Specifically, see Figure 2 (e) In this embodiment, the adhesive layer 30 and the carrier plate 40 can be removed by thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc.

[0043] Through the above-mentioned implementation mode, in the fan-out packaging method provided in the present application, an annular retaining wall 20 is pre-arranged around the non-functional area 1012 of the first surface 101 of the chip 10, and the annular retaining wall 20 higher than the first surface 101 of the chip 10 is used to block the colloid of the plastic sealing layer 50 overflowing during the plastic sealing process, thereby reducing the risk of contamination of the grains in the functional area 1011 of the chip 10, effectively improving the yield of the chip 10, ensuring the subsequent weldability of the chip 10 and the quality of the overall product, and significantly improving the packaging structure of the chip 10.

[0044] In this embodiment, after the above step S104, a process of removing the retaining wall is also included. For the specific process of removing the retaining wall, please refer to Figure 5 , Figure 5 yes Figure 1 The process flow diagram of an implementation method after step S104 in FIG. 1 is shown in FIG. 2 . The step of removing the retaining wall includes:

[0045] S301: Covering the first surface of the chip with an insulating layer, with the retaining wall exposed from the insulating layer.

[0046] Specifically, the chip is protected by the insulating layer, mainly to protect the functional area in the first surface of the chip from being damaged.

[0047] S302: etching to remove the retaining wall.

[0048] Specifically, all the retaining wall portions disposed on the first surface of the chip are removed by etching. Of course, in other embodiments, other process methods may be used, which are determined according to the material of the retaining wall and are not specifically limited here.

[0049] S303: forming a first opening at a pad position of the insulating layer corresponding to the functional area.

[0050] Specifically, the pad is disposed inside the functional area of ​​the chip and needs to be exposed from the insulating layer to achieve subsequent electrical connection with external devices, thereby realizing the function of the chip.

[0051] In this embodiment, the above step S303 may also include removing the entire insulating layer, leaving only the chip covered by the plastic packaging layer on five sides, and subsequent packaging steps may also be performed to realize the chip function.

[0052] Through the above-mentioned implementation, the retaining wall structure can be removed. Since the retaining wall plays a role in preventing glue overflow during plastic sealing and avoiding contamination of the grains in the chip in the packaging method provided in the present application, the redundant retaining wall structure can be removed before implementing the rewiring process.

[0053] In another embodiment, please refer to Figure 6 and Figure 7 , Figure 6 yes Figure 1 A flow chart of another embodiment after step S104, Figure 7 A schematic diagram of the structure of an embodiment of a fan-out packaging device of the present application. After the above step S104, it also includes:

[0054] S401 : forming a first dielectric layer 60 on the first surface 101 , and the first dielectric layer 60 covers the retaining wall 20 .

[0055] Specifically, the first dielectric layer 60 can be made of a low-k material and covers the first surface 101 of the chip 10 , the pad 103 and the upper portion of the barrier wall 20 .

[0056] In another embodiment, if the barrier wall 20 structure is removed from the first surface 101 after the packaging method performs the above-mentioned step of removing the barrier wall 20 , the first dielectric layer 60 formed is located above the first surface 101 of the chip 10 and the pad 103 .

[0057] S402 : forming a second opening 601 at a position of the pad 103 in the first dielectric layer 60 corresponding to a functional area (not shown in the figure).

[0058] Specifically, the pad 103 is disposed inside the functional area of ​​the chip 10 , and the pad 103 needs to be exposed from the second opening 601 to achieve electrical connection with an external device, thereby achieving the function of the chip 10 .

[0059] S403 : forming a rewiring layer 70 on the first dielectric layer 60 , wherein the rewiring layer 70 fills the second opening 601 to be electrically connected to the pad 103 .

[0060] Specifically, the rewiring layer 70 may be made of metal materials such as copper and tin, and the fan-out packaging device 100 is electrically connected to external devices through the rewiring layer 70 .

[0061] Please also read Figure 7 and Figure 8 , Figure 8 yes Figure 6 After step S403, the process further includes:

[0062] S501 : forming a second dielectric layer 80 on a side of the rewiring layer 70 away from the chip 10 , and a third opening 801 is provided on a side of the second dielectric layer 80 corresponding to the rewiring layer 70 .

[0063] Specifically, the second dielectric layer 80 may be made of a low dielectric material, and the first dielectric layer 60 and the second dielectric layer 80 wrap the rewiring layer 70. When both the first dielectric layer 60 and the second dielectric layer 80 are made of low dielectric materials, the leakage current of the rewiring layer 70 can be reduced, and the capacitance effect between the wires can be reduced; in addition, the heat generation of the rewiring layer 70 can be reduced, the function of the chip can be enhanced, and the quality of the fan-out package device 100 can be improved.

[0064] S502 : implanting solder balls 90 in the third openings 801 , and electrically connecting the solder balls 90 to the redistribution layer 70 .

[0065] Specifically, in this embodiment, a ball planting machine may be used to plant solder balls 90 in the third openings 801 , and the fan-out package device 100 may be directly electrically connected to an external device through the solder balls 90 .

[0066] The fan-out package device formed by the above steps in this application is further described from the structural aspect. Figure 7 The fan-out packaging device 100 provided in the present application includes:

[0067] The chip 10 includes a first surface 101 and a second surface 102, wherein the first surface 101 includes a functional area (not shown in the figure) and a non-functional area (not shown in the figure), and the non-functional area is arranged around the periphery of the functional area. In this embodiment, the chip 10 can be a silicon substrate, a germanium substrate, etc., wherein the first surface 101 is the front side of the chip 10, and the second surface 102 is the back side of the chip 10. In this embodiment, the shape of the functional area can be circular, rectangular, square, etc., and the non-functional area corresponds to other areas of the first surface 101 excluding the functional area.

[0068] The retaining wall 20 is arranged in a ring shape around the periphery of the functional area. In the present embodiment, the retaining wall 20 is made of metal, such as copper, tin, etc. In the present embodiment, the height of the retaining wall 20 ranges from 10 to 50 microns, such as 10 microns, 20 microns, 40 microns, 50 microns, etc. Through the above-mentioned implementation, the plastic encapsulation colloid can be effectively prevented from flowing into the functional area of ​​the chip, the grains on the surface of the chip 10 can be prevented from being contaminated, the yield of the chip 10 can be effectively improved, and the subsequent weldability of the chip 10 and the quality of the overall product can be guaranteed.

[0069] The plastic encapsulation layer 50 covers the second surface 102 and the side of the chip 10, and one side surface of the plastic encapsulation layer 50 is flush with the first surface 101, and the retaining wall 20 is exposed from the plastic encapsulation layer 50. In this embodiment, the material of the plastic encapsulation layer 50 can be epoxy resin, etc., and the second surface 102 of the chip 10, that is, the back and all the side areas are covered by the plastic encapsulation layer 50, so that the fan-out package device 100 can achieve the effect of five-sided coating.

[0070] Please continue reading Figure 7 , the packaged device 100 provided in the present application further includes:

[0071] The pad 103 is located on one side of the first surface 101 of the chip 10 and in the functional area. In this embodiment, the pad 103 is used to achieve electrical connection with external devices to ensure the welding performance of the chip 10 and further achieve the function of the chip 10.

[0072] The first dielectric layer 60 is located on the side of the plastic encapsulation layer 50 close to the first surface 101, and a second opening 601 is provided at a position corresponding to the pad 103. In this embodiment, the first dielectric layer 60 may be made of a low dielectric constant material, covering the first surface 101 of the chip 10, the pad 103 and the upper part of the retaining wall 20, and a second opening 601 is provided at a position corresponding to the pad 103, and the pad 103 needs to be exposed from the second opening 601 to achieve electrical connection with an external device, thereby achieving the function of the chip 10.

[0073] The rewiring layer 70 is located on the side of the first dielectric layer 60 away from the chip 10 and is electrically connected to the pad 103. In this embodiment, the rewiring layer 70 can be made of metal materials such as copper and tin, and the fan-out package device 100 is electrically connected to external devices through the rewiring layer 70.

[0074] The second dielectric layer 80 is located on the side of the rewiring layer 70 away from the chip 10, and a third opening 801 is provided on the side corresponding to the rewiring layer 70. In this embodiment, the second dielectric layer 80 can be made of a low dielectric constant material, and the first dielectric layer 60 and the second dielectric layer 80 wrap the rewiring layer 70. When both the first dielectric layer 60 and the second dielectric layer 80 are made of low dielectric constant materials, the leakage current of the rewiring layer 70 can be reduced, and the capacitance effect between the wires can be reduced; in addition, the heating of the rewiring layer 70 can be alleviated, the function of the chip 10 can be enhanced, and the quality of the packaged device can be improved.

[0075] The solder ball 90 is located in the third opening 801 and is electrically connected to the redistribution layer 70. In this embodiment, a ball implanter can be used to implant the solder ball 90 in the third opening 801, and the fan-out package device 100 can be directly electrically connected to an external device through the solder ball 90.

[0076] In summary, different from the prior art, the fan-out packaging method provided by the present application includes a step of pre-setting an annular retaining wall around the non-functional area of ​​the first surface of the chip before forming the plastic encapsulation layer, and utilizing the annular retaining wall higher than the first surface of the chip to block the colloid that overflows from the plastic encapsulation layer during the plastic encapsulation process, thereby reducing the risk of contamination of grains in the functional area of ​​the chip, effectively improving the yield of the chip, ensuring the subsequent weldability of the chip and the quality of the overall product, and significantly improving the chip packaging structure.

[0077] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging method, characterized in that: include: A chip is provided, the chip comprising a first surface and a second surface disposed opposite to each other, wherein the first surface comprises a functional area and a non-functional area, the non-functional area is disposed around the periphery of the functional area, and the non-functional area is provided with an annular retaining wall, the retaining wall is disposed around the periphery of the functional area; The first surface of the chip is fixed on a carrier having an adhesive layer, and the retaining wall is embedded in the adhesive layer; Forming a plastic sealing layer on the side of the adhesive layer where the chip is arranged, wherein the plastic sealing layer covers the second surface and side surfaces of the chip; removing the adhesive layer and the carrier plate; The step of providing a chip includes: Electroplating the retaining wall in the non-functional area; Wherein, the step of electroplating the retaining wall in the non-functional area comprises: Forming a first annular sub-retaining wall in the non-functional area; An annular second sub-retaining wall is formed on the side of the first sub-retaining wall away from the first surface, wherein the first sub-retaining wall and the second sub-retaining wall form the retaining wall, and the width of the second sub-retaining wall is smaller than that of the first sub-retaining wall.

2. The fan-out packaging method according to claim 1, characterized in that: The retaining wall is made of metal.

3. The fan-out packaging method according to claim 1, characterized in that: After the step of removing the glue layer and the carrier plate, the method further includes: The retaining wall is removed.

4. The fan-out packaging method according to claim 3, characterized in that: The step of removing the retaining wall comprises: An insulating layer is covered on the first surface of the chip, and the retaining wall is exposed from the insulating layer; Etching and removing the retaining wall; A first opening is formed in the insulating layer at a position corresponding to the pad of the functional area.

5. The fan-out packaging method according to claim 1, characterized in that: After the step of removing the glue layer and the carrier plate, the method further includes: forming a first dielectric layer on the first surface, wherein the first dielectric layer covers the retaining wall; forming a second opening at a position of the first dielectric layer corresponding to the pad of the functional area; A rewiring layer is formed on the first dielectric layer, the rewiring layer filling the second opening to be electrically connected to the pad.

6. The fan-out packaging method according to claim 5, characterized in that: After the step of forming a rewiring layer on the first dielectric layer, wherein the rewiring layer fills the second opening to be electrically connected to the pad, the method further includes: forming a second dielectric layer on a side of the rewiring layer away from the chip, and a third opening is provided on a side of the second dielectric layer corresponding to the rewiring layer; A solder ball is implanted in the third opening, and the solder ball is electrically connected to the redistribution layer.

7. A fan-out packaging device, characterized in that: include: The chip comprises a first surface and a second surface, wherein the first surface comprises a functional area and a non-functional area, and the non-functional area is arranged around the periphery of the functional area; A retaining wall, the retaining wall is annular and arranged around the periphery of the functional area; A plastic encapsulation layer, covering the second surface and the side surface of the chip, with one side surface of the plastic encapsulation layer flush with the first surface, and the retaining wall exposed from the plastic encapsulation layer; The retaining wall comprises a first sub-retaining wall and a second sub-retaining wall, the second sub-retaining wall is located on a side of the first sub-retaining wall away from the first surface, and the width of the second sub-retaining wall is smaller than the width of the first sub-retaining wall.

8. The fan-out package device according to claim 7, characterized in that: The height of the retaining wall is 10-50 microns.

9. The fan-out package device according to claim 7, characterized in that: Also includes: A pad, located on the first surface of the chip; A first dielectric layer is located on a side of the plastic packaging layer close to the first surface and is provided with a second opening corresponding to the position of the pad; a redistribution layer, located on a side of the first dielectric layer away from the chip and electrically connected to the pad; A second dielectric layer is located on a side of the rewiring layer away from the chip, and a third opening is provided on a side corresponding to the rewiring layer; The solder ball is located in the third opening and is electrically connected to the redistribution layer.

Images