Semiconductor package including stacked semiconductor chips and method for manufacturing the same

Abstract

A semiconductor package including stacked semiconductor chips and a method for manufacturing the same. A semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; and a bump structure interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core and a shell, the shell surrounding all side walls of the core, and wherein the shell has a higher melting point than the core.

Description

Technical Field

[0001] The present patent document relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips stacked on a substrate. Background Art

[0002] Electronic products need to process large amounts of data while being smaller in size. Therefore, there is an increasing need to increase the integration of semiconductor devices used in such electronic products.

[0003] However, due to the limitation of semiconductor integration technology, the required functions cannot be realized by only a single semiconductor chip. Therefore, a semiconductor package in which a plurality of semiconductor chips are embedded is manufactured. Summary of the invention

[0004] In one embodiment, a semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip; and a bump structure inserted between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core and a shell, the shell surrounds all side walls of the core, and the shell has a higher melting point than the core.

[0005] In one embodiment, a method for manufacturing a semiconductor package may include the following steps: forming a first bump on the upper surface of a first semiconductor chip, the first bump including: a first core portion, the first core portion having a first side wall and other side walls, and the first side wall of the first core portion faces a second core portion; and a first shell portion, the first shell portion surrounding part or all of the other side walls of the first core portion; forming a second bump on the lower surface of a second semiconductor chip, the second bump including: a second core portion, the second core portion having a first side wall and other side walls, and the first side wall of the second core portion faces the first side wall of the first core portion; and a second shell portion, which surrounds part or all of the other side walls of the second core portion; and forming a core portion by combining the first side wall of the first core portion and the first side wall of the second core portion, wherein all side walls of the core portion are surrounded by the first shell portion and the second shell portion, and wherein the first portion and the second shell portion have higher melting points than the first core portion and the second core portion, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view showing a first semiconductor chip and a second semiconductor chip of a semiconductor package according to an embodiment.

[0007] Figure 2 It is shown Figure 1 an upper surface of the first semiconductor chip and Figure 1 A plan view of the lower surface of the second semiconductor chip.

[0008] Figure 3 It is shown Figure 1 A cross-sectional view of a state in which a first semiconductor chip and a second semiconductor chip are stacked.

[0009] Figure 4 It is shown in Figure 3 A plan view of the upper surface of the first semiconductor chip and / or the lower surface of the second semiconductor chip in a state.

[0010] Figure 5 is a plan view showing an upper surface of a first semiconductor chip and a lower surface of a second semiconductor chip of a semiconductor package according to another embodiment.

[0011] Figure 6 It is shown in Figure 5 A plan view of an upper surface of the first semiconductor chip and / or a lower surface of the second semiconductor chip in a state where the first semiconductor chip and the second semiconductor chip are stacked.

[0012] Figure 7 is a plan view showing an upper surface of a first semiconductor chip and a lower surface of a second semiconductor chip of a semiconductor package according to another embodiment.

[0013] Figure 8 It is shown in Figure 7 A plan view of an upper surface of the first semiconductor chip and / or a lower surface of the second semiconductor chip in a state where the first semiconductor chip and the second semiconductor chip are stacked.

[0014] Fig. 9 is a cross-sectional view showing first to fourth semiconductor chips of a semiconductor package according to another embodiment.

[0015] Fig.10 is a cross-sectional view showing a semiconductor package according to another embodiment.

[0016] Fig.11 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to one embodiment is shown.

[0017] Fig.12 A block diagram showing another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0018] Hereinafter, various examples and embodiments of the technology of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] The drawings are not necessarily drawn to scale, and in some cases, the proportions of at least some of the structures in the drawings may be exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example of two or more layers having a multilayer structure is presented in the drawings or descriptions, the relative positional relationship of the layers shown or the order in which the layers are arranged reflects the specific embodiment of the described or illustrated example, and different relative positional relationships or orders of arranging the layers may exist. In addition, the example of the multilayer structure described or shown may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer, or "on" or "above" a substrate, the first layer may be formed directly on the second layer or substrate, but may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0020] It should be understood that although the terms "first", "second", "third", etc. are used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0021] In addition, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0022] Various embodiments relate to a semiconductor package including stacked semiconductor chips, which can improve performance and reduce process constraints and process defects, and a method of manufacturing the same.

[0023] Figures 1 to 4 2 is a diagram for describing a semiconductor package and a method for manufacturing the same according to an embodiment of the present disclosure. Figure 1 is a cross-sectional view showing a first semiconductor chip and a second semiconductor chip of a semiconductor package according to an embodiment. Figure 1 The diagram shows an alignment state of the first semiconductor chip and the second semiconductor chip before the second semiconductor chip is stacked on the first semiconductor chip. Figure 2 It is shown Figure 1 an upper surface of the first semiconductor chip and Figure 1 A plan view of the lower surface of the second semiconductor chip. Figure 3 It is shown Figure 1 A cross-sectional view of a state in which a first semiconductor chip and a second semiconductor chip are stacked. Figure 4 It is shown in Figure 3 For ease of description, in Figure 2 and Figure 4 Also shown in FIG. 1 are penetrating electrodes that are not visible from the upper surface of the first semiconductor chip and the lower surface of the second semiconductor chip. Figure 1 The first semiconductor chip corresponds to the Figure 2 The section of line A1-A1', and Figure 1 The second semiconductor chip corresponds to the Figure 2 A section along line A2-A2'. Figure 3 The stacked first semiconductor chip and the second semiconductor chip correspond to the Figure 4 A cross section along line A1-A1' and / or line A2-A2'.

[0024] First, the manufacturing method will be described.

[0025] Reference Figure 1 and Figure 2 , a first semiconductor chip 110 and a second semiconductor chip 120 to be stacked up and down may be provided.

[0026] The first semiconductor chip 110 may include a first body portion 112 , a first through electrode 114 , and a first bump 116 .

[0027] The first body portion 112 may include a semiconductor material, such as silicon (Si) or germanium (Ge). Although not shown, various wiring and / or circuit structures may be formed in the first body portion 112. The first body portion 112 may have a plate-like shape defined by a lower surface 112-1, an upper surface 112-2, and side surfaces connecting them to each other. For example, the first body portion 112 may have a square plate shape.

[0028] The first penetration electrode 114 may have a columnar shape extending from the upper surface 112-2 of the first body portion 112 to the lower surface 112-1, and the first penetration electrode 114 penetrates the first body portion 112. For example, the first penetration electrode 114 may be a through silicon via (TSV). The first penetration electrode 114 may include various conductive materials, such as copper (Cu), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co) or a combination thereof. A plurality of first penetration electrodes 114 may penetrate the first body portion 112, and at least one of the plurality of first penetration electrodes 114 may be electrically connected to the wiring and / or circuit structure of the first body portion 112. In the present embodiment, a plurality of first penetration electrodes 114 are shown as being arranged in a row at regular intervals along one direction (e.g., along the horizontal direction in the plan view). However, the arrangement of the first penetration electrode 114 may be changed.

[0029] A plurality of first bumps 116 may be formed on the upper surface 112-2 of the first body portion 112 to be electrically connected to the upper ends of the plurality of first penetration electrodes 114, respectively. Each first bump 116 may include a first core portion 116A and a first shell portion 116B. The first core portion 116A and the first shell portion 116B may be arranged side by side on the upper surface 112-2 of the first body portion 112, and the side walls of the first core portion 116A and the first shell portion 116B are in contact with each other. Here, the first shell portion 116B of the first bump 116 may overlap with the first penetration electrode 114 and may be electrically connected to the first penetration electrode 114. On the other hand, the first core portion 116A may not overlap with the first penetration electrode 114 and may be arranged on one side of the first penetration electrode 114 and / or on one side of the first shell portion 116B. Therefore, the first core portion 116A may be electrically connected to the first penetration electrode 114 through the first shell portion 116B. The arrangement and shape of the first core portion 116A and the first shell portion 116B will be described below.

[0030] The first shell portion 116B may overlap with the first penetration electrode 114, and therefore, the lower surface of the first shell portion 116B may be in direct contact with the upper end of the first penetration electrode 114 or with a pad (not shown) connected to the upper end of the first penetration electrode 114. In addition, the first shell portion 116B may be used not only to overlap / connect with the first penetration electrode 114, but also to surround a portion of the side wall of the first core portion 116A and / or the second core portion 126A to be described later. To this end, the first shell portion 116B may include an overlapping portion that overlaps with the first penetration electrode 114 and contacts a portion of the side wall of the first core portion 116A, and may include an extension portion that extends from the overlapping portion and covers another portion of the side wall of the first core portion 116A and / or a portion of the side wall of the second core portion 126A. Hereinafter, the overlapping portion of the first shell portion 116B will be referred to as the first overlapping portion 116B-1, and the extension portion of the first shell portion 116B will be referred to as the first extension portion 116B-2. Since the first overlapping portion 116B-1 of the first shell portion 116B overlaps the first through-electrode 114, the vertical axis passing through the first overlapping portion 116B-1 and the vertical axis passing through the first through-electrode 114 may be aligned with each other along a straight line. However, the plane area of ​​the first overlapping portion 116B-1 may be greater than the plane area of ​​the first through-electrode 114. The first extension portion 116B-2 of the first shell portion 116B may extend from the first overlapping portion 116B-1 toward the first core portion 116A (e.g., toward the right side) to surround another portion of the sidewall of the first core portion 116A.

[0031] The first core portion 116A may be disposed on one side of the first overlapping portion 116B-1. More specifically, the first core portion 116A may be disposed in consideration of the position of the second core portion 126A of the second bump 126 of the second semiconductor chip 120 to be described later. That is, the first core portion 116A may be disposed on a side facing the second core portion 126A based on the first overlapping portion 116B-1. In the present embodiment, since the second core portion 126A is disposed on the right side compared to the first core portion 116A, the first core portion 116A may be disposed on the right side of the first overlapping portion 116B-1. The first penetration electrode 114 may not overlap and / or contact the first core portion 116A.

[0032] The first core 116A may have a columnar shape. In the present embodiment, the columnar shape of the first core 116A may have a planar rectangular shape. Therefore, the first core 116A may include a first side wall S11 closest to the first penetration electrode 114, a third side wall S13 arranged opposite to the first side wall S11, a second side wall S12 connecting the first side wall S11 and the third side wall S13, and a fourth side wall S14 located on the opposite side of the second side wall S12. In the present embodiment, in a plan view, the first side wall S11, the second side wall S12, the third side wall S13, and the fourth side wall S14 may correspond to the left side wall, the upper side wall, the right side wall, and the lower side wall, respectively. In this case, the first overlapping portion 116B-1 may contact the first side wall S11 of the first core 116A, and the first extension portion 116B-2 may be bent toward the first core 116A (e.g., toward the right side) to contact the second side wall S12 of the first core 116A. The first shell portion 116B can contact the first side wall S11 and the second side wall S12 of the first core portion 116A, and therefore, the first shell portion 116B can have a curved shape similar to the shape of ┌ around half of the side wall (2 / 4) of the first core portion 116A. However, the present disclosure is not limited thereto, and in a plan view, the shape of the first core portion 116A and the relative position and / or shape of the first shell portion 116B can be changed. For example, the first extension portion 116B-2 can be set to contact the fourth side wall S14 of the first core portion 116A, rather than the second side wall S12 of the first core portion 116A. In this case, the first shell portion 116B can have a curved shape similar to the shape of └.

[0033] At the same time, the first extension portion 116B-2 can contact the second side wall S12 of the first core portion 116A, and can protrude further than the second side wall S12 of the first core portion 116A in its extension direction (e.g., toward the right side). This is to further surround a portion of the side wall of the second core portion 126A, which will be described in the relevant section below.

[0034] The first core 116A and the first shell 116B may include a conductive material, such as a metal material. However, the first core 116A may be formed by a material having a melting point lower than that of the first shell 116B. For example, the first core 116A may include tin (Sn), copper (Cu), silver (Ag), lead (Pb) or a combination thereof, and the first shell 116B may include nickel (Ni), copper (Cu), tungsten (W), titanium (Ti) or a combination thereof. The material forming the first core 116A may melt at a specific reflow temperature to form a joint between the materials, while the material forming the first shell 116B may not melt at the reflow temperature.

[0035] The above-mentioned first semiconductor chip 110 may include volatile memory (e.g., dynamic random access memory (DRAM), static RAM (SRAM), etc.), non-volatile memory (e.g., NAND flash memory, resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), etc.) and various other active devices or passive devices.

[0036] The second semiconductor chip 120 may include a second body portion 122 , a second through electrode 124 , and a second bump 126 .

[0037] The second body portion 122 may include a semiconductor material, such as silicon (Si) or germanium (Ge). Although not shown, various wiring and / or circuit structures may be formed in the second body portion 122. The second body portion 122 may have a plate-like shape defined by a lower surface 122-1, an upper surface 122-2, and side surfaces connecting them to each other. For example, the second body portion 122 may have a rectangular plate shape.

[0038] The second penetration electrode 124 may have a columnar shape extending from the upper surface 122-2 of the second body portion 122 to the lower surface 122-1 to penetrate the second body portion 122. For example, the second penetration electrode 124 may be a TSV. The second penetration electrode 124 may include various conductive materials, such as copper (Cu), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co) or a combination thereof. A plurality of second penetration electrodes 124 may penetrate the second body portion 122, and at least one of the plurality of second penetration electrodes 124 may be electrically connected to the wiring and / or circuit structure of the second body portion 122. In the present embodiment, a plurality of second penetration electrodes 124 are shown as being arranged in a row at regular intervals along one direction (e.g., along the horizontal direction in the plan view). However, the arrangement of the second penetration electrode 124 may be changed. However, in the plan view, the arrangement / position of the first penetration electrode 114 and the sizes of the first bump 116 and the second bump 126 may be considered to determine the arrangement / position of the second penetration electrode 124. When one of the second penetration electrodes 124 needs to be connected to one of the corresponding first penetration electrodes 114, the second penetration electrode 124 may be adjacent to the corresponding first penetration electrode 114 without overlapping the corresponding first penetration electrode 114. That is, the first penetration electrode 114 and the second penetration electrode 124 may be spaced apart from each other in a plan view so that a vertical axis passing through the second penetration electrode 124 may not be aligned with a vertical axis passing through the corresponding first penetration electrode 114. As in the present embodiment, when the first penetration electrodes 114 are repeatedly arranged at regular intervals in the horizontal direction, the second penetration electrodes 124 may also be repeatedly arranged at the same intervals in the horizontal direction. However, compared with the first penetration electrode 114, the second penetration electrode 124 may be arranged to be offset to the right by a certain distance (see D1).

[0039] A plurality of second bumps 126 may be formed on the lower surface 122-1 of the second body portion 122 to be electrically connected to the lower ends of the plurality of second penetration electrodes 124, respectively. Each second bump 126 may include a second core portion 126A and a second shell portion 126B. The second core portion 126A and the second shell portion 126B may be arranged side by side on the lower surface 122-1 of the second body portion 122, and the side walls of the second core portion 126A and the second shell portion 126B are in contact with each other. Here, the second shell portion 126B of the second bump 126 may overlap with the second penetration electrode 124 and may be electrically connected to the second penetration electrode 124. On the other hand, the second core portion 126A may not overlap with the second penetration electrode 124 and may be arranged on one side of the second penetration electrode 124 and / or on one side of the second shell portion 126B. Therefore, the second core portion 126A may be electrically connected to the second penetration electrode 124 through the second shell portion 126B. The arrangement and shape of the second core portion 126A and the second shell portion 126B will be described below.

[0040] The second shell portion 126B may overlap with the second penetration electrode 124, and thus, the upper surface of the second shell portion 126B may be in direct contact with the lower end of the second penetration electrode 124 or with a pad (not shown) connected to the lower end of the second penetration electrode 124. In addition, the second shell portion 126B may be used not only to overlap / connect with the second penetration electrode 124, but also to surround a portion of the sidewall of the second core portion 126A and / or the first core portion 116A. To this end, the second shell portion 126B may include a second overlapping portion 126B-1 that overlaps with the second penetration electrode 124 and contacts a portion of the sidewall of the second core portion 126A, and may include a second extending portion 126B-2 that extends from the second overlapping portion 126B-1 and covers another portion of the sidewall of the second core portion 126A and / or a portion of the sidewall of the first core portion 116A. Since the second overlapping portion 126B-1 overlaps the second through-electrode 124, a vertical axis passing through the second overlapping portion 126B-1 and a vertical axis passing through the second through-electrode 124 may be aligned with each other along a straight line. The second extending portion 126B-2 may extend from the second overlapping portion 126B-1 toward the second core portion 126A (e.g., toward the left side) to surround another portion of the sidewall of the second core portion 126A.

[0041] The second core portion 126A may be disposed on one side of the second overlapping portion 126B-1. More specifically, the second core portion 126A may be disposed in consideration of the position of the first core portion 116A. That is, the second core portion 126A may be disposed on a side facing the first core portion 116A based on the second overlapping portion 126B-1. In the present embodiment, since the first core portion 116A is disposed on the left side compared to the second core portion 126A, the second core portion 126A may be disposed on the left side of the second overlapping portion 126B-1. The second penetration electrode 124 may not overlap and / or contact the second core portion 126A.

[0042] The second core 126A may have a columnar shape. In the present embodiment, the columnar shape of the second core 126A may have a planar rectangular shape. Therefore, the second core 126A may include a first side wall S21 closest to the second penetration electrode 124, a third side wall S23 arranged opposite to the first side wall S21, a second side wall S22 connecting the first side wall S21 and the third side wall S23, and a fourth side wall S24 located on the opposite side of the second side wall S22. In the present embodiment, in a plan view, the first side wall S21, the second side wall S22, the third side wall S23, and the fourth side wall S24 may correspond to the right side wall, the lower side wall, the left side wall, and the upper side wall, respectively. In this case, the second overlap portion 126B-1 may contact the first side wall S21 of the second core 126A, and the second extension portion 126B-2 may be bent toward the second core 126A (e.g., toward the left side) to contact the second side wall S22 of the second core 126A. The second shell portion 126B may contact the first side wall S21 and the second side wall S22 of the second core portion 126A, and therefore, the second shell portion 126B may have a curved shape similar to the shape of ┘ surrounding half of the side wall (2 / 4) of the second core portion 126A. However, the present disclosure is not limited thereto, and in a plan view, the shape of the second core portion 126A and the relative position and / or shape of the second shell portion 126B may be changed. In this case, the relative position or shape of the shape of the second core portion 126A and the second shell portion 126B may be determined by considering the position / shape of the first core portion 116A and the first shell portion 116B. For example, when the first extension portion 116B-2 contacts the fourth side wall S14 of the first core portion 116A instead of the second side wall S12 of the first core portion 116A, the second extension portion 126B-2 of the second shell portion 126B can be configured to contact the fourth side wall S24 of the second core portion 126A, and therefore, the second extension portion 126B-2 of the second shell portion 126B can have a curved shape similar to a ┐ shape.

[0043] At the same time, the second extension portion 126B-2 can contact the second side wall S22 of the second core portion 126A, and can protrude further than the second side wall S22 of the second core portion 126A in its extension direction (e.g., toward the left side). This is to further surround a portion of the side wall of the first core portion 116A, which will be described in the relevant section below.

[0044] The second core 126A and the second shell 126B may include a conductive material, such as a metal material. However, the second core 126A may be formed by a material having a melting point lower than that of the second shell 126B. For example, the second core 126A may include tin (Sn), copper (Cu), silver (Ag), lead (Pb) or a combination thereof, and the second shell 126B may include nickel (Ni), copper (Cu), tungsten (W), titanium (Ti) or a combination thereof. The material forming the second core 126A may melt at a specific reflow temperature to form a bond between the materials, while the material forming the second shell 126B may not melt at the reflow temperature. The material forming the second core 126A may be the same as the material forming the first core 116A. The material forming the second shell 126B may be the same as the material forming the first shell 116B. However, in other embodiments, the material forming the second core portion 126A and the material forming the first core portion 116A may be different from each other, and / or the material forming the second shell portion 126B and the material forming the first shell portion 116B may be different from each other.

[0045] The above-mentioned second semiconductor chip 120 may include volatile memory (for example, dynamic random access memory (DRAM), static RAM (SRAM), etc.), non-volatile memory (for example, NAND flash memory, resistive RAM (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), etc.) and various other active devices or passive devices.

[0046] The second semiconductor chip 120 may be the same semiconductor chip as the first semiconductor chip 110, or a different semiconductor chip from the first semiconductor chip 110. In addition, the sizes of the first semiconductor chip 110 and the second semiconductor chip 120 may be the same or different. However, regardless of the types and sizes of the first semiconductor chip 110 and the second semiconductor chip 120, the shape / arrangement of the second bumps 126 of the second semiconductor chip 120 may be the same as the first bumps 116 of the first semiconductor chip 110 rotated 180 degrees.

[0047] Next, refer to Figure 3 and Figure 4 , can be stacked while maintaining alignment Figure 1 and Figure 2Here, the first semiconductor chip 110 and the second semiconductor chip 120 may be stacked such that the A1-A1' line and the A2-A2' line may overlap each other.

[0048] More specifically, the first core portion 116A of the first bump 116 of the first semiconductor chip 110 may contact the second core portion 126A of the second bump 126 of the second semiconductor chip 120. At this time, the third side wall (see FIG. 1 ) of the first core portion 116A facing the second core portion 126A Figure 2 S13) can contact the third side wall (see S13) of the second core portion 126A facing the first core portion 116A Figure 2 For example, the right side wall of the first core portion 116A may contact the left side wall of the second core portion 126A.

[0049] In the above state, the first core 116A and the second core 126A can be joined by performing a reflow process at a specific temperature. That is, the first bump 116 and the second bump 126 can form a side contact structure and / or a side bonding structure. In this figure, for ease of description, the boundary between the first core 116A and the second core 126A is shown. However, the first core 116A and the second core 126A can be melted together to form a lump. The lump will be referred to as core CP1. When the first core 116A and the second core 126A are formed by the same material, the core CP1 may include the same material. Alternatively, when the first core 116A and the second core 126A are formed by different materials, the core CP1 may include an alloy of these different materials.

[0050] On the other hand, during the reflow process, the first shell portion 116B and the second shell portion 126B can maintain their original shapes without being deformed like the first core portion 116A and the second core portion 126A. For ease of description, the first shell portion 116B and the second shell portion 126B will be collectively referred to as the shell portion SP1. In addition, the core portion CP1 and the shell portion SP1 will be collectively referred to as the bump structure BS1. Since the lower surface of the shell portion SP1 contacts the upper surface 112-2 of the first body portion 112 of the first semiconductor chip 110, and the upper surface of the shell portion SP1 contacts the lower surface 122-1 of the second body portion 122 of the second semiconductor chip 120, the shell portion SP1 can be used to maintain the gap between the first semiconductor chip 110 and the second semiconductor chip 120 in the vertical direction. This is because even if the first core portion 116A and the second core portion 126A melt in the reflow process, the first shell portion 116B and the second shell portion 126B also maintain their original shapes. The height of the shell portion SP1 in the vertical direction may be the same as the distance between the first semiconductor chip 110 and the second semiconductor chip 120 .

[0051] After forming the side contact / joining of the first core portion 116A and the second core portion 126A, all side walls of the core portion CP1 can be completely surrounded by the shell portion SP1. Since the first shell portion 116B and the second shell portion 126B are not deformed during the reflow process and maintain their original shapes, the core portion CP1 can maintain the combined shape of the first core portion 116A and the second core portion 126A based on the rectangular hole pattern in the center of the shell portion SP1 despite the reflow process. For example, as in the present embodiment, the core portion CP1 can have a rectangular columnar shape. Here, the first side wall of the first core 116A (for example, see Figure 2 S11, left side wall) and second side wall (see, for example, Figure 2 S12, upper side wall) can be covered by the first shell portion 116B. In addition, the fourth side wall (for example, see Figure 2 The lower side wall of the second core portion 126A (S14, lower side wall) can be covered by the second shell portion 126B, in particular, by the protrusion of the extension portion 126B-2 of the second shell portion 126B that protrudes further toward the left side than the second core portion 126A. In addition, the first side wall of the second core portion 126A (for example, see Figure 2 S21, right side wall) and second side wall (see, for example, Figure 2 S22, lower side wall) can be covered by the second shell portion 126B. In addition, the fourth side wall (e.g., see Figure 2 The upper side wall of S24 may be covered by the first shell portion 116B, in particular, by a protrusion of the extension portion 116B-2 of the first shell portion 116B that protrudes further toward the right side than the first core portion 116A. For reference, the third side walls of the first core portion 116A facing each other (e.g., see Figure 2 S13, right side wall) and the third side wall of the second core portion 126A (for example, see Figure 2 S23, left side wall) can contact and engage with each other.

[0052] In addition, the first extension portion 116B-2 of the first shell portion 116B may protrude further to the right than the core portion CP1 to contact the second shell portion 126B. In addition, the second extension portion 126B-2 of the second shell portion 126B may protrude further to the left than the core portion CP1 to contact the first shell portion 116B. In this case, the shell portion SP1 may firmly surround the side wall of the core portion CP1.

[0053] The first semiconductor chip 110 and the second semiconductor chip 120 may be connected by a bump structure BS1, wherein the first bump 116 and the second bump 126 are combined on one side. In particular, the first through-electrode 114 of the first semiconductor chip 110 may be electrically connected to the second through-electrode 124 of the second semiconductor chip 120 by the first shell 116B, the core CP1, and the second shell 126B.

[0054] Therefore, a semiconductor package in which the first semiconductor chip 110 and the second semiconductor chip 120 are stacked may be realized. The semiconductor package may have the following advantages.

[0055] First, since the bump structure BS1 disposed between the first semiconductor chip 110 and the second semiconductor chip 120 includes a core CP1 and a shell SP1 completely surrounding the core CP1, even if the semiconductor package of the present embodiment enters multiple high-temperature processes and the core CP1 having a relatively low melting point melts again, the structure of the shell SP1 having a relatively high melting point can be maintained, and the movement of the molten metal of the core CP1 can be prevented. Therefore, bridging failures between adjacent bump structures BS1 can be avoided.

[0056] Furthermore, due to the presence of the shell portion SP1 , even when pressure is applied to the bump structure BS1 when the first semiconductor chip 110 and the second semiconductor chip 120 are combined, collapse of the bump structure BS1 may be avoided.

[0057] In addition, since the bridging failure between the bump structures BS1 is avoided and the collapse of the bump structures BS1 is prevented as described above, the gap between the bump structures BS1 can be reduced. Therefore, the gap between the first through electrodes 114 and / or the gap between the second through electrodes 124 can be reduced. That is, the first semiconductor chip 110 and the second semiconductor chip 120 can be implemented with a finer pitch.

[0058] As a result, the performance of the semiconductor package of this embodiment can be improved.

[0059] Furthermore, in the past, in order to prevent bridging failure between bumps, the gaps between bumps must be filled. However, according to the semiconductor package of the present embodiment, since bridging between bump structures BS1 is substantially blocked, there is no problem even if the gaps between bump structures BS1 are narrowed and the filling characteristics are reduced.

[0060] As a result, process constraints and / or process defects during semiconductor package manufacturing may be reduced.

[0061] Furthermore, since the core portion CP1 and the shell portion SP1 of the bump structure BS1 are disposed in a horizontal direction, the height of the space between the first semiconductor chip 110 and the second semiconductor chip 120 can be reduced. As a result, the height of the semiconductor package of the present embodiment can be reduced.

[0062] According to the present embodiment, the first shell portion 116B may surround half of the side wall of the core portion CP1, and the second shell portion 126B may surround the other half of the side wall of the core portion CP1. This is because in the above-mentioned embodiment, the shape / arrangement of the second bump 126 is the same as the first bump 116, but rotated 180 degrees. However, the present disclosure is not limited to this. As long as the shell portion SP1 surrounds all the side walls of the core portion CP1, and the first semiconductor chip 110 and the second semiconductor chip 120 are connected by the bump structure BS1, the shapes of the first shell portion 116B and the second shell portion 126B may be changed. Figure 5 and Figure 6 Such an example is described.

[0063] Figure 5 is a plan view showing an upper surface of a first semiconductor chip and a lower surface of a second semiconductor chip of a semiconductor package according to another embodiment. Figure 6 It is shown in Figure 5 A plan view of the upper surface of the first semiconductor chip and / or the lower surface of the second semiconductor chip in a state where the first semiconductor chip and the second semiconductor chip are stacked. Figure 5 The cross section of line A3-A3' can be Figure 1 The cross-sections of the first semiconductor chips are substantially the same, along Figure 5 The cross section of line A4-A4' can be Figure 1 The cross-section of the second semiconductor chip is substantially the same as that of Figure 6 The cross section of line A3-A3' and / or A4-A4' may be Figure 3 The cross-sections of the first semiconductor chip and the second semiconductor chip are substantially the same. Therefore, the cross-sectional view is omitted when describing the present embodiment. The differences between the above-mentioned embodiment and the present embodiment will be described below.

[0064] First, refer to Figure 5 , a first semiconductor chip 210 and a second semiconductor chip 220 to be stacked up and down may be provided.

[0065] The first semiconductor chip 210 may include a first through-electrode 214 and a first bump 216. The first bump 216 may be connected to the first through-electrode 214. The second semiconductor chip 220 may include a second through-electrode 224 and a second bump 226. The second bump 226 may be connected to the second through-electrode 224.

[0066] Here, the first bump 216 may include a first core 216A and a first shell 216B. The first shell 216B may include a first overlap 216B-1 that overlaps the first penetration electrode 214, and a first extension 216B-2 and a second extension 216B-3 that extend from the first overlap 216B-1 and bend toward the first core 216A. The first core 216A may have a rectangular columnar shape. The first core 216A may be disposed on the right side of the first overlap 216B-1. Therefore, the left side wall of the first core 216A may contact the first overlap 216B-1. The first extension 216B-2 may contact the upper side wall of the first core 216A, and the second extension 216B-3 may contact the lower side wall of the first core 216A. That is, the first shell 216B may cover three of the four side walls of the first core 216A (except for the right side wall that will eventually contact the second core 226A).

[0067] In addition, each of the first extension 216B-2 and the second extension 216B-3 of the first shell portion 216B may protrude further to the right than the first core portion 216. This is to further surround a portion of the side wall of the second core portion 226A of the second bump 226, which will be described later. In addition, this is to contact the second shell portion 226B, which will also be described later.

[0068] The second bump 226 may include a second core portion 226A and a second shell portion 226B. The second shell portion 226B may overlap with the second penetration electrode 224 and have a rectangular columnar shape. The second core portion 226A may have a rectangular columnar shape and may be disposed on the left side of the second shell portion 226B. Therefore, the right side wall of the second core portion 226A may contact the second shell portion 226B.

[0069] Next, refer to Figure 6 , can be stacked while maintaining alignment Figure 5 , and the first semiconductor chip 210 and the second semiconductor chip 220 described in detail.

[0070] More specifically, the first core portion 216A of the first bump 216 of the first semiconductor chip 210 may contact the second core portion 226A of the second bump 226 of the second semiconductor chip 220. At this time, the right side wall of the first core portion 216A may contact the left side wall of the second core portion 226A.

[0071] In the above state, when a reflow process is performed at a specific temperature, the first core portion 216A and the second core portion 226A may be melted together to form the core portion CP2.

[0072] The left side wall, the upper side wall and the lower side wall of the core CP2 may contact the first shell 216B, and the right side wall of the core CP2 may contact the second shell 226B. Therefore, all side walls of the core CP2 may be surrounded by the first shell 216B and the second shell 226B. For ease of description, the first shell 216B and the second shell 226B will be collectively referred to as the shell SP2. In addition, the core CP2 and the shell SP2 will be collectively referred to as the bump structure BS2.

[0073] Therefore, the first semiconductor chip 210 and the second semiconductor chip 220 may be connected to each other through the bump structure BS2. The bump structure BS2 may include a core CP2 and a shell SP2. The shell SP2 may surround all sidewalls of the core CP2.

[0074] Meanwhile, in the above-mentioned embodiment, the case where the first cores 116A and 126A, the second cores 216A and 226A, and the cores CP1 and CP2 have a planar rectangular shape has been described. However, the present disclosure is not limited thereto. The first core and the second core may be a columnar type having various planar shapes, such as half of a polygon, a semicircle, a semi-ellipse, etc., and the combined core may be a columnar type having a planar shape, such as a polygon, a circle, an ellipse, etc. Reference will be made to Figure 7 and Figure 8 Such an example is described.

[0075] Figure 7 is a plan view showing an upper surface of a first semiconductor chip and a lower surface of a second semiconductor chip of a semiconductor package according to another embodiment. Figure 8 It is shown in Figure 7 A plan view of the upper surface of the first semiconductor chip and / or the lower surface of the second semiconductor chip in a state where the first semiconductor chip and the second semiconductor chip are stacked. Figure 7 The cross section of line A5-A5' can be Figure 1 The cross-sections of the first semiconductor chips are substantially the same, along Figure 7 The cross section of line A6-A6' can be Figure 1 The cross-section of the second semiconductor chip is substantially the same as that of Figure 8 The cross section of line A5-A5' and / or A6-A6' may be Figure 3 The cross-sections of the first semiconductor chip and the second semiconductor chip are substantially the same. Therefore, the cross-sectional view is omitted when describing the present embodiment. The differences between the above-mentioned embodiment and the present embodiment will be described below.

[0076] First, refer to Figure 7 , a first semiconductor chip 310 and a second semiconductor chip 320 to be stacked up and down may be provided.

[0077] The first semiconductor chip 310 may include a first through electrode 314 and a first bump 316 connected to the first through electrode 314. The second semiconductor chip 320 may include a second through electrode 324 and a second bump 326 connected to the second through electrode 324.

[0078] Here, the first bump 316 may include a first core 316A and a first shell 316B. The planar shape of the first core 316A may be semicircular. Therefore, the first core 316A may have a straight sidewall corresponding to the diameter of the semicircle and a curved sidewall corresponding to the circumference of the semicircle. For example, the straight sidewall of the first core 316A may be arranged to face the second core 326A (e.g., the right side), and the curved sidewall may be arranged on the left side of the straight sidewall. The first shell 316B may be arranged on the left side of the first core 316A and may surround the curved sidewall of the first core 316A. The first shell 316B may overlap with the first penetration electrode 314.

[0079] The second bump 326 may include a second core 326A and a second shell 326B. The planar shape of the second core 326A may be semicircular. Therefore, the second core 326A may have a straight sidewall corresponding to the semicircular diameter and a curved sidewall corresponding to the semicircular circumference. The straight sidewall of the second core 326A may be arranged to face the first core 316A (e.g., the left side), and the curved sidewall may be arranged on the right side of the straight sidewall. The second shell 326B may be arranged on the right side of the second core 326A, and may surround the curved sidewall of the second core 326A. The second shell 326B may overlap with the second penetration electrode 324.

[0080] Next, refer to Figure 8 , can be stacked while maintaining alignment Figure 7 The first semiconductor chip 310 and the second semiconductor chip 320 described in FIG.

[0081] More specifically, the first core portion 316A of the first bump 316 of the first semiconductor chip 310 may contact the second core portion 326A of the second bump 326 of the second semiconductor chip 320. At this time, the straight sidewall of the first core portion 316A may contact the straight sidewall of the second core portion 326A.

[0082] In the above state, when a reflow process is performed at a specific temperature, the first core portion 316A and the second core portion 326A may be melted together to form the core portion CP3.

[0083] The left half of the curved sidewall of the core CP3 may contact the first shell 316B, and the right half of the curved sidewall of the core CP3 may contact the second shell 326B. Therefore, all sidewalls of the core CP3 may be surrounded by the first shell 316B and the second shell 326B. The first shell 316B and the second shell 326B will be collectively referred to as the shell SP3. In addition, the core CP3 and the shell SP3 will be collectively referred to as the bump structure BS3.

[0084] Therefore, the first semiconductor chip 310 and the second semiconductor chip 320 may be connected to each other through the bump structure BS3. The bump structure BS3 may include a core CP3 and a shell SP3. The shell SP3 may surround all sidewalls of the core CP3.

[0085] In the above embodiment, only two semiconductor chips are stacked. However, the present disclosure is not limited thereto, and three or more semiconductor chips may be stacked. Fig. 9 Such an example is described.

[0086] Fig. 9 is a cross-sectional view showing first to fourth semiconductor chips of a semiconductor package according to another embodiment. Fig. 9 An alignment state of the first to fourth semiconductor chips before stacking the first to fourth semiconductor chips is shown.

[0087] Reference Fig. 9 The first semiconductor chip 410 may include: a first body portion 412 having a lower surface 412-1 and an upper surface 412-2; a first through-electrode 414 that penetrates the first body portion 412; and a first upper surface bump 416 that is disposed on the upper surface 412-2 of the first body portion 412 and connected to the first through-electrode 414. The first upper surface bump 416 may include a first upper surface core portion 416A and a first upper surface shell portion 416B. The first semiconductor chip 410 may be connected to the above Figure 1 The first semiconductor chips 110 are substantially the same.

[0088] In the present embodiment, it is assumed that the first semiconductor chip 410 is located at the bottom of the stack, and no bump is shown on the lower surface 412-1 of the first semiconductor chip 410. However, when the first semiconductor chip 410 is connected to a substrate (not shown) or another semiconductor chip (not shown) below it, the lower surface bump (not shown) can be arranged on the lower surface 412-1 of the first main body 412 of the first semiconductor chip 410. The lower surface bump can be formed in the same shape as the first upper surface bump 416 at the same position. In this case, the first semiconductor chip 410 can be the same as the third semiconductor chip 430 to be described later. That is, the shape and arrangement of the first through-electrode 414, the first upper surface bump 416 and the lower surface bump (not shown) of the first semiconductor chip 410 can be the same as the shape and arrangement of the third through-electrode 434, the third upper surface bump 436 and the third lower surface bump 438 of the third semiconductor chip 430. However, the present disclosure is not limited thereto, and the shape and arrangement of the lower surface bumps of the first semiconductor chip 410 may be different from the shape and arrangement of the first upper surface bumps 416 .

[0089] The second semiconductor chip 420 may include: a second main body portion 422 having a lower surface 422-1 and an upper surface 422-2; a second through-electrode 424 that penetrates the second main body portion 422; a second lower surface bump 426 that is connected to the second through-electrode 424 on the lower surface 422-1 of the second main body portion 422; and a second upper surface bump 428 that is connected to the second through-electrode 424 on the upper surface 422-2 of the second main body portion 422. The second lower surface bump 426 may include a second lower surface core portion 426A and a second lower surface shell portion 426B. The second upper surface bump 428 may include a second upper surface core portion 428A and a second upper surface shell portion 428B. In addition to including the second upper surface bump 428, the second semiconductor chip 420 may be similar to the above-mentioned Figure 1 The second semiconductor chip 120 is substantially the same.

[0090] The second upper surface bump 428 may be formed in the same shape at the same position as the second lower surface bump 426. That is, in a plan view, the second upper surface core portion 428A and the second upper surface shell portion 428B may overlap with the second lower surface core portion 426A and the second lower surface shell portion 426B. The second semiconductor chip 420 may further include a second upper surface bump 428 to connect with a third semiconductor chip 430 to be stacked on the second semiconductor chip 420.

[0091] Similar to the above-described embodiment, the first semiconductor chip 410 and the second semiconductor chip 420 may be stacked based on a combination of the first upper surface bump 416 and the second lower surface bump 426. That is, the first upper surface core portion 416A of the first upper surface bump 416 and the second lower surface core portion 426A of the second lower surface bump 426 are combined on one side to form a core portion, and the first upper surface shell portion 416B and the second lower surface shell portion 426B may surround the sidewall of the core portion, thereby forming a bump structure between the first semiconductor chip 410 and the second semiconductor chip 420 to connect the two semiconductor chips together.

[0092] The third semiconductor chip 430 may include: a third main body portion 432 having a lower surface 432-1 and an upper surface 432-2; a third penetrating electrode 434 penetrating the third main body portion 432; a third lower surface bump 438 connected to the third penetrating electrode 434 on the lower surface 432-1 of the third main body portion 432; and a third upper surface bump 436 connected to the third penetrating electrode 434 on the upper surface 432-2 of the third main body portion 432. The third lower surface bump 438 may include a third lower surface core portion 438A and a third lower surface shell portion 438B. The third upper surface bump 436 may include a third upper surface core portion 436A and a third upper surface shell portion 436B. In addition to including the third lower surface bump 438, the third semiconductor chip 430 may be connected to the first semiconductor chip 410 or the above Figure 1 The first semiconductor chips 110 are substantially the same.

[0093] The third lower surface bump 438 may be formed in the same shape at the same position as the third upper surface bump 436. That is, in a plan view, the third lower surface core portion 438A and the third lower surface shell portion 438B may overlap with the third upper surface core portion 436A and the third upper surface shell portion 436B. The third semiconductor chip 430 may further include a third lower surface bump 438 to connect with the second semiconductor chip 420.

[0094] Similar to the above, the second semiconductor chip 420 and the third semiconductor chip 430 may be stacked based on a combination of the second upper surface bump 428 and the third lower surface bump 438. That is, the second upper surface core portion 428A of the second upper surface bump 428 and the third lower surface core portion 438A of the third lower surface bump 438 may be combined on one side to form one core portion, and the second upper surface shell portion 428B and the third lower surface shell portion 438B may surround the sidewall of the core portion, thereby forming a bump structure, which is disposed between the second semiconductor chip 420 and the third semiconductor chip 430 to connect the two semiconductor chips together.

[0095] The fourth semiconductor chip 440 may include: a fourth body portion 442 having a lower surface 442-1 and an upper surface 442-2; a fourth through-electrode 444 penetrating the fourth body portion 442; and a fourth lower surface bump 446 connected to the fourth through-electrode 444 on the lower surface 442-1 of the fourth body portion 442. The fourth lower surface bump 446 may include a fourth lower surface core portion 446A and a fourth lower surface shell portion 446B. The fourth semiconductor chip 440 may be similar to the above Figure 1 The second semiconductor chip 120 is substantially the same.

[0096] The third semiconductor chip 430 and the fourth semiconductor chip 440 may be stacked in a manner similar to the other semiconductor chips described above based on a combination of the third upper surface bump 436 and the fourth lower surface bump 446. That is, the third upper surface core portion 436A of the third upper surface bump 436 and the fourth lower surface core portion 446A of the fourth lower surface bump 446 may be combined on one side to form a core portion, and the third upper surface shell portion 436B and the fourth lower surface shell portion 446B may surround the sidewall of the core portion, thereby forming a bump structure, which is disposed between the third semiconductor chip 430 and the fourth semiconductor chip 440 to connect the two semiconductor chips together.

[0097] In the present embodiment, it is assumed that the fourth semiconductor chip 440 is located at the top of the stack, and no bump is shown on the upper surface 442-2 of the fourth semiconductor chip 440. However, when the fourth semiconductor chip 440 is connected to another semiconductor chip (not shown) thereon, the upper surface bump (not shown) may be provided on the upper surface 442-2 of the fourth main body 442 of the fourth semiconductor chip 440. The upper surface bump may be formed in the same shape as the fourth lower surface bump 446 at the same position. In this case, the fourth semiconductor chip 440 may be the same as the second semiconductor chip 420. That is, the shape and arrangement of the fourth penetration electrode 444, the fourth lower surface bump 446 and the upper surface bump (not shown) of the fourth semiconductor chip 440 may be the same as the shape and arrangement of the second penetration electrode 424, the second lower surface bump 426 and the second upper surface bump 428 of the second semiconductor chip 420. However, the present disclosure is not limited thereto, and the shape and arrangement of the upper surface bump of the fourth semiconductor chip 440 may be different from the shape and arrangement of the fourth lower surface bump 446.

[0098] A plurality of semiconductor chips can be stacked in this manner, and thus, a higher degree of integration of a semiconductor package can be achieved.

[0099] like Fig. 9As shown, in a semiconductor package in which a plurality of semiconductor chips are vertically stacked, the arrangement of the through electrodes of the odd-numbered semiconductor chips may be identical to each other, and the arrangement of the through electrodes of the even-numbered semiconductor chips may be identical to each other. The vertical axes passing through the through electrodes of the odd-numbered semiconductor chips may be aligned with each other (see FIG. Fig. 9 AX1), and the vertical axes of the through electrodes passing through the even-numbered semiconductor chips can also be aligned with each other (see Fig. 9 AX2). However, the vertical axis passing through the through-electrode of the odd-numbered semiconductor chips and the vertical axis passing through the through-electrode of the even-numbered semiconductor chips may not be located on a straight line, but may be arranged to be staggered with each other. In addition, the shape and arrangement of the bumps of the odd-numbered semiconductor chips may be the same as each other, and the shape and arrangement of the bumps of the even-numbered semiconductor chips may be the same as each other. However, the bottom bump of the bottommost semiconductor chip may be omitted, or may have a different shape or arrangement to connect with the substrate. In addition, the top bump of the topmost semiconductor chip may be omitted, or may have a different shape or arrangement to connect with other components. At the same time, the bump structures in which the upper bumps and the lower bumps are combined may overlap with each other. That is, the vertical axes passing through the centers of the multiple bump structures arranged in the vertical direction may be aligned with each other (see Fig. 9 AX3). These vertical axes (see Fig. 9 AX3) may be located at a vertical axis (see Fig. 9 AX1) and the vertical axis of the through-electrode passing through the even-numbered semiconductor chip (see Fig. 9 between AX2).

[0100] Fig.10 is a cross-sectional view showing a semiconductor package according to another embodiment.

[0101] Reference Fig.10 , the semiconductor package of the present embodiment may include a substrate 500 and first to fourth semiconductor chips 510 , 520 , 530 , and 540 stacked on the substrate 500 .

[0102] The substrate 500 may be a substrate for a semiconductor package having a wiring and / or circuit structure for electrical signal transmission, such as a printed circuit board (PCB). The substrate 500 may include an upper surface on which the first to fourth semiconductor chips 510, 520, 530, and 540 are disposed, and a lower surface on which external connection terminals 570 are disposed to connect the semiconductor package to an external device, the lower surface being located on the opposite side of the upper surface.

[0103] The first semiconductor chip 510 may include a first penetration electrode 514. A first bump structure BS1' that connects the first penetration electrode 514 to the substrate 500 may be disposed between the first semiconductor chip 510 and the substrate 500. The first bump structure BS1' may include a first core CP1' and a first shell SP1' surrounding the sidewall of the first core CP1'. The lower end of the first penetration electrode 514 may be connected to a portion of the first shell SP1' at one side of the first core CP1 (e.g., at the left side of the first core CP1). A bonding pad (not shown) or the like on the upper surface of the substrate 500 may be directly or indirectly connected to the first shell SP1'.

[0104] The second semiconductor chip 520 may include a second penetration electrode 524. A second bump structure BS2' connecting the first penetration electrode 514 to the second penetration electrode 524 may be disposed between the first semiconductor chip 510 and the second semiconductor chip 520. The second bump structure BS2' may include a second core CP2' and a second shell SP2' surrounding the sidewall of the second core CP2'. The upper end of the first penetration electrode 514 may be connected to a portion of the second shell SP2' at one side of the second core CP2' (e.g., on the left side of the second core CP2'). The lower end of the second penetration electrode 524 may be connected to another portion of the second shell SP2' at the other side of the second core CP2' (e.g., on the right side of the second core CP2').

[0105] The third semiconductor chip 530 may include a third penetration electrode 534. A third bump structure BS3' connecting the third penetration electrode 534 to the second penetration electrode 524 may be disposed between the third semiconductor chip 530 and the second semiconductor chip 520. The third bump structure BS3' may include a third core CP3' and a third shell SP3' surrounding the sidewall of the third core CP3'. The upper end of the second penetration electrode 524 may be connected to a portion of the third shell SP3' on one side of the third core CP3' (e.g., on the right side of the third core CP3'). The lower end of the third penetration electrode 534 may be connected to another portion of the third shell SP3' on the other side of the third core CP3' (e.g., on the left side of the third core CP3').

[0106] The fourth semiconductor chip 540 may be located at the top, and therefore may not include a penetration electrode. However, in another embodiment, the fourth semiconductor chip 540 may include a penetration electrode arranged in the same manner as the second penetration electrode 524. The fourth bump structure BS4' connecting the third penetration electrode 534 to the chip pad (not shown) of the fourth semiconductor chip 540 may be arranged between the third semiconductor chip 530 and the fourth semiconductor chip 540. The fourth bump structure BS4' may include a fourth core CP4' and a fourth shell SP4' around the sidewall of the fourth core CP4'. The upper end of the third penetration electrode 534 may be connected to a part of the fourth shell SP4' on one side of the fourth core CP4' (for example, on the left side of the fourth core CP4'). The chip pad (not shown) of the fourth semiconductor chip 540 may be directly or indirectly connected to the fourth shell SP4'.

[0107] The spaces between the first semiconductor chip 510 and the substrate 500, between the first semiconductor chip 510 and the second semiconductor chip 520, between the second semiconductor chip 520 and the third semiconductor chip 530, and between the third semiconductor chip 530 and the fourth semiconductor chip 540 may be filled with the filling material 550. However, since the semiconductor chips have fine pitches, the spaces between the first bump structures BS1', between the second bump structures BS2', between the third bump structures BS3', and between the fourth bump structures BS4' may become narrower. Therefore, the filling material 550 may not completely fill these spaces, and micro voids may be generated in the filling material 550.

[0108] Here, since the first to fourth bump structures BS1', BS2', BS3', BS4' have a structure in which the sidewalls of the cores CP1', CP2', CP3', and CP4' are surrounded by shells SP1', SP2', SP3', and SP4' having a high melting point, even if the metal material melts in a high temperature process link, the movement of the metal material forming the cores CP1', CP2', CP3', and CP4' can be blocked. Therefore, even if the gaps between the first bump structures BS1', between the second bump structures BS2', between the third bump structures BS3', and between the fourth bump structures BS4' are narrow, and even if the filling material 550 is not completely filled and there are micro voids in the filling material 550, bridging failures due to the movement of the metal material can be prevented.

[0109] The substrate 500 and the first to fourth semiconductor chips 510, 520, 530, and 540 may be surrounded by a mold layer 560. That is, the mold layer 560 may be formed to cover the first to fourth semiconductor chips 510, 520, 530, and 540 on the upper surface of the substrate 500. The mold layer 560 may include various molding materials, such as epoxy molding compound (EMC).

[0110] Fig.11 A block diagram showing an electronic system including a memory card 7800 employing at least one semiconductor package according to an embodiment is shown. The memory card 7800 includes a memory 7810 (e.g., a nonvolatile memory device) and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiments.

[0111] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 to read stored data or store data in response to a read / write request from the host 7830 .

[0112] Fig.12 A block diagram showing an electronic system 8710 including at least one semiconductor package according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715, which provides a path for data movement.

[0113] In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to an embodiment of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0114] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0115] The electronic system 8710 may further include an interface 8714, which is configured to send data to and receive data from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired transceiver or a wireless transceiver.

[0116] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0117] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), enhanced time division multiple access (E-TDMA), wideband code division multiple access (WCDMA), CDMA2000, long term evolution (LTE), or wireless broadband Internet (Wibro) technology.

[0118] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the following claims.

[0119] CROSS-REFERENCE TO RELATED APPLICATIONS

[0120] This application claims priority to Korean Patent Application No. 10-2020-0022310, filed on February 24, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; a second semiconductor chip, the second semiconductor chip being disposed on the first semiconductor chip; as well as a bump structure, the bump structure being interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, The bump structure includes a core and a shell, wherein the shell surrounds all side walls of the core, and wherein the shell has a higher melting point than the core, The shell portion includes a first shell portion and a second shell portion, the first shell portion is formed on an upper surface of the first semiconductor chip and connected to the first semiconductor chip, and the second shell portion is formed on a lower surface of the second semiconductor chip and connected to the second semiconductor chip, wherein the first shell part partially surrounds the side wall of the core, and The second shell portion partially surrounds the remaining side walls of the core, so that the combination of the first shell portion and the second shell portion completely surrounds all side walls of the core.

2. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a first through electrode overlapping a portion of the first shell portion, and The second semiconductor chip includes a second through electrode overlapping a portion of the second shell portion.

3. The semiconductor package according to claim 2, wherein: A first vertical axis aligned with the first through-electrode is different from a second vertical axis aligned with the second through-electrode, and Wherein, a vertical axis passing through the core is located between the first vertical axis and the second vertical axis.

4. The semiconductor package according to claim 1, wherein: The core has a cylindrical shape.

5. The semiconductor package according to claim 1, wherein The first shell portion and the second shell portion each cover a half of a side wall of the core portion.

6. The semiconductor package according to claim 1, wherein One of the first shell portion and the second shell portion includes a protrusion that protrudes farther than the core portion, and the protrusion contacts the other of the first shell portion and the second shell portion.

7. The semiconductor package according to claim 1, wherein: The second shell portion is the same as the first shell portion in a state rotated 180 degrees, and the core portion is located between the second shell portion and the first shell portion.

8. The semiconductor package according to claim 1, further comprising: one or more semiconductor chips, the one or more semiconductor chips being arranged on the second semiconductor chip, The bump structure is further inserted between the second semiconductor chip and a semiconductor chip adjacent to the second semiconductor chip among the one or more semiconductor chips, or the bump structure is further inserted between two semiconductor chips adjacent to each other among the one or more semiconductor chips.

9. The semiconductor package according to claim 8, wherein: each of the first semiconductor chip, the second semiconductor chip, and the one or more semiconductor chips includes a through electrode, wherein the through-electrodes of the first semiconductor chip and the through-electrodes of odd-numbered semiconductor chips among the one or more semiconductor chips are aligned with each other, wherein the through-electrodes of the second semiconductor chip and the through-electrodes of even-numbered semiconductor chips among the one or more semiconductor chips are aligned with each other, and The first vertical axis aligned with the through-electrodes of the first semiconductor chip and the odd-numbered semiconductor chips is different from the second vertical axis aligned with the through-electrodes of the second semiconductor chip and the even-numbered semiconductor chips.

10. The semiconductor package according to claim 9, wherein The through electrodes of the first semiconductor chip and the odd-numbered semiconductor chips overlap with a first portion of the shell portion, and The through electrodes of the second semiconductor chip and the even-numbered semiconductor chips overlap with the second portion of the shell portion.

11. The semiconductor package according to claim 10, wherein: The first portion of the shell and the second portion of the shell are located at opposite sides to each other, and the core is located between the first portion of the shell and the second portion of the shell.

12. The semiconductor package according to claim 10, wherein: The first portion of the shell and the second portion of the shell are asymmetrical.

13. The semiconductor package according to claim 1, wherein An upper surface and a lower surface of the shell portion contact the second semiconductor chip and the first semiconductor chip, respectively.

14. The semiconductor package according to claim 1, wherein: The height of the shell portion is equal to the distance between the first semiconductor chip and the second semiconductor chip.

15. A method for manufacturing a semiconductor package, the method comprising the following steps: A first bump is formed on the upper surface of the first semiconductor chip, the first bump comprising: a first core portion, the first core portion having a first side wall and other side walls, and the first side wall of the first core portion faces the second core portion; and a first shell portion, the first shell portion surrounding part or all of the other side walls of the first core portion; forming a second bump on the lower surface of the second semiconductor chip, the second bump comprising: the second core portion, the second core portion having a first side wall and other side walls, and the first side wall of the second core portion facing the first side wall of the first core portion; and a second shell portion, the second shell portion surrounding part or all of the other side walls of the second core portion; and forming a core by combining the first side wall of the first core portion and the first side wall of the second core portion, wherein all side walls of the core are surrounded by the first shell and the second shell, and The first shell portion and the second shell portion have higher melting points than the first core portion and the second core portion, respectively.

16. The method according to claim 15, wherein: The step of forming the core portion is performed by a reflow process at a temperature at which the first core portion and the second core portion are melted but the first shell portion and the second shell portion are not melted.

17. The method according to claim 15, wherein: Each of the first core portion and the second core portion has a columnar shape.

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