A dual-threshold anti-jitter fast-response extended AGC dynamic circuit

Abstract

The invention discloses an extended AGC dynamic circuit with dual-threshold anti-jitter and fast response, including a comparator, a NOT gate, an AND gate and an R / S trigger; the comparator includes a comparator A and a comparator B, the NOT gate includes a first NOT gate and a second NOT gate; the AND gate includes a first AND gate and a second AND gate; the pin 4 of the comparator A is respectively connected to the first NOT gate and the second AND gate; the pin 4 of the comparator B is respectively connected to the second NOT gate and the second AND gate; the pin 2, pin 9, pin 10 and pin 1 of the R / S trigger are all used as output pins. The invention adopts an AGC control loop composed of a power detection circuit, a dual-threshold comparison circuit, a logic circuit and an R / S trigger, which solves the amplitude jitter problem existing in the traditional single-loop analog AGC circuit and the problem of too long AGC stabilization time caused by the digital AGC circuit. In the AGC circuit of the digital ADC radio frequency agile receiver, it is operable and practical.

Description

Technical Field

[0001] The invention belongs to the field of receiver circuits for analog radio frequency signals, and in particular is an extended AGC dynamic circuit with dual-threshold anti-jitter and fast response. Background Art

[0002] The AGC control circuit is an important component of the RF receiving system, and its performance index directly determines the performance of the entire receiver link. The function of the AGC control circuit is to attenuate the large dynamic signal received in the receiving system through the amplifier and digitally controlled attenuator according to the actual environment, so that the large signal is attenuated by a large amount, the small signal is attenuated by a small amount or even not attenuated, so that the output signal amplitude varies within a specific range to meet the signal dynamic range requirements of the subsequent baseband analog-to-digital converter (ADC) and ensure the smooth operation of the system.

[0003] In traditional wireless receiving communication systems, there are usually two methods, analog AGC circuit and digital AGC circuit. In the analog AGC circuit, power detector and comparator are used to form a closed loop, and the AGC system is controlled by controlling VGA. The digital AGC circuit uses a microcontroller or FPGA, a detection circuit, and an amplifier, and controls the digitally controlled attenuator through the digital logic of the controller to realize the AGC function. This method will be affected by the transmission rate or control logic of the controller and cannot meet the requirements of fast AGC. Especially in the application of fast frequency conversion, it is greatly restricted, and the output signal is prone to saturation or distortion, causing the receiver to not work properly or the weak signal to be submerged by noise and cannot be correctly demodulated. Summary of the invention

[0004] The object of the present invention is to provide an extended AGC dynamic circuit with dual-threshold anti-jitter and fast response, so as to solve the problems of slow response and output spectrum amplitude jitter caused by the traditional digital AGC circuit structure proposed in the background technology.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] An extended AGC dynamic circuit with dual-threshold anti-jitter and fast response includes a comparator, a NOT gate, an AND gate and an R / S trigger; the comparator includes a comparator A and a comparator B, the NOT gate includes a first NOT gate and a second NOT gate; the AND gate includes a first AND gate and a second AND gate;

[0007] Pin 1 of comparator A is connected to the peripheral circuit; Pin 3 of comparator A is connected to the first comparison voltage circuit, and Pin 4 of comparator A is respectively connected to Pin 2 of the first NOT gate and Pin 1 of the second AND gate; Pin 5 of comparator A is connected to the power supply, and Pin 2 of comparator A is grounded; Pin 1 of comparator B is connected to the peripheral circuit; Pin 3 of comparator B is connected to the second comparison voltage circuit, and Pin 4 of comparator B is respectively connected to Pin 2 of the second NOT gate and Pin 2 of the second AND gate; Pin 5 of comparator B is connected to the power supply, and Pin 2 of comparator B is grounded; Both the first NOT gate and the second NOT gate are connected to the first AND gate;

[0008] The first AND gate is connected to the pin of the R / S trigger; the second AND gate is connected to the pin of the R / S trigger; pin 5 of the R / S trigger is connected to pin 16 of the R / S trigger and the power supply; pin 8 of the R / S trigger is grounded; pin 2, pin 9, pin 10 and pin 1 of the R / S trigger are all used as output pins.

[0009] According to the above technical solution, pin 1 of the first NOT gate is open circuited, pin 5 of the first NOT gate is connected to the power supply, and pin 4 of the first NOT gate is connected to pin 1 of the first AND gate.

[0010] According to the above technical solution, pin 1 of the second NOT gate is disconnected, pin 5 of the second NOT gate is connected to the power supply, and pin 4 of the second NOT gate is connected to pin 2 of the first AND gate.

[0011] According to the above technical solution, a capacitor C1 is connected to the connection circuit between the pin 5 of the comparator A and the power supply, one end of the capacitor C1 is grounded, and the capacitor C1 is used for power supply filtering.

[0012] According to the above technical solution, a resistor R3 and a capacitor C2 are connected in series in the connection circuit between pin 4 of comparator A and the first NOT gate and the second AND gate. The resistor R3 and the capacitor C2 form an RC low-pass filter to filter the output voltage of comparator A.

[0013] According to the above technical solution, a capacitor C3 is connected to the connection circuit between the pin 5 of the comparator B and the power supply, one end of the capacitor C3 is grounded, and the capacitor C3 is used for power supply filtering.

[0014] According to the above technical solution, a resistor R7 and a capacitor C4 are connected in series in the connection circuit between pin 4 of comparator B and the second NOT gate and the second AND gate. Resistor R7 and capacitor C4 form an RC low-pass filter to filter the output voltage of comparator B.

[0015] According to the above technical solution, pin 3 of the first AND gate is grounded, pin 5 of the first AND gate is connected to the power supply, and pin 4 of the first AND gate is respectively connected to pin 4, pin 6, pin 12 and pin 14 of the R / S trigger.

[0016] According to the above technical solution, pin 3 of the second AND gate is grounded, pin 5 of the second AND gate is connected to the power supply, and pin 4 of the second AND gate is respectively connected to pin 3, pin 7, pin 11 and pin 15 of the R / S trigger.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention adopts an AGC control loop composed of a power detection circuit, a dual threshold comparison circuit, a logic circuit and an R / S trigger, and sets a dual threshold voltage comparison circuit and a logic circuit to prevent the jitter of the circuit. The attenuation position of the digital controlled attenuator in the radio frequency link is directly controlled by an analog control method, thereby solving the amplitude jitter problem existing in the traditional single-loop analog AGC circuit and the problem of too long AGC stabilization time caused by the digital AGC circuit. In the AGC circuit of the digital ADC radio frequency agile receiver, the invention has operability and practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The block diagram of the extended AGC dynamic circuit for dual threshold anti-jitter fast response;

[0020] Figure 2 The schematic diagram of the extended AGC dynamic circuit with dual threshold anti-jitter and fast response.

[0021] Markings in the figure: 1-comparator A, 2-comparator B, 3-first NOT gate, 4-second NOT gate, 5-first AND gate, 6-second AND gate, 7-R / S trigger, 8-digitally controlled attenuator, 9-detector. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] Embodiment 1

[0024] See also Figure 1 and Figure 2 ,like Figure 1 As shown, a dual-threshold anti-jitter fast-response extended AGC dynamic circuit includes a comparator, a NOT gate, an AND gate and an R / S trigger 7; the comparator includes a comparator A1 and a comparator B2, the NOT gate includes a first NOT gate 3 and a second NOT gate 4; the AND gate includes a first AND gate 5 and a second AND gate 6;

[0025] Pin 1 of comparator A1 is connected to a peripheral circuit; Pin 3 of comparator A1 is connected to a first comparison voltage circuit, and Pin 4 of comparator A1 is respectively connected to Pin 2 of a first NOT gate 3 and Pin 1 of a second AND gate 6; Pin 5 of comparator A1 is connected to a power supply, and Pin 2 of comparator A1 is grounded; Pin 1 of comparator B2 is connected to a peripheral circuit; Pin 3 of comparator B2 is connected to a second comparison voltage circuit, and Pin 4 of comparator B2 is respectively connected to Pin 2 of a second NOT gate 4 and Pin 2 of a second AND gate 6; Pin 5 of comparator B2 is connected to a power supply, and Pin 2 of comparator B2 is grounded; Both the first NOT gate 3 and the second NOT gate 4 are connected to the first AND gate 5;

[0026] The first AND gate 5 is connected to the pin of the R / S trigger 7; the second AND gate 6 is connected to the pin of the R / S trigger 7; pin 5 of the R / S trigger 7 is connected to pin 16 of the R / S trigger 7 and the power supply; pin 8 of the R / S trigger 7 is grounded; pin 2, pin 9, pin 10 and pin 1 of the R / S trigger 7 are all used as output pins.

[0027] Pin 1 of the first NOT gate 3 is open circuit, pin 5 of the first NOT gate 3 is connected to the power supply, and pin 4 of the first NOT gate 3 is connected to pin 1 of the first AND gate 5 .

[0028] The pin 1 of the second NOT gate 4 is open circuited, the pin 5 of the second NOT gate 4 is connected to the power supply, and the pin 4 of the second NOT gate 4 is connected to the pin 2 of the first AND gate 5 .

[0029] A capacitor C1 is connected to the connection circuit between the pin 5 of the comparator A1 and the power supply. One end of the capacitor C1 is grounded. The capacitor C1 is used for power supply filtering.

[0030] A resistor R3 and a capacitor C2 are connected in series in the connection circuit between the pin 4 of the comparator A1 and the first NOT gate 3 and the second AND gate 6. The resistor R3 and the capacitor C2 form an RC low-pass filter to filter the output voltage of the comparator A1.

[0031] A capacitor C3 is connected to the connection circuit between the pin 5 of the comparator B2 and the power supply. One end of the capacitor C3 is grounded. The capacitor C3 is used for power supply filtering.

[0032] A resistor R7 and a capacitor C4 are connected in series in the connection circuit between the pin 4 of the comparator B2 and the second NOT gate 4 and the second AND gate 6. The resistor R7 and the capacitor C4 form an RC low-pass filter to filter the output voltage of the comparator B2.

[0033] Pin 3 of the first AND gate 5 is grounded, pin 5 of the first AND gate 5 is connected to a power source, and pin 4 of the first AND gate 5 is connected to pin 4, pin 6, pin 12 and pin 14 of the R / S trigger 7 respectively.

[0034] Pin 3 of the second AND gate 6 is grounded, pin 5 of the second AND gate 6 is connected to the power supply, and pin 4 of the second AND gate 6 is connected to pin 3, pin 7, pin 11 and pin 15 of the R / S trigger 7 respectively.

[0035] Furthermore, pin 3 of comparator A1 is connected to a first comparison voltage circuit; the first comparison voltage circuit includes resistors R9, R4 and R10; resistor R4 is connected in parallel with resistor R9 and then in series with resistor R10, and is grounded through resistor R10.

[0036] Furthermore, the pin 3 of the comparator B2 is connected to a second comparison voltage circuit; the second comparison voltage circuit includes a resistor R8, a resistor R11 and a resistor R12; the resistor R8 is connected in parallel with the resistor R11 and then connected in series with the resistor R12, and is grounded through the resistor R12.

[0037] Embodiment 2

[0038] This embodiment is a further refinement of the first embodiment. Figure 1 As shown, the peripheral circuit includes a digitally controlled attenuator 8 and a detector 9;

[0039] The comparator A1 and the comparator B2 are both connected to the detector 9 .

[0040] The R / S trigger 7 is connected to the V1 and V2 pins of the digitally controlled attenuator 8 .

[0041] The output end of the digital controlled attenuator 8 is connected to the detector 9, and a coupler, an amplifier, a filter and a mixer are arranged on the connection circuit between the digital controlled attenuator 8 and the detector 9. The radio frequency signal conditioned by the digital controlled attenuator 8 is down-converted to an intermediate frequency signal by the mixer, which is beneficial to the subsequent circuit in terms of device selection and signal processing difficulty. The local oscillator leakage, radio frequency leakage and image frequency of the mixer are filtered out by the filter, and the intermediate frequency signal after mixing is amplified by the amplifier, so that the power of the signal is still within the detectable power dynamic range of the detector through the coupler. The coupler is used for power distribution, and its through-terminal is connected to the output port RF_OUT, and the coupled terminal is connected to the input end of the detector.

[0042] Pins V3, V4 and V5 of the digital controlled attenuator 8 are connected to the FPGA.

[0043] The digitally controlled attenuator 8 is connected to the input terminal of the radio frequency signal to be conditioned.

[0044] The circuit in this embodiment provides two AGC functions. When the amplitude of the input signal RF_IN is large, the AGC circuit composed of the analog loop can respond quickly, so that the signal is quickly output to the signal amplitude within the control voltage range of the dual threshold. When the amplitude of the input signal RF_IN is within the allowable power range of the subsequent circuit, the user can perform fine-tuning control through the host computer.

[0045] The comparator adopts the existing LMV331 IDCKT, the NOT gate adopts the existing 74LVC1G04, the AND gate adopts the existing 74LVC1G08, and the R / S trigger 7 adopts the existing CD4043BPWR.

[0046] Embodiment 3

[0047] This embodiment is a further refinement of the first embodiment. The RF AGC circuit is mainly used to increase the RF input dynamic range and improve the RF input sensitivity.

[0048] When a single-threshold control loop is used, the RF output signal will jitter. The reason is that: when the input signal amplitude is large, the voltage value of the detection signal is higher than the set comparison voltage threshold, the output of the comparator is high, and the digital attenuator will be set to the corresponding attenuation value; when the current state is set to the corresponding attenuation, the power at the RF output will change accordingly, and the output of the comparator will be low at this time, and the digital attenuator will turn off the attenuation value of the original fixed attenuator. Therefore, the attenuation of the attenuator will be turned off immediately after the attenuation is set, resulting in frequent switching on and off of the signal output at the same attenuation, causing signal jitter. For example: the current RF link output power is -5dBm. Assuming that the single threshold is set to output power -15dBm, the corresponding detection amplitude is Vout. The comparison voltage value is high after the comparison circuit, which directly controls V1~V3 of the digital attenuator. According to the manual, the attenuation corresponding to these three attenuation control bits is 2dB, 4dB, and 8dB respectively. At this time, the digital attenuator attenuates by at least 14dB in total. This attenuation will be immediately reflected at the output end of the RF link. At this time, the power at the RF output end becomes -19dBm. The comparison voltage value is low after the comparison circuit. At this time, the digital attenuator shows the direct insertion loss of the device itself. Here, it is assumed that the direct insertion loss of the digital attenuator is very small and can be ignored. At this time, the output power of the RF link becomes -5dBm again. The circuit can output stably only when the output power is greater than -1dBm.

[0049] Based on this, a dual-threshold control scheme is proposed. When the level value detected by the detector is higher than the comparison voltage values ​​of the two high and low thresholds at the same time, the logic circuit output is a low level; when the level value detected by the detector is lower than the comparison voltage values ​​of the two high and low thresholds at the same time, the logic circuit output is a high level; when the level value detected by the detector is higher than the low threshold of the comparator and lower than the low threshold of the comparator, the logic circuit output remains unchanged in the original state, that is, the control logic is composed of a latch memory function. The specific control logic is shown in Table 1.

[0050] Table 1 Control logic

[0051] A B S R Q 1 1 0 1 0 1 0 0 0 NC 0 1 0 0 NC 0 0 1 0 1

[0052] A, B represent the comparison values ​​of the detection voltage and the high and low threshold comparators;

[0053] S, R represent the control terminals of the R / S trigger;

[0054] NC, which means Not Change, does not change and keeps the original status.

[0055] From the above control logic, the port truth table of the R / S trigger can be obtained as follows:

[0056] Table 2 Truth table of S port

[0057]

[0058] The logical expression of the S port can be obtained from the truth table:

[0059] Table 3 Truth table of R port

[0060]

[0061] The logical expression of the R port can be obtained from the truth table: R = A·B.

[0062] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0063] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A dual-threshold anti-jitter fast-response extended AGC dynamic circuit, characterized in that: It includes a comparator, a NOT gate, an AND gate and an R / S trigger (7); the comparator includes a comparator A (1) and a comparator B (2); the NOT gate includes a first NOT gate (3) and a second NOT gate (4); and the AND gate includes a first AND gate (5) and a second AND gate (6); Pin 1 of comparator A (1) is connected to the peripheral circuit; pin 3 of comparator A (1) is connected to the first comparison voltage circuit, and pin 4 of comparator A (1) is respectively connected to pin 2 of the first NOT gate (3) and pin 1 of the second AND gate (6); pin 5 of comparator A (1) is connected to the power supply, and pin 2 of comparator A (1) is grounded; pin 3 of comparator B (2) is connected to the second comparison voltage circuit, and pin 4 of comparator B (2) is respectively connected to pin 2 of the second NOT gate (4) and pin 2 of the second AND gate (6). The first AND gate (5) is connected to the first AND gate (5); the pin 1 of the comparator A (1) is a non-inverting input terminal for inputting a signal; the pin 2 of the comparator A (1) is grounded; the pin 3 of the comparator A (1) is a reverse input terminal for inputting a signal; the pin 4 of the comparator A (1) is an output terminal for outputting a signal; the pin 5 of the comparator A (1) is a power pin for connecting a power supply; Pin 1 of comparator B (2) is a non-inverting input terminal for signal input; Pin 2 of comparator B (2) is grounded; Pin 3 of comparator B (2) is a negative input terminal for signal input; Pin 4 of comparator B (2) is an output terminal for signal output; Pin 5 of comparator B (2) is a power pin for connecting a power supply; The first AND gate (5) is connected to a pin of the R / S trigger (7); the second AND gate (6) is connected to a pin of the R / S trigger (7); pin 5 of the R / S trigger (7) is connected to pin 16 of the R / S trigger (7) and a power supply; pin 8 of the R / S trigger (7) is grounded; pins 2, 9, 10 and 1 of the R / S trigger (7) are all used as output pins; pin 3 of the first AND gate (5) is grounded, pin 5 of the first AND gate (5) is connected to a power supply, and pin 4 of the first AND gate (5) is respectively connected to pin 4, pin 6, pin 12 and pin 14 of the R / S trigger (7); Pin 1 and pin 2 of the first AND gate (5) are both signal input terminals, used for signal input; pin 3 of the first AND gate (5) is a ground pin, and pin 4 of the first AND gate (5) is an output pin, used for signal output; pin 5 of the first AND gate (5) is a power pin; Pin 3 of the second AND gate (6) is grounded, pin 5 of the second AND gate (6) is connected to a power supply, and pin 4 of the second AND gate (6) is respectively connected to pin 3, pin 7, pin 11 and pin 15 of the R / S trigger (7); Pin 1 and pin 2 of the second AND gate (6) are both signal input terminals, used for signal input; pin 3 of the second AND gate (6) is a ground pin, and pin 4 of the second AND gate (6) is an output pin, used for signal output; pin 5 of the second AND gate (6) is a power pin; Pin 1 of the first NOT gate (3) is disconnected, pin 5 of the first NOT gate (3) is connected to a power supply, and pin 4 of the first NOT gate (3) is connected to pin 1 of the first AND gate (5); Pin 2 of the first NOT gate (3) is a signal input terminal, used for signal input; Pin 3 of the first NOT gate (3) is a ground pin; Pin 4 of the first NOT gate (3) is a signal output terminal, used for signal output; Pin 5 of the first NOT gate (3) is a power pin; Pin 1 of the second NOT gate (4) is disconnected, pin 5 of the second NOT gate (4) is connected to a power supply, and pin 4 of the second NOT gate (4) is connected to pin 2 of the first AND gate (5); Pin 2 of the second NOT gate (4) is a signal input terminal for signal input; Pin 3 of the second NOT gate (4) is a ground pin; Pin 4 of the second NOT gate (4) is a signal output terminal for signal output; Pin 5 of the second NOT gate (4) is a power pin.

2. The extended AGC dynamic circuit with dual threshold anti-jitter and fast response according to claim 1, characterized in that: A capacitor C1 is connected to the connection circuit between pin 5 of the comparator A (1) and the power supply. One end of the capacitor C1 is grounded. The capacitor C1 is used for power supply filtering.

3. The extended AGC dynamic circuit with dual threshold anti-jitter and fast response according to claim 1, characterized in that: A resistor R3 and a capacitor C2 are connected in series in the connection circuit between the pin 4 of the comparator A (1) and the first NOT gate (3) and the second AND gate (6). The resistor R3 and the capacitor C2 form an RC low-pass filter to filter the output voltage of the comparator A (1).

4. The extended AGC dynamic circuit with dual threshold anti-jitter and fast response according to claim 1, characterized in that: A capacitor C3 is connected to the connection circuit between pin 5 of comparator B (2) and the power supply. One end of the capacitor C3 is grounded. The capacitor C3 is used for power supply filtering.

5. The extended AGC dynamic circuit with dual threshold anti-jitter and fast response according to claim 1, characterized in that: A resistor R7 and a capacitor C4 are connected in series in the connection circuit between the pin 4 of the comparator B (2) and the second NOT gate (4) and the second AND gate (6). The resistor R7 and the capacitor C4 form an RC low-pass filter to filter the output voltage of the comparator B (2).

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