Method and device for monitoring gate signal of power semiconductor
By generating and comparing expected signals with actual signals, using the combination of capacitors and resistors, combining mathematical operations and signal envelope comparison, the accuracy of power semiconductor gate driver fault diagnosis is solved, and the gate driver and power are realized Effective monitoring and diagnosis of semiconductors improves the accuracy of fault diagnosis and maintenance efficiency.
Patent Information
- Application Number
- CN202080015436.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-03-01
- Filing Date
- 2020-01-16
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2040-01-16
AI Technical Summary
In field applications, gate driver failures of power semiconductors are often reported as desaturation errors, resulting in false alarms or real short circuits. Existing protection methods are difficult to accurately diagnose the root cause of the fault, and replacing the gate driver may affect the entire system.
A device and method for monitoring the gate signal of a power semiconductor is designed to determine whether there is deterioration of the gate driver and power semiconductor by comparing it with the actual signal, generate the expected signal using capacitors and resistors, and pass differential The detection module and the diagnostic module are analyzed, combined with mathematical operations and signal envelope comparison, and detect the deterioration.
Effective monitoring and diagnosis of gate drivers and power semiconductors is achieved, the accuracy of fault diagnosis is improved, unnecessary replacement and system impact is avoided, and maintenance costs are reduced.
Smart Images
Figure CN113474667B_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to a method and a system for an apparatus for monitoring a gate signal of a power semiconductor. Background Art
[0002] In field applications such as traction, faults of gate drivers of power semiconductors are mostly reported as desaturation errors, i.e., the gate driver reports an abnormal situation where the gate voltage is at a high level and the voltage across the semiconductor is above a threshold. Reports of such anomalies are usually false alarms, i.e., a problem is notified despite the gate driver and power semiconductor working properly. In some other cases, such reports may be true, i.e., when a short circuit occurs.
[0003] Short circuits are usually caused by the gate driver itself, the controller, the power semiconductor, or the load. Commonly implemented protection methods avoid catastrophic failures but do not help maintenance teams understand the root cause of the failure. In some cases of gate driver failure, simply replacing the gate driver board at a low cost should solve the problem, but it may change the entire system.
[0004] Therefore, it is important to effectively monitor the operation of the gate driver itself, the operation of the power semiconductors and to improve diagnostics. Summary of the invention
[0005] The present invention aims to allow efficient monitoring of gate drivers and power semiconductors.
[0006] To this end, the present invention relates to a device for monitoring a gate signal of a power semiconductor, the gate signal of the power semiconductor being provided by a gate driver, wherein the device comprises:
[0007] - means for generating an expected signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor;
[0008] - means for comparing the expected signal with the signal output by the gate driver;
[0009] - means for using the comparison result of the expected signal with the signal output by the gate driver to determine whether there is degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor.
[0010] The present invention also relates to a method for monitoring a gate signal of a power semiconductor, the gate signal of the power semiconductor being provided by a gate driver, wherein the method comprises the following steps:
[0011] - generating an expected signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor;
[0012] - compare the expected signal with the signal output by the gate driver;
[0013] - Using the comparison result of the expected signal with the signal output by the gate driver to determine whether there is degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor.
[0014] Thus, anomalies in the gate signal traces are extracted at high speed during commutation. This then improves diagnostics.
[0015] According to a particular feature, the means for generating the expected signal comprises at least a capacitor and a resistor. Thus, the implementation is performed with readily available and low-cost electronic components.
[0016] According to a particular feature, the gate driver comprises a first isolation module, and the output of the means for determining whether degradation has occurred is connected to a second isolation module. Therefore, the requirements on the second isolation (eg response time, bandwidth) are low.
[0017] According to a particular feature, the gate driver and the means for generating the expected signal receive a pulse width modulated signal and a signal obtained on a connection of the semiconductor different from the gate signal. It is thus possible to diagnose a gate driver using a signal from a power semiconductor for protection or gate track control.
[0018] According to a particular feature, the means for determining whether degradation has occurred processes the comparison result of the expected signal with the signal output by the gate driver by comparing the comparison result with a threshold value, and / or by performing integration and / or averaging and / or extreme value calculation of the comparison result and comparing these integrations and / or average values and / or extreme values with a threshold value to detect degradation, and / or by comparing the comparison result with a stored signal envelope. Therefore, the means for determining whether degradation has occurred can be implemented with a high-bandwidth analog circuit.
[0019] According to a particular feature, the value of at least one threshold value is predetermined. Thus, the method is operable from the first operation of the power semiconductor and the designer is able to select the sensitivity to certain faults.
[0020] According to a particular feature, the value of at least one threshold is equal to X% of the maximum value observed during the first 100 operating cycles of the device, X being predefined and higher than 100%. Thus, the method does not require the designer to define in advance and adapt to the specificities of the system in which it is integrated (e.g. variability of power semiconductors, operating conditions).
[0021] According to a particular feature, the value of the threshold is equal to X% of the maximum value observed since the start of operation of the device, X being predefined and higher than 100%. Thus, the method detects sudden degradations but not gradual degradations. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The features of the invention will become more apparent upon reading the following description of exemplary embodiments, which is produced with reference to the accompanying drawings, in which:
[0023] [ Figure 1A ]
[0024] Figure 1A A first example of an architecture for a gate driver for a power semiconductor implementing the present invention is shown.
[0025] [ Figure 1B ]
[0026] Figure 1B A second example of an architecture for a gate driver for a power semiconductor implementing the present invention is shown.
[0027] [ Figure 1C ]
[0028] Figure 1C A third example of an architecture for a gate driver for a power semiconductor implementing the present invention is shown.
[0029] [ Figure 1D ]
[0030] Figure 1D A fourth example of an architecture for a gate driver for a power semiconductor device implementing the present invention is shown.
[0031] [ Figure 2 ]
[0032] Figure 2 is a diagram showing the architecture of a diagnostic module implementing the present invention.
[0033] [ Figure 3 ]
[0034] Figure 3 represents the algorithm executed according to the present invention.
[0035] [ Figure 4 ]
[0036] Figure 4 Shows examples of signals that may occur during operation of a gate driver of a power semiconductor.
[0037] [ Figure 5 ]
[0038] Figure 5An example of an envelope used by the diagnostic module to determine whether a fault has occurred during operation of the drive and power semiconductors.
[0039] [ Figure 6 ]
[0040] Figure 6 The average, minimum, maximum, and integrated values corresponding to the differences observed when no degradation occurs and when various degradations occur are shown. DETAILED DESCRIPTION
[0041] Figure 1A A first example of an architecture for a gate driver for a power semiconductor implementing the present invention is shown.
[0042] According to a first example of implementation, the regulator 10a generates an expected gate signal VGexp from an input signal In provided to a gate driver 12a, which provides a gate signal VGmeas to a power semiconductor S1. The gate signal VGmeas is compared with the expected gate driver signal VGexp by a differential detection module 13a to determine the deviation of VGmeas and VGexp. The comparison may be to subtract one signal from the other and amplify the subtraction result. The output of the differential detection module 13a is provided to a diagnostic module 14a, which quantifies the output of the differential detection module 13a using, for example, comparison with different kinds of signal envelopes, mathematical operations (e.g., maximization, averaging, and integration).
[0043] The generation of the expected gate signal VGexp by the regulator 10a may be tuned to reflect the specificities and / or operating conditions relative to the power semiconductor.Based on the input signal, the generation of VGexp is performed using a model whose transfer function reproduces the transfer function of the gate driver 12a under normal operation.
[0044] The input signal In is, for example, Figure 1A The PWM signal is generated by an external controller not shown in the figure.
[0045] The transfer function used by the regulator 10a is a circuit consisting of a buffer buf introducing a fixed delay t1 and an RC circuit, VGexp being the voltage between the R component and the C component. The R and / or C values can be tuned according to the power semiconductor S1. The fixed delay t1 has the same value as the delay generated by the gate driver 12a. The time constant of the circuit RC is equal to the time constant of a typical gate resistor (internal + external) and the equivalent input capacitance of the power semiconductor S1. For example, the value of the resistor is about 10Ω and the capacitor C is about 10nF. The regulator 10a can implement nonlinear controlled capacitor and / or resistor values.
[0046] In a particular feature, the voltage supply of the regulator 10a is lower than the voltage supply of the gate driver 12a by a factor K. In this case, the voltage between R and C is amplified by a factor K. Therefore, the power required to supply the regulator 10a is reduced by a factor K. 2 .
[0047] The expected signal VGexp is a signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor.
[0048] Figure 1B A second example of an architecture for a gate driver for a power semiconductor implementing the present invention is shown.
[0049] According to a second example of implementation, the regulator 10b generates an expected gate signal VGexp from an input signal In provided to a gate driver 12b, which provides a gate signal VGmeas to the power semiconductor S1. The gate signal VGmeas is compared with the expected gate driver signal VGexp by a differential detection module 13b to determine the deviation of VGmeas and VGexp. The comparison may be to subtract one signal from the other and amplify the subtraction result. The output of the differential detection module 13b is provided to a diagnostic module 14b, which quantifies the output of the differential detection module 13b using, for example, comparison with different kinds of signal envelopes, mathematical operations (e.g., maximization, averaging, and integration).
[0050] The expected gate signal VGexp generated by the regulator 10b is controlled by the diagnostic module 14b to achieve the value of the controlled capacitor and / or resistor provided by the diagnostic module to more accurately represent the expected gate signal VGexp. The diagnostic module 14b can select a transfer function from several transfer functions. The regulator 10b can generate the signal VGexp using a processing unit and a digital-to-analog converter based on a lookup table, model or transfer function provided by the diagnostic module 14b.
[0051] The expected signal VGexp is a signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor.
[0052] Figure 1C A third example of an architecture for a gate driver for a power semiconductor implementing the present invention is shown.
[0053] According to a third example of implementation, the regulator 10c generates an expected gate signal VGexp from an input signal In provided to a gate driver 12c, which provides a gate signal VGmeas to the power semiconductor S1. The gate signal VGmeas is compared with the expected gate driver signal VGexp by a differential detection module 13c to determine the deviation of VGmeas and VGexp. The comparison may be to subtract one signal from the other and amplify the subtraction result. The output of the differential detection module 13c is provided to a diagnostic module 14c, which quantifies the output of the differential detection module 13c using, for example, comparison with different kinds of signal envelopes, mathematical operations (e.g., maximization, averaging, and integration).
[0054] The generation of the expected gate signal VGexp by the regulator 10c may utilize a specific process taking into account the feedback signal, such as Figure 1A or Figure 1B as disclosed in .
[0055] The input signal In is, for example, Figure 1C The PWM signal is generated by an external controller not shown in the figure.
[0056] In a third example of implementation, the gate driver 12c uses the input signal In together with a feedback signal from the power semiconductor. An example of a feedback signal is the collector voltage of the power semiconductor that can be used for protection and / or active gate signal trajectory control. The feedback signal is typically combined with the PWM signal through the gate driver 12c and the regulator 10c.
[0057] The generation of the desired gate signal VGexp by the regulator 10c may utilize specific processing taking into account the feedback signal, such as Figure 1A or Figure 1B as disclosed in .
[0058] The expected signal VGexp is a signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor.
[0059] Figure 1D A fourth example of an architecture for a gate driver for a power semiconductor device implementing the present invention is shown.
[0060] According to a fourth example of implementation, the regulator 10d generates an expected gate signal VGexp from an input signal In provided to a gate driver 12d, which provides a gate signal VGmeas to a power semiconductor S1. A differential detection module 13d compares the gate signal VGmeas with the expected gate driver signal VGexp to determine the deviation of VGmeas and VGexp. The comparison may be to subtract one signal from the other and amplify the subtraction result. The output of the differential detection module 13d is provided to a diagnostic module 14d, which quantifies the output of the differential detection module 13d using, for example, comparison with different kinds of signal envelopes, mathematical operations (e.g., maximization, averaging, and integration).
[0061] The input signal In is, for example, Figure 1D The PWM signal is generated by an external controller not shown in the figure.
[0062] exist Figure 1D In the example of FIG. 1 , the driver 12 c is composed of a preprocessing module PR, an isolation module IS and a buffer BU. The output of the isolation module IS is provided as an input signal to the regulator 10 d.
[0063] At the output of the diagnostic module 14d a second insulation module IS2 is provided.The expected signal VGexp is a signal corresponding to the signal output by the gate driver in the absence of degradation of the gate driver and / or the power semiconductor and / or a load coupled to the power semiconductor.
[0064] Figure 2 1 is a diagram showing the architecture of the diagnostic module implementing the present invention. The diagnostic module 100, which may be 14a, 14b, 14c or 14d, has components connected together by bus 201 and by Figure 3 The architecture of the processor 200 controlled by the program disclosed in .
[0065] The bus 201 links the processor 200 to a read-only memory ROM 202 , a random access memory RAM 203 , an input-output interface 205 and finally an alarm module 206 .
[0066] Memory 203 contains data intended to receive variables and Figure 3 The registers of the program instructions related to the disclosed algorithm.
[0067] The read-only memory 202 contains Figure 3 The program instructions related to the algorithm disclosed in are transferred to the random access memory 203 when the diagnostic module 100 is powered on.
[0068] The following is about Figure 3Any and all steps of the described algorithms may be implemented in software by executing a set of instructions or a program by a programmable computing machine such as a PC (personal computer), DSP (digital signal processor) or microcontroller; or in hardware by a machine or dedicated components such as an FPGA (field programmable gate array) or ASIC (application-specific integrated circuit).
[0069] In other words, the diagnostic module 100 includes a circuit or a device containing a circuit so that the diagnostic module 100 performs the following Figure 3 The memory 202 includes the following: Figure 5 The envelope signal disclosed in .
[0070] Figure 3 In step S30, as shown in FIG. Figures 1A to 1D In step S31 , the gate driver provides a gate signal VGmeas to the power semiconductor S1 .
[0071] In step S32 , the regulator 10 provides the expected signal VGexp. In step S33 , the differential detection module 13 provides a signal representing the comparison result of the gate signal VGmeas and the expected signal VGexp to the diagnosis module 100. In step S34 , the diagnosis module 100 analyzes the signal received from the differential detection module 13 .
[0072] exist Figure 4 An example of a signal received from the differential detection module 13 is given in FIG. Figure 4 Figure 1 shows examples of signals that may occur during operation of a gate driver for a power semiconductor. Figure 4 , the signals In, VGmeas, VGexp, and the signal D as the signal at the output of the differential detection module 13 are shown during different intervals marked T1 to T6 .
[0073] In the time interval T1, the signals VGmeas and VGexp are almost the same. The shapes of the signals VGmeas and VGexp represent the normal operation of the gate driver 12 and the power semiconductor S1.
[0074] During the time interval T2, the output of the gate driver 12 provides an erroneous logic level and the signal difference D saturates indicating a fault.
[0075] During time interval T3, the input characteristic of power semiconductor S1 presents a lower resistance (eg, gate resistor short circuit), and the signal difference D indicates an anomaly as a short and high-value pulse during the transition. Furthermore, during the transition, the differential signal D has an opposite sign compared to normal operation.
[0076] During the time interval T4, the input characteristic of the power semiconductor S1 presents a higher resistance (twice greater than normal), and the differential signal D indicates the abnormality as a large and high-valued pulse.
[0077] During the time interval T5 , the power supply level of the gate driver 12 has a voltage drop, and the differential signal D indicates a constant error that does not return to zero.
[0078] During the time interval T6 , the gate driver 12 has an abnormal delay time, and the differential signal D indicates a spike of a high value during the transition period.
[0079] The diagnostic module 100 may compare the differential signal D to a threshold value to detect degradation, such as the example given in time intervals T2, T3, and T6. The value of the threshold value is predefined, or initially automatically defined (e.g., 120% of the maximum value observed during the first 100 cycles of operation), or continuously automatically defined (e.g., until 120% of the maximum value observed so far). The diagnostic module 100 may integrate the differential signal D to detect degradation, such as the degradation disclosed in time interval T5. The diagnostic module 100 may check whether the signal D is within a predetermined envelope stored in a memory in order to detect degradation.
[0080] exist Figure 5 An example of such an envelope is given in . Figure 5 An example of an envelope used by the diagnostic module to determine whether a fault has occurred during operation of the drive and power semiconductors.
[0081] The envelope EnvA corresponds to Figure 4 The envelope EnvB corresponds to the signal in the time interval T1. Figure 4 The envelope EnvC corresponds to the signal in the time interval T2. Figure 4 The signal is shown in the time interval T3.
[0082] The envelope EnvD corresponds to Figure 4 The envelope EnvE corresponds to the signal shown in the time interval T4. Figure 4 The envelope EnvF corresponds to the signal shown in the time interval T5. Figure 4 The signal is shown in the time interval T6.
[0083] Figure 6 The average value, minimum value, maximum value, and integrated value corresponding to the differences observed when no degradation occurs and when various degradations occur are shown.
[0084] The calculation marked as calc1 corresponds to the calculation of Figure 4The calculation result labeled Me1 corresponds to the average value of the signal shown in the time interval T1, the calculation result labeled Mi1 corresponds to the minimum value of the signal as shown in the time interval T1, the calculation result labeled Ma1 corresponds to the maximum value of the signal as shown in the time interval T1, and the calculation result labeled In1 corresponds to the integral of the signal as shown in the time interval T1.
[0085] The calculations in the section marked calc2 correspond to the calculations Figure 4 The calculation result labeled Me2 corresponds to the average value of the signal as shown in the time interval T2, the calculation result labeled Mi2 corresponds to the minimum value of the signal as shown in the time interval T2, the calculation result labeled Ma2 corresponds to the maximum value of the signal as shown in the time interval T2, and the calculation result labeled In2 corresponds to the integral of the signal as shown in the time interval T2.
[0086] The calculations in the section marked calc3 correspond to the calculations Figure 4 The calculation result labeled Me3 corresponds to the average value of the signal as shown in the time interval T3, the calculation result labeled Mi3 corresponds to the minimum value of the signal as shown in the time interval T3, the calculation result labeled Ma3 corresponds to the maximum value of the signal as shown in the time interval T3, and the calculation result labeled In3 corresponds to the integral of the signal as shown in the time interval T3.
[0087] The calculations in the section marked calc4 correspond to the calculations Figure 4 The calculation result labeled Me4 corresponds to the average value of the signal as shown in the time interval T4, the calculation result labeled Mi4 corresponds to the minimum value of the signal as shown in the time interval T4, the calculation result labeled Ma4 corresponds to the maximum value of the signal as shown in the time interval T4, and the calculation result labeled In4 corresponds to the integral of the signal as shown in the time interval T4.
[0088] The calculation marked as calc5 corresponds to the calculation of Figure 4 The calculation result labeled Me5 corresponds to the average value of the signal as shown in the time interval T5, the calculation result labeled Mi5 corresponds to the minimum value of the signal as shown in the time interval T5, the calculation result labeled Ma5 corresponds to the maximum value of the signal as shown in the time interval T5, and the calculation result labeled In5 corresponds to the integral of the signal as shown in the time interval T5.
[0089] The calculations in the section labeled calc6 correspond to the calculations Figure 4 The calculation result labeled Me6 corresponds to the average value of the signal as shown in the time interval T6, the calculation result labeled Mi6 corresponds to the minimum value of the signal as shown in the time interval T6, the calculation result labeled Ma6 corresponds to the maximum value of the signal as shown in the time interval T6, and the calculation result labeled In6 corresponds to the integral of the signal as shown in the time interval T6.
[0090] For example, if the average value is better than the null value, the value is considered to correspond to no degradation, otherwise the value is considered to correspond to degradation. If the minimum value is better than the negative ten value, the value is considered to correspond to no degradation, otherwise the value is considered to correspond to degradation. If the maximum value is better than the ten value, the value is considered to correspond to no degradation, otherwise the value is considered to correspond to degradation. If the integrated value is better than the negative five, the value is considered to correspond to no degradation, otherwise the value is considered to correspond to degradation.
[0091] These calculations can be implemented with simple fast analog circuits. Comparison of these indicators with threshold values gives unique patterns that allow identification of degradation as described above. If one of the comparisons shows degradation, the diagnostic module detects degradation. The diagnostic module can provide the comparison result as an output signal.
[0092] As a result, if degradation has occurred, the alarm block 206 or the output signal Out is activated to notify that degradation has occurred and what kind of degradation has occurred.
[0093] If such degradation occurs, the differential signal D and / or the comparison result is stored by the diagnostic module in order to provide data that may be useful to maintenance personnel.
[0094] In a variant of operation, the diagnostic module performs an initial verification of communication with the gate driver. In this mode, the gate driver is disabled so that VGmeas=0. Therefore, D=VGexp and the signal D is the image of the input signal. Thus, in the case of a misconnection of the input or output signal, or in the case of a fault in the regulator, an anomaly is easily detected.
Claims
1. A device for monitoring a gate signal of a power semiconductor, wherein the gate signal of the power semiconductor is provided by a gate driver, wherein: The device includes: means for generating an expected reference signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and the power semiconductor and a load coupled to the power semiconductor; means for comparing said expected reference signal with said signal output by said gate driver; Means for determining whether degradation exists in the gate driver and the power semiconductor and a load coupled to the power semiconductor using a comparison result of the expected reference signal and the signal output by the gate driver.
2. The device according to claim 1, wherein: The means for generating the expected reference signal comprises at least a capacitor and a resistor.
3. The device according to claim 1, wherein: The gate driver and the means for generating the expected reference signal are each configured to receive a pulse width modulated signal and a signal derived from a connection of the power semiconductor different from the gate signal.
4. The device according to claim 2, wherein: The gate driver and the means for generating the expected reference signal are each configured to receive a pulse width modulated signal and a signal derived from a connection of the power semiconductor different from the gate signal.
5. The device according to any one of claims 1 to 4, wherein: The means for determining whether degradation has occurred processes a comparison result of the expected reference signal with the signal output by the gate driver by comparing the comparison result with a threshold value.
6. The device according to any one of claims 1 to 4, wherein: The means for determining whether degradation has occurred processes a comparison result of the expected reference signal with the signal output by the gate driver by comparing the comparison result with a stored signal envelope.
7. The device according to claim 5, wherein: The value of the threshold is predetermined.
8. The device according to claim 5, wherein: The value of the threshold is equal to X% of the corresponding maximum value observed during the first 100 operating cycles of the device, X% being predefined and higher than 100%.
9. The device according to claim 5, wherein: The value of the threshold is equal to X% of the maximum value observed since the start of operation of the device, X% being predefined and higher than 100%.
10. A method for monitoring a gate signal of a power semiconductor, wherein the gate signal of the power semiconductor is provided by a gate driver, wherein: The method comprises the following steps: generating an expected reference signal corresponding to a signal output by the gate driver in the absence of degradation of the gate driver and the power semiconductor and a load coupled to the power semiconductor; means for comparing said expected reference signal with said signal output by said gate driver; Means for determining whether the gate driver and the power semiconductor and a load coupled to the power semiconductor are degraded using a comparison result of the expected reference signal with the signal output by the gate driver.