Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a layer to be etched; an initial sacrificial layer located on the layer to be etched; a protective layer located on the initial sacrificial layer, the density of the protective layer being greater than the density of the initial sacrificial layer, and the density of the protective layer being greater than the density of the oxide of the initial sacrificial layer; and a mask structure located on the protective layer. The pattern formed by the semiconductor structure has good stability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous improvement of VLSI performance, the gradual reduction of device size and the continuous increase in density, the process nodes continue to shrink. Due to the insufficient light source power of the next generation of lithography technology, extreme ultraviolet lithography (EUV), its time to put into mass production has been delayed, so the 193 nanometer (nm) deep ultraviolet (DUV) immersion lithography technology will inevitably continue to be used for a long time. However, the resolution of a single exposure of deep ultraviolet immersion lithography technology is about 38 nanometers (nm). To further reduce the process node, a new process method must be used: self-aligned multiple patterning (SAMP), which first uses a lithography process to form a mandrel (Mandrel or Core), and then forms (once or multiple times) a sidewall (Spacer) structure on both sides of each mandrel, and finally removes the mandrel by a selective etching process. The density of the remaining sidewall structure can be several times higher than that of the original mandrel. When 193nm deep ultraviolet immersion lithography is used in combination with the SAMP process, the spatial half-period of the circuit can be reduced several times. The self-aligned triple patterning technology (SATP) in SAMP can reduce the circuit half-period to about 13nm, the self-aligned quadruple patterning technology (SAQP) can reduce the half-period to about 10nm, and the self-aligned sextuple patterning technology (SASP) can reduce the half-period to about 7nm.

[0003] Developing in parallel with the self-aligned multiple forming technology (SAMP) is the introduction of a variety of pattern-forming materials. The materials can be modified under appropriate conditions. Under certain conditions, the modified materials have a larger etching selectivity ratio than the original materials, thereby being able to form an ordered pattern of structural units of nanometer (nm) size, forming the pattern of the semiconductor structure to be formed.

[0004] However, as the semiconductor technology node is further reduced, the existing method of using material modification as a pattern to form a semiconductor structure needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the pattern of forming the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a layer to be etched; an initial sacrificial layer located on the layer to be etched; a protective layer located on the initial sacrificial layer, the density of the protective layer is greater than the density of the initial sacrificial layer, and the density of the protective layer is greater than the density of the initial sacrificial layer oxide; and a mask structure located on the protective layer.

[0007] Optionally, the material of the protective layer includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, silicon oxycarbide, titanium nitride, aluminum nitride and aluminum oxide.

[0008] Optionally, the material of the initial sacrificial layer includes an amorphous material;

[0009] The amorphous material includes amorphous silicon (a-Si, Amorphous Silicon).

[0010] Optionally, the thickness of the protective layer is in the range of

[0011] Optionally, the protection layer exposes a portion of the top surface of the initial sacrificial layer.

[0012] Optionally, the layer to be etched includes: a substrate, a device layer located on the substrate, and a transition layer located on the device layer, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode or a metal wire, etc.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; forming an initial protective layer on the initial sacrificial layer, the density of the initial protective layer is greater than the density of the initial sacrificial layer, and the density of the initial protective layer is greater than the density of the initial sacrificial layer oxide; forming a mask structure on the initial protective layer, the mask structure exposing a portion of the surface of the initial protective layer; using the mask structure as a mask, modifying the initial sacrificial layer, forming a modified sacrificial layer on the layer to be etched, and forming a sacrificial layer on the layer to be etched; after forming the modified sacrificial layer, removing the mask structure and the initial protective layer; after removing the initial protective layer, removing the modified sacrificial layer.

[0014] Optionally, after forming the mask structure and before performing the modification treatment on the initial sacrificial layer, the method further includes: using the mask structure as a mask to remove a portion of the initial protective layer until the surface of the initial sacrificial layer is exposed to form a protective layer.

[0015] Optionally, the process of removing part of the initial protective layer includes a dry etching process.

[0016] Optionally, the material of the initial protective layer includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, silicon oxycarbide, titanium nitride, aluminum nitride and aluminum oxide.

[0017] Optionally, the process of forming the initial protection layer includes a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a thermal treatment process.

[0018] Optionally, the process of removing the initial protective layer includes a wet etching process.

[0019] Optionally, the thickness of the initial protective layer is in the range of

[0020] Optionally, the process of removing the modified sacrificial layer includes a dry etching process.

[0021] Optionally, the material of the initial sacrificial layer includes an amorphous material.

[0022] Optionally, the amorphous material includes amorphous silicon (a-Si, Amorphous Silicon).

[0023] Optionally, the process of modifying the initial sacrificial layer includes an ion implantation process, and the implanted ions include carbon ions, nitrogen ions or fluorine ions.

[0024] Optionally, after removing the modified sacrificial layer, the method further includes: forming a side wall on the side wall of the sacrificial layer; after forming the side wall, removing the sacrificial layer; after removing the sacrificial layer, etching the layer to be etched using the side wall as a mask to form a groove in the layer to be etched; and forming a conductive layer in the groove.

[0025] Optionally, the material of the conductive layer includes metal, and the metal includes a combination of one or more of copper, cobalt, nickel and titanium nitride.

[0026] Optionally, the method for forming the conductive layer includes: forming a conductive material layer in the groove and on the surface of the layer to be etched; and planarizing the conductive material layer until the surface of the layer to be etched is exposed to form the conductive layer.

[0027] Optionally, the process of removing the sacrificial layer includes a wet etching process.

[0028] Optionally, the method for forming the sidewall includes: forming a sidewall material layer on the layer to be etched, the top surface of the sacrificial layer and the sidewall surface; etching back the sidewall material layer until the surface of the layer to be etched is exposed, and forming a sidewall on the sidewall of the sacrificial layer.

[0029] Optionally, the material of the sidewall includes inorganic material.

[0030] Optionally, the inorganic material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, silicon carbide and titanium oxide.

[0031] Optionally, the layer to be etched includes: a substrate, a device layer located on the substrate, and a transition layer located on the device layer, the device layer includes an isolation structure and a device structure located within the isolation structure; the device structure includes a transistor, a diode, a triode or a metal wire.

[0032] Optionally, the process of removing the mask structure includes a dry etching process.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] In the semiconductor structure of the technical solution of the present invention, the initial sacrificial layer has a protective layer, so that the protective layer can protect the initial sacrificial layer, preventing the initial sacrificial layer from being damaged or forming defect impurities on the surface during lithography, etching, modification and subsequent mask structure removal processes, thereby preventing the damage and defect impurities from being transmitted downward along with the pattern formed by the initial sacrificial layer and causing semiconductor structure defects, thereby improving the performance of the formed semiconductor structure.

[0035] Furthermore, the protective layer exposes a portion of the top surface of the initial sacrificial layer, and the mask structure is located on the protective layer, so that when the initial sacrificial layer is subsequently modified using the mask structure as a mask, such as ion implantation or doping, the protective layer can locate the position of the modification treatment, thereby avoiding the problem of the position of the initial sacrificial layer being offset due to damage to the mask structure during the modification process.

[0036] In the formation method of the technical solution described in the present invention, an initial protective layer is formed on the initial sacrificial layer, so that the initial protective layer can protect the initial sacrificial layer and prevent the initial sacrificial layer from being damaged during lithography, etching, modification and subsequent mask structure removal processes, thereby preventing the formation of defect impurities on the surface of the initial sacrificial layer. The defect impurities are transmitted downward along with the pattern formed by the initial sacrificial layer to cause semiconductor structure defects, thereby improving the performance of the formed semiconductor structure.

[0037] Furthermore, a portion of the initial protective layer is removed to form a protective layer. When the initial sacrificial layer is modified using the mask structure as a mask, the protective layer can locate the position of the modification treatment, thereby avoiding the problem of the position of the initial sacrificial layer being shifted due to damage to the mask structure during the modification treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0039] Figures 4 to 13 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] As described in the background art, the existing method of forming patterns needs to be improved. Now, it is analyzed and explained in conjunction with specific embodiments.

[0041] Figures 1 to 3 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0042] Please refer to Figure 1 , providing a substrate 100; forming a dielectric layer 101 on the substrate 100; forming a transition layer 102 on the dielectric layer 101; forming an initial sacrificial layer 103 on the transition layer 102; forming a patterned layer 104 on the initial sacrificial layer 103, wherein the patterned layer 104 exposes a portion of the surface of the initial sacrificial layer 103; using the patterned layer 104 as a mask, ion implantation is performed on the initial sacrificial layer 103 to form a modified sacrificial layer 105.

[0043] Please refer to Figure 2 , remove the patterned layer 104 ; remove the modified sacrificial layer 105 ; and form a sidewall 108 on the sidewall of the initial sacrificial layer 103 .

[0044] Please refer to Figure 3, removing the initial sacrificial layer 103 ; etching the transition layer 102 and the dielectric layer 101 using the sidewall 108 as a mask until the surface of the substrate 100 is exposed, and forming a groove 109 in the dielectric layer 101 .

[0045] During the formation of the semiconductor structure, the material of the patterned layer 104 includes photoresist, the material of the initial sacrificial layer 103 includes silicon, the process of removing the patterned layer 104 includes a dry etching process, and the process of removing the initial sacrificial layer 103 includes a wet etching process. Therefore, when removing the patterned layer 104, the dry etching process is likely to cause damage to the surface of the initial sacrificial layer 103, so that the surface of the initial sacrificial layer 103 has defects such as holes, and the reaction byproducts of removing the patterned layer 104 will enter the defects on the surface of the initial sacrificial layer 103 to form impurities 107, and when the initial sacrificial layer 103 is removed by the wet etching process, the impurities 107 are difficult to be completely removed; at the same time, during the pattern transfer process, a part of the material forming the sidewall 108 will also enter the defects on the surface of the initial sacrificial layer 103, and together with the reaction byproducts of the patterned layer 104, form the impurities 107. The impurity 107 will increase in volume as the pattern is transferred layer by layer, and will eventually be formed in the groove 109. When a conductive layer is subsequently formed in the groove 109, the volume of the impurity 107 is relatively large. The impurity 107 in the conductive layer will cause the electrical connection of the conductive layer to be blocked, thereby destroying the conductive performance of the conductive layer, and further affecting the electrical and structural performance of the semiconductor structure.

[0046] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, wherein an initial protective layer is formed on the initial sacrificial layer, so that the protective layer can protect the initial sacrificial layer, thereby preventing the initial sacrificial layer from being damaged or forming defect impurities on the surface during lithography, etching, modification and subsequent mask structure removal processes, so that the defect impurities are transmitted downward along the pattern formed by the initial sacrificial layer, causing semiconductor structure defects, thereby improving the performance of the formed semiconductor structure.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 4 to 13 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0049] Please refer to Figure 4 , providing a layer to be etched.

[0050] The layer to be etched includes: a substrate 200, a device layer 201 located on the substrate 200, and a transition layer 202 located on the device layer 201, the device layer 201 includes an isolation structure (not shown) and a device structure (not shown) located within the isolation structure; the device structure includes a transistor, a diode, a triode or a metal wire, etc.

[0051] The material of the substrate 200 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide or silicon on insulator, etc. The material of the transition layer 202 includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride and silicon oxycarbon nitride.

[0052] In this embodiment, the material of the substrate 200 includes silicon; the material of the transition layer 202 includes silicon nitride.

[0053] The transition layer 202 is used to stably transfer the pattern to the layer to be etched.

[0054] Please refer to Figure 5 , forming an initial sacrificial layer 203 on the layer to be etched.

[0055] The material of the initial sacrificial layer 203 includes an amorphous material.

[0056] In this embodiment, the material of the initial sacrificial layer 203 includes amorphous silicon (a-Si, Amorphous Silicon). The material of the initial sacrificial layer 203 includes amorphous silicon (a-Si, Amorphous Silicon), and the initial sacrificial layer is subsequently modified to form a modified sacrificial layer, and the modified sacrificial layer can have a larger etching selectivity ratio with the initial sacrificial layer, so that when the modified sacrificial layer is subsequently removed, the removal process causes less damage to the initial sacrificial layer, so that the initial sacrificial layer can form a pattern with good morphology and precise size, and then after the pattern is transferred to the layer to be etched, a semiconductor structure with good morphology and precise size can be formed.

[0057] The process of forming the initial sacrificial layer 203 includes a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal treatment process, or the like.

[0058] In this embodiment, the process of forming the initial sacrificial layer 203 includes a chemical vapor deposition (CVD) process.

[0059] Please continue to refer to Figure 5 , an initial protection layer 204 is formed on the initial sacrificial layer 203 , the density of the initial protection layer 204 is greater than the density of the initial sacrificial layer 203 , and the density of the initial protection layer 204 is greater than the density of the oxide of the initial sacrificial layer 203 .

[0060] The density of the initial protective layer 204 is greater than the density of the initial sacrificial layer 203, so that in the subsequent process of removing the mask structure, the initial protective layer 204 can protect the initial sacrificial layer 203, and prevent the initial sacrificial layer 203 from being damaged during lithography (Litho), etching (Etch), modification treatment and subsequent removal of the mask structure. When defect impurities are formed on the surface, the initial protective layer 204 can block the defect impurities from entering the surface of the initial sacrificial layer 203, thereby preventing the defect impurities from being transferred downward along with the pattern formed by the initial sacrificial layer 203; the density of the initial protective layer 204 is greater than the density of the oxide of the initial sacrificial layer 203, so that the initial protective layer 204 can block the defect impurities from entering the oxide layer on the surface of the initial sacrificial layer 203, thereby preventing the defect impurities from being transferred downward along with the pattern formed by the initial sacrificial layer 203.

[0061] The material of the initial protection layer 204 includes one or more of silicon nitride, silicon carbide nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, silicon oxycarbide, titanium nitride, aluminum nitride and aluminum oxide. The process of forming the initial protection layer 204 includes a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a thermal treatment process.

[0062] In this embodiment, the material of the initial protective layer 204 includes silicon nitride; the process for forming the initial protective layer 204 includes an atomic layer deposition (ALD) process, and the atomic layer deposition (ALD) process can form an initial protective layer 204 with a dense structure and uniform thickness, so that the initial protective layer 204 can protect the initial sacrificial layer 203, and prevent the initial sacrificial layer 203 from being damaged during lithography (Litho), etching (Etch), modification treatment and subsequent removal of the mask structure, thereby avoiding the formation of defect impurities on the surface of the initial sacrificial layer 203. The defect impurities are transmitted downward along with the pattern formed by the initial sacrificial layer 203 to cause semiconductor structure defects, thereby improving the performance of the formed semiconductor structure.

[0063] In this embodiment, the thickness of the initial protective layer 204 is in the range of

[0064] If the thickness of the initial protective layer 204 is too thin, i.e., less than The protective effect of the initial protective layer 204 on the initial sacrificial layer 203 is not obvious; if the thickness of the initial protective layer 204 is too thick, that is, greater than Subsequent removal requires more complicated process conditions, longer process cycles and higher process costs, thus resulting in process waste.

[0065] Please refer to Figure 6 , a mask structure is formed on the initial protection layer 204 , wherein the mask structure exposes a portion of the surface of the initial protection layer 204 .

[0066] The patterned mask structure includes: a liner layer 205 ; an anti-reflection layer 206 located on the liner layer; and a photoresist layer 207 located on the anti-reflection layer 206 .

[0067] The method for forming the mask structure includes: forming a liner material layer (not shown) on the initial protective layer 204; forming an anti-reflective material layer (not shown) on the liner material layer; forming a patterned photoresist layer 207 on the anti-reflective material layer; etching the anti-reflective material layer and the liner material layer using the patterned photoresist layer 207 as a mask until the surface of the initial protective layer 204 is exposed to form the mask structure.

[0068] The material of the pad layer 205 includes an organic material or an inorganic material; the organic material includes a carbon-containing organic material or a silicon-containing organic material; the inorganic material includes a combination of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. The material of the anti-reflection layer 206 includes an organic material or an inorganic material, the organic material includes a silicon-containing organic material, and the inorganic material includes silicon nitride, silicon carbide nitride, or titanium nitride. The process of etching the anti-reflection material layer and the pad material layer includes a combination of one or more of a dry etching process and a wet etching process.

[0069] In this embodiment, the material of the liner layer 205 includes organic matter containing carbon; the material of the anti-reflection layer 206 includes silicon nitride. The process of etching the anti-reflection material layer and the liner material layer includes a dry etching process, and the dry etching process can form a mask structure with good sidewall morphology, so that the size of the initial protection layer 204 exposed by the mask structure can be accurately controlled. When the initial sacrificial layer 203 is subsequently modified, the modified area can be accurately controlled, so that the size accuracy of the subsequently formed pattern is better.

[0070] Please refer to Figure 7 , using the patterned mask structure as a mask, partially remove the initial protection layer 204 until the surface of the initial sacrificial layer 203 is exposed, thereby forming a protection layer 208 .

[0071] Part of the initial protective layer 204 is removed to form a protective layer 208. When the initial sacrificial layer 203 is modified using the mask structure as a mask, the protective layer 208 can locate the position of the modification treatment to prevent the mask structure from being damaged during the modification treatment, causing the position of the modification treatment to be offset.

[0072] The process of removing part of the initial protection layer 204 includes a combination of one or more of a dry etching process and a wet etching process.

[0073] In this embodiment, the process of removing part of the initial protective layer 204 includes a dry etching process, and the dry etching process can accurately remove the initial protective layer 204 exposed by the mask structure, so that the formed protective layer 208 can locate the position of the modification treatment, thereby avoiding the mask structure being damaged during the modification treatment, causing the position of the modification treatment to be offset.

[0074] In other embodiments, the initial protection layer exposed by the mask structure may not be removed.

[0075] Please refer to Figure 8 , using the patterned mask structure as a mask, the initial sacrificial layer 203 is modified to form a modified sacrificial layer 209 on the layer to be etched, and a sacrificial layer 210 is formed on the layer to be etched.

[0076] In this embodiment, the process of modifying the initial sacrificial layer 203 includes an ion implantation process, and the implanted ions include carbon ions, nitrogen ions or fluorine ions.

[0077] The initial sacrificial layer 203 is ion implanted, and the modified sacrificial layer 209 and the sacrificial layer 210 formed after the ion implantation have a large etching selectivity ratio, so that when the modified sacrificial layer 209 is subsequently removed, the removal process causes less damage to the sacrificial layer 210, so that the sacrificial layer 210 can form a pattern with good morphology and precise size, and then after the pattern is transferred to the layer to be etched, a semiconductor structure with good morphology and precise size can be formed.

[0078] In other embodiments, the process of modifying the initial sacrificial layer includes a doping process.

[0079] In other embodiments, the initial protective layer exposed by the mask structure is not removed, and when ion implantation is performed on the initial sacrificial layer, the implanted ions can pass through the initial protective layer and reach the initial sacrificial layer to form the modified sacrificial layer.

[0080] Please refer to Fig. 9 After forming the modified sacrificial layer 209, the mask structure is removed.

[0081] The process of removing the mask structure includes a dry etching process and a wet etching process or a combination of one or more of the above.

[0082] In this embodiment, the process of removing the mask structure includes a dry etching process, which can remove the mask structure quickly and efficiently.

[0083] In the process of removing the mask structure, the protective layer 208 can protect the sacrificial layer 210, preventing the sacrificial layer 210 from being damaged during the processes of photolithography (Litho), etching (Etch), modification and removal of the mask structure, thereby preventing the formation of defect impurities on the surface of the sacrificial layer 210. The defect impurities are transmitted downward along the pattern formed by the sacrificial layer 210 to cause semiconductor structure defects, thereby improving the performance of the formed semiconductor structure.

[0084] Please continue to refer to Fig. 9 After removing the mask structure, the protection layer 208 is removed.

[0085] The process of removing the protection layer 208 includes a dry etching process and a wet etching process or a combination of one or more of the above.

[0086] In this embodiment, the process of removing the protection layer 208 includes a wet etching process.

[0087] In this embodiment, the solution of the wet etching process includes a hydrofluoric acid solution, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is in the range of 1:50 to 1:300, and the etching time is in the range of 30 seconds to 30 minutes.

[0088] In another embodiment, the solution of the wet etching process includes a 50% concentration phosphoric acid solution, and the etching time is 5 minutes to 30 minutes.

[0089] The wet etching process is used to remove the protective layer 208, so that in the process of removing the mask structure, the defect impurities formed on the surface of the protective layer 208 are also removed, thereby avoiding the defect impurities from being transferred downward along with the pattern formed by the sacrificial layer 210, thereby improving the structural performance and electrical connection performance of the formed semiconductor.

[0090] Please continue to refer to Fig. 9 After removing the protection layer 208 , the modified sacrificial layer 209 is removed.

[0091] The process of removing the modified sacrificial layer 209 includes a combination of one or more of a dry etching process and a wet etching process.

[0092] In this embodiment, the process of removing the modified sacrificial layer 209 includes a dry etching process, and the etching gas of the dry etching process has a large etching selectivity ratio for the sacrificial layer 210. Therefore, when removing the modified sacrificial layer 209, the dry etching process causes less damage to the sacrificial layer 210, so that the sacrificial layer 210 can form a pattern with good morphology and precise size, and then after the pattern is transferred to the layer to be etched, a semiconductor structure with good morphology and precise size can be formed.

[0093] Please refer to Fig.10 After removing the modified sacrificial layer 209 , a sidewall 211 is formed on the sidewall of the sacrificial layer 210 .

[0094] The method for forming the sidewall 211 includes: forming a sidewall material layer (not shown) on the layer to be etched, the top surface of the sacrificial layer 210 and the sidewall surface; etching back the sidewall material layer until the surface of the layer to be etched is exposed, and forming the sidewall 211 on the sidewall of the sacrificial layer 210.

[0095] The material of the sidewall 211 includes an inorganic material, and the inorganic material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide and titanium oxide. The process of forming the sidewall material layer includes a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0096] In this embodiment, the material of the spacer 211 includes titanium oxide; and the process of forming the spacer material layer includes a chemical vapor deposition (CVD) process.

[0097] Please refer to Fig.11 After forming the sidewall 211, the sacrificial layer 210 is removed.

[0098] The process of removing the sacrificial layer 210 includes a combination of one or more of a dry etching process and a wet etching process. In the present embodiment, the process of removing the sacrificial layer 210 includes a wet etching process, and the wet etching process can remove the sacrificial layer 210 completely, thereby avoiding the sacrificial layer 210 from remaining on the layer to be etched, thereby affecting the morphology of the semiconductor structure formed subsequently.

[0099] Please refer to Fig.12 After removing the sacrificial layer 210 , the transition layer 202 and the device layer 201 are etched using the sidewall 211 as a mask to form a groove 212 in the device layer 201 , wherein the groove 212 exposes a portion of the device structure in the device layer 201 .

[0100] The process of etching the transition layer 202 and the device layer 201 includes a combination of one or more of a dry etching process and a wet etching process. In this embodiment, the process of etching the transition layer 202 and the device layer 201 includes a dry etching process, and the dry etching process can stably transfer the pattern of the sidewall 211 to the layer to be etched, so that the formed semiconductor structure has good morphology and dimensional accuracy.

[0101] Please refer to Fig.13 , a conductive layer 213 is formed in the groove 212 .

[0102] The method for forming the conductive layer 213 includes: forming a conductive material layer (not shown) in the groove 212 and on the surface of the device layer 201 ; and planarizing the conductive material layer until the surface of the device layer 201 is exposed to form the conductive layer 213 .

[0103] The conductive layer 213 may be made of metal, which may be one or more of copper, cobalt, nickel, tantalum, tantalum nitride, tungsten and titanium nitride. The conductive material layer may be formed by physical vapor deposition (PVD) or electroplating.

[0104] In this embodiment, the material of the conductive layer 213 includes copper; the process of forming the conductive material layer includes a physical vapor deposition (PVD) process; and the process of planarizing the conductive material layer includes a chemical mechanical polishing (CMP) process.

[0105] At this point, an initial protective layer is formed on the initial sacrificial layer, so that the initial protective layer can protect the initial sacrificial layer and prevent the initial sacrificial layer from being damaged in the subsequent process of removing the mask structure, thereby preventing defect impurities from being formed on the surface of the initial sacrificial layer. The defect impurities are transmitted downward along the pattern formed by the initial sacrificial layer, causing the formed semiconductor structure to be defective, thereby improving the performance of the formed semiconductor structure.

[0106] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please refer to Figure 7 ,include:

[0107] A layer to be etched;

[0108] An initial sacrificial layer 203 located on the layer to be etched;

[0109] A protection layer 208 located on the initial sacrificial layer 203, wherein the density of the protection layer 208 is greater than the density of the initial sacrificial layer 203, and the density of the protection layer 208 is greater than the density of the oxide of the initial sacrificial layer 203;

[0110] The mask structure is located on the protection layer 203 .

[0111] In the present embodiment, the material of the protection layer 208 includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, silicon oxycarbide, titanium nitride, aluminum nitride and aluminum oxide.

[0112] In this embodiment, the material of the initial sacrificial layer 203 includes an amorphous material;

[0113] In this embodiment, the amorphous material includes amorphous silicon (a-Si).

[0114] In this embodiment, the thickness of the protective layer 208 is in the range of

[0115] In this embodiment, the protection layer 208 exposes a portion of the top surface of the initial sacrificial layer 203 .

[0116] In this embodiment, the layer to be etched includes: a substrate 200, a device layer 201 located on the substrate 200, and a transition layer 202 located on the device layer 201, the device layer 201 includes an isolation structure (not shown) and a device structure (not shown) located within the isolation structure, and the device structure includes a transistor, a diode, a triode or a metal wire, etc.

[0117] In this embodiment, the patterned mask structure includes: a liner layer 205 ; an anti-reflection layer 206 located on the liner layer 205 ; and a photoresist layer 207 located on the anti-reflection layer 206 .

[0118] In this embodiment, the material of the pad layer 206 includes organic material or inorganic material; the organic material includes carbon-containing organic matter or silicon-containing organic matter; the inorganic material includes one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride and silicon carbide.

[0119] In this embodiment, the material of the anti-reflection layer 207 includes an organic material or an inorganic material. The organic material includes a silicon-containing organic material, and the inorganic material includes silicon nitride, silicon carbide, or titanium nitride.

[0120] In the semiconductor structure, a protective layer 208 is provided on the initial sacrificial layer 203, so that the protective layer 208 can protect the initial sacrificial layer 203, and prevent the initial sacrificial layer 203 from being damaged or forming defect impurities on the surface during lithography (Litho), etching (Etch), modification treatment and subsequent mask structure removal processes, so that the defect impurities are transmitted downward along the pattern formed by the initial sacrificial layer 203, causing semiconductor structure defects, thereby improving the performance of the formed semiconductor structure.

[0121] Furthermore, the protective layer 208 exposes a portion of the top surface of the initial sacrificial layer 203, and the mask structure is located on the protective layer 208, so that when the initial sacrificial layer 203 is subsequently modified using the mask structure as a mask, the protective layer 208 can locate the position of the modification treatment, thereby avoiding the problem of the position of the modification treatment being offset when the mask structure is damaged during the modification treatment.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; forming an initial protective layer on the initial sacrificial layer, wherein the density of the initial protective layer is greater than the density of the initial sacrificial layer, and the density of the initial protective layer is greater than the density of the oxide of the initial sacrificial layer; Forming a mask structure on the initial protective layer, wherein the mask structure exposes a portion of the surface of the initial protective layer, the mask structure comprising: a liner layer, an anti-reflection layer on the liner layer, and a photoresist layer on the anti-reflection layer, wherein the material of the liner layer comprises an organic material; Using the mask structure as a mask, modifying the initial sacrificial layer to form a modified sacrificial layer on the layer to be etched, and forming a sacrificial layer on the layer to be etched; After forming the modified sacrificial layer, removing the mask structure and the initial protective layer; After removing the initial protection layer, the modified sacrificial layer is removed.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that After forming the mask structure and before modifying the initial sacrificial layer, the method further includes: using the mask structure as a mask to remove part of the initial protective layer until the surface of the initial sacrificial layer is exposed to form a protective layer.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The process of removing part of the initial protection layer includes a dry etching process.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the initial protection layer includes one or more combinations of silicon nitride, silicon carbide nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, silicon oxycarbide, titanium nitride, aluminum nitride and aluminum oxide.

5. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process of forming the initial protection layer includes a chemical vapor deposition process, an atomic layer deposition process or a thermal treatment process.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process of removing the initial protection layer includes a wet etching process.

7. The method for forming a semiconductor structure according to claim 1, It is characterized in that The thickness of the initial protective layer ranges from 10 angstroms to 100 angstroms.

8. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process of removing the modified sacrificial layer includes a dry etching process.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the initial sacrificial layer includes an amorphous material.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The amorphous material includes amorphous silicon.

11. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process of modifying the initial sacrificial layer includes an ion implantation process, and the implanted ions include carbon ions, nitrogen ions or fluorine ions.

12. The method for forming a semiconductor structure according to claim 1, It is characterized in that After removing the modified sacrificial layer, the method further includes: forming a side wall on the side wall of the sacrificial layer; after forming the side wall, removing the sacrificial layer; after removing the sacrificial layer, etching the layer to be etched using the side wall as a mask to form a groove in the layer to be etched; and forming a conductive layer in the groove.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that The material of the conductive layer includes metal, and the metal includes one or more combinations of copper, cobalt, nickel and titanium nitride.

14. The method for forming a semiconductor structure according to claim 12, It is characterized in that The method for forming the conductive layer comprises: forming a conductive material layer in the groove and on the surface of the layer to be etched; and planarizing the conductive material layer until the surface of the layer to be etched is exposed to form the conductive layer.

15. The method for forming a semiconductor structure according to claim 12, It is characterized in that The process of removing the sacrificial layer includes a wet etching process.

16. The method for forming a semiconductor structure according to claim 12, It is characterized in that The method for forming the sidewall comprises: forming a sidewall material layer on the layer to be etched, the top surface of the sacrificial layer and the sidewall surface; etching back the sidewall material layer until the surface of the layer to be etched is exposed, and forming a sidewall on the sidewall of the sacrificial layer.

17. The method for forming a semiconductor structure according to claim 12, It is characterized in that The material of the sidewall includes inorganic material.

18. The method for forming a semiconductor structure according to claim 17, It is characterized in that The inorganic material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, silicon carbide and titanium oxide.

19. The method for forming a semiconductor structure according to claim 1, It is characterized in that The layer to be etched includes: a substrate, a device layer located on the substrate and a transition layer located on the device layer, the device layer includes an isolation structure and a device structure located in the isolation structure; the device structure includes a transistor, a diode, a triode or a metal wire.

20. The method for forming a semiconductor structure according to claim 3, It is characterized in that The process of removing the mask structure includes a dry etching process.

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