Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate, the substrate comprising a base; a gate structure located on the substrate, the gate structure having one or more areas to be contacted, the top surface of the gate structure having a first isolation layer; a conductive layer located between the gate structures; a second isolation layer located on the conductive layer on both sides of the areas to be contacted; a first dielectric layer located on the substrate, the gate structure, the conductive layer and the second isolation layer, the first dielectric layer having a second opening; a third opening located in the second isolation layer, the second opening exposing the top of the third opening; and gate plugs located in the second opening and the third opening, the gate plugs being electrically connected to the top of the areas to be contacted. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits, the circuit density inside the integrated circuits is getting higher and higher, and the number of components contained is also increasing. This development makes the metal interconnection process on the wafer surface increasingly difficult.

[0003] In order to meet the interconnection line requirements after the components are reduced, the design of the interconnection metal layer has become a method commonly used in the ultra-large-scale integrated circuit technology. At present, the conduction between the interconnection metal layer and the device in the substrate is achieved through contact plugs.

[0004] However, as semiconductor technology nodes are further reduced, the existing contact plug formation process needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a base; a gate structure located on the substrate, the gate structure having one or more areas to be contacted, and the top surface of the gate structure having a first isolation layer; a conductive layer located between the gate structures; a second isolation layer located on the conductive layer on both sides of the areas to be contacted; a first dielectric layer located on the substrate, the gate structure, the conductive layer and the second isolation layer, the first dielectric layer having a second opening; a third opening located in the second isolation layer, the second opening exposing the top of the third opening; gate plugs located in the second opening and in the third opening, the gate plugs being electrically connected to the top of the areas to be contacted.

[0007] Optionally, the substrate further includes: source-drain doped regions, the source-drain doped regions are located in the substrate on both sides of the gate structure, the conductive layer is electrically connected to the source-drain doped regions; and a second dielectric layer, the gate structure is located in the second dielectric layer.

[0008] Optionally, the material of the second isolation layer is different from that of the first isolation layer.

[0009] The method also includes: a second isolation layer located on the conductive layer outside the two sides of the area to be contacted.

[0010] Optionally, the gate structure includes: a gate dielectric layer; a gate layer located on the gate dielectric layer; and a sidewall located on a sidewall of the gate layer.

[0011] Optionally, the substrate further includes: a plurality of fin structures located on the base, the gate structure spanning the fin structures; and a third isolation layer located on the base surface and the sidewall surfaces of the plurality of fin structures, the top surface of the third isolation layer being lower than the top surface of the fin structure.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base; forming a gate structure on the base, the gate structure having one or more areas to be contacted, and the top surface of the gate structure having a first isolation layer; forming a conductive layer between adjacent gate structures; removing part of the conductive layer on both sides of the area to be contacted, forming a first opening in the conductive layer, the first opening exposing the side wall surface of the area to be contacted; forming a second isolation layer in the first opening; forming a first dielectric layer on the substrate, the gate structure, the conductive layer and the second isolation layer, the first dielectric layer having a second opening, the second opening exposing the surface of the first isolation layer on the surface of the area to be contacted; removing the first isolation layer exposed by the second opening, forming a third opening in the second isolation layer; forming gate plugs in the second opening and the third opening.

[0013] Optionally, the method for forming the gate plug includes: forming a plug material layer in the second opening, in the third opening and on the surface of the first dielectric layer; and planarizing the plug material layer until the surface of the first dielectric layer is exposed to form the gate plug.

[0014] Optionally, the method for forming the second opening includes: forming a first mask layer on the surface of the first dielectric layer, the first mask layer exposing the surface of the first dielectric layer at the top surface of the area to be contacted; etching the first dielectric layer using the first mask layer as a mask to form a second opening in the first dielectric layer.

[0015] After forming the conductive layer and before forming the second isolation layer, the method further includes: removing a portion of the conductive layer outside the two sides of the area to be contacted, forming a first opening in the conductive layer, wherein the first opening exposes the sidewall surface of the gate structure.

[0016] Optionally, the substrate further includes: source-drain doped regions, the source-drain doped regions are located in the substrate on both sides of the gate structure, the conductive layer is electrically connected to the source-drain doped regions; and a second dielectric layer, the gate structure is located in the second dielectric layer.

[0017] Optionally, the method for forming the first isolation layer includes: etching back the gate structure to form a first groove in the second dielectric layer; forming a first isolation material layer in the first groove and on the surface of the second dielectric layer; planarizing the first isolation material layer until the surface of the second dielectric layer is exposed, and forming a first isolation layer on the top surface of the gate structure.

[0018] Optionally, the method for forming the conductive layer includes: forming a second mask layer on the surface of the second dielectric layer, the second mask layer exposing the surface of the second dielectric layer on the surface of the source and drain doped regions; etching the second dielectric layer using the second mask layer as a mask until the surface of the source and drain doped regions is exposed, and forming a second groove in the second dielectric layer; forming a conductive material layer in the second groove and on the surface of the second dielectric layer; and planarizing the conductive material layer until the surface of the second dielectric layer is exposed, and forming a conductive layer between gate structures.

[0019] Optionally, the method for forming the second isolation layer includes: forming a third mask layer on the surface of the conductive layer, the third mask layer exposing the conductive layer surfaces on both sides of the area to be contacted and the first isolation layer surface of the area to be contacted; etching the conductive layer using the third mask layer as a mask to form a first opening in the conductive layer; forming a second isolation material layer in the first opening; flattening the second isolation material layer until the top surface of the first isolation layer is exposed, forming a second isolation layer in the first opening.

[0020] Optionally, before forming the third mask layer on the surface of the conductive layer, the method further includes: forming a hard mask layer on the surface of the conductive layer and the surface of the first isolation layer, wherein the material of the hard mask layer is different from that of the first isolation layer.

[0021] Optionally, the material of the hard mask layer includes one or more combinations of amorphous carbon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon carbonitride oxide.

[0022] Optionally, the method for forming the gate structure includes: forming a dummy gate structure on a substrate; forming a second dielectric layer on the substrate, wherein the dummy gate structure is located in the second dielectric layer; removing the dummy gate structure to form a gate opening in the second dielectric layer; and forming a gate structure in the gate opening.

[0023] Optionally, the material of the second isolation layer is different from that of the first isolation layer.

[0024] Optionally, the process of removing the first isolation layer includes a dry etching process.

[0025] Optionally, the gate structure includes: a gate dielectric layer; a gate layer located on the gate dielectric layer; and a sidewall located on a sidewall of the gate layer.

[0026] Optionally, the substrate further includes: a plurality of fin structures located on the base, the gate structure spanning the fin structures; and a third isolation layer located on the base surface and the sidewall surfaces of the plurality of fin structures, the top surface of the third isolation layer being lower than the top surface of the fin structure.

[0027] Optionally, the method further includes: forming source-drain plugs in the first dielectric layer, wherein the source-drain plugs are electrically connected to the conductive layer outside the two sides of the area to be contacted.

[0028] Optionally, the method for forming the source-drain plug includes: forming a fourth mask layer on the surface of the first dielectric layer, the fourth mask layer exposing a portion of the surface of the first dielectric layer; etching the first dielectric layer using the fourth mask layer as a mask until the top surface of the conductive layer is exposed, forming a third groove in the first dielectric layer; and forming a source-drain plug in the third groove.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] The semiconductor structure of the technical solution of the present invention has a second isolation layer on the conductive layer on both sides of the area to be contacted, and a gate plug is provided in the first dielectric layer, and the gate plug is electrically connected to the top of the area to be contacted, so that the second isolation layer can isolate the gate plug from the conductive layer on both sides of the area to be contacted, thereby avoiding the situation that when the position of the gate plug is offset during the formation of the gate plug, the gate plug contacts the conductive layer on both sides of the area to be contacted and short-circuits; at the same time, when the gate plug is formed on the top of the area to be contacted, the second isolation layer can protect the conductive layer on both sides of the area to be contacted, and avoid the process of forming the gate plug from damaging the conductive layer on both sides of the area to be contacted. In summary, the performance of the semiconductor structure is improved, and the utilization rate of the chip area is improved.

[0031] Furthermore, the material of the second isolation layer is different from that of the first isolation layer, so that when the first isolation layer on the surface of the area to be contacted is removed and the third opening is formed in the second isolation layer, the process of removing the first isolation layer has a larger etching selectivity for the second isolation layer, so that the process of removing the first isolation layer causes less damage to the second isolation layer, so that the second isolation layer can protect the conductive layers on both sides of the area to be contacted and avoid the process of forming the gate plug from causing damage to the conductive layers on both sides of the area to be contacted.

[0032] In the method of the technical solution of the present invention, a first isolation layer is formed on the top surface of the gate structure, and a second isolation layer is formed on the surface of the conductive layer on both sides of the area to be contacted, so that when a gate plug is formed on the top of the gate structure, the second isolation layer can protect the conductive layers on both sides of the area to be contacted, and avoid the process of forming the gate plug causing damage to the conductive layers on both sides of the area to be contacted; at the same time, the second isolation layer can fully isolate the conductive layers on both sides of the area to be contacted from the gate plug, and avoid the situation where the gate plug contacts the conductive layers on both sides of the area to be contacted and short-circuit occurs when the position of the gate plug is offset, thereby improving the performance of the semiconductor structure and improving the utilization rate of the chip area.

[0033] Furthermore, the material of the second isolation layer is different from that of the first isolation layer, so that when the first isolation layer on the surface of the area to be contacted is removed and the third opening is formed in the second isolation layer, the process of removing the first isolation layer has a larger etching selectivity for the second isolation layer, so that the process of removing the first isolation layer causes less damage to the second isolation layer, so that the second isolation layer can protect the conductive layers on both sides of the area to be contacted and avoid the process of forming the gate plug from causing damage to the conductive layers on both sides of the area to be contacted. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure in one embodiment;

[0035] Figures 2 to 14 is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment of the present invention;

[0036] Figures 15 to 18 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the existing contact plug forming process needs to be improved. Now, it is analyzed and explained in conjunction with a specific embodiment.

[0038] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor structure in one embodiment.

[0039] Please refer to Figure 1, comprising: a substrate, the substrate comprising a first region I and a second region II, the substrate comprising a base 100 and a fin structure 101 located on the base 100; a first gate structure 105 located on the first region I, the first gate structure 105 spanning the fin structure 101; a second gate structure 104 located on the second region II, the second gate structure 104 spanning the fin structure 101; a first source-drain doped layer 103 in the fin structure 101 on both sides of the first gate structure 105 on the first region I; a first source-drain doped layer 103 in the fin structure 101 on both sides of the second gate structure 104 on the second region II A second source-drain doped layer 102 in the structure 101; an isolation structure 108 located on the surface of the first source-drain doped layer 103; a first metal layer 109 located on the top surface of the first gate structure 105; a second metal layer 106 located on the surface of the second source-drain doped layer 102; a dielectric layer 110 located on the substrate; a gate plug 111 located in the dielectric layer 110, the gate plug 111 is electrically connected to the top of the first gate structure 105; a first source-drain plug 112 located in the dielectric layer 110, the first source-drain plug 112 is electrically connected to the top of the second metal layer 106.

[0040] In the semiconductor structure, the gate plug 111 is electrically connected to the top of the first gate structure 105, and the first source-drain plug 112 is electrically connected to the second source-drain doped layer 102 on the second region II. In the process of forming the gate plug 111, it is necessary to first form a hard mask layer 107, form a first metal layer 109 on the top of the first gate structure 105 through the hard mask layer 107, and then form a dielectric layer 110 on the surface of the first metal layer 109. By forming a through hole in the dielectric layer 110 to expose the surface of the first metal layer 109, and then forming the gate plug 111 in the through hole, the gate plug 111 is electrically connected to the top of the first gate structure 105. The first source-drain plug 112 is electrically connected to the second source-drain doped layer 102 through the second metal layer 106, the second metal layer 106 and the first metal layer 109 are formed simultaneously through the hard mask layer 107, and the first source-drain plug 112 and the gate plug 111 are formed simultaneously.

[0041] Since the size of the semiconductor structure is small, when the gate plug 111 is formed on the top surface of the first gate structure 105 by the above process, due to the influence of precision, the second metal layer cannot be formed on the surface of the first source-drain doped layer 103 at the same time, so as to avoid the position shift of the gate plug 111, thereby short-circuiting the second metal layer on the surface of the first source-drain doped layer 103. Therefore, the hard mask layer 107 covers the surface of the isolation structure 108 on the first source-drain doped layer 103 to ensure that the second metal layer electrically connected to the first source-drain doped layer 103 is not formed, thereby avoiding the gate plug 111 from short-circuiting the second metal layer.

[0042] However, in advanced semiconductor technology, as the size of the semiconductor structure is further reduced, while forming a gate plug 111 on the top surface of the first gate structure 105, it is necessary to form a second metal layer on the surface of the first source-drain doped layer 103 to improve circuit efficiency, increase chip area utilization, achieve miniaturization of semiconductor devices, and adapt to advanced semiconductor processes.

[0043] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by forming a first isolation layer on the top surface of the gate structure, and forming a second isolation layer on the surface of the conductive layer on both sides of the area to be contacted, the material of the second isolation layer is different from the material of the first isolation layer, so that when a gate plug is formed on the top of the gate structure, the second isolation layer can protect the conductive layer on both sides of the area to be contacted, and avoid the process of forming the gate plug causing damage to the conductive layer on both sides of the area to be contacted; at the same time, the second isolation layer can fully isolate the conductive layer on both sides of the area to be contacted from the gate plug, and avoid the situation where the gate plug contacts the conductive layer on both sides of the area to be contacted and short-circuit occurs when the position of the gate plug is offset, thereby improving the performance of the semiconductor structure and improving the utilization rate of the chip area.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 2 to 14 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0046] Please refer to Figure 2 , providing a substrate, wherein the substrate includes a base 200.

[0047] In this embodiment, the substrate also includes: a plurality of fin structures 201 located on the base 200; a third isolation layer (not shown) located on the surface of the base 200 and the sidewall surfaces of the plurality of fin structures 201, wherein the top surface of the third isolation layer is lower than the top surface of the fin structure 201.

[0048] The material of the substrate 200 is single crystal silicon; the material of the fin structure includes single crystal silicon.

[0049] In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator.

[0050] The material of the third isolation layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, and silicon carbide nitride. In this embodiment, the material of the third isolation layer includes silicon oxide.

[0051] In other embodiments, the substrate is a planar substrate.

[0052] Please refer to Figure 3 , a gate structure (not shown) is formed on the substrate, wherein the gate structure has one or more contact regions 202 , and a first isolation layer 206 is formed on the top surface of the gate structure.

[0053] The method for forming the gate structure includes: forming a dummy gate structure (not shown) on a substrate 200; forming a second dielectric layer 205 on the substrate 200, wherein the dummy gate structure is located in the second dielectric layer 205; removing the dummy gate structure and forming a gate opening (not shown) in the second dielectric layer 205; and forming a gate structure in the gate opening.

[0054] The gate structure includes: a gate dielectric layer (not shown) and a gate layer (not labeled) located on the gate dielectric layer.

[0055] In this embodiment, it further includes: a sidewall spacer (not shown) located on the sidewall of the gate layer.

[0056] The method for forming the first isolation layer 206 includes: etching back the gate layer to form a first groove (not shown) in the second dielectric layer 205; forming a first isolation material layer (not shown) in the first groove and on the surface of the second dielectric layer 205; planarizing the first isolation material layer until the surface of the second dielectric layer 205 is exposed, and forming the first isolation layer 206 on the top surface of the gate layer.

[0057] The material of the first isolation layer 206 includes a dielectric material, which includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride and silicon carbon nitride; the material of the second dielectric layer 205 includes a dielectric material, which includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride and silicon carbon nitride.

[0058] The material of the first isolation layer 206 is different from the material of the second dielectric layer 205 .

[0059] In this embodiment, the material of the first isolation layer 206 includes silicon nitride; the material of the second dielectric layer 205 includes silicon oxide.

[0060] The process of forming the first isolation material layer in the first groove and on the surface of the second dielectric layer 205 includes a chemical vapor deposition process or an atomic layer deposition process; the process of planarizing the first isolation material layer includes a chemical mechanical polishing process or an etch-back process.

[0061] In this embodiment, the process of forming the first isolation material layer includes a chemical vapor deposition process; the process of planarizing the first isolation material layer includes a chemical mechanical polishing process, and the material of the first isolation layer 206 is different from the material of the second dielectric layer 205, so that the process of planarizing the first isolation material layer can stop on the surface of the second dielectric layer 205.

[0062] After forming the dummy gate structure and before forming the second dielectric layer 205 , the method further includes: forming source-drain doped regions 203 in the fin structure 201 on both sides of the dummy gate structure.

[0063] The source-drain doping region 203 has doping ions in it. The doping ions are of N-type or P-type. The N-type ions include phosphorus ions or arsenic ions. The P-type ions include boron ions or indium ions.

[0064] In this embodiment, the process of forming the source-drain doping region 203 includes an ion implantation process. In other embodiments, the process of forming the source-drain doping layer includes an in-situ doping process.

[0065] Please refer to Figure 4 , a conductive layer 207 is formed between adjacent gate structures.

[0066] The conductive layer 207 is electrically connected to the source-drain doped region 203 .

[0067] The method for forming the conductive layer 207 includes: forming a second mask layer (not shown) on the surface of the second dielectric layer 205, the second mask layer exposing the surface of the second dielectric layer 205 on the surface of the source-drain doped region 203; etching the second dielectric layer 205 using the second mask layer as a mask until the surface of the source-drain doped region 203 is exposed, and forming a second groove (not shown) in the second dielectric layer 205; forming a conductive material layer (not shown) in the second groove and on the surface of the second dielectric layer 205; and planarizing the conductive material layer until the surface of the second dielectric layer 205 is exposed, and forming a conductive layer 207 between gate structures.

[0068] The material of the conductive layer 207 includes metal, and the metal includes one or more combinations of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper; the process of forming the conductive material layer includes physical vapor deposition process or electroplating process.

[0069] In this embodiment, the material of the conductive layer 207 includes tungsten; and the process of forming the conductive material layer includes a physical vapor deposition process.

[0070] Next, part of the conductive layer 207 on both sides of the area to be contacted 202 is removed to form a first opening in the conductive layer 207, wherein the first opening exposes the sidewall surface of the area to be contacted 202. For the specific formation process of the first opening, please refer to Figure 5 and Figure 6 .

[0071] Please refer to Figure 5 , a hard mask layer 208 is formed on the surface of the conductive layer 207 and the surface of the first isolation layer 206; a third mask layer 209 is formed on the surface of the hard mask layer 208, and the third mask layer 209 exposes the surface of the conductive layer 207 on both sides of the area to be contacted 202 and the surface of the hard mask layer 208 on the surface of the area to be contacted 202.

[0072] The material of the hard mask layer 208 is different from that of the first isolation layer 206. The material of the hard mask layer 208 includes one or more of amorphous carbon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon carbonitride.

[0073] In this embodiment, the material of the hard mask layer 208 includes silicon oxide. The material of the hard mask layer 208 is different from the material of the first isolation layer 206. When the hard mask layer 208 and the conductive layer 207 are subsequently etched using the third mask layer 209 as a mask, the etching process causes less damage to the first isolation layer 206, thereby avoiding over-etching and damaging the gate structure.

[0074] In other embodiments, the hard mask layer may not be formed.

[0075] In this embodiment, the material of the third mask layer 209 includes photoresist.

[0076] Please refer to Figure 6 and Figure 7 , Figure 7 for Figure 6 A top view of Figure 6 for Figure 7 The schematic cross-sectional structure diagram along the section line MM′ direction shows that the hard mask layer 208 and the conductive layer 207 are etched using the third mask layer 209 as a mask to form a first opening 210 in the conductive layer 207 . The first opening 210 exposes the sidewall surface of the area to be contacted 202 .

[0077] The process of etching the hard mask layer 208 and the conductive layer 207 using the third mask layer 209 as a mask includes a combination of one or more of a dry etching process and a wet etching process.

[0078] In this embodiment, the process of etching the hard mask layer 208 and the conductive layer 207 using the third mask layer 209 as a mask includes a dry etching process.

[0079] After forming the first opening 210, the third mask layer 209 is removed. In this embodiment, the process of removing the third mask layer 209 includes an ashing process.

[0080] Part of the conductive layer 207 on both sides of the area to be contacted 202 is removed, so that the height of the conductive layer 207 outside the area to be contacted 202 is guaranteed, so that when the source-drain plug electrically connected to the conductive layer 207 outside the area to be contacted 202 is subsequently formed, the cross-sectional area of ​​the current passing through the conductive layer 207 outside the area to be contacted 202 is larger, so that the conductive layer 207 outside the area to be contacted 202 has a relatively small resistance, so that the semiconductor structure can have a larger current, and the performance of the semiconductor structure is improved.

[0081] In other embodiments, the method further includes: removing a portion of the conductive layer outside the two sides of the area to be contacted, and forming a first opening in the conductive layer, wherein the first opening exposes the sidewall surface of the gate structure.

[0082] Please refer to Figure 8 and Fig. 9 , Fig. 9 for Figure 8 A top view of Figure 8 for Fig. 9 A schematic cross-sectional structure diagram along the section line NN′ shows that a second isolation layer 211 is formed in the first opening 210 .

[0083] The method for forming the second isolation layer 211 includes: forming a second isolation material layer (not shown) in the first opening 210 ; planarizing the second isolation material layer until the top surface of the first isolation layer 206 is exposed, and forming the second isolation layer 211 in the first opening 210 .

[0084] In this embodiment, the hard mask layer 208 is removed while planarizing the second isolation material layer.

[0085] The material of the second isolation layer 211 is different from that of the first isolation layer 206 .

[0086] The material of the second isolation layer 211 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride and silicon carbon nitride; the process of forming the second isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process; the process of planarizing the second isolation material layer includes a chemical mechanical polishing process or an etching back process.

[0087] In this embodiment, the material of the second isolation layer 211 includes silicon oxide; the process of forming the second isolation material layer includes a chemical vapor deposition process; and the process of planarizing the second isolation material layer includes a chemical mechanical polishing process.

[0088] The material of the second isolation layer 211 is different from that of the first isolation layer 206, so that when the second isolation material layer is planarized to form the second isolation layer, the first isolation layer 206 can serve as a stop layer for the planarization process; at the same time, when the first isolation layer 206 on the surface of the area to be contacted 202 is subsequently removed and a third opening is formed in the second isolation layer 211, the process of removing the first isolation layer 206 has a larger etching selectivity for the second isolation layer 211, so that the process of removing the first isolation layer 206 causes less damage to the second isolation layer 211, so that the second isolation layer 211 can protect the conductive layer 207 on both sides of the area to be contacted 202, thereby preventing the subsequent process of forming a gate plug from damaging the conductive layer 207 on both sides of the area to be contacted 202.

[0089] A first isolation layer 206 is formed on the top surface of the gate structure, and a second isolation layer 211 is formed on the surface of the conductive layer 207 on both sides of the area to be contacted 202. When a gate plug is subsequently formed on the top of the gate structure, the second isolation layer 211 can protect the conductive layer 207 on both sides of the area to be contacted 202, thereby preventing the process of forming the gate plug from damaging the conductive layer 207 on both sides of the area to be contacted 202. At the same time, the second isolation layer 211 can fully isolate the conductive layer 207 on both sides of the area to be contacted 202 from the gate plug, thereby preventing the gate plug from short-circuiting with the conductive layer 207 on both sides of the area to be contacted 202 when the position of the gate plug is offset, thereby improving the performance of the semiconductor structure and improving the utilization rate of the chip area.

[0090] Please refer to Fig.10 A first dielectric layer 212 is formed on the substrate, the gate structure, the conductive layer 207 and the second isolation layer 211. The first dielectric layer 212 has a second opening 214. The second opening 214 exposes the surface of the first isolation layer 206 on the surface of the area to be contacted 202.

[0091] The method for forming the second opening 214 includes: forming a dielectric material layer (not shown) on the substrate, the gate structure, the conductive layer 207 and the second isolation layer 211; forming a first mask layer 213 on the dielectric material layer, the first mask layer 213 exposing the surface of the dielectric material layer on the contact area 202; etching the dielectric material layer using the first mask layer 213 as a mask until the first isolation layer 206 is exposed, thereby forming the first dielectric layer 212 and the second opening 214.

[0092] The first dielectric layer 212 is used to protect the first isolation layer 206 outside the area to be contacted 202 to avoid damaging the first isolation layer 206 outside the area to be contacted 202 when removing the first isolation layer 206 on the surface of the area to be contacted 202, thereby damaging the gate structure outside the area to be contacted 202.

[0093] The material of the first dielectric layer 212 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride and silicon carbon nitride; the process of forming the dielectric material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0094] In this embodiment, the material of the first dielectric layer 212 includes silicon oxide; and the process of forming the dielectric material layer includes a chemical vapor deposition process.

[0095] The material of the first dielectric layer 212 is different from the material of the first isolation layer 206 , so that during the process of removing the first isolation layer 206 , the removal process causes less damage to the first dielectric layer 212 .

[0096] In this embodiment, the material of the first mask layer 213 includes photoresist.

[0097] Please refer to Fig.11 and Fig.12 , Fig.12 for Fig.11 A top view of Fig.11 for Fig.12 The schematic cross-sectional structure diagram along the section line LL′ shows that the first isolation layer 206 exposed by the second opening 214 is removed, and a third opening 215 is formed in the second isolation layer 211 .

[0098] The process of removing the first isolation layer 206 includes a combination of one or more of a dry etching process and a wet etching process.

[0099] In this embodiment, the process of removing the first isolation layer 206 includes a dry etching process.

[0100] The material of the second isolation layer 211 is different from that of the first isolation layer 206. Therefore, when the first isolation layer 206 on the surface of the area to be contacted 202 is removed and the third opening 215 is formed in the second isolation layer 211, the process of removing the first isolation layer 206 has a larger etching selectivity ratio for the second isolation layer 211. Therefore, the process of removing the first isolation layer 206 causes less damage to the second isolation layer 211. Therefore, the second isolation layer 211 can protect the conductive layer 207 on both sides of the area to be contacted 202, thereby preventing the subsequent process of forming a gate plug from damaging the conductive layer 207 on both sides of the area to be contacted 202.

[0101] The material of the first dielectric layer 212 is different from the material of the first isolation layer 206, so that in the process of removing the first isolation layer 206, the removal process causes less damage to the first dielectric layer 212, so that the first dielectric layer 212 can protect the first isolation layer 206 outside the area to be contacted 202, and avoid the situation where the first isolation layer 206 outside the area to be contacted 202 is also damaged when the first isolation layer 206 on the surface of the area to be contacted 202 is removed, thereby damaging the gate structure outside the area to be contacted 202.

[0102] After forming the third opening 215, the first mask layer 213 is removed. In this embodiment, the process of removing the first mask layer 213 includes an ashing process.

[0103] In other embodiments, the first mask layer can be removed after the first dielectric layer is formed.

[0104] Please continue to refer to Fig.11 and Fig.12 After the third opening 215 is formed, a third groove 216 is formed in the first dielectric layer 212 .

[0105] The third groove 216 is used to subsequently form a source-drain plug in the third groove 216 , and the source-drain plug is electrically connected to the conductive layer 207 outside the two sides of the region to be contacted 202 .

[0106] The method for forming the third groove 216 includes: forming a fourth mask layer (not shown) on the surface of the first dielectric layer 212, wherein the fourth mask layer exposes a portion of the surface of the first dielectric layer 212; etching the first dielectric layer 212 using the fourth mask layer as a mask until the top surface of the conductive layer 207 is exposed, thereby forming the third groove 216 in the first dielectric layer 212.

[0107] After forming the third groove 216 , the fourth mask layer is removed.

[0108] Please refer to Fig.13 and Fig.14, Fig.14 for Fig.13 A top view of Fig.13 for Fig.14 The schematic cross-sectional structure diagram along the section line QQ′ shows that a gate plug 217 is formed in the second opening 214 and the third opening 215 , and a source-drain plug 218 is formed in the third groove 216 .

[0109] The method for forming the gate plug 217 and the source-drain plug 218 includes: forming a plug material layer (not shown) in the second opening 214, the third opening 215, the third groove 216 and the surface of the first dielectric layer 212; and planarizing the plug material layer until the surface of the first dielectric layer 212 is exposed to form the gate plug 217 and the source-drain plug 218.

[0110] The material of the gate plug 217 includes metal, and the metal includes one or more combinations of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper; the material of the source and drain plug 218 includes metal, and the metal includes one or more combinations of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper; the process of forming the plug material layer includes a physical vapor deposition process or an electroplating process; the process of planarizing the plug material layer includes a chemical mechanical polishing process or a back etching process.

[0111] In this embodiment, the material of the gate plug 217 includes tungsten; the material of the source and drain plugs 218 includes tungsten; the process of forming the plug material layer includes a physical vapor deposition process; and the process of planarizing the plug material layer includes a chemical mechanical polishing process.

[0112] Since the first isolation layer 206 is formed on the top surface of the gate structure, and the second isolation layer 211 is formed on the surface of the conductive layer 207 on both sides of the area to be contacted 202, when the gate plug 217 is formed on the top of the gate structure, the second isolation layer 211 can protect the conductive layer 207 on both sides of the area to be contacted 202, and prevent the process of forming the gate plug 217 from causing damage to the conductive layer 207 on both sides of the area to be contacted 202; at the same time, the second isolation layer 211 can fully isolate the conductive layer 207 on both sides of the area to be contacted 202 from the gate plug 217, and prevent the gate plug 217 from short-circuiting with the conductive layer 207 on both sides of the area to be contacted 202 when the position of the gate plug 217 is offset, thereby improving the performance of the semiconductor structure and improving the utilization rate of the chip area.

[0113] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please refer to 13 and Fig.14 ,include:

[0114] A substrate, the substrate comprising a base 200;

[0115] A gate structure (not shown) located on a substrate 200, wherein the gate structure has one or more contact regions 202, and a first isolation layer 206 is provided on a top surface of the gate structure;

[0116] A conductive layer 207 located between the gate structures;

[0117] A second isolation layer 211 located on the conductive layer 207 on both sides of the area to be contacted 202;

[0118] A first dielectric layer 212 located on the substrate, the gate structure, the conductive layer 207 and the second isolation layer 211, wherein the first dielectric layer 212 has a second opening (not shown);

[0119] a third opening (not shown) located in the second isolation layer 211, wherein the second opening exposes a top of the third opening;

[0120] The gate plug 217 is located in the second opening and the third opening, and the gate plug 217 is electrically connected to the top of the region to be contacted 202 .

[0121] In this embodiment, the substrate also includes: source-drain doped regions 203, the source-drain doped regions 203 are located in the substrate 200 on both sides of the gate structure, the conductive layer 207 is electrically connected to the source-drain doped regions 203; a second dielectric layer (not shown), the gate structure is located in the second dielectric layer.

[0122] In this embodiment, the material of the second isolation layer 211 is different from the material of the first isolation layer 206 .

[0123] In the present embodiment, the material of the first isolation layer 206 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbonitride oxynitride.

[0124] In the present embodiment, the material of the second isolation layer 211 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon carbonitride oxynitride.

[0125] In this embodiment, the gate structure includes: a gate dielectric layer (not shown); a gate layer (not labeled) located on the gate dielectric layer; and a sidewall (not labeled) located on the sidewall of the gate layer.

[0126] In this embodiment, the substrate also includes: a plurality of fin structures 201 located on the base 200, and the gate structure spans the fin structures 201; a third isolation layer (not shown) located on the surface of the base 200 and the sidewall surfaces of the plurality of fin structures 201, and the top surface of the third isolation layer is lower than the top surface of the fin structure 201.

[0127] In this embodiment, it further includes: a source-drain plug 218 located in the first dielectric layer 212 , and the source-drain plug 218 is electrically connected to the conductive layer 207 outside the two sides of the area to be contacted 202 .

[0128] The semiconductor structure has a second isolation layer 211 on the conductive layer 207 on both sides of the region to be contacted 202, and the first dielectric layer 212 has a gate plug 217, and the gate plug 217 is electrically connected to the top of the region to be contacted 202, so that the second isolation layer 211 can isolate the gate plug 217 from the conductive layer 207 on both sides of the region to be contacted 202, thereby avoiding the situation that the gate plug 217 contacts and shorts with the conductive layer 207 on both sides of the region to be contacted 202 when the position of the gate plug 217 is offset during the formation of the gate plug 217; at the same time, when the gate plug 217 is formed on the top of the region to be contacted 202, the second isolation layer 211 can protect the conductive layer 207 on both sides of the region to be contacted 202, and avoid the process of forming the gate plug 217 causing damage to the conductive layer 207 on both sides of the region to be contacted 202. In summary, the performance of the semiconductor structure is improved, and the utilization rate of the chip area is improved.

[0129] Furthermore, the material of the second isolation layer 211 is different from that of the first isolation layer 206, so that when the first isolation layer 206 on the surface of the area to be contacted 202 is removed and the third opening is formed in the second isolation layer 211, the process of removing the first isolation layer 206 has a larger etching selectivity for the second isolation layer 211, so that the process of removing the first isolation layer 206 causes less damage to the second isolation layer 211, so that the second isolation layer 211 can protect the conductive layer 207 on both sides of the area to be contacted 202, and avoid the process of forming the gate plug 217 from causing damage to the conductive layer 207 on both sides of the area to be contacted 202.

[0130] Figures 15 to 18 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0131] Please refer to Fig.15 and Fig.16 , Fig.15 is Figure 4 The structural diagram of the foundation, Fig.15 yes Fig.16 Schematic diagram of the cross-sectional structure along the section line RR'. Fig.16 for Fig.15 In the top view, a portion of the conductive layer 207 on the substrate is removed, and a first opening 301 is formed in the conductive layer 207, wherein the first opening 301 exposes a portion of the sidewall surface of the gate structure.

[0132] The method for forming the first opening 301 includes: etching back the conductive layer 207 to form the first opening 301 in the conductive layer 207 .

[0133] Removing part of the conductive layer 207 on the substrate simplifies the process of removing part of the conductive layer 207, avoiding the need to add an additional mask layer when removing part of the conductive layer in a local area, thereby simplifying the production process and reducing production costs.

[0134] Please refer to Fig.17 and Fig.18 , Fig.17 yes Fig.18 Schematic diagram of the cross-sectional structure along the section line SS'. Fig.18 for Fig.17 A second isolation layer 302 is formed in the first opening 301.

[0135] The method for forming the second isolation layer 302 includes: forming a second isolation material layer (not shown) in the first opening 301 ; planarizing the second isolation material layer until the top surface of the first isolation layer 206 is exposed, and forming the second isolation layer 302 in the first opening 301 .

[0136] The material of the second isolation layer 302 is different from the material of the first isolation layer 206 .

[0137] The material of the second isolation layer 302 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride and silicon carbon nitride; the process of forming the second isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process; the process of planarizing the second isolation material layer includes a chemical mechanical polishing process or an etching back process.

[0138] In this embodiment, the material of the second isolation layer 302 includes silicon oxide; the process of forming the second isolation material layer includes a chemical vapor deposition process; and the process of planarizing the second isolation material layer includes a chemical mechanical polishing process.

[0139] The material of the second isolation layer 302 is different from that of the first isolation layer 206, so that when the second isolation material layer is planarized to form the second isolation layer, the first isolation layer 206 can serve as a stop layer for the planarization process; at the same time, when the first isolation layer 206 on the surface of the area to be contacted 202 is subsequently removed and a third opening is formed in the second isolation layer 302 on both sides of the area to be contacted 202, the process of removing the first isolation layer 206 has a larger etching selectivity for the second isolation layer 302, so that the process of removing the first isolation layer 206 causes less damage to the second isolation layer 302, so that the second isolation layer 302 can protect the conductive layer 207 on both sides of the area to be contacted 202, thereby preventing the subsequent process of forming a gate plug from causing damage to the conductive layer 207 on both sides of the area to be contacted 202.

[0140] By forming a first isolation layer 206 on the top surface of the gate structure and forming a second isolation layer 302 on the surface of the conductive layer 207 on both sides of the area to be contacted 202, when a gate plug is subsequently formed on the top of the gate structure, the second isolation layer 302 can protect the conductive layer 207 on both sides of the area to be contacted 202, and avoid the process of forming the gate plug causing damage to the conductive layer 207 on both sides of the area to be contacted 202; at the same time, the second isolation layer 302 can fully isolate the conductive layer 207 on both sides of the area to be contacted 202 from the gate plug, and avoid the situation where the gate plug contacts the conductive layer 207 on both sides of the area to be contacted 202 when the position of the gate plug is offset, thereby improving the performance of the semiconductor structure and improving the utilization rate of the chip area.

[0141] Next, a first dielectric layer is formed on the substrate, on the gate structure, and on the second isolation layer, wherein the first dielectric layer has a second opening, and the second opening exposes the surface of the first isolation layer on the surface of the area to be contacted; the first isolation layer exposed by the second opening is removed, and a third opening is formed in the second isolation layer; and a gate plug is formed in the second opening and the third opening. For the specific formation method, process, and materials of the process, please refer to Figures 10 to 14 , I will not go into details here.

[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a base; A gate structure located on the substrate, the gate structure having one or more areas to be contacted, and a first isolation layer on the top surface of the gate structure; a conductive layer located between the gate structures; a second isolation layer on the conductive layer on both sides of the area to be contacted; A first dielectric layer located on the substrate, the gate structure, the conductive layer, and the second isolation layer, wherein the first dielectric layer has a second opening; a third opening located in the second isolation layer, wherein the second opening exposes the top of the third opening, the third opening exposes the surface of the area to be contacted, and the third opening does not expose the surface of the conductive layer; A gate plug is located in the second opening and the third opening, and the gate plug is electrically connected to the top of the region to be contacted.

2. The semiconductor structure according to claim 1, wherein: The substrate further comprises: source-drain doping regions, the source-drain doping regions are located in the substrate at both sides of the gate structure, the conductive layer is electrically connected to the source-drain doping regions; and a second dielectric layer, the gate structure is located in the second dielectric layer.

3. The semiconductor structure according to claim 1, wherein: The material of the second isolation layer is different from that of the first isolation layer.

4. The semiconductor structure according to claim 1, wherein: Also includes: A second isolation layer is located on the conductive layer outside the area to be contacted on both sides.

5. The semiconductor structure according to claim 1, wherein: The gate structure comprises: a gate dielectric layer; a gate layer located on the gate dielectric layer; and a sidewall located on the sidewall of the gate layer.

6. The semiconductor structure according to claim 1, wherein: The substrate further includes: a plurality of fin structures on the base, the gate structure spanning the fin structures; a third isolation layer located on the base surface and the sidewall surfaces of the plurality of fin structures, the top surface of the third isolation layer being lower than the top surface of the fin structure.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a base; Forming a gate structure on a substrate, wherein the gate structure has one or more areas to be contacted, and a top surface of the gate structure has a first isolation layer; forming a conductive layer between adjacent gate structures; Removing part of the conductive layer on both sides of the area to be contacted, forming a first opening in the conductive layer, wherein the first opening exposes the side wall surface of the area to be contacted; forming a second isolation layer in the first opening; Forming a first dielectric layer on the substrate, the gate structure, the conductive layer and the second isolation layer, wherein the first dielectric layer has a second opening; removing the first isolation layer exposed by the second opening, and forming a third opening in the second isolation layer, wherein the third opening exposes the surface of the area to be contacted, and the third opening does not expose the surface of the conductive layer; Gate plugs are formed in the second opening and the third opening.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the gate plug includes: forming a plug material layer in the second opening, in the third opening and on the surface of the first dielectric layer; and planarizing the plug material layer until the surface of the first dielectric layer is exposed to form the gate plug.

9. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the second opening includes: forming a first mask layer on the surface of the first dielectric layer, the first mask layer exposing the surface of the first dielectric layer at the top surface of the area to be contacted; etching the first dielectric layer using the first mask layer as a mask to form a second opening in the first dielectric layer.

10. The method for forming a semiconductor structure according to claim 7, wherein: After forming the conductive layer and before forming the second isolation layer, the method further includes: removing a portion of the conductive layer outside the two sides of the area to be contacted, forming a first opening in the conductive layer, wherein the first opening exposes the sidewall surface of the gate structure.

11. The method for forming a semiconductor structure according to claim 7, wherein: The substrate further comprises: source-drain doping regions, the source-drain doping regions are located in the substrate at both sides of the gate structure, the conductive layer is electrically connected to the source-drain doping regions; and a second dielectric layer, the gate structure is located in the second dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first isolation layer includes: etching back the gate structure to form a first groove in the second dielectric layer; forming a first isolation material layer in the first groove and on the surface of the second dielectric layer; flattening the first isolation material layer until the surface of the second dielectric layer is exposed, and forming a first isolation layer on the top surface of the gate structure.

13. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the conductive layer comprises: forming a second mask layer on the surface of the second dielectric layer, the second mask layer exposing the surface of the second dielectric layer on the surface of the source-drain doped region; etching the second dielectric layer using the second mask layer as a mask until the surface of the source-drain doped region is exposed, and forming a second groove in the second dielectric layer; forming a conductive material layer in the second groove and on the surface of the second dielectric layer; and flattening the conductive material layer until the surface of the second dielectric layer is exposed, and forming a conductive layer between gate structures.

14. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the second isolation layer includes: forming a third mask layer on the surface of the conductive layer, the third mask layer exposing the conductive layer surfaces on both sides of the area to be contacted and the first isolation layer surface of the area to be contacted; etching the conductive layer using the third mask layer as a mask to form a first opening in the conductive layer; forming a second isolation material layer in the first opening; flattening the second isolation material layer until the top surface of the first isolation layer is exposed, forming a second isolation layer in the first opening.

15. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the third mask layer on the surface of the conductive layer, the method further includes: forming a hard mask layer on the surface of the conductive layer and the surface of the first isolation layer, wherein the material of the hard mask layer is different from that of the first isolation layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the hard mask layer includes one or more of amorphous carbon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon carbonitride oxide.

17. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the gate structure includes: forming a dummy gate structure on a substrate; forming a second dielectric layer on the substrate, wherein the dummy gate structure is located in the second dielectric layer; removing the dummy gate structure to form a gate opening in the second dielectric layer; and forming a gate structure in the gate opening.

18. The method for forming a semiconductor structure according to claim 7, wherein: The material of the second isolation layer is different from that of the first isolation layer.

19. The method for forming a semiconductor structure according to claim 7, wherein: The process of removing the first isolation layer includes a dry etching process.

20. The method for forming a semiconductor structure according to claim 7, wherein: The gate structure comprises: a gate dielectric layer; a gate layer located on the gate dielectric layer; and a sidewall located on the sidewall of the gate layer.

21. The method for forming a semiconductor structure according to claim 7, wherein: The substrate further includes: a plurality of fin structures on the base, the gate structure spanning the fin structures; a third isolation layer located on the base surface and the sidewall surfaces of the plurality of fin structures, the top surface of the third isolation layer being lower than the top surface of the fin structure.

22. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: A source-drain plug is formed in the first dielectric layer, and the source-drain plug is electrically connected to the conductive layer outside the two sides of the area to be contacted.

23. The method for forming a semiconductor structure according to claim 22, wherein: The method for forming the source-drain plug comprises: forming a fourth mask layer on the surface of the first dielectric layer, wherein the fourth mask layer exposes a portion of the surface of the first dielectric layer; etching the first dielectric layer using the fourth mask layer as a mask until the top surface of the conductive layer is exposed, thereby forming a third groove in the first dielectric layer; and forming the source-drain plug in the third groove.

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