A chip, a signal displacement circuit and an electronic device

Abstract

The present application discloses a chip and a signal displacement circuit, which are applied to mobile terminals such as chargers or adapters. The chip is co-packaged with a first silicon-based driving die and a second silicon-based driving die fabricated using a silicon-based process, as well as a first gallium nitride die and a second gallium nitride die fabricated using a gallium nitride process. The first silicon-based driving die is connected to two output terminals of a controller. A first silicon-based circuit is integrated on the first silicon-based driving die, a second silicon-based circuit is integrated on the second silicon-based driving die, and a gallium nitride circuit is integrated on the first gallium nitride die. The gallium nitride circuit is high-voltage resistant. The first silicon-based circuit receives a pulse signal HI output by the controller and transmits HI to the gallium nitride circuit. The gallium nitride circuit shares the input voltage VB of the second silicon-based circuit and transmits HI to the second silicon-based circuit. This can ensure that the low-voltage second silicon-based driving die fabricated using a low-voltage silicon-based process is not damaged by a high input voltage, thereby reducing the cost of the chip.

Description

[0001] This application claims the priority of a Chinese patent application with the application number 201910172026.7, titled "A Chip, Signal Displacement Circuit and Electronic Device", which was filed with the Chinese Patent Office on March 7, 2019. The entire content of which is incorporated herein by reference. Technical Field

[0002] This application relates to the field of power supply technology, and particularly to a chip, a signal displacement circuit and an electronic device. Background Art

[0003] In the field of power management, half-bridge, full-bridge, active clamp fly-back converter (ACF), etc. are common topological structures. Taking the half-bridge architecture as an example, as Figure 1 shown, it includes a controller, a high-side driving device, a low-side driving device, a high-side power transistor and a low-side power transistor. Among them, one end of the low-side driving device is grounded, and the other end is connected to the power supply VCC. The input voltage of one end of the high-side driving device is VB, and the other end is connected to the floating ground (SW). SW is the reference voltage point of the high-side driving device. As Figure 2 shown, VB can be the voltage transmitted by the VCC through a high-voltage diode. The low side and the high side are relative. The grounded side is usually the low side, and the side connected to SW is usually the high side. The voltage of SW is related to the input voltage VDD of the high-side power device and varies between 0 and VDD, so SW also changes.

[0004] Since one end of the high-side driving device is connected to VB and SW changes, the value of VB also changes. The value of VB can reach several hundred volts in one cycle. Therefore, the high-side driving device needs to be able to withstand high voltage. Devices that can withstand high voltage usually use high-voltage BCD devices fabricated by high-voltage silicon-based processes. The high-voltage silicon-based process has high requirements, resulting in very high costs for high-voltage silicon-based devices.

[0005] Therefore, it has become an urgent problem to select a device with a simpler process to replace the high-side driving while enabling the pulse signal of the controller to be normally transmitted to the high-side driving. Summary of the Invention

[0006] Embodiments of this application provide a chip and a signal displacement circuit, which can ensure that a low-voltage silicon-based driving die fabricated by a low-voltage silicon-based process is not damaged by a high input voltage when used as a high-side driving device, and can also normally receive the pulse signal output by the controller, thereby reducing the costs of the chip and the signal displacement circuit. Embodiments of this application also provide corresponding electronic devices.

[0007] The first aspect of the present application provides a chip, which is connected to a controller. The chip may include:

[0008] A first silicon-based driving die, a second silicon-based driving die, a first gallium nitride die, and a second gallium nitride die. Among them, the first silicon-based driving die is connected to the first gallium nitride die, the second silicon-based driving die is connected to the second gallium nitride die, and the first gallium nitride die is connected to the second silicon-based driving die;

[0009] The first silicon-based driving die is connected to the first output terminal and the second output terminal of the controller. The pulse signal output by the first output terminal is used to drive the high-side gallium nitride power transistor, and the pulse signal output by the second output terminal is used to drive the low-side gallium nitride power transistor;

[0010] The first silicon-based driving die integrates a first silicon-based circuit, the second silicon-based driving die integrates a second silicon-based circuit, the first gallium nitride die integrates a gallium nitride circuit and a low-side gallium nitride power transistor, the second gallium nitride die integrates a high-side gallium nitride power transistor, and the gallium nitride circuit is high-voltage resistant;

[0011] The first silicon-based circuit is connected to the gallium nitride circuit, and the gallium nitride circuit is connected to the second silicon-based circuit;

[0012] The first silicon-based circuit receives the pulse signal output by the first output terminal and transmits the pulse signal to the gallium nitride circuit;

[0013] The gallium nitride circuit is used to share the input voltage VB of the second silicon-based circuit;

[0014] The gallium nitride circuit transmits the pulse signal to the second silicon-based circuit.

[0015] As can be seen from the above first aspect, by integrating a first silicon-based circuit on the first silicon-based driving die, a second silicon-based circuit on the second silicon-based driving die, and a high-voltage resistant gallium nitride circuit on the first gallium nitride die. In this way, by connecting the high-voltage resistant gallium nitride circuit to the second silicon-based circuit, and then connecting the two output terminals of the controller to the first silicon-based driving die, the pulse signal HI of the controller can be transmitted to the second silicon-based circuit through the gallium nitride circuit. Because the gallium nitride circuit can share the input voltage VB of the second silicon-based circuit, it is not necessary for the second silicon-based circuit to be high-voltage resistant either. In this way, the second silicon-based circuit can be a low-voltage silicon-based circuit, thereby reducing the manufacturing complexity of the chip and also reducing the cost.

[0016] Combined with the first aspect, in a first possible implementation manner, the first silicon-based driving die, the second silicon-based driving die, the first gallium nitride die, and the second gallium nitride die are encapsulated in a co-packaged manner.

[0017] As can be seen from the first possible implementation of the first aspect, by using the co-packaging method, the chip area can be effectively reduced.

[0018] Combined with the first aspect or the first possible implementation of the first aspect, in the second possible implementation,

[0019] The first silicon-based circuit may include a first low-voltage MOS transistor, the gallium nitride circuit may include a first high-voltage MOS transistor, and the drain of the first low-voltage MOS transistor is connected to the source of the first high-voltage MOS transistor;

[0020] The first low-voltage MOS transistor conducts and passes a first current under the action of the rising edge signal of the pulse signal. The first current flows from the second silicon-based circuit to the first high-voltage MOS transistor, from the source of the first high-voltage MOS transistor to the drain of the first low-voltage MOS transistor, and from the source of the first low-voltage MOS transistor to the ground;

[0021] The first voltage shared by the first high-voltage MOS transistor is the product of the first current and the internal resistance of the first high-voltage MOS transistor.

[0022] As can be seen from the second possible implementation of the first aspect, under the action of the rising edge signal of the pulse signal HI, by sharing the input voltage VB through the first high-voltage MOS transistor, the input voltage of the second silicon-based driving die can be effectively shared.

[0023] Combined with the second possible implementation of the first aspect, in the third possible implementation,

[0024] The second silicon-based circuit may include a first resistor. The input voltage VB is input from one end of the first resistor, and the other end of the first resistor is connected to the first voltage output end of the second silicon-based circuit;

[0025] The product of the first resistor and the first current is the first output voltage of the second silicon-based circuit generated under the action of the rising edge signal, and the first output voltage is output through the first voltage output end.

[0026] As can be seen from the third possible implementation of the first aspect, by generating the first output voltage through the first resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0027] Combined with the second or third possible implementation of the first aspect, in the fourth possible implementation,

[0028] The first silicon-based circuit may further include a second low-voltage MOS transistor, and the gallium nitride circuit may further include a second high-voltage MOS transistor. The drain of the second low-voltage MOS transistor is connected to the source of the second high-voltage MOS transistor;

[0029] The second low-voltage MOS transistor conducts under the action of the falling-edge signal of the pulse signal and passes a second current. The second current flows from the second silicon-based circuit to the second high-voltage MOS transistor, from the source of the second high-voltage MOS transistor to the drain of the second low-voltage MOS transistor, and from the source of the second low-voltage MOS transistor to ground;

[0030] The second voltage borne by the second high-voltage MOS transistor is the product of the second current and the internal resistance of the second high-voltage MOS transistor.

[0031] As can be seen from the fourth possible implementation manner of the first aspect, under the action of the falling-edge signal of the pulse signal HI, by sharing the input voltage VB through the second high-voltage MOS transistor, the input voltage of the second silicon-based driving die can be effectively shared.

[0032] Combined with the fourth possible implementation manner of the first aspect, in the fifth possible implementation manner,

[0033] The second silicon-based circuit may further include a second resistor. The input voltage VB is input from one end of the second resistor, and the other end of the second resistor is connected to the second voltage output terminal of the second silicon-based circuit;

[0034] The product of the second resistor and the second current is the second output voltage of the second silicon-based circuit generated under the action of the falling-edge signal of the pulse signal, and the second output voltage is output through the second voltage output terminal.

[0035] As can be seen from the fifth possible implementation manner of the first aspect, by generating the second output voltage through the second resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0036] Combined with the first aspect or the first possible implementation manner of the first aspect, in the sixth possible implementation manner,

[0037] The first silicon-based circuit may include a first voltage input terminal, and the gallium nitride circuit may include a third high-voltage MOS transistor. The first voltage input terminal is connected to the gate of the third high-voltage MOS transistor;

[0038] The first voltage input terminal receives the rising-edge signal of the pulse signal and transmits the rising-edge signal to the gate of the third high-voltage MOS transistor;

[0039] The third high-voltage MOS transistor conducts under the action of the rising-edge signal and passes a third current, which flows from the second silicon-based circuit to the third high-voltage MOS transistor and from the source of the third high-voltage MOS transistor to the ground;

[0040] The third voltage shared by the third high-voltage MOS transistor is the product of the third current and the internal resistance of the third high-voltage MOS transistor.

[0041] As can be seen from the sixth possible implementation manner of the first aspect, under the action of the rising-edge signal of the pulse signal HI, by sharing the input voltage VB through the third high-voltage MOS transistor, the input voltage of the second silicon-based drive die can be effectively shared.

[0042] Combined with the sixth possible implementation manner of the first aspect, in the seventh possible implementation manner,

[0043] The second silicon-based circuit may further include a third resistor. The input voltage VB is input from one end of the third resistor, and the other end of the third resistor is connected to the third voltage output terminal of the second silicon-based circuit;

[0044] The product of the third resistor and the third current is the third output voltage of the second silicon-based circuit generated under the action of the rising-edge signal, and the third output voltage is output through the third voltage output terminal.

[0045] As can be seen from the seventh possible implementation manner of the first aspect, by generating the third output voltage through the third resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0046] Combined with the sixth or seventh possible implementation manner of the first aspect, in the eighth possible implementation manner,

[0047] The first silicon-based circuit may further include a second voltage input terminal, and the gallium nitride circuit may further include a fourth high-voltage MOS transistor. The second voltage input terminal is connected to the gate of the fourth high-voltage MOS transistor;

[0048] The second voltage input terminal receives the falling-edge signal of the pulse signal and transmits the falling-edge signal to the gate of the fourth high-voltage MOS transistor;

[0049] The fourth high-voltage MOS transistor conducts under the action of the falling-edge signal and passes a fourth current, which flows from the second silicon-based circuit to the fourth high-voltage MOS transistor and from the source of the fourth high-voltage MOS transistor to the ground;

[0050] The fourth voltage shared by the fourth high-voltage MOS transistor is the product of the fourth current and the internal resistance of the fourth high-voltage MOS transistor.

[0051] As can be seen from the eighth possible implementation of the first aspect, under the action of the falling edge signal of the pulse signal HI, the fourth high-voltage MOS transistor shares the voltage of the input voltage VB, and the input voltage of the second silicon-based drive die can be effectively shared.

[0052] Combined with the eighth possible implementation of the first aspect, in the ninth possible implementation,

[0053] The second silicon-based circuit may further include a fourth resistor. The input voltage VB is input from one end of the fourth resistor, and the other end of the fourth resistor is connected to the fourth voltage output end of the second silicon-based circuit;

[0054] The product of the fourth resistor and the fourth current is the fourth output voltage of the second silicon-based circuit generated under the action of the falling edge signal, and the fourth output voltage is output through the fourth voltage output end.

[0055] As can be seen from the ninth possible implementation of the first aspect, by generating the fourth output voltage through the fourth resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0056] The second aspect of the present application provides a signal displacement circuit, which may include:

[0057] A first silicon-based circuit, a second silicon-based circuit, and a gallium nitride circuit. Among them, the gallium nitride circuit is high-voltage resistant. The first silicon-based circuit is connected to the gallium nitride circuit, and the gallium nitride circuit is connected to the second silicon-based circuit;

[0058] The first silicon-based circuit is integrated on a first silicon-based drive die, the second silicon-based circuit is integrated on a second silicon-based drive die, and the gallium nitride circuit and the low-side gallium nitride power transistor are integrated on a first gallium nitride die;

[0059] The first silicon-based drive die is connected to the first output end and the second output end of the controller. The pulse signal output by the first output end is used to drive the high-side gallium nitride power transistor, and the pulse signal output by the second output end is used to drive the low-side gallium nitride power transistor. The high-side gallium nitride power transistor is integrated on a second gallium nitride die, and the gallium nitride die is connected to the second silicon-based drive die;

[0060] The first silicon-based circuit receives the pulse signal output by the first output end and transmits the pulse signal to the gallium nitride circuit;

[0061] The gallium nitride circuit is used to share the input voltage VB of the second silicon-based circuit;

[0062] The gallium nitride circuit transfers the pulse signal to the second silicon-based circuit.

[0063] As can be seen from the above second aspect, by integrating the first silicon-based circuit on the first silicon-based driving die, integrating the second silicon-based circuit on the second silicon-based driving die, and integrating the high-voltage-resistant gallium nitride circuit on the first gallium nitride die. In this way, by connecting the high-voltage-resistant gallium nitride circuit to the second silicon-based circuit, and then connecting both output terminals of the controller to the first silicon-based driving die, the pulse signal HI of the controller can be transferred to the second silicon-based circuit through the gallium nitride circuit. Since the gallium nitride circuit can share the input voltage VB of the second silicon-based circuit, it is not necessary for the second silicon-based circuit to also be high-voltage-resistant. Thus, the second silicon-based circuit can be a low-voltage silicon-based circuit, which reduces the manufacturing complexity of the signal displacement circuit and also reduces the cost.

[0064] Combined with the second aspect, in the first possible implementation

[0065] The first silicon-based circuit may include a first low-voltage MOS transistor, the gallium nitride circuit may include a first high-voltage MOS transistor, and the drain of the first low-voltage MOS transistor is connected to the source of the first high-voltage MOS transistor;

[0066] The first low-voltage MOS transistor conducts and passes a first current under the action of the rising edge signal of the pulse signal. The first current flows from the second silicon-based circuit to the first high-voltage MOS transistor, from the source of the first high-voltage MOS transistor to the drain of the first low-voltage MOS transistor, and from the source of the first low-voltage MOS transistor to ground;

[0067] The first voltage shared by the first high-voltage MOS transistor is the product of the first current and the internal resistance of the first high-voltage MOS transistor.

[0068] As can be seen from the first possible implementation of the second aspect, under the action of the rising edge signal of the pulse signal HI, by sharing the input voltage VB through the first high-voltage MOS transistor, the input voltage of the second silicon-based driving die can be effectively shared.

[0069] Combined with the first possible implementation of the second aspect, in the second possible implementation

[0070] The second silicon-based circuit may include a first resistor. The input voltage VB is input from one end of the first resistor, and the other end of the first resistor is connected to the first voltage output terminal of the second silicon-based circuit;

[0071] The product of the first resistor and the first current is the first output voltage of the second silicon-based circuit generated under the action of the rising edge signal, and the first output voltage is output through the first voltage output terminal.

[0072] As can be seen from the second possible implementation manner of the second aspect, by generating a first output voltage through the first resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0073] Combining the first or second possible implementation manner of the second aspect, in the third possible implementation manner,

[0074] The first silicon-based circuit may further include a second low-voltage MOS transistor, the gallium nitride circuit may further include a second high-voltage MOS transistor, and the drain of the second low-voltage MOS transistor is connected to the source of the second high-voltage MOS transistor;

[0075] The second low-voltage MOS transistor conducts and passes a second current under the action of the falling-edge signal of the pulse signal. The second current flows from the second silicon-based circuit to the second high-voltage MOS transistor, from the source of the second high-voltage MOS transistor to the drain of the second low-voltage MOS transistor, and from the source of the second low-voltage MOS transistor to the ground;

[0076] The second voltage shared by the second high-voltage MOS transistor is the product of the second current and the internal resistance of the second high-voltage MOS transistor.

[0077] As can be seen from the third possible implementation manner of the second aspect, under the action of the falling-edge signal of the pulse signal HI, by sharing the input voltage VB through the second high-voltage MOS transistor, the input voltage of the second silicon-based driving die can be effectively shared.

[0078] Combining the third possible implementation manner of the second aspect, in the fourth possible implementation manner,

[0079] The second silicon-based circuit may further include a second resistor. The input voltage VB is input from one end of the second resistor, and the other end of the second resistor is connected to the second voltage output terminal of the second silicon-based circuit;

[0080] The product of the second resistor and the second current is the second output voltage of the second silicon-based circuit generated under the action of the falling-edge signal of the pulse signal, and the second output voltage is output through the second voltage output terminal.

[0081] As can be seen from the fourth possible implementation manner of the second aspect, by generating a second output voltage through the second resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0082] Combining the first aspect, in the fifth possible implementation manner,

[0083] The first silicon-based circuit may include a first voltage input terminal, the gallium nitride circuit may include a third high-voltage MOS transistor, and the first voltage input terminal is connected to the gate of the third high-voltage MOS transistor;

[0084] The first voltage input terminal receives the rising edge signal of the pulse signal and transmits the rising edge signal to the gate of the third high-voltage MOS transistor;

[0085] The third high-voltage MOS transistor conducts under the action of the rising edge signal and passes a third current, and the third current flows from the second silicon-based circuit to the third high-voltage MOS transistor and from the source of the third high-voltage MOS transistor to the ground;

[0086] The third voltage shared by the third high-voltage MOS transistor is the product of the third current and the internal resistance of the third high-voltage MOS transistor.

[0087] As can be seen from the fifth possible implementation manner of the second aspect, under the action of the rising edge signal of the pulse signal HI, by sharing the input voltage VB through the third high-voltage MOS transistor, the input voltage of the second silicon-based drive die can be effectively shared.

[0088] Combined with the fifth possible implementation manner of the second aspect, in the sixth possible implementation manner,

[0089] The second silicon-based circuit may further include a third resistor, the input voltage VB is input from one end of the third resistor, and the other end of the third resistor is connected to the third voltage output terminal of the second silicon-based circuit;

[0090] The product of the third resistor and the third current is the third output voltage of the second silicon-based circuit generated under the action of the rising edge signal, and the third output voltage is output through the third voltage output terminal.

[0091] As can be seen from the sixth possible implementation manner of the second aspect, by generating a third output voltage through the third resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0092] Combined with the fifth or sixth possible implementation manner of the second aspect, in the seventh possible implementation manner,

[0093] The first silicon-based circuit may further include a second voltage input terminal, the gallium nitride circuit may further include a fourth high-voltage MOS transistor, and the second voltage input terminal is connected to the gate of the fourth high-voltage MOS transistor;

[0094] The second voltage input terminal receives the falling edge signal of the pulse signal and transmits the falling edge signal to the gate of the fourth high-voltage MOS transistor;

[0095] The fourth high-voltage MOS transistor conducts under the action of the falling-edge signal and passes a fourth current, and the fourth current flows from the second silicon-based circuit to the fourth high-voltage MOS transistor and from the source electrode of the fourth high-voltage MOS transistor to the ground;

[0096] The fourth voltage borne by the fourth high-voltage MOS transistor is the product of the fourth current and the internal resistance of the fourth high-voltage MOS transistor.

[0097] It can be seen from the seventh possible implementation manner of the second aspect that under the action of the falling-edge signal of the pulse signal HI, by sharing the input voltage VB through the fourth high-voltage MOS transistor, the input voltage of the second silicon-based driving die can be effectively shared.

[0098] Combined with the seventh possible implementation manner of the second aspect, in the eighth possible implementation manner,

[0099] The second silicon-based circuit may further include a fourth resistor, the input voltage VB is input from one end of the fourth resistor, and the other end of the fourth resistor is connected to the fourth voltage output end of the second silicon-based circuit;

[0100] The product of the fourth resistor and the fourth current is the fourth output voltage of the second silicon-based circuit generated under the action of the falling-edge signal, and the fourth output voltage is output through the fourth voltage output end.

[0101] It can be seen from the eighth possible implementation manner of the second aspect that by generating the fourth output voltage through the fourth resistor, the high-side gallium nitride power transistor on the second gallium nitride die can be effectively driven to work.

[0102] The third aspect of the present application provides an electronic device, which may be a charger or an adapter, and the electronic device may include a controller, a rectifier, a transformer, a chip and a capacitor;

[0103] The rectifier is used to connect to an AC power supply and is connected to the transformer, and the rectifier is also connected to the chip through the capacitor; the transformer is connected to the chip, and the controller is connected to the chip;

[0104] The rectifier is used to convert alternating current into direct current, input the direct current into the transformer, and supply power to the chip through the capacitor;

[0105] The transformer is used to reduce the voltage of the direct current;

[0106] The controller is used to output a pulse signal to the chip;

[0107] The chip is the chip described in the first aspect or any possible implementation manner of the first aspect.

[0108] As can be seen from the above solution, for the chip provided in the embodiment of the present application, by integrating a first silicon-based circuit on the first silicon-based driving die, integrating a second silicon-based circuit on the second silicon-based driving die, and integrating a high-voltage-resistant gallium nitride circuit on the first gallium nitride die. In this way, by connecting the high-voltage-resistant gallium nitride circuit to the second silicon-based circuit, and then connecting both output terminals of the controller to the first silicon-based driving die, the pulse signal HI of the controller can be transmitted to the second silicon-based circuit through the gallium nitride circuit. Since the gallium nitride circuit can share the input voltage VB of the second silicon-based circuit, there is no need for the second silicon-based circuit to also be high-voltage-resistant, so the second silicon-based circuit can be a low-voltage silicon-based circuit, thereby reducing the manufacturing complexity of the chip and also reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] Figure 1 is a circuit topology diagram of a half-bridge structure;

[0110] Figure 2 is a voltage conduction schematic diagram;

[0111] Figure 3 is a schematic diagram of an applicable scenario of the electronic device in the embodiment of the present application;

[0112] Figure 4 is a schematic diagram of the structure of the chip in the embodiment of the present application;

[0113] Figure 5 is a schematic diagram of a signal displacement circuit in the embodiment of the present application;

[0114] Figure 6 is another schematic diagram of the signal displacement circuit in the embodiment of the present application;

[0115] Figure 7 is an example schematic diagram of the pulse signal in the embodiment of the present application;

[0116] Figure 8 is another schematic diagram of the signal displacement circuit in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0117] Next, with reference to the accompanying drawings, the embodiments of the present application will be described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0118] The embodiments of the present application provide a chip, which can ensure that the second silicon-based driving die serving as a high-side driving device is not damaged in a high-voltage working environment and can also normally receive the pulse signal HI output by the controller, thereby reducing the manufacturing complexity of the chip and also reducing the cost. The embodiments of the present application also provide a corresponding signal displacement circuit and an electronic device. The following will be described in detail respectively.

[0119] The embodiments of the present application provide a signal displacement circuit, and also provide a chip and an electronic device. The signal displacement circuit can be integrated in the chip, the chip can be installed in the electronic device, and the electronic device can be a charger or an adapter. Taking the scenario where the electronic device is a charger or an adapter as an example, the electronic device of the present application will be introduced below.

[0120] Figure 3 It is a schematic diagram of an applicable scenario of the electronic device according to the embodiments of the present application.

[0121] As Figure 3 shown, the electronic device 10 provided by the embodiments of the present application can be connected to an AC power supply 20 at one end and a load 30 at the other end. The AC power supply 20 can be the 220V mains used at home or an AC power supply with other voltage values. The load 30 can be other terminal devices that need to be charged, such as mobile phones, tablet computers, laptop computers, wearable devices, and navigation devices.

[0122] The electronic device 20 includes a chip 100, a controller 200, a rectifier 300, a transformer 400, and a capacitor 500.

[0123] One end of the rectifier 300 is connected to the AC power supply 20. The rectifier 300 is used to convert alternating current into direct current. For example, it converts 220V alternating current into 300V direct current. The other end of the rectifier 300 is connected to the first end of the transformer 400. The rectifier 300 inputs direct current to the transformer 400. The transformer 400 can lower the voltage of the direct current. For example, it adjusts the 300V direct current voltage to 20V direct current and supplies power to the load 30 through the second end of the transformer 400 using the adjusted voltage.

[0124] The third end of the transformer 400 is connected to the chip 100 to provide an input voltage VCC for the chip 100.

[0125] The rectifier 300 is also connected to the chip 100 through the capacitor 500 to provide another input voltage VDD for the chip 100.

[0126] The controller 200 is connected to the chip 100. The controller 200 is used to output a pulse signal to the chip 100 to control the operation of the chip. The controller 200 is also connected to the load 30. In this way, when the load 30 is fully charged, it can notify the controller 200, and the controller 200 can then notify the chip 100 to control the transformer 400 to stop charging the load, thereby avoiding damage to the load due to overcharging.

[0127] Regarding the chip 100, it can be involved in Figure 4 the understanding.

[0128] Figure 4 This is a schematic structural diagram of the chip 100 in an embodiment of the present application.

[0129] As Figure 4 shown, the chip 100 provided in the embodiment of the present application is connected to the controller 200. The chip 100 includes a first silicon-based drive die 101, a second silicon-based drive die 102, a first gallium nitride die 103, and a second gallium nitride die 104. A first silicon-based circuit 1011 is integrated on the first silicon-based drive die 101, and a low-side drive device may also be integrated. A second silicon-based circuit 1021 is integrated on the second silicon-based drive die 102, and a high-side drive device may also be integrated. A gallium nitride circuit 1031 and a low-side gallium nitride power transistor 1032 are integrated on the first gallium nitride die 103. A high-side gallium nitride power transistor 1041 is integrated on the second gallium nitride die 104.

[0130] Both output ports of the controller 200 are respectively connected to the first silicon-based drive die. The pulse signal LI output by the controller 200 becomes LO after passing through the first silicon-based drive die 101 to drive the low-side gallium nitride power transistor. The process from the pulse signal LI to LO is usually a signal amplification process. The pulse signal HI output by the controller 200 is transmitted to the second silicon-based drive die 102 and becomes HO to drive the high-side gallium nitride power transistor. The transmission process of the pulse signal HI is from the first silicon-based circuit 1011, the gallium nitride circuit 1031, then to the second silicon-based circuit 1021, and finally the signal HO is output from the second silicon-based drive die 102 to drive the high-side gallium nitride power transistor 1041 to operate.

[0131] As can be seen from the above solution, for the chip 100 provided in the embodiment of the present application, by integrating the first silicon-based circuit 1011 on the first silicon-based driving die 101, integrating the second silicon-based circuit 1021 on the second silicon-based driving die 102, and integrating the high-voltage-resistant gallium nitride circuit 1031 on the first gallium nitride die 103. In this way, by connecting the high-voltage-resistant gallium nitride circuit 1031 to the second silicon-based circuit 1021, and then connecting both output terminals of the controller 200 to the first silicon-based driving die 101, the pulse signal HI of the controller can be transmitted to the second silicon-based circuit 1021 through the gallium nitride circuit. Since the gallium nitride circuit 1031 can share the input voltage VB of the second silicon-based circuit, it is not necessary for the second silicon-based circuit to also be high-voltage-resistant. In this way, the second silicon-based circuit can be a low-voltage silicon-based circuit, thereby reducing the manufacturing complexity of the chip and also reducing the cost.

[0132] The first silicon-based driving die 101, the second silicon-based driving die 102, the first gallium nitride die 103, and the second gallium nitride die 104 are encapsulated in a co-packaging manner, which can effectively reduce the area of the chip.

[0133] It should be noted that the low side and the high side in the embodiment of the present application are relative. The grounded side is usually the low side, and the side connected to SW is usually the high side. The high voltage and the low voltage in the embodiment of the present application are also relative, generally determined by the definition in this field. The gallium nitride circuit 1031 can usually withstand a high voltage of several hundred volts or more than a thousand volts.

[0134] Above Figure 4 The first silicon-based circuit 1011, the second silicon-based circuit 1021, and the gallium nitride circuit 1031 and the connection lines between the three belong to the signal displacement circuit. This signal displacement circuit can be combined with the Figure 4 scheme described above, or can be an independent signal displacement circuit. It can be located in one device, or can be respectively integrated into different devices according to actual usage requirements. The signal displacement circuit 1000 in the embodiment of the present application will be introduced below in combination with Figure 5 Figure.

[0135] Figure 5 FIG.

[0136] As Figure 5As shown, the signal displacement circuit 1000 in the embodiment of the present application includes a first silicon-based circuit 1011, a second silicon-based circuit 1021, and a gallium nitride circuit 1031. The gallium nitride circuit 1031 is high-voltage resistant. Among them, the first silicon-based circuit 1011 is connected to the gallium nitride circuit 1031, and the connection method can be through a wire 1061. The gallium nitride circuit 1031 is connected to the second silicon-based circuit 1021, and the connection method can be through a wire 1071. Among them, the wire 1061 or 1071 can be a connecting wire such as a Bondires or a leadframe.

[0137] The first silicon-based circuit 1011 is connected to the first output terminal 201 of the controller 200. Among them, the pulse signal output by the first output terminal 201 is used to drive the high-side gallium nitride power transistor. The pulse signal output by the first output terminal 201 can be represented by HI. The second output terminal of the controller 200 is connected to the first BCD drive die. The pulse signal output by the second output terminal is used to drive the low-side gallium nitride power transistor. The pulse signal output by the second output terminal can be represented by LI. Regarding the pulse signal LI output by the second output terminal, it has been introduced in the above Figure 4 embodiment and will not be repeated here.

[0138] After the pulse signal HI output by the first output terminal 201 reaches the first silicon-based circuit 1011, it can be transmitted to the gallium nitride circuit 1031 through the wire 1061.

[0139] In the embodiment of the present application, both output terminals of the controller are connected to the first silicon-based drive die and do not need to be connected to the high-side drive die.

[0140] The first silicon-based circuit 1011 receives the pulse signal HI output by the first output terminal 201 of the controller 200 and transmits the pulse signal HI to the gallium nitride circuit 1031 through the wire 1061. The gallium nitride circuit 1031 can be connected to the second silicon-based circuit 1021 through the wire 1071, so as to share the input voltage VB of the second silicon-based circuit 1021. The gallium nitride circuit 1031 transmits the pulse signal HI to the second silicon-based circuit 1021 through the wire 1071.

[0141] As can be seen from the above solution, in the embodiment of the present application, the gallium nitride circuit 1031 is connected to the second silicon-based circuit 1021, and then both output terminals of the controller 200 are connected to the first silicon-based drive die. In this way, the pulse signal HI of the controller 200 can be transmitted to the second silicon-based circuit 1021 through the gallium nitride circuit 1031. Since the gallium nitride circuit 1031 can share the input voltage VB of the second silicon-based circuit 1021, it is not necessary for the second silicon-based circuit 1021 to be resistant to high voltage. Thus, the second silicon-based circuit 1021 can be a low-voltage silicon-based circuit, and the second silicon-based drive die can also be a low-voltage silicon-based drive die, thereby reducing the cost of the signal displacement circuit.

[0142] The working process of the signal displacement circuit 1000 and the controller 200 is described above as a whole. Since the embodiment of the present application focuses on describing how to transmit the pulse signal to the second silicon-based circuit 1021 through the first silicon-based circuit 1011 and the gallium nitride circuit 1031, the following will describe this process through different embodiments respectively.

[0143] Figure 6 It is a schematic structural diagram of the signal displacement circuit in the embodiment of the present application.

[0144] As Figure 6 shown, in another embodiment of the signal displacement circuit 1000 provided by the embodiment of the present application, the first silicon-based circuit 1011 includes a first low-voltage MOS transistor 10111, the gallium nitride circuit 1031 includes a first high-voltage MOS transistor 10311, and the drain of the first low-voltage MOS transistor 10111 is connected to the source of the first high-voltage MOS transistor 10311.

[0145] The first low-voltage MOS transistor 10111 conducts under the action of the rising edge signal S HI of the pulse signal and passes a first current. The first current flows from the second silicon-based circuit 1021 to the first high-voltage MOS transistor 10311, from the source of the first high-voltage MOS transistor 10311 to the drain of the first low-voltage MOS transistor 10111, and from the source of the first low-voltage MOS transistor 10111 to the ground. The first voltage shared by the first high-voltage MOS transistor 10311 is the product of the first current and the internal resistance of the first high-voltage MOS transistor.

[0146] The second silicon-based circuit 1021 includes a first resistor 10211. The input voltage VB is input from one end of the first resistor 10211, and the other end of the first resistor 10211 is connected to the first voltage output terminal of the second silicon-based circuit 1021. The voltage output from this first voltage output terminal is S HO . The product of the first resistor 10211 and the first current is the first output voltage S HI of the second silicon-based circuit 1021 generated under the action of the rising edge signal S HOand outputs a first output voltage S through a first voltage output terminal HO .

[0147] As Figure 6 shown, the first silicon-based circuit 1011 further includes a second low-voltage MOS transistor 10113, and the gallium nitride circuit 1031 further includes a second high-voltage MOS transistor 10312. The drain of the second low-voltage MOS transistor 10113 is connected to the source of the second high-voltage MOS transistor 10312.

[0148] The second low-voltage MOS transistor 10113 conducts under the action of the falling edge signal R of the pulse signal HI and passes a second current. The second current flows from the second silicon-based circuit 1021 to the second high-voltage MOS transistor 10312, from the source of the second high-voltage MOS transistor 10312 to the drain of the second low-voltage MOS transistor 10113, and from the source of the second low-voltage MOS transistor 10113 to the ground. The second voltage shared by the second high-voltage MOS transistor 10312 is the product of the second current and the internal resistance of the second high-voltage MOS transistor.

[0149] The second silicon-based circuit 1021 further includes a second resistor 10212. The input voltage VB is input from one end of the second resistor 10212, and the other end of the second resistor 10212 is connected to the second voltage output terminal of the second silicon-based circuit 1021; the product of the second resistor and the second current is the second output voltage R of the second silicon-based circuit 1021 generated under the action of the falling edge signal of the pulse signal HO and outputs the second output voltage R through the second voltage output terminal HO .

[0150] The following combines Figure 6 and Figure 7 to describe the voltage division process of the above-mentioned gallium nitride circuit 1031 in another way, and the process of the signal from S HI to S HO , from R HI to R HO .

[0151] As Figure 6 shown, one port in the first silicon-based circuit 1011 is connected to the gate of the first high-voltage MOS transistor 10311 through a wire 10613, and the first high-voltage MOS transistor 10311 is turned on through the input voltage V H . In this way, when the first low-voltage MOS transistor 10111 is at the rising edge signal S of the pulse signal HI HIAfter being turned on under the action, a path is formed from one end of the first resistor 10211 connected to the input voltage VB through the wire 10711 to the drain of the first high-voltage MOS transistor 10311, then to the source, through the wire 10611 to the drain of the first low-voltage MOS transistor 10111 and then to the source, then to the resistor 10112 and then to the ground. The first current flows from the first resistor 10211 to the ground through the above path. The pulse signal HI is usually 6V, as long as it can turn on the first low-voltage MOS transistor 10111, and the emission value of the pulse signal HI can be determined according to the actual situation.

[0152] The voltage of the above path is VB, and the first current flows from the first resistor 10211 to the ground. During the flow of the first current, voltage division is achieved. The first current flows through the first high-voltage MOS transistor 10311, and the voltage shared by the first high-voltage MOS transistor 10311 is the product of the first current and the internal resistance of the first high-voltage MOS transistor 10311. Since the internal resistance of the first high-voltage MOS transistor 10311 is very large, the first high-voltage MOS transistor 10311 will also share a large voltage. The other end of the first resistor 10211 is connected to the output end of the second silicon-based circuit 1021, and the voltage S output by this output end HO is the product of the first current and the first resistor 10211. The resistance value of this first resistor is usually not large, so this S HO is not large either, and the second silicon-based circuit can use low-voltage BCD devices.

[0153] Similarly, for the falling-edge signal R of the pulse signal HI HI at one end, the process is basically the same. One port in the first silicon-based circuit 1011 is connected to the gate of the second high-voltage MOS transistor 10312 through the wire 10613, and the second high-voltage MOS transistor 10312 is turned on through the input voltage V H . In this way, when the second low-voltage MOS transistor 10112 is turned on under the action of the falling-edge signal R of the pulse signal HI HI , a path is formed from one end of the second resistor 10212 connected to the input voltage VB through the wire 10712 to the drain of the second high-voltage MOS transistor 10312, then to the source, through the wire 10612 to the drain of the second low-voltage MOS transistor 10113 and then to the source, then to the resistor 10114 and then to the ground. The second current flows from the second resistor 10212 to the ground through the above path. The pulse signal HI is usually 6V, as long as it can turn on the second low-voltage MOS transistor 10113, and the emission value of the pulse signal HI can be determined according to the actual situation.

[0154] The voltage of the above-mentioned path is VB. The second current flows from the second resistor 10212 to the ground. During the flow of the second current, voltage division is achieved. The second current flows through the second high-voltage MOS transistor 10312. The voltage borne by the second high-voltage MOS transistor 10312 is the product of the second current and the internal resistance of the second high-voltage MOS transistor 10312. Since the internal resistance of the second high-voltage MOS transistor 10312 is very large, the second high-voltage MOS transistor 10312 also bears a large voltage. The other end of the second resistor 10212 is connected to the output terminal of the second silicon-based circuit 1021, and the voltage R HO output at this output terminal is the product of the second current and the second resistor 10212. The resistance value of this second resistor is usually not large, so this R HO is not large either. The second silicon-based circuit can use low-voltage BCD devices.

[0155] The above Figure 6 describes one implementation method. Next, another implementation method will be described in combination with Figure 8 the description.

[0156] Figure 8 is another structural schematic diagram of the signal displacement circuit in the embodiment of the present application.

[0157] As Figure 8 shown, in the signal displacement circuit in the embodiment of the present application, the first silicon-based circuit 1011 includes a first voltage input terminal 10115, and the gallium nitride circuit 1031 includes a third high-voltage MOS transistor 10313. The first voltage input terminal 10115 is connected to the gate of the third high-voltage MOS transistor 10313.

[0158] The first voltage input terminal receives the rising edge signal S HI of the pulse signal and transmits the rising edge signal S HI to the gate of the third high-voltage MOS transistor 10313. The third high-voltage MOS transistor 10313 conducts under the action of the rising edge signal and passes a third current. The third current flows from the second silicon-based circuit 1021 to the third high-voltage MOS transistor 10313 and flows from the source of the third high-voltage MOS transistor 10313 to the ground. The third voltage borne by the third high-voltage MOS transistor 10313 is the product of the third current and the internal resistance of the third high-voltage MOS transistor.

[0159] The second silicon-based circuit 1021 further includes a third resistor 10213. The input voltage VB is input from one end of the third resistor 10213, and the other end of the third resistor 10213 is connected to the third voltage output terminal of the second silicon-based circuit 1021. The product of the third resistor 10213 and the third current is the third output voltage of the second silicon-based circuit 1021 generated under the action of the rising edge signal, and the third output voltage S HO is output through the third voltage output terminal.

[0160] The first silicon-based circuit 1011 further includes a second voltage input terminal 10116, and the gallium nitride circuit 1031 further includes a fourth high-voltage MOS transistor 10315. The second voltage input terminal 10116 is connected to the gate of the fourth high-voltage MOS transistor 10315; the second voltage input terminal 10116 receives the falling-edge signal R of the pulse signal HI , and transmits the falling-edge signal R HI to the gate of the fourth high-voltage MOS transistor 10315; the fourth high-voltage MOS transistor 10315 conducts under the action of the falling-edge signal and passes a fourth current. The fourth current flows from the second silicon-based circuit 1021 to the fourth high-voltage MOS transistor 10315 and from the source of the fourth high-voltage MOS transistor 10315 to the ground; the fourth voltage shared by the fourth high-voltage MOS transistor 10315 is the product of the fourth current and the internal resistance of the fourth high-voltage MOS transistor 10315.

[0161] The second silicon-based circuit 1021 further includes a fourth resistor 10214. The input voltage VB is input from one end of the fourth resistor 10214, and the other end of the fourth resistor 10214 is connected to the fourth voltage output terminal of the second silicon-based circuit 1021; the product of the fourth resistor 10214 and the fourth current is the fourth output voltage of the second silicon-based circuit 1021 generated under the action of the falling-edge signal, and the fourth output voltage is output through the fourth voltage output terminal R HO .

[0162] The following combines Figure 7 and Figure 8 to describe the voltage division process of the above-mentioned gallium nitride circuit 1031 in another way, as well as the process of the signal from S HI to S HO , from R HI to R HO .

[0163] After the rising-edge signal S HI is input from the first voltage input terminal 10115, it is conducted to the gate of the third high-voltage MOS transistor 10313 through the wire 10614, and then the third high-voltage MOS transistor 10313 is turned on, thereby forming a path from the end of the third resistor 10213 with the input voltage VB through the wire 10713 to the drain and then to the source of the third high-voltage MOS transistor 10313, through the resistor 10314 to the ground.

[0164] The voltage of the above-mentioned path is VB. The third current flows from the third resistor 10213 to the ground. During the flow of the third current, voltage division is achieved. The third current flows through the third high-voltage MOS transistor 10313. The voltage borne by the third high-voltage MOS transistor 10313 is the product of the third current and the internal resistance of the third high-voltage MOS transistor 10313. Since the internal resistance of the third high-voltage MOS transistor 10313 is very large, the third high-voltage MOS transistor 10313 will also bear a large voltage. The other end of the third resistor 10212 is connected to the output terminal of the second silicon-based circuit 1021, and the voltage S output by this output terminal HO is the product of the third current and the third resistor 10213. The resistance value of this third resistor 10213 is usually not large, so this R HO is not large either. The second silicon-based circuit 1021 can use low-voltage BCD devices.

[0165] Similarly, for the falling-edge signal R of the pulse signal HI HI at one end, the process is basically the same. After the falling-edge signal R HI is input from the second voltage input terminal 10116, it is conducted through the wire 10615 to the gate of the fourth high-voltage MOS transistor 10315, thereby turning on the fourth high-voltage MOS transistor 10315, thus forming a path from the end of the fourth resistor 10214 with an input voltage of VB through the wire 10714 to the drain and then to the source of the fourth high-voltage MOS transistor 10315, and then through the resistor 10316 to the ground.

[0166] The voltage of the above-mentioned path is VB. The fourth current flows from the fourth resistor 10214 to the ground. During the flow of the fourth current, voltage division is achieved. The fourth current flows through the fourth high-voltage MOS transistor 10315. The voltage borne by the fourth high-voltage MOS transistor 10315 is the product of the fourth current and the internal resistance of the fourth high-voltage MOS transistor 10315. Since the internal resistance of the fourth high-voltage MOS transistor 10315 is very large, the fourth high-voltage MOS transistor 10315 will also bear a large voltage. The other end of the fourth resistor 10214 is connected to the output terminal of the second silicon-based circuit 1021, and the voltage R output by this output terminal HO is the product of the fourth current and the fourth resistor 10214. The resistance value of this fourth resistor 10214 is usually not large, so this R HO is not large either. The second silicon-based circuit 1021 can use low-voltage BCD devices, thereby reducing the cost of the signal displacement circuit.

[0167] It should be noted that in the above-mentioned embodiments, only the half-bridge is used as an example for illustration. In fact, circuits with other structures can also use the idea of the signal displacement circuit provided by the embodiments of the present application.

[0168] The above has introduced in detail the signal displacement circuit, chip and electronic device provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A chip, characterized in that, the chip is connected to a controller, and the chip includes: a first silicon-based drive die, a second silicon-based drive die, a first gallium nitride die, and a second gallium nitride die, wherein the first silicon-based drive die is connected to the first gallium nitride die, the second silicon-based drive die is connected to the second gallium nitride die, and the first gallium nitride die is connected to the second silicon-based drive die; a first silicon-based circuit is integrated on the first silicon-based drive die, a second silicon-based circuit is integrated on the second silicon-based drive die, a gallium nitride circuit and a low-side gallium nitride power transistor are integrated on the first gallium nitride die, the gallium nitride circuit is high-voltage resistant, and a high-side gallium nitride power transistor is integrated on the second gallium nitride die; the first silicon-based drive die is connected to the first output terminal and the second output terminal of the controller, and the pulse signal output by the first output terminal is used to drive the high-side gallium nitride power transistor, and the pulse signal output by the second output terminal is used to drive the low-side gallium nitride power transistor; the first silicon-based circuit is connected to the gallium nitride circuit, and the gallium nitride circuit is connected to the second silicon-based circuit; the first silicon-based circuit receives the pulse signal output by the first output terminal and transmits the pulse signal to the gallium nitride circuit; the gallium nitride circuit is used to share the input voltage VB of the second silicon-based circuit; the gallium nitride circuit transmits the pulse signal to the second silicon-based circuit; the first silicon-based drive die, the second silicon-based drive die, the first gallium nitride die, and the second gallium nitride die are encapsulated in a co-packaging manner; the first silicon-based circuit includes a first low-voltage MOS transistor, the gallium nitride circuit includes a first high-voltage MOS transistor, and the drain of the first low-voltage MOS transistor is connected to the source of the first high-voltage MOS transistor; the first low-voltage MOS transistor is turned on under the action of the rising edge signal of the pulse signal and passes a first current, and the first current flows from the second silicon-based circuit to the first high-voltage MOS transistor, from the source of the first high-voltage MOS transistor to the drain of the first low-voltage MOS transistor, and from the source of the first low-voltage MOS transistor to ground; the first voltage shared by the first high-voltage MOS transistor is the product of the first current and the internal resistance of the first high-voltage MOS transistor.

2. The chip according to claim 1, characterized in that, the second silicon-based circuit includes a first resistor, the input voltage VB is input from one end of the first resistor, and the other end of the first resistor is connected to the first voltage output terminal of the second silicon-based circuit; the product of the first resistor and the first current is the first output voltage of the second silicon-based circuit generated under the action of the rising edge signal, and the first output voltage is output through the first voltage output terminal.

3. The chip according to claim 1 or 2, characterized in that, the first silicon-based circuit further includes a second low-voltage MOS transistor, the gallium nitride circuit further includes a second high-voltage MOS transistor, and the drain of the second low-voltage MOS transistor is connected to the source of the second high-voltage MOS transistor; The second low-voltage MOS transistor conducts and passes a second current under the action of the falling-edge signal of the pulse signal. The second current flows from the second silicon-based circuit to the second high-voltage MOS transistor, from the source electrode of the second high-voltage MOS transistor to the drain electrode of the second low-voltage MOS transistor, and from the source electrode of the second low-voltage MOS transistor to the ground; The second voltage borne by the second high-voltage MOS transistor is the product of the second current and the internal resistance of the second high-voltage MOS transistor.

4. The chip according to claim 3, wherein, the second silicon-based circuit further includes a second resistor. The input voltage VB is input from one end of the second resistor, and the other end of the second resistor is connected to the second voltage output terminal of the second silicon-based circuit; The product of the second resistor and the second current is the second output voltage of the second silicon-based circuit generated under the action of the falling-edge signal of the pulse signal, and the second output voltage is output through the second voltage output terminal.

5. The chip according to claim 1, wherein, the first silicon-based circuit includes a first voltage input terminal, the gallium nitride circuit includes a third high-voltage MOS transistor, and the first voltage input terminal is connected to the gate electrode of the third high-voltage MOS transistor; The first voltage input terminal receives the rising-edge signal of the pulse signal and transmits the rising-edge signal to the gate electrode of the third high-voltage MOS transistor; The third high-voltage MOS transistor conducts and passes a third current under the action of the rising-edge signal. The third current flows from the second silicon-based circuit to the third high-voltage MOS transistor and from the source electrode of the third high-voltage MOS transistor to the ground; The third voltage borne by the third high-voltage MOS transistor is the product of the third current and the internal resistance of the third high-voltage MOS transistor.

6. The chip according to claim 5, wherein, the second silicon-based circuit further includes a third resistor. The input voltage VB is input from one end of the third resistor, and the other end of the third resistor is connected to the third voltage output terminal of the second silicon-based circuit; The product of the third resistor and the third current is the third output voltage of the second silicon-based circuit generated under the action of the rising-edge signal, and the third output voltage is output through the third voltage output terminal.

7. The chip according to claim 5 or 6, wherein, the first silicon-based circuit further includes a second voltage input terminal, the gallium nitride circuit further includes a fourth high-voltage MOS transistor, and the second voltage input terminal is connected to the gate electrode of the fourth high-voltage MOS transistor; The second voltage input terminal receives the falling-edge signal of the pulse signal and transmits the falling-edge signal to the gate electrode of the fourth high-voltage MOS transistor; The fourth high-voltage MOS transistor conducts and passes a fourth current under the action of the falling-edge signal. The fourth current flows from the second silicon-based circuit to the fourth high-voltage MOS transistor and from the source electrode of the fourth high-voltage MOS transistor to the ground; The fourth voltage borne by the fourth high-voltage MOS transistor is the product of the fourth current and the internal resistance of the fourth high-voltage MOS transistor.

8. The chip according to claim 7, wherein, the second silicon-based circuit further includes a fourth resistor, the input voltage VB is input from one end of the fourth resistor, and the other end of the fourth resistor is connected to the fourth voltage output terminal of the second silicon-based circuit; the product of the fourth resistor and the fourth current is the fourth output voltage of the second silicon-based circuit generated under the action of the falling edge signal, and the fourth output voltage is output through the fourth voltage output terminal.

9. A signal displacement circuit, wherein, it includes: a first silicon-based circuit, a second silicon-based circuit, and a gallium nitride circuit, wherein the gallium nitride circuit is high-voltage resistant, the first silicon-based circuit is connected to the gallium nitride circuit, and the gallium nitride circuit is connected to the second silicon-based circuit; the first silicon-based circuit is integrated on a first silicon-based drive die, the second silicon-based circuit is integrated on a second silicon-based drive die, and the gallium nitride circuit and a low-side gallium nitride power transistor are integrated on a first gallium nitride die; the first silicon-based drive die is connected to the first output terminal and the second output terminal of the controller, the pulse signal output from the first output terminal is used to drive a high-side gallium nitride power transistor, the pulse signal output from the second output terminal is used to drive the low-side gallium nitride power transistor, the high-side gallium nitride power transistor is integrated on a second gallium nitride die, and the second gallium nitride die is connected to the second silicon-based drive die; the first silicon-based circuit receives the pulse signal output from the first output terminal and transmits the pulse signal to the gallium nitride circuit; the gallium nitride circuit is used to share the input voltage VB of the second silicon-based circuit; the gallium nitride circuit transmits the pulse signal to the second silicon-based circuit; the first silicon-based drive die, the second silicon-based drive die, the first gallium nitride die, and the second gallium nitride die are packaged in a co-packaged manner; the first silicon-based circuit includes a first low-voltage MOS transistor, the gallium nitride circuit includes a first high-voltage MOS transistor, and the drain of the first low-voltage MOS transistor is connected to the source of the first high-voltage MOS transistor; the first low-voltage MOS transistor conducts and passes a first current under the action of the rising edge signal of the pulse signal, the first current flows from the second silicon-based circuit to the first high-voltage MOS transistor, from the source of the first high-voltage MOS transistor to the drain of the first low-voltage MOS transistor, and from the source of the first low-voltage MOS transistor to the ground; the first voltage shared by the first high-voltage MOS transistor is the product of the first current and the internal resistance of the first high-voltage MOS transistor.

10. The signal displacement circuit according to claim 9, wherein, the second silicon-based circuit includes a first resistor, the input voltage VB is input from one end of the first resistor, and the other end of the first resistor is connected to the first voltage output terminal of the second silicon-based circuit; the product of the first resistor and the first current is the first output voltage of the second silicon-based circuit generated under the action of the rising edge signal, and the first output voltage is output through the first voltage output terminal.

11. The signal displacement circuit according to claim 9 or 10, characterized in that, the first silicon-based circuit further includes a second low-voltage MOS transistor, the gallium nitride circuit further includes a second high-voltage MOS transistor, and the drain of the second low-voltage MOS transistor is connected to the source of the second high-voltage MOS transistor; the second low-voltage MOS transistor is turned on under the action of the falling-edge signal of the pulse signal and passes a second current, and the second current flows from the second silicon-based circuit to the second high-voltage MOS transistor, and from the source of the second high-voltage MOS transistor to the drain of the second low-voltage MOS transistor, and from the source of the second low-voltage MOS transistor to the ground; the second voltage shared by the second high-voltage MOS transistor is the product of the second current and the internal resistance of the second high-voltage MOS transistor.

12. The signal displacement circuit according to claim 11, characterized in that, the second silicon-based circuit further includes a second resistor, the input voltage VB is input from one end of the second resistor, and the other end of the second resistor is connected to the second voltage output terminal of the second silicon-based circuit; the product of the second resistor and the second current is the second output voltage of the second silicon-based circuit generated under the action of the falling-edge signal of the pulse signal, and the second output voltage is output through the second voltage output terminal.

13. The signal displacement circuit according to claim 9, characterized in that, the first silicon-based circuit includes a first voltage input terminal, the gallium nitride circuit includes a third high-voltage MOS transistor, and the first voltage input terminal is connected to the gate of the third high-voltage MOS transistor; the first voltage input terminal receives the rising-edge signal of the pulse signal and transmits the rising-edge signal to the gate of the third high-voltage MOS transistor; the third high-voltage MOS transistor is turned on under the action of the rising-edge signal and passes a third current, and the third current flows from the second silicon-based circuit to the third high-voltage MOS transistor, and from the source of the third high-voltage MOS transistor to the ground; the third voltage shared by the third high-voltage MOS transistor is the product of the third current and the internal resistance of the third high-voltage MOS transistor.

14. The signal displacement circuit according to claim 13, characterized in that, the second silicon-based circuit further includes a third resistor, the input voltage VB is input from one end of the third resistor, and the other end of the third resistor is connected to the third voltage output terminal of the second silicon-based circuit; the product of the third resistor and the third current is the third output voltage of the second silicon-based circuit generated under the action of the rising-edge signal, and the third output voltage is output through the third voltage output terminal.

15. The signal displacement circuit according to claim 13 or 14, characterized in that, the first silicon-based circuit further includes a second voltage input terminal, the gallium nitride circuit further includes a fourth high-voltage MOS transistor, and the second voltage input terminal is connected to the gate of the fourth high-voltage MOS transistor; the second voltage input terminal receives the falling-edge signal of the pulse signal and transmits the falling-edge signal to the gate of the fourth high-voltage MOS transistor; The fourth high-voltage MOS transistor conducts and passes a fourth current under the action of the falling-edge signal. The fourth current flows from the second silicon-based circuit to the fourth high-voltage MOS transistor and from the source electrode of the fourth high-voltage MOS transistor to the ground; The fourth voltage borne by the fourth high-voltage MOS transistor is the product of the fourth current and the internal resistance of the fourth high-voltage MOS transistor.

16. The signal displacement circuit according to claim 15, characterized in that, The second silicon-based circuit further includes a fourth resistor. The input voltage VB is input from one end of the fourth resistor, and the other end of the fourth resistor is connected to the fourth voltage output terminal of the second silicon-based circuit; The product of the fourth resistor and the fourth current is the fourth output voltage of the second silicon-based circuit generated under the action of the falling-edge signal, and the fourth output voltage is output through the fourth voltage output terminal.

17. An electronic device, characterized in that, comprising a controller, a rectifier, a transformer, a chip and a capacitor; The rectifier is used to connect to an AC power supply and is connected to the transformer. The rectifier is also connected to the chip through the capacitor; the transformer is connected to the chip, and the controller is connected to the chip; The rectifier is used to convert alternating current into direct current, input the direct current into the transformer, and supply power to the chip through the capacitor; The transformer is used to lower the voltage of the direct current; The controller is used to output a pulse signal to the chip; The chip is the chip according to any one of claims 1-8 above.

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