Ion implantation for nano-FETs

Abstract

This application relates to ion implantation for nanoFETs. A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by an iterative recess and implant process, performed while recessing the source / drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral distribution of the doped channel junctions.

Description

Technical Field

[0001] The present disclosure generally relates to ion implantation for nanoFETs. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material onto a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a first nanostructure, the first nanostructure including a first doped channel junction at either end; a second nanostructure, above the first nanostructure, the second nanostructure including a second doped channel junction at either end; a gate structure, disposed above the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure; and a source / drain region, adjacent to the gate structure, the source / drain region contacting the first nanostructure and the second nanostructure.

[0005] According to a second aspect of the present disclosure, a transistor is provided, comprising: a first nanostructure; a second nanostructure above the first nanostructure, wherein at least one of the first nanostructure or the second nanostructure comprises a first doped channel junction at each end and a first undoped channel length between the first doped channel junctions; a gate structure disposed above the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure; and a source / drain region adjacent to the gate structure, the source / drain region contacting the first nanostructure and the second nanostructure.

[0006] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a plurality of nanostructures above a substrate; forming a gate structure above the plurality of nanostructures; performing a first angled ion implantation to implant a first dopant into a first channel end of a first nanostructure among the plurality of nanostructures, the first channel end being below the gate structure; etching the first nanostructure among the plurality of nanostructures to form a first groove in the first nanostructure adjacent to the gate structure, the etching exposing the first channel end of the first nanostructure; performing a second angled ion implantation to implant a second dopant into a second channel end of a second nanostructure, the second channel end being below the gate structure; etching the second nanostructure among the plurality of nanostructures to extend the first groove and form a second groove in the second nanostructure adjacent to the gate structure, the etching exposing the second channel end of the second nanostructure; etching to extend the second groove to form a third groove above the substrate; and depositing a source / drain region in the third groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET or nanosheet FET) is shown in a three-dimensional view in accordance with some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 15E 、 Figure 15F 、 Figure 15G 、 Figure 15H 、 Figure 15I 、 Figure 15J 、 Figure 15K 、 Figure 15L 、 Figure 15M 、 Figure 15N 、 Figure 15O 、 Figure 15P 、 Figure 15Q 、 Figure 15R 、 Figure 15S 、 Figure 15T 、 Figure 15U 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 20A 、 Figure 20B 、 Figure 21A 、 Figure 21B 、 Figure 22A 、 Figure 22B 、 Figure 23A 、 Figure 23B 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 25A 、 Figure 25B 、 Figure 25C 、 Figure 26A 、 Figure 26B and Figure 26C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET, according to some embodiments.

[0010] Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 15E 、 Figure 15F 、 Figure 15G 、 Figure 15H 、 Figure 15I 、 Figure 15J 、 Figure 15K 、 Figure 15L 、 Figure 15M 、 Figure 15N 、 Figure 15O 、 Figure 15P 、 Figure 15Q 、 Figure 15R 、 Figure 15S 、 Figure 15T and Figure 15UVarious arrangements of implant regions according to various embodiments are further shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] Embodiments advantageously provide a process by which the channel region of a nanoFET can be reliably doped by implanting ions. The doping process provides a lateral channel junction at either end of the stacked channel region, thereby reducing the channel resistance. The embodiment process can customize the channel junction width for each nanostructure of the nanoFET. When manufacturing grooves for the subsequent formation of source / drain regions, multiple grooves and an angled implantation process are used to selectively implant dopant ions into the ends of the nanosheet channel below the transistor gate. The use of multiple grooves and an implantation process provides the ability to control the lateral implant depth or lateral strag of the channel junction.

[0014] Figure 1An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view according to some embodiments is shown. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, which may be above and protrude from between adjacent isolation regions 68. Although the isolation regions 68 are shown / described as being separate from the substrate 50, as used herein, the term "substrate" may refer solely to a semiconductor substrate, or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to the portion extending between adjacent isolation regions 68.

[0015] A gate dielectric layer 100 is over the top surface of the fin 66 and along the top, sidewalls, and bottom surfaces of the nanostructures 55. A gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0016] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 98 and is perpendicular to the direction of current flow, for example, between the epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of the nanoFET's fin 66 and is perpendicular to the direction of current flow, for example, between the epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects for use in fin field-effect transistors (FinFETs).

[0018] Figures 2 to 26C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET, according to some embodiments. Figures 2 to 5 、 Figure 6A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A 、 Figure 25A and Figure 26A Shown Figure 1 Reference section AA' is shown. Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 15E 、 Figure 15F 、 Figure 15G 、 Figure 15H 、 Figure 15I 、 Figure 15J 、 Figure 15K 、 Figure 15L 、 Figure 15M 、 Figure 15N 、 Figure 15O 、 Figure 15P 、 Figure 15Q 、 Figure 15R 、 Figure 15S 、 Figure 15T 、 Figure 15U 、 Figure 16B 、 Figure 17B 、 Figure 17C 、 Figure 18B 、 Figure 18D 、 Figure 19B 、 Figure 20B 、 Figure 21B 、 Figure 22B 、 Figure 23B 、 Figure 24B 、 Figure 25B and Figure 26B Shown Figure 1 Reference section BB' is shown. Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 18C 、 Figure 19C 、 Figure 24C 、 Figure 25C and Figure 26C Shown Figure 1 Reference section CC' is shown.

[0019] exist Figure 2In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, for example, an NMOS transistor, such as an n-type nano FET, and the p-type region 50P can be used to form a p-type device, for example, a PMOS transistor, such as a p-type nano SFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (for example, other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further in Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively, first semiconductor layers 51) and second semiconductor layers 53A-C (collectively, second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the second semiconductor layer 53 will be removed, and the first semiconductor layer 51 will be patterned to form the channel region of the nanoFET in the p-type region 50P. In addition, the first semiconductor layer 51 will be removed, and the second semiconductor layer 53 will be patterned to form the channel region of the nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nanoFET in the p-type region 50P. In yet other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P.

[0022] For illustrative purposes, multilayer stack 64 is shown as including three layers of each of first semiconductor layer 51 and second semiconductor layer 53. In some embodiments, multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer in multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), and the like. In various embodiments, first semiconductor layer 51 may be formed from a first semiconductor material suitable for p-type nanoFETs, such as silicon germanium, pure germanium, and the like, and second semiconductor layer 53 may be formed from a second semiconductor material suitable for n-type nanoFETs, such as silicon, carbon silicon, silicon phosphorus, and the like. In some embodiments, the same material may be used for both n-type nanoFETs and p-type nanoFETs. For illustrative purposes, multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for p-type nanoFETs. In some embodiments, multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for n-type nanoFETs.

[0023] The first semiconductor material and the second semiconductor material can be materials having a high etch selectivity relative to each other. Thus, in n-type region 50N, first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing second semiconductor layer 53 of the second semiconductor material, thereby allowing second semiconductor layer 53 to be patterned to form the channel region of an n-type nanoFET. Similarly, in p-type region 50P, second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing first semiconductor layer 51 of the first semiconductor material, thereby allowing first semiconductor layer 51 to be patterned to form the channel region of a p-type nanoFET.

[0024] Now refer to Figure 3 According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 can be further collectively referred to as nanostructures 55.

[0025] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithographic processes, including a double patterning process or a multi-patterning process. Typically, a double patterning or multi-patterning process combines a photolithographic process and a self-aligned process, allowing patterns to be created with, for example, a smaller pitch than can be obtained using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0026] For illustrative purposes, Figure 3Fins 66 in n-type region 50N and p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of fins 66 in n-type region 50N may be greater or less than the width of fins 66 in p-type region 50P. Further, while each of fins 66 and nanostructures 55 is shown as having a uniform width, in other embodiments, fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of fins 66 and / or nanostructures 55 continuously increases in a direction toward substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0027] exist Figure 4 In the embodiment shown, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as that described above can be formed over the liner.

[0028] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be employed. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is completed.

[0029] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., an etching process that etches the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructures 55). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) can be employed.

[0030] The above about Figures 2 to 4 The process described is only one example of how the fins 66 and nanostructures 55 may be formed. In some embodiments, the fins 66 and / or nanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include the alternating semiconductor materials discussed above, for example, a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and / or subsequent implantation, but in situ doping and implantation doping may be used together.

[0031] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials in the p-type region 50P and the n-type region 50N, or may be formed in a different order.

[0032] Further in Figure 4In the embodiment having different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fins 66 and the STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., which is implanted into the region at a concentration of about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0033] After or before the implantation of the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., which is implanted into the region at a concentration of about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0034] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may eliminate implantation, but in-situ doping and implantation doping may be used together.

[0035] These implants may include implanting impurities into regions of nanostructure 55 that will subsequently become the channel regions of the p-type nanoFETs and n-type nanoFETs. However, it should be noted that these implants may be primarily uniform throughout nanostructure 55 and the subsequently formed channel regions. Instead, the embodiments described herein provide a method for forming junctions in the channel regions to increase the dopant concentration in the junctions and further reduce the channel resistance. This will be described in more detail below.

[0036] exist Figure 5 , a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 760, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive material or a non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. Dummy gate layer 72 can be made of other materials with high etch selectivity relative to etching of the isolation regions. Mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across n-type region 50N and p-type region 50P. Note that dummy dielectric layer 70 is shown as covering only fins 66 and / or nanostructures 55 for illustrative purposes only. In some embodiments, dummy dielectric layer 70 can be deposited such that dummy dielectric layer 70 covers STI region 68, such that dummy dielectric layer 70 extends between dummy gate layer 72 and STI region 68.

[0037] Figures 6A to 26C Various additional steps in fabricating embodiment devices are shown. Figure 7A 、 Figure 8A 、 Figure 14A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 18C 、 Figure 19A 、 Figure 19C 、 Figure 20A 、 Figure 21A 、 Figure 24C 、 Figure 25C and Figure 26C The features of either the n-type region 50N or the p-type region 50P are shown. Figure 6A and Figure 6B In the embodiment, the mask layer 74 can be patterned using acceptable photolithography and etching techniques (see Figure 5 ) to form mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectric 71, respectively. Dummy gates 76 cover corresponding channel regions of fins 66. The pattern of mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. Dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of corresponding fins 66.

[0038] exist Figure 7A and Figure 7B In Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In the embodiment of the present invention, a first spacer layer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0039] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implant for lightly doped source / drain (LDD) regions (not separately shown) may be performed. In embodiments with different device types, similar to the above, Figure 4As discussed above, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of an appropriate type (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of an appropriate type (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities, and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have a density of approximately 1×10 15 atoms / cm 3 to about 1×10 19 atoms / cm 3 Annealing can be used to repair implantation damage and activate the implanted impurities.

[0040] exist Figure 8A and Figure 8B , the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83. As will be discussed in more detail below, the first spacers 81 and the second spacers 83 are used to self-align with the subsequently formed source and drain regions, and to protect the sidewalls of the fins 66 and / or the nanostructures 55 during subsequent processes. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, for example, an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that the first spacer layer 80 can serve as an etch stop layer when patterning the second spacer layer 82, and the second spacer layer 82 can serve as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in FIG. Figure 8A Thereafter, the second spacer 83 is used as a mask while etching the exposed portion of the first spacer layer 80, thereby forming a Figure 8A A first spacer 81 is shown.

[0041] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8BAs shown, in some embodiments, the second spacer layer 82 can be removed from over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacers 81 are disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 70. In other embodiments, a portion of the second spacer layer 82 can remain over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0042] Note that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc. Furthermore, different structures and steps may be used to form n-type devices and p-type devices.

[0043] exist Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A and Figure 14B In the nanoFET process, a series of implantation and recessing steps are used to implant ions into the region that will become the channel region of the nanoFET. The implanted ions can form a channel junction, which reduces the channel resistance and reduces the resistance between the subsequently formed source / drain regions and the channel region. In other words, the channel junction serves to reduce the resistance at the interface between the subsequently formed source / drain regions and the channel region.

[0044] In embodiments with different device types, the devices in the n-type region 50N can be processed separately from the devices in the p-type region 50P. Figure 4 As discussed above, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P. A series of implantation and recessing steps may then be performed in the p-type region 50P until a layer of N-type ... Figure 14A and Figure 14B The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N. A series of implantation and recessing steps may then be performed in the n-type region 50N until a cavitation layer is formed in the n-type region 50N. Figure 14A and Figure 14BThe mask may then be removed. In some embodiments, the n-type region 50N may be processed to form Figure 14A and Figure 14B The process then proceeds to process the p-type region 50P. Using this process, a single mask can be used to protect one device region while processing another. Other embodiments may utilize other orders for processing the n-type region 50N and the p-type region 50P, including, for example, using multiple masks to process groups of first nanostructures 52 and / or second nanostructures 54 together.

[0045] Figure 9A and Figure 9B An implantation process 59N in the n-type region 50N and an implantation process 59P in the p-type region 50P are shown. The n-type impurities used may be any of the n-type impurities previously discussed and may include arsenic, phosphorus, and antimony. The p-type impurities used may be any of the p-type impurities previously discussed and may include boron, BF2, indium, and gallium.

[0046] The implantation process 59N and the implantation process 59P can be performed using configurable process conditions, including, for example, implantation energy, implantation angle, implantation temperature, and implantation duration. In general, each of these process conditions can be adjusted based on the dopant used, the target implantation concentration, and the desired (vertical and lateral) implantation depth. The implantation process 59N and the implantation process 59P produce an implanted region 57C, a portion of which includes a channel junction 56C in the p-type region 50P and a channel junction 58C in the n-type region 50N. After the implantation, a portion of the first nanostructure 52 and the second nanostructure 54 will be removed, leaving another portion of the first nanostructure 52 and the second nanostructure 54 that will serve as the channel region. The implantation process 59N and the implantation process 59P are performed to form a channel junction 58C that extends below the first spacer 81 and below the dummy gate electrode 76. Therefore, the size of the channel junction 58N is ultimately determined by the lateral spread of the implanted ions (see, for example Figure 10B LS c ). Thus, as will be discussed further below, process conditions can be selected to achieve a desired amount of lateral spread.

[0047] For each of implantation process 59N and implantation process 59P, the implantation angle may have a tilt angle between approximately 3 degrees and 15 degrees and a rotation angle between 0 and 360 degrees, but other angles may be considered and used. The tilted implantation angle may be configured to provide a channel junction below the first spacer 81. Implantation process 59N and implantation process 59P may be performed at a temperature range between approximately room temperature (approximately 20° C.) and approximately 450° C., but other temperatures may be considered and used. Implantation process 59N and implantation process 59P may be performed for a duration between approximately 10 seconds and 300 seconds, but other durations may be considered and used. The implantation energy depends on the dopant used. For implantation process 59N, arsenic may be implanted using an energy between approximately 3 keV and 15 keV, phosphorus may be implanted using an energy between approximately 2 keV and 10 keV, and antimony may be implanted using an energy between approximately 4 keV and 17 keV. For implantation process 59P, boron may be implanted using an energy between about 1.5 keV and 8 keV, BF2 may be implanted using an energy between about 2.5 keV and 12 keV, indium may be implanted using an energy between about 4 keV and 50 keV, and gallium may be implanted using an energy between about 4 keV and 17 keV. It will be appreciated that other dopants may be used, and other implant energies may be utilized depending on the dopants used (and other process conditions). The peak implant concentrations achieved for the trench junction may be between about 1×10 18 cm -3 and 1×10 22 cm -3 and for antimony, indium, and gallium can be between about 1×10 18 cm -3 and 1×10 21 cm -3 between.

[0048] After implantation process 59N, implantation region 57C includes a channel junction 58C formed in nanostructure 54C, which extends below first spacer 81. In addition, implantation process 59N may also implant dopants into nanostructure 52C as part of implantation region 57C. When a subsequent process removes the exposed portion of nanostructure 54C, the corresponding portion of nanostructure 52C is also removed, and a portion of implantation region 57C (and the implanted dopants) may remain in nanostructure 52C.

[0049] In some embodiments, for example Figure 9A and Figure 9BAs shown, after removing the exposed portion of nanostructure 54C to expose nanostructure 52C, an implantation process 59P is performed on nanostructure 52C. In such an embodiment, implanted region 57C may include the region overlying nanostructure 54C below first spacer 81 and below dummy gate dielectric 71. In other embodiments, implantation process 59P is performed using process conditions sufficient to implant ions into both nanostructures 52C and 54C. Such an embodiment is illustrated by replacing implantation process 59P with implantation process 59N, starting from n-type region 50N. Implanted region 57C will then include a portion of channel junction 56C and overlying nanostructure 54C.

[0050] After implantation process 59P, implanted regions 57C and 57B include a channel junction 56C formed in nanostructure 52C, which extends below first spacer 81. Implantation process 59P may also implant dopants into nanostructure 54B to form implanted region 57B, and / or implant dopants into nanostructure 54C to form implanted region 57C.

[0051] Figure 10A and Figure 10B The dry etching process and surface cleaning process for recessing the first and second nanostructures 52 and 54 are shown, wherein the epitaxial source / drain regions 92 will be formed (see FIG. Figure 18A and Figure 18B ). The dry etching can be performed using any suitable etchant to remove the exposed portions of the nanostructures 52C and 54C in the n-type region 50N and the exposed portions of the nanostructures 52C and 54B in the p-type region 50P. When etching the nanostructure 54C in the n-type region 50N, the underlying nanostructure 52C can serve as an etch stop layer, or a timed etch can be used. When etching the nanostructure 52C in the n-type region 50N or the p-type region 50P, the nanostructure 54B can serve as an etch stop layer, or a timed etch can be used. In some embodiments, after etching the nanostructure 52C in the p-type device region, the exposed nanostructure 54B is etched to expose the nanostructure 52B, which can serve as an etch stop layer, or a timed etch can be used. This dry etching process removes the damaged areas of the nanostructures 52C and 54C that were damaged by the ion implantation without laterally etching the channel junctions 56C and 58C or the implanted region 57C under the gate spacer 81.

[0052] After each dry etching, a surface cleaning process can be used to remove the residues and by-products produced by the dry etching. Suitable etchants for dry etching can include XeF2, BrF3, ClF3, CF4, SiF4, NF3, etc., or a combination thereof. Corresponding surface cleaning chemicals, mixtures or solutions can be used, for example, HF, HNO=, O3, H2SO4:H2O (sulfuric acid-hydrogen peroxide mixture (SPM), ratio of, for example, 1:4), NH=OH:H2O2:H2O (ammonium hydroxide-hydrogen peroxide-water mixture (APM), ratio of, for example, 0.25:1:5), and HCl:H2O2:H2O (hydrochloric acid-hydrogen peroxide-water mixture (HPM), ratio of, for example, 1:1:5), etc., or a combination thereof.

[0053] In some embodiments, the ion implantation, dry etching, and surface cleaning processes can each be performed in a separate processing chamber. In other embodiments, each processing chamber can be part of a cluster tool. In such embodiments, the cluster tool can be configured to maintain specific environmental conditions across each tool processing chamber. For example, a vacuum level can be maintained between the ion implantation, dry etching, and surface cleaning processes. The cluster tool can also have a processing chamber that provides processes for applying masking layers, patterning photosensitive materials, and the like. One or more of these processes can be performed in a separate tool.

[0054] After dry etching and surface cleaning, implanted region 57C includes implanted regions of nanostructure 52C and nanostructure 54C below first spacer 81, including channel junctions 56C and 58C. The width or lateral spread LS of channel junctions 56C and 58C is C From the edge of the opening (e.g. Figure 14A and Figure 14B A portion of the first recess 86, or the sidewalls of the channel junctions 56C and 58C, extends to a depth of about 1×10 18 cm -3 The dopant concentration threshold value corresponds to a lateral depth of 100 nm, after which the dopant concentration further decreases logarithmically in nanostructures 54C and 52C. In some embodiments, the lateral spread LS C Between about 3 nm and 5 nm. The channel junctions 56C and 58C may be damaged by the ion implantation, which may be repaired or recrystallized by a subsequent annealing process, which may be performed after the surface cleaning process or at a subsequent stage.

[0055] exist Figure 11A and Figure 11B, second implantation processes 59N and 59P are shown. In the n-type region 50N, the second implantation process 59N implants dopants into the nanostructure 54B to form a channel junction 58B, and in the p-type region 50P, the second implantation process 59P implants dopants into the nanostructure 52B to form a channel junction 56B. The implantation regions 57 (e.g., 57A, 57B, and 57C) include these channel junctions 56B, 58B and the dotted line region, similar to Figure 9A and Figure 9B As shown above. Figure 9A and Figure 9B The second implantation processes 59N and 59P may be performed using similar processes and materials as discussed above and will not be repeated. The implanted dopants used in the second implantation processes 59N and 59P may be the same as those used in the Figure 9A and Figure 9B The dopants used in the first implantation processes 59N and 59P may be the same or different. In addition, the process conditions (e.g., energy level, tilt, rotation, duration, temperature, etc.) used in the second implantation processes 59N and 59P may be different from those used in the first implantation processes 59N and 59P to form a desired channel junction.

[0056] Figure 12A and Figure 12B The dry etching process and surface cleaning process for the recessed first and second nanostructures 52 and 54 are shown, wherein the epitaxial source / drain regions 92 will be formed (see FIG. Figure 18A and Figure 18B ), and the above Figure 10A and Figure 10B The dry etch may be performed using any suitable etchant to remove the exposed portions of the nanostructures 52B and 54B in the n-type region 50N and the exposed portions of the nanostructures 52B and 54A in the p-type region 50P. The width or lateral spread LS of the channel junctions 56B and 58B may be determined by the following equation: B The thickness may be between about 3 nm and 5 nm. The channel junctions 56B and 58B may be damaged by the ion implantation, and they may be repaired or recrystallized by a subsequent annealing process, which may be performed after the surface cleaning process or at a subsequent stage.

[0057] exist Figure 13A and Figure 13B, third implantation processes 59N and 59P are shown. In the n-type region 50N, the second implantation process 59N implants dopants into the nanostructure 54B to form a channel junction 58B, and in the p-type region 50P, the second implantation process 59P implants dopants into the nanostructure 52B to form a channel junction 56B. The implantation regions 57 (e.g., 57A, 57B, and 57C) include these channel junctions 56B, 58B and the dotted line region, similar to Figure 9A and Figure 9B As shown above. Figure 9A and Figure 9B The third implantation processes 59N and 59P are performed using similar processes and materials as discussed above and are not repeated. The implanted dopants used in the third implantation processes 59N and 59P may be the same as those used in the Figure 9A and Figure 9B Dopants used in the first implantation processes 59N and 59P, and / or Figure 11A and Figure 11B The dopant species used in the second implantation processes 59N and 59P can be the same as or different from the dopant species used in the third implantation processes 59N and 59P. Furthermore, the process conditions (e.g., energy level, tilt, rotation, duration, temperature, etc.) used in the third implantation processes 59N and 59P can be different from those used in the first implantation processes 59N and 59P and / or the second implantation processes 59N and 59P to achieve the desired channel junction. In embodiments with more nanostructures and additional implantation steps, the dopant species can be the same as or different from the species used in the other nanosheets.

[0058] Figure 14A and Figure 14B The dry etching process and surface cleaning process for recessing the first and second nanostructures 52 and 54 are shown, wherein the epitaxial source / drain regions 92 will be formed (see FIG. Figure 18A and Figure 18B ), and the above Figure 10A and Figure 10B The dry etch may be performed using any suitable etchant to remove the exposed portions of the nanostructures 52A and 54A in the n-type region 50N and the exposed portions of the nanostructure 52A in the p-type region 50P. The width or lateral spread LS of the channel junctions 56A and 58A may be determined by the following equation: A The thickness of the first trench 86 may be between about 3 nm and 5 nm. The dry etching process and the surface cleaning process may be continued to etch a portion of the substrate 50, thereby forming a first recess 86 between the nanostructures 55. The channel junctions 56A and 58A may be damaged by the ion implantation, which may be repaired or recrystallized by a subsequent annealing process, which may be performed after the surface cleaning process or at a subsequent stage.

[0059] Figures 15A to 15U Various embodiments of the resulting channel junctions 56 and 58 of nanostructure 55 are shown. While these figures explicitly illustrate the channel junction 58 for n-type region 50N, it can be readily understood that the same illustrations can be used to understand the same concepts as applied to p-type region 50P. As described above, because the process conditions for the ion implantation processes (i.e., implantation processes 59N and 59P) are configurable, the resulting channel junctions 56 and 58 can be configured to have different lateral spreads (LS) for each nanostructure 55. When considered together, the different channel junctions LS produce different junction types (JT). Figures 15A to 15U Each of the figures shows a different junction type for a three sheet nanostructure configuration. Those skilled in the art will appreciate that modifications can be made for a two sheet nanostructure configuration, or a four sheet or more nanostructure configuration. By using additional masking processes for each junction type, these different junction types can be combined in the same device area. When the following description describes the first distance of implantation as being approximately the same as the second distance of implantation, in some embodiments, the first distance is within 15% of the second distance. In other embodiments, the first distance being approximately the same as the second distance means that the process conditions for the implantation of the first distance are the same as the process conditions for the implantation of the second distance.

[0060] refer to Figure 15A , the junction type JT has a trapezoidal shape with a base that is wider at the bottom than at the top. The junction type JT is determined by the undoped channel length L between the two channel junctions 58 at either end. For example, in Figure 15A In the example, the lateral spread LS of the channel junction 58C is C greater than the lateral spread LS of the channel junction 58B B , the lateral spread LS of the channel junction 58B B greater than the lateral spread LS of the channel junction 58A A The corresponding undoped channel length L between each of these channel junctions 58 is opposite to the lateral spread LS, such that the undoped channel length L C Less than the undoped channel length L B , the undoped channel length L B Less than the undoped channel length L A The resulting shape of the undoped channel length L is a trapezoid. A similar junction type JT can be realized for the p-type region 50P and the channel junction 56.

[0061] Different junction types demonstrate the ability to provide nanosheet junctions with variable and configurable lateral spreading LS. The controllable junctions can be configured to, for example, provide customized device-to-device control of device properties, including DC boosting, short channel effects, and leakage control.

[0062] exist Figure 15B In the nanostructure 54B, the undoped channel length L C Greater than the undoped channel length L B The undoped channel length L in the nanostructure 54B is B Greater than the undoped channel length L in nanostructure 54A A The lateral spread LS of the channel junction 58C C smaller than the lateral spread LS of the channel junction 58B B The lateral spread LS of the channel junction 58B B smaller than the lateral spread LS of the channel junction 58A A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0063] exist Figure 15C In the nanostructure 54B, the undoped channel length L C Greater than the undoped channel length L B The undoped channel length L in the nanostructure 54B is B is less than the undoped channel length L in the nanostructure 54A A The undoped channel length L C and L A The lateral spread LS of the channel junction 58C is approximately the same. C smaller than the lateral spread LS of the channel junction 58B B The lateral spread LS of the channel junction 58B B greater than the lateral spread LS of the channel junction 58A A . Horizontal spread LS C and LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0064] exist Figure 15D In the example, the junction type JT has a rectangular shape. The undoped channel length L C , L B and L A Roughly the same. Horizontal spread LS C LS B and LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0065] exist Figure 15E In the nanostructure 54B, the undoped channel length L C Less than the undoped channel length L BThe undoped channel length L in the nanostructure 54B is B Greater than the undoped channel length L in nanostructure 54A A The undoped channel length L C and L A The lateral spread LS of the channel junction 58C is approximately the same. C greater than the lateral spread LS of the channel junction 58B B The lateral spread LS of the channel junction 58B B smaller than the lateral spread LS of the channel junction 58A A . Laterally spread LS C and LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0066] exist Figure 15F The junction type JT has a spike shape. The undoped channel length L C With the undoped channel length L B The undoped channel length L A Less than the undoped channel length L B and the undoped channel length L C . Horizontal spread LS C With lateral dispersion LS B Roughly the same. Horizontal spread LS A Greater than lateral dispersion LS B and LS C A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0067] exist Figure 15G The junction type JT has an anti-spike shape. The undoped channel length L B With the undoped channel length L A The undoped channel length L C Less than the undoped channel length L B and the undoped channel length L A . Horizontal spread LS B With lateral dispersion LS A Roughly the same. Horizontal spread LS C Greater than lateral dispersion LS B and LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0068] exist Figure 15H In the case of a junction type JT, the junction has an inverted funnel shape. The undoped channel length L C With the undoped channel length L BThe undoped channel length L A Greater than the undoped channel length L B and the undoped channel length L C . Horizontal spread LS C With lateral dispersion LS B Roughly the same. Horizontal spread LS A Less than lateral dispersion LS B and LS C A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0069] exist Figure 15I The junction type JT has a funnel shape. The undoped channel length L B With the undoped channel length L A The undoped channel length L C Greater than the undoped channel length L B and the undoped channel length L A . Horizontal spread LS B With lateral dispersion LS A Roughly the same. Horizontal spread LS C Less than lateral dispersion LS B and LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0070] Figures 15J to 15U A further configuration is shown in which some of the nanostructures have ion implantation omitted, for example, implantation process 59N or 59P. Thus, one or more of the first nanostructures 52 and / or 54 may not have channel junctions 56 and / or 58. In other words, one or more of the first nanostructures 52 and / or 54 may have channel junctions 56 and / or 58, while one or more of the second nanostructures 52 and / or 54 may not have channel junctions 56 and / or 58. For the purposes of the following discussion, it should be understood that when a nanostructure 54 is described as "undoped," this means that implantation processes 59N and 59P have not been used for that particular nanostructure (e.g., nanostructure 54B). Dopants may still be present, but at a concentration less than that in channel junctions 56 and / or 58, such that they do not function as channel junctions.

[0071] exist Figure 15J In the example, the junction type JT has a trapezoidal shape. The undoped channel length L C Less than the undoped channel length L A Nanostructure 54B remains undoped. Laterally diffused LS C Greater than lateral dispersion LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0072] exist Figure 15K In the case of a junction type JT, the junction has an inverted trapezoidal shape. The undoped channel length L C Greater than the undoped channel length L A Nanostructure 54B remains undoped. Laterally diffused LS C Less than lateral dispersion LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0073] exist Figure 15L In the case of a junction type JT, the junction has an inverted trapezoidal shape. The undoped channel length L B Greater than the undoped channel length L A The nanostructure 54C remains undoped. Laterally diffused LS B Less than lateral dispersion LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0074] exist Figure 15M In the example, the junction type JT has a trapezoidal shape. The undoped channel length L B Less than the undoped channel length L A The nanostructure 54C remains undoped. Laterally diffused LS B Greater than lateral dispersion LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0075] exist Figure 15N In the example, the junction type JT has a rectangular shape. The undoped channel length L B With the undoped channel length L A The nanostructure 54C remains undoped. Laterally diffused LS B With lateral dispersion LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0076] exist Figure 15O In the case of a junction type JT, the junction has an inverted trapezoidal shape. The undoped channel length L C Greater than the undoped channel length L B Nanostructure 54A remains undoped. Laterally diffused LS C Less than lateral dispersion LS B A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0077] exist Figure 15P In the example, the junction type JT has a trapezoidal shape. The undoped channel length L CLess than the undoped channel length L B Nanostructure 54A remains undoped. Laterally diffused LS C Greater than lateral dispersion LS B A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0078] exist Figure 15Q In the example, the junction type JT has a rectangular shape. The undoped channel length L C With the undoped channel length L B The nanostructure 54A remains undoped. C With lateral dispersion LS B A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0079] exist Figure 15R In FIG. 5 , the junction type JT has a rectangular shape, and only one of the nanostructures 55 and 54B is doped to form the channel junction 58B. Nanostructures 54A and 54C remain undoped. A similar junction type JT can be implemented for the p-type region 50P and the channel junction 56.

[0080] exist Figure 15S In FIG. 5 , the junction type JT has a rectangular shape, and only one of the nanostructures 55 and 54C is doped to form the channel junction 58C. Nanostructures 54B and 54A remain undoped. A similar junction type JT can be implemented for the p-type region 50P and the channel junction 56.

[0081] exist Figure 15T In FIG. 5 , the junction type JT has a rectangular shape, and only one of the nanostructures 55 and 54A is doped to form the channel junction 58A. Nanostructures 54B and 54C remain undoped. A similar junction type JT can be implemented for the p-type region 50P and the channel junction 56.

[0082] exist Figure 15U In the example, the junction type JT has a rectangular shape. The undoped channel length L C With the undoped channel length L A Nanostructure 54B remains undoped. Laterally diffused LS C With lateral dispersion LS A A similar junction type JT can be realized for the p-type region 50P and the channel junction 56 .

[0083] exist Figure 16A and Figure 16BIn the embodiment, the portion of the sidewalls of the layers of the nanostructure 55 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first groove 86 is etched to form a sidewall groove 88 in the n-type region 50N, and the portion of the sidewalls of the layers of the nanostructure 55 formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the first groove 86 is etched to form a sidewall groove 88 in the p-type region 50P. Figure 16B The sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight, but these sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process (e.g., wet etching, etc.). A mask (not shown) can be used to protect the p-type region 50P, while the first nanostructure 52 is etched using an etchant selective to the first semiconductor material, so that in the n-type region 50N, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N, while the second nanostructure 54 is etched using an etchant selective to the second semiconductor material, so that in the p-type region 50P, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, the sidewalls of the first nanostructure 52 in the n-type region 50N may be etched using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like, and the sidewalls of the second nanostructure 54 in the p-type region 50P may be etched using a dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like.

[0084] In some embodiments, after recessing the sidewalls of the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P, in some embodiments, the sidewalls of the first nanostructure 52 and the second nanostructure 54 may be recessed less than the lateral depth of the implanted region 57 (see FIG. Figure 14A and Figure 14B ). In such an embodiment, the sidewalls of the first and second nanostructures 52, 54 adjacent to the associated sidewall recesses 88 include a portion of the implanted region 57. Thus, the implanted ions (dopant) can be observed at the recessed sidewalls of the first and second nanostructures 52, 54. In other embodiments, the implanted region 57 can be removed from the first and second nanostructures 52, 54 when the sidewalls of the first and second nanostructures 52, 54 are recessed.

[0085] exist Figures 17A-17C In the embodiment, a first inner spacer 90 is formed in the sidewall groove 88. Figure 16A and Figure 16B An internal spacer layer (not separately shown) is deposited over the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with corresponding gate structures.

[0086] The inner spacer layer can be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer can include a material such as silicon nitride or silicon oxynitride, but any suitable material can be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer can then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown as being flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 can extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0087] In addition, despite Figure 17B The outer sidewall of the first inner partition 90 is shown as straight, but the outer sidewall of the first inner partition 90 can be concave or convex. As an example, Figure 17C An embodiment is shown in which, in the n-type region 50N, the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the second nanostructure 54. An embodiment is also shown in which, in the p-type region 50P, the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the first nanostructure 52. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent etching of the source / drain regions (e.g., as described below with respect to FIG. 1 ) that are subsequently formed by a subsequent etching process (e.g., an etching process for forming a gate structure). Figures 18A-18D Damage to the epitaxial source / drain regions 92) is discussed.

[0088] During deposition, the first inner spacer 90 may be free of dopants, which may remain in the sidewall recesses 88 of the first nanostructure 52 and the sidewall recesses 88 of the second nanostructure 54, as described above. However, subsequent processing may cause the corresponding dopants in the implanted regions 57 of the n-type region 50N and the implanted regions 57 of the p-type region 50P to diffuse from the sidewalls of the first nanostructure 52 and / or the second nanostructure 54 into the first inner spacer 90. Thus, the corresponding n-type dopant may be found in the first inner spacer 90 of the n-type region 50N, and the p-type dopant may be found in the first inner spacer 90 of the p-type region 50P. The peak concentration of the corresponding dopant may be found at the interface 90i between the sidewalls of the first nanostructure 52 or the second nanostructure 54 and the first inner spacer 90. The concentration of the dopant at the interface 90 i may decrease gradually from the interface in either lateral direction, ie, laterally deeper into the first inner spacer 90 from the interface 90 i and laterally deeper into the first nanostructure 52 or the second nanostructure 54 from the interface 90 i .

[0089] exist Figures 18A-18D In the embodiment, epitaxial source / drain regions 92 are formed in the first recesses 86. In some embodiments, the epitaxial source / drain regions 92 can exert stress on the second nanostructures 54 in the n-type region 50N and the first nanostructures 52 in the p-type region 50P, thereby improving performance. Figure 18B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76 by an appropriate lateral distance, and first inner spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting nanoFET.

[0090] Epitaxial source / drain regions 92 in n-type region 50N (e.g., NMOS region) can be formed by masking p-type region 50P (e.g., PMOS region). Epitaxial source / drain regions 92 are then epitaxially grown in first recess 86 in n-type region 50N. Epitaxial source / drain regions 92 can include any acceptable material suitable for n-type nanoFETs. For example, if second nanostructure 54 is silicon, epitaxial source / drain regions 92 can include a material that applies tensile strain to second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, etc. Epitaxial source / drain regions 92 can have surfaces that are raised from the corresponding upper surfaces of nanostructure 55 and can have small facets.

[0091] The epitaxial source / drain regions 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain regions 92 are then epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain regions 92 can include any acceptable material suitable for use in a p-type nanoFET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain regions 92 can include a material that applies compressive strain to the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 92 can also have surfaces that protrude from the corresponding upper surfaces of the nanostructure 55 and can have small facets.

[0092] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The impurity concentration of the source / drain regions may be approximately 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0093] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets allow adjacent epitaxial source / drain regions 92 of the same NSFET to merge, e.g., Figure 18A In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in FIG. Figure 18C As shown. Figure 18A and Figure 18C In the illustrated embodiment, first spacers 81 can be formed on the top surface of STI regions 68 to prevent epitaxial growth. In some other embodiments, first spacers 81 can cover portions of the sidewalls of nanostructures 55 to further prevent epitaxial growth. In some other embodiments, the spacer etch used to form first spacers 81 can be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of STI regions 68.

[0094] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than that of the second semiconductor material layer 92B and greater than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0095] Figure 18D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 18D As shown, epitaxial source / drain regions 92 may be formed in contact with the first inner spacer 90 and may extend beyond sidewalls of the second nanostructures 54 in the n-type region 50N and beyond sidewalls of the first nanostructures 52 in the p-type region 50P.

[0096] exist Figures 19A-19C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Figure 6A 、 Figure 18B and Figure 18A Above the structure shown ( Figures 7A-18B The process does not change Figure 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacers 81. The CESL 94 may include a dielectric material having a different etch rate than the material of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0097] exist Figure 20A and Figure 20B During the planarization process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0098] exist Figure 21A and Figure 21B In one or more etching steps, dummy gate 76 and mask 78 (if present) are removed, thereby forming second recesses 98. Portions of dummy gate dielectric layer 71 within second recesses 98 may also be removed. In some embodiments, dummy gate 76 and dummy gate dielectric layer 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches dummy gate 76 at a faster rate than first ILD 96 or first spacers 81. Each second recess 98 exposes and / or overlies portions of nanostructure 55 that serve as channel regions in the subsequently completed nanoFET. The portions of nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, dummy gate dielectric layer 71 may serve as an etch stop when etching dummy gate 76. Dummy gate dielectric layer 71 may then be removed after dummy gate 76 is removed.

[0099] exist Figure 22A and Figure 22B In the embodiment, first nanostructure 52 in n-type region 50N and second nanostructure 54 in p-type region 50P are removed, while second recess 98 is expanded. First nanostructure 52 can be removed by forming a mask (not shown) over p-type region 50P and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant selective for the material of first nanostructure 52, while second nanostructure 54, substrate 50, and STI region 68 remain relatively unetched compared to first nanostructure 52. In embodiments where first nanostructure 52 comprises, for example, SiGe and second nanostructures 54A-54C comprise, for example, Si or SiC, first nanostructure 52 in n-type region 50N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0100] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant that is selective for the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 includes, for example, SiGe and the first nanostructure 52 includes, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, etc. can be used to remove the second nanostructure 54 in the p-type region 50P.

[0101] After removing the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P, the spacer 90 spanning between the remaining second nanostructure 54 and the first nanostructure 52, respectively, may be doped. As described above, the dopant in the removed nanostructure 55 may diffuse into the spacer 90. The concentration of the dopant in the spacer 90 is the highest on the side of the spacer opposite the source / drain region 92, and the concentration decreases in a gradient toward the source / drain region 92.

[0102] exist Figure 23A and Figure 23B, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68.

[0103] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0104] The gate electrode 102 is deposited on the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. For example, although Figure 23A and Figure 23B A single-layer gate electrode 102 is shown in FIG. 1 , but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers comprising the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the nanostructures 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0105] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed using a different process, such that the gate dielectric layer 100 can be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region can be formed using a different process, such that the gate electrode 102 can be a different material and / or have a different number of layers. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0106] After filling the second recess 98, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are above the top surface of the first ILD 96. The material of the gate electrode 102 and the remaining portions of the gate dielectric layer 100 thus form a replacement gate structure for the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as a "gate structure."

[0107] exist Figures 24A-24C In the process, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed to form a groove directly above the gate structure and between the opposite portion of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and a planarization process is then performed to remove excess portions of the dielectric material extending above the first ILD 96. The gate contact (e.g., as described below) is subsequently formed. Figure 26A and Figure 26B The gate contact 114 discussed here passes through the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0108] like Figures 24A-24C As further shown, a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0109] exist Figures 25A-25C10. In the embodiment of the present invention, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108, exposing the surface of the epitaxial source / drain regions 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; etched through the gate mask 104 using a second etching process; and then etched through the CESL 94 using a third etching process. A mask (e.g., a photoresist) can be formed over the second ILD 106 and patterned to shield portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, so that the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level or at the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Figure 25B The third recess 108 is shown exposing the epitaxial source / drain regions 92 and the gate structure in the same cross-section. However, in various embodiments, the epitaxial source / drain regions 92 and the gate structure may be exposed in different cross-sections to reduce the risk of shorting contacts formed subsequently. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain regions 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon germanium, germanium) of the epitaxial source / drain regions 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portions of the epitaxial source / drain regions 92, and then performing a thermal annealing process to form the silicide region 110. The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although silicide region 110 is referred to as a silicide region, silicide region 110 may also be a germanide region or a silicon-germanide region (e.g., a region including silicide and germanide). In an embodiment, silicide region 110 includes TiSi and has a thickness in a range between about 2 nm and about 10 nm.

[0110] Next, in Figures 26A-26CIn the embodiment of the present invention, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer 116 and a conductive material 118 and are electrically coupled to underlying conductive features (e.g., in the illustrated embodiment, the gate electrode 102 and / or the silicide region 110). Gate contact 114 is electrically coupled to gate electrode 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. Barrier layer 116 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. Conductive material 118 may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of second ILD 106.

[0111] Embodiments can achieve advantages. For example, channel junctions can be formed in the nanostructures, thereby reducing the overall channel resistance. In addition, the use of a multi-step ion implantation process provides the ability to achieve adjustable lateral distribution for each nanostructure implanted. The use of a multi-step trench and implantation system provides the ability to dope each nanosheet differently in the channel region below the gate of the nanoFET. Each nanosheet can have an undoped channel width that can be configured to have a specific lateral distribution, ion concentration, and dopant type for each nanosheet. Because each nanosheet can be individually configured, each nanosheet can have different technical specifications, including completely omitting implantation from selected nanostructures.

[0112] One embodiment is a device comprising a first nanostructure comprising a first doped channel junction at either end. The device further comprises a second nanostructure above the first nanostructure, the second nanostructure comprising a second doped channel junction at either end. The device further comprises a gate structure disposed above the first and second nanostructures, the gate structure extending between the first and second nanostructures. The device further comprises source / drain regions adjacent to the gate structure, the source / drain regions contacting the first and second nanostructures. In one embodiment, the device further comprises: an internal spacer disposed at either end of the first nanostructure, the internal spacer extending between the first and second nanostructures, the internal spacer interposed between a gate dielectric and the source / drain regions of the gate structure. In one embodiment, the internal spacer comprises a first dopant having a peak concentration at an interface between the internal spacer and the gate dielectric. In one embodiment, the first doped channel junction has a first lateral spread between 3 nm and 5 nm. In one embodiment, the second doped channel junction has a second lateral spread different from the first lateral spread. In one embodiment, the first dopant concentration in the first doped channel junction is between 1×10 18 cm -3 and 1×10 22 cm -3 between.

[0113] Another embodiment provides a transistor comprising a first nanostructure and a second nanostructure above the first nanostructure, wherein at least one of the first nanostructure or the second nanostructure comprises a first doped channel junction at each end and a first undoped channel length between the first doped channel junctions. The transistor further comprises a gate structure disposed above the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure. The transistor further comprises a source / drain region adjacent to the gate structure, the source / drain region contacting the first nanostructure and the second nanostructure. In one embodiment, at least the second of the first nanostructure or the second nanostructure comprises a second doped channel junction at each end and a second undoped channel length between the second doped channel junctions. In one embodiment, the first undoped channel length is a different value from the second undoped channel length. In one embodiment, the third nanostructure comprises a third doped channel junction at each end and a third undoped channel length between the third doped channel junctions. In one embodiment, at least two of the first undoped channel length, the second undoped channel length, and the third undoped channel length are different values. In one embodiment, the first undoped channel length, the second undoped channel length, and the third undoped channel length are all different values.

[0114] Another embodiment is a method comprising forming alternating nanostructures on a substrate. The method further comprises forming a gate structure on the alternating nanostructures. The method further comprises performing a first angled ion implantation to implant a first dopant into a first channel end of the first nanostructure, the first channel end being below the gate structure. The method further comprises etching a first nanostructure in the alternating nanostructures to form a first recess in the first nanostructure adjacent to the gate structure, the etching exposing the first channel end of the first nanostructure. The method further comprises performing a second angled ion implantation to implant a second dopant into a second channel end of the second nanostructure, the second channel end being below the gate structure. The method further comprises etching a second nanostructure in the alternating nanostructures to extend the first recess and form a second recess in the second nanostructure adjacent to the gate structure, the etching exposing the second channel end of the second nanostructure. The method further comprises etching to extend the second recess to form a third recess in the substrate. The method further comprises depositing source / drain regions in the third recess. In one embodiment, the method may comprise recessing a sidewall of the third nanostructure disposed between the first and second nanostructures; and depositing internal spacers on the sidewalls of the third nanostructure. In one embodiment, the sidewalls of the third nanostructure may include ions from the first angled ion implantation or the second angled ion implantation, and the method may include: annealing the third nanostructure and the internal spacer to diffuse the implanted ions from the third nanostructure to the internal spacer. In one embodiment, the first angled ion implantation implants a first dopant into a first channel end of the first nanostructure at a first lateral distance, and wherein the second angled ion implantation implants a second dopant into a second channel end of the second nanostructure at a second lateral distance. In one embodiment, the first lateral distance and the second lateral distance have different values. In one embodiment, the first lateral distance and the second lateral distance are each between 3 nm and 5 nm. In one embodiment, the method may include: after etching the first nanostructure to form the first groove, performing a surface cleaning of the first groove. In one embodiment, the first dopant is a different substance than the second dopant.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0116] Example 1. A semiconductor device comprising: a first nanostructure, the first nanostructure including a first doped channel junction at either end; a second nanostructure, above the first nanostructure, the second nanostructure including a second doped channel junction at either end; a gate structure, disposed above the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure; and a source / drain region adjacent to the gate structure, the source / drain region contacting the first nanostructure and the second nanostructure.

[0117] Example 2. The semiconductor device according to Example 1 further includes: an internal spacer disposed at either end of the first nanostructure, the internal spacer extending between the first nanostructure and the second nanostructure, the internal spacer being interposed between the gate dielectric of the gate structure and the source / drain region.

[0118] Example 3. The semiconductor device of Example 2, wherein the inner spacer comprises a first dopant having a peak concentration at an interface of the inner spacer and the gate dielectric.

[0119] Example 4. The semiconductor device of Example 1, wherein the first doped channel junction has a first lateral spread between 3 nm and 5 nm.

[0120] Example 5. The semiconductor device of Example 1, wherein the second doped channel junction has a second lateral spread that is different from the first lateral spread.

[0121] Example 6. The semiconductor device of Example 1, wherein the first dopant concentration in the first doped channel junction is between 1×10 18 cm -3 and 1×10 22 cm -3 between.

[0122] Example 7. A transistor comprising: a first nanostructure; a second nanostructure above the first nanostructure, wherein at least one of the first nanostructure or the second nanostructure includes a first doped channel junction at each end and a first undoped channel length between the first doped channel junctions; a gate structure disposed above the first nanostructure and the second nanostructure, the gate structure extending between the first nanostructure and the second nanostructure; and a source / drain region adjacent to the gate structure, the source / drain region contacting the first nanostructure and the second nanostructure.

[0123] Example 8. The transistor of Example 7, wherein at least a second of the first nanostructure or the second nanostructure includes a second doped channel junction at each end and a second undoped channel length between the second doped channel junctions.

[0124] Example 9. The transistor of Example 8, wherein the first undoped channel length is a different value than the second undoped channel length.

[0125] Example 10. The transistor of Example 8, further comprising a third nanostructure above the second nanostructure, the gate structure extending between the second nanostructure and the third nanostructure, wherein the third nanostructure comprises a third doped channel junction at each end and a third undoped channel length between the third doped channel junctions.

[0126] Example 11. The transistor of Example 10, wherein at least two of the first undoped channel length, the second undoped channel length, and the third undoped channel length are different values.

[0127] Example 12. The transistor of Example 11, wherein the first undoped channel length, the second undoped channel length, and the third undoped channel length are all different values.

[0128] Example 13. A method for forming a semiconductor device, comprising: forming a plurality of nanostructures above a substrate; forming a gate structure above the plurality of nanostructures; performing a first angled ion implantation to implant a first dopant into a first channel end of a first nanostructure among the plurality of nanostructures, the first channel end being below the gate structure; etching the first nanostructure among the plurality of nanostructures to form a first groove in the first nanostructure adjacent to the gate structure, the etching exposing the first channel end of the first nanostructure; performing a second angled ion implantation to implant a second dopant into a second channel end of a second nanostructure, the second channel end being below the gate structure; etching the second nanostructure among the plurality of nanostructures to extend the first groove and form a second groove in the second nanostructure adjacent to the gate structure, the etching exposing the second channel end of the second nanostructure; etching to extend the second groove to form a third groove above the substrate; and depositing a source / drain region in the third groove.

[0129] Example 14. The method of Example 13, further comprising: recessing a sidewall of a third nanostructure of the plurality of nanostructures disposed between the first nanostructure and the second nanostructure; and depositing an internal spacer on a sidewall of the third nanostructure.

[0130] Example 15. A method according to Example 14, wherein the sidewalls of the third nanostructure include implanted ions from the first angled ion implantation or the second angled ion implantation, the method further comprising: annealing the third nanostructure and the internal spacer, the annealing diffusing the implanted ions from the third nanostructure to the internal spacer.

[0131] Example 16. A method according to Example 14, wherein the first angled ion implantation implants a first dopant into the first channel end of the first nanostructure at a first lateral distance, and wherein the second angled ion implantation implants a second dopant into the second channel end of the second nanostructure at a second lateral distance.

[0132] Example 17. The method of Example 16, wherein the first lateral distance and the second lateral distance have different values.

[0133] Example 18. The method of Example 16, wherein the first lateral distance and the second lateral distance are each between 3 nm and 5 nm.

[0134] Example 19. The method of Example 13, further comprising: performing surface cleaning of the first groove after etching the first nanostructure to form the first groove.

[0135] Example 20. The method of Example 13, wherein the first dopant is a different substance than the second dopant.

Claims

1. A semiconductor device comprising: a first nanostructure comprising a first doped channel junction at either end; a second nanostructure above the first nanostructure, the second nanostructure comprising a second doped channel junction at either end; a gate structure, disposed on the first nanostructure and the second nanostructure, wherein the gate structure extends between the first nanostructure and the second nanostructure; as well as a source / drain region, adjacent to the gate structure, wherein the source / drain region is in contact with the first nanostructure and the second nanostructure; as well as an inner spacer disposed at either end of the first nanostructure, the inner spacer extending between the first nanostructure and the second nanostructure, the inner spacer being interposed between a gate dielectric of the gate structure and the source / drain regions, and the inner spacer comprising a first dopant, the peak concentration of the first dopant being at an interface between the inner spacer and the gate dielectric.

2. The semiconductor device according to claim 1, wherein The first doped channel junction has a first lateral spread between 3 nm and 5 nm.

3. The semiconductor device according to claim 2, wherein The second doped channel junction has a second lateral spread different from the first lateral spread.

4. The semiconductor device according to claim 1, wherein The first dopant concentration in the first doped channel junction is 1×10 18 cm -3 and 1×10 22 cm -3 between.

5. A transistor comprising: a first nanostructure comprising a first doped channel junction at each end and a first undoped channel length between the first doped channel junctions; a second nanostructure above the first nanostructure, the second nanostructure comprising a second doped channel junction at each end and a second undoped channel length between the second doped channel junctions, wherein the first undoped channel length is a different value than the second undoped channel length; a gate structure, disposed on the first nanostructure and the second nanostructure, wherein the gate structure extends between the first nanostructure and the second nanostructure; a source / drain region adjacent to the gate structure, the source / drain region contacting the first nanostructure and the second nanostructure; and an inner spacer disposed at either end of the first nanostructure, the inner spacer extending between the first nanostructure and the second nanostructure, the inner spacer being interposed between a gate dielectric of the gate structure and the source / drain regions, and the inner spacer comprising a first dopant, the peak concentration of the first dopant being at an interface between the inner spacer and the gate dielectric.

6. The transistor according to claim 5, further comprising a third nanostructure, the third nanostructure being above the second nanostructure, the gate structure extending between the second nanostructure and the third nanostructure, wherein: The third nanostructure includes a third doped channel junction at each end and a third undoped channel length between the third doped channel junctions.

7. The transistor according to claim 6, wherein At least two of the first undoped channel length, the second undoped channel length, and the third undoped channel length are different values.

8. The transistor according to claim 7, wherein The first undoped channel length, the second undoped channel length, and the third undoped channel length are all different values.

9. A method for forming a semiconductor device, comprising: forming a plurality of nanostructures on a substrate; forming a gate structure over the plurality of nanostructures; performing a first angled ion implantation to implant a first dopant into a first channel end of a first nanostructure of the plurality of nanostructures, the first channel end being below the gate structure; Etching the first nanostructure among the plurality of nanostructures to form a first recess in the first nanostructure adjacent to the gate structure, wherein the etching exposes the first channel end of the first nanostructure; performing a second angled ion implantation to implant a second dopant into a second channel end of a second nanostructure, the second channel end being below the gate structure; etching the second nanostructure among the plurality of nanostructures to extend the first recess and form a second recess in the second nanostructure adjacent to the gate structure, the etching exposing the second channel end of the second nanostructure; performing etching to extend the second groove to form a third groove on the substrate; as well as depositing a source / drain region in the third recess; as well as An inner spacer is formed, the inner spacer being disposed at either end of the first nanostructure, the inner spacer extending between the first nanostructure and the second nanostructure, the inner spacer being interposed between a gate dielectric of the gate structure and the source / drain regions, and the inner spacer comprising a first dopant having a peak concentration at an interface between the inner spacer and the gate dielectric.

10. The method according to claim 9, further comprising: recessing a sidewall of a third nanostructure disposed between the first nanostructure and the second nanostructure; as well as Internal spacers are deposited on sidewalls of the third nanostructure.

11. The method according to claim 10, wherein: The sidewalls of the third nanostructure include implanted ions from the first angled ion implantation or the second angled ion implantation, the method further comprising annealing the third nanostructure and the inner spacer, the annealing diffusing the implanted ions from the third nanostructure to the inner spacer.

12. The method according to claim 10, wherein: The first angled ion implantation implants a first dopant into the first channel end of the first nanostructure at a first lateral distance, and wherein the second angled ion implantation implants a second dopant into the second channel end of the second nanostructure at a second lateral distance.

13. The method according to claim 12, wherein: The first lateral distance and the second lateral distance have different values.

14. The method according to claim 12, wherein: The first lateral distance and the second lateral distance are each between 3 nm and 5 nm.

15. The method according to claim 9, further comprising: After etching the first nanostructure to form the first groove, surface cleaning of the first groove is performed.

16. The method according to claim 9, wherein The first dopant is a substance different from the second dopant.

Images