Inspection apparatus and method for inspecting a semiconductor device

Abstract

Disclosed are an inspection apparatus and method for inspecting a semiconductor device. The inspection apparatus includes: a stage on which a semiconductor device is disposed; a first light source that irradiates high-frequency light onto an inspection region of the semiconductor device to reduce a potential barrier of a PN junction in the semiconductor device; a beam scanner that is disposed above the semiconductor device and irradiates a charged particle beam onto the inspection region of the semiconductor device to generate secondary electrons; and a defect detector that generates a detection image corresponding to the inspection region and detects a defect image from a plurality of detection images based on a voltage contrast between a reference image and the plurality of detection images, the defect image indicating a defect of the semiconductor device.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0051230, filed with the Korean Intellectual Property Office on April 28, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments relate to an inspection apparatus for inspecting semiconductor devices and a method for inspecting semiconductor devices using the inspection apparatus, and more specifically, to an inspection apparatus for inspecting semiconductor devices by using charged particles and a method for inspecting semiconductor devices using the inspection apparatus. Background Technology

[0004] Due to the recent high integration of semiconductor devices, the contact area and critical dimensions of semiconductor devices have been reduced to below the threshold wavelength of inspection devices. This makes it more difficult to inspect semiconductor devices using optical inspection equipment.

[0005] For these reasons, charged particle inspection devices, which use charged particle beams, have been widely used to inspect nanoscale defects in semiconductor devices instead of optical inspection devices, because charged particle inspection devices have relatively high resolution compared to optical inspection devices.

[0006] In conventional charged particle inspection equipment, a beam of charged particles is irradiated onto a semiconductor device, and secondary electrons generated from the semiconductor device in response to the charged particle beam can then be detected. Multiple inspection images can be obtained based on the detection voltage of the secondary electrons, and each inspection image is compared with a reference image to determine the difference in brightness (voltage contrast inspection). Therefore, voltage contrast inspection is used to determine defects and their locations within the semiconductor device.

[0007] However, the size of the inspection area is so small (less than 2 nm) that the charged particle inspection device and the beam scanner used to irradiate the charged particle beam require at least a dwell time to detect a sufficient amount of secondary electrons to generate a detection image. For these reasons, the inspection efficiency / speed of the charged particle inspection device is much lower / slower than that of the optical inspection device.

[0008] As the patterned structures of semiconductor devices have become increasingly smaller, there is a trend towards the more widespread use of charged particle inspection devices, replacing optical inspection devices. However, it is well known that the inspection speed of charged particle inspection devices is less than 1% of that of optical inspection devices. Summary of the Invention

[0009] Example embodiments of the inventive concept provide an inspection apparatus for inspecting a semiconductor device by voltage contrast, in which secondary electrons are sufficiently enhanced and dwell time of a beam scanner is sufficiently reduced.

[0010] Other example embodiments of the inventive concept provide a method of inspecting a semiconductor device by the above-described inspection apparatus.

[0011] According to example embodiments of the inventive concept, there is provided an inspection apparatus including a stage on which a semiconductor device can be placed, the semiconductor device including a plurality of PMOS devices and a plurality of NMOS devices; a first light source that irradiates high-frequency light onto an inspection region of the semiconductor device to reduce a potential barrier of a PN junction in the semiconductor device; a beam scanner disposed above the semiconductor device and irradiating a charged particle beam onto the inspection region of the semiconductor device such that secondary electrons are generated from the inspection region in response to the charged particle beam; and a defect detector that generates a detection image corresponding to the inspection region in response to a voltage of the secondary electrons, and detects a defect image from a plurality of detection images based on voltage contrast between a reference image and the plurality of detection images, the defect image indicating a defect of the semiconductor device.

[0012] According to other example embodiments of the inventive concept, there is provided a method of inspecting a semiconductor device. The semiconductor device including a plurality of NMOS devices and a plurality of PMOS devices can be fixed to a stage. High-frequency light can be irradiated onto a plurality of inspection regions of the semiconductor device to reduce a potential barrier of a PN junction in the semiconductor device. Low-frequency light having an energy greater than a band gap energy of the PN junction can be irradiated onto the plurality of inspection regions to generate a photovoltaic electromotive force at the PN junction in the semiconductor device. Then, a charged particle beam can be irradiated onto the plurality of inspection regions to generate a plurality of secondary electrons from the semiconductor device. The secondary electrons enhanced by the photovoltaic electromotive force can be detected, thereby obtaining a plurality of detection images corresponding to the plurality of inspection regions of the semiconductor device. The detection images can be compared with a reference image, and then detection images satisfying a defect criterion can be detected as defect images indicating defects of corresponding inspection regions of the semiconductor device.

[0013] According to example embodiments of the inventive concept, high-frequency light can be irradiated onto a semiconductor device to reduce a potential barrier of a PN junction, and low-frequency light having an energy greater than a band gap energy of the PN junction can be irradiated onto the semiconductor device to generate a photovoltaic electromotive force in the PN junction. When a charged particle beam is irradiated onto the semiconductor device and secondary electrons are generated from a well region of the semiconductor device, a defect detector can detect a large number of secondary electrons E having enhanced energy.

[0014] The enhanced secondary electron generation detection image can be detected with sufficiently high contrast in a shorter dwell time of the defect detector. Therefore, defects of the semiconductor device can be detected with sufficiently high precision and efficiency by the voltage contrast inspection, regardless of the NMOS device and the PMOS device. Due to the reduced dwell time of the defect detector and the high voltage contrast of the detection image, the inspection process can be performed with high precision on the entire surface of the wafer. BRIEF DESCRIPTION OF DRAWINGS

[0015] These and other features of the present inventive concepts will become more apparent from the detailed description in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a block diagram illustrating a configuration of an inspection apparatus for inspecting a semiconductor device by using a charged particle beam according to an example embodiment of the present inventive concepts;

[0017] Figure 2 is a plan view illustrating a scanning direction of a charged particle beam on a wafer in the inspection apparatus illustrated in Figure 1

[0018] Figure 3 is a block diagram illustrating a first modified type of a beam scanner of the inspection apparatus illustrated in Figure 1

[0019] Figure 4 is a block diagram illustrating a second modified type of the beam scanner of the inspection apparatus illustrated in Figure 1

[0020] Figure 5 is a graph illustrating a relationship between a current and a voltage in a forward current region of a PN junction diode when high frequency light is irradiated onto the PN junction diode;

[0021] Figure 6 is a graph illustrating a relationship between a current and a voltage in a reverse current region of a PN junction diode when low frequency light is irradiated onto the PN junction diode in a case where an energy of the low frequency light is greater than a band gap energy of the PN junction diode;

[0022] Figure 7 is a block diagram illustrating a behavior of secondary electrons generated from an inspection region of a semiconductor device illustrated in Figure 1

[0023] Figure 8 is a table illustrating a detection image of the inspection region of the semiconductor device illustrated in Figure 7

[0024] Figure 9 ​​​​​is a plan view showing an irradiation region of a charged particle beam, high frequency light, and low frequency light according to an example embodiment of the present inventive concept;

[0025] Figure 10 is a graph showing a relationship between a current and a voltage of a PN junction diode when high frequency light and low frequency light are simultaneously irradiated onto the PN junction diode;

[0026] Figure 11 is a block diagram showing a configuration of a modified inspection apparatus for inspecting a semiconductor device by using a charged particle beam according to another example embodiment of the present inventive concept; and

[0027] Figure 12 is a flowchart showing a method of inspecting a semiconductor device by using voltage contrast in the inspection apparatus shown in Figure 1 DETAILED DESCRIPTION

[0028] Reference will now be made to example embodiments illustrated in the drawings, where like reference numerals can refer to like components throughout the drawings.

[0029] Figure 1 is a block diagram showing an inspection apparatus for inspecting a semiconductor device by using a charged particle beam according to an example embodiment of the present inventive concept. Figure 2 is a plan view showing a scanning direction of a charged particle beam on a wafer in the inspection apparatus shown in Figure 1

[0030] Referring to Figure 1 , an inspection apparatus 1000 according to an example embodiment of the present inventive concept can include a stage 100 on which a semiconductor device C can be placed, a beam scanner arranged above the stage and irradiating a charged particle beam CPB onto the semiconductor device C to fall in an inspection region I so that secondary electrons E can be generated from the inspection region I in response to the charged particle beam CPB, a first light source 300 irradiating high frequency light HL to the inspection region I, a second light source 400 irradiating low frequency light LL to the inspection region I, and a defect detector 500 generating a detection image corresponding to the inspection region I in response to a voltage of the detected secondary electrons E and inspecting a defect image indicating a defect in the semiconductor device C from among the detection image by voltage contrast. As used herein, a semiconductor device can refer to a device such as a semiconductor chip (e.g., a memory chip and / or a logic chip formed on a die) or a stack of semiconductor chips. As shown, for example, in Figure 2 , a plurality of semiconductor devices C are arranged on a wafer.

[0031] ​​In an example embodiment, the stage 100 can be arranged in an inspection chamber (not shown), and a semiconductor device C to be inspected can be mounted on the stage 100. Accordingly, the semiconductor device C can be fixed to the stage 100 during an inspection process. For example, the stage 100 can include a chuck 110 on which the semiconductor device C can be fixed, and a position controller 120 connected to the chuck 110 and controlling a position of the semiconductor device C by rotating and tilting the chuck 110.

[0032] The semiconductor device C can include, for example, a chip on a wafer W. The wafer W can be arranged on the chuck 110, and a plurality of semiconductor devices C can be arranged on the wafer W. An inspection process can be sequentially performed on each semiconductor device C along a scan direction SD. The chuck 110 can include an electrostatic chuck (ESC) on which the wafer W can be fixed by an electrostatic force.

[0033] For example, the position controller 120 can include a support column supporting the chuck 110, a linear driver for linearly moving the support column in three-dimensional directions, a rotation driver for rotating the support column with respect to a rotation axis, and a tilt driver for tilting the chuck 110 by a certain angle with respect to a horizontal plane of the support column.

[0034] The position controller 120 can control the chuck 110 to move and be positioned at a position at which the charged particle beam CPB, the high-frequency light HL, and the low-frequency light LL can be simultaneously focused on the inspection region I of the semiconductor device C, according to positions of the beam scanner 200, the first light source 300, and the second light source 400.

[0035] On the contrary, the beam scanner 200, the first light source 300, and the second light source 400 can be controlled in such a manner that the charged particle beam CPB, the high-frequency light HL, and the low-frequency light LL can be focused on the inspection region I of the semiconductor device C, respectively. In particular, the beam scanner 200, the first light source 300, and the second light source 400 can be controlled to be focused on the inspection region I of the semiconductor device C, respectively, while the chuck 110 can be kept stationary at its original position. Accordingly, the charged particle beam CPB, the high-frequency light HL, and the low-frequency light LL can be focused on the inspection region I of the semiconductor device C.

[0036] When an inspection process of the semiconductor device C is initiated, the beam scanner 200, the first light source 300, and the second light source 400 can move on the wafer W in the scan direction SD in units of the inspection region I. An entire surface of the wafer W can be inspected by the inspection region I in the scan direction SD.

[0037] The wafer W can include a plurality of semiconductor devices C, and the inspection process can be repeated for each semiconductor device C on the wafer W according to the size of the inspection region I. For example, when the inspection region I is set to about 10% of the entire size of a single semiconductor device C, the inspection process can be repeated 10 times for each single semiconductor device C.

[0038] Accordingly, the size of the inspection region I can vary according to the characteristics of the semiconductor device C, the characteristics of the inspection apparatus 1000, and the requirements of the inspection process. In the present exemplary embodiment, the inspection region I can be set to a square pixel having a lateral length of about 1 nanometer or several nanometers to several tens of nanometers.

[0039] The semiconductor device C can include a single semiconductor chip or a group of semiconductor chips that can be stacked on the wafer W, and the configuration of the beam scanner 200 can vary according to the single chip or the group of chips.

[0040] The semiconductor device C can include various structures according to the steps of the semiconductor manufacturing process, and the inspection process performed on the semiconductor device C can be performed as an in-process inspection. For example, the semiconductor device C can include an in-process device in which a direct contact (DC) structure can be provided in contact with a drain electrode, or a buried contact (BC) structure and a DC structure can be provided in contact with a source electrode. In addition, the semiconductor device C can include an in-process device in which a metal wiring can be disposed on an insulating intermediate layer as well as the DC structure and the BC structure.

[0041] In particular, the semiconductor device C can include a CMOS device in which a plurality of NMOS devices and a plurality of PMOS devices are disposed. However, the semiconductor device C can also include a plurality of NMOS devices or a plurality of PMOS devices.

[0042] In the exemplary embodiment, the beam scanner 200 can be disposed above the stage 100, and can irradiate the charged particle beam CPB onto the inspection region I of the semiconductor device C. The secondary electrons E can be generated from the inspection region I in response to the charged particle beam CPB. Preferably, the beam scanner 200 can be disposed above the stage 100 in a configuration in which the charged particle beam CPB can be irradiated vertically onto the semiconductor device C, and the secondary electrons E can be diffused toward the beam scanner 200, around which the electron detector 510 of the defect detector 500 can be disposed.

[0043] For example, beam scanner 200 may include: beam generator 210 that generates a charged particle beam CPB from a beam source material; deflector 220 arranged around beam generator 210 and controlling the path of charged particle beam CPB toward semiconductor device C; and illuminator 230 that focuses the charged particle beam CPB onto inspection area I.

[0044] The beam generator 210 may include: a beam source BS that generates an electron beam or ion beam as a charged particle beam CPB; and a guide chamber GC through which the charged particle beam CPB can be guided from the beam source BS toward the inspection area I. A deflector 220 may be arranged on one side of the guide chamber GC and can control the movement of the charged particle beam CPB toward the semiconductor device C by changing the strength of the electric and magnetic fields. An irradiator 230 may be located at the end of the guide chamber GC and can irradiate the inspection area I with the charged particle beam CPB. The irradiator 230 may include, for example, a beam projector (not shown) for projecting the charged particle beam CPB onto the semiconductor device C; a focus controller (not shown) for controlling the focus of the charged particle beam CPB; and a gap controller (not shown) for controlling the gap distance between the semiconductor device C and the beam projector.

[0045] For example, a charged particle beam (CPB) can include an electron beam. However, depending on the characteristics of the semiconductor device C and the requirements of the inspection process, a charged particle beam (CPB) can also include an ion beam.

[0046] In this example embodiment, a single beam scanner 200 may be disposed on the inspection device 1000. For example... Figure 2 As shown, the wafer W may include multiple semiconductor devices C. Each of the multiple semiconductor devices C may include multiple inspection areas I. A single beam scanner 200 may move across the multiple inspection areas I in the scan direction SD until each of the multiple inspection areas I has been inspected, thereby inspecting the multiple semiconductor devices C. For each individual semiconductor device C, the beam scanner 200 may stay in each inspection area I for a preset time (referred to as the dwell time), and the charged particle beam CPB may irradiate each inspection area I for the dwell time. Therefore, all inspection areas I of a single semiconductor device C can be sequentially irradiated one by one by the beam scanner 200 along the scan direction SD. Therefore, the total inspection time for inspecting the semiconductor device C can be determined as the number of inspection areas I multiplied by the dwell time.

[0047] In a modified example embodiment, multiple charged particle beams (CPBs) can be simultaneously irradiated onto a set of inspection areas I to reduce the total inspection time. In this case, multiple independent inspection processes can be performed simultaneously within the inspection apparatus 1000.

[0048] Figure 3 is a configuration diagram showing a first modified type of beam scanner of the inspection apparatus shown in Figure 1

[0049] Referring to Figure 3 A plurality of beam scanners 200 can be arranged above a single semiconductor device C in a configuration in which each beam scanner 200 respectively corresponds to an inspection region I, and a plurality of charged particle beams CPB can simultaneously irradiate the respective inspection regions I independently of each other.

[0050] For example, the first modified type of beam scanner (hereinafter, referred to as a first modified scanner 200a) can include a beam generation group 210a including a plurality of beam generators 211 to 214 respectively for generating charged particle beams CPB, a deflector group 220a having a plurality of deflectors 221 to 224 respectively controlling paths of the charged particle beams CPB toward the respective inspection regions I, and an illuminator group 230a including a plurality of illuminators 231 to 234 for irradiating the respective inspection regions I with the charged particle beams.

[0051] For example, the first beam generator 211 to the fourth beam generator 214 can be respectively arranged above the first inspection region to the fourth inspection region II1, II2, I21, and I22, and the first beam generator 211 to the fourth beam generator 214 can include their own beam sources S1 to S4 and guide chambers GC1 to GC4. The first deflector 221 to the fourth deflector 224 can be respectively arranged at one side of the first guide chamber GC1 to the fourth guide chamber GC4, and the first illuminator 231 to the fourth illuminator 234 can be respectively arranged at an end of the first guide chamber GC1 to the fourth guide chamber GC4.

[0052] The first semiconductor device CI can include the first inspection region II1 and the second inspection region II2. The second semiconductor device C2 can include the third inspection region I21 and the fourth inspection region I22. A first charged particle split beam CPB1 can be irradiated onto the first inspection region II1 by the first illuminator 231, and a second charged particle split beam CPB2 can be irradiated onto the second inspection region II2 by the second illuminator 232. A third charged particle split beam CPB3 can be irradiated onto the third inspection region I21 by the third illuminator 233, and a fourth charged particle split beam CPB4 can be irradiated onto the fourth inspection region I22 by the fourth illuminator 234.

[0053] In this case, each of the illuminators 231 to 234 can be sufficiently spaced apart from each other in a configuration in which secondary electrons E generated from each inspection region I can be respectively detected by the defect detector 500 without any substantial interference between the secondary electrons E generated from the adjacent inspection regions I. ​

[0054] For example, the first illuminator 231 and the second illuminator 232 can be sufficiently spaced apart from each other in such a manner that interference between the first group of secondary electrons E1 and the second group of secondary electrons E2 generated from the first inspection region I11 and the second inspection region I12 can be sufficiently prevented or minimized. Also, the first inspection region I11 and the second inspection region I12 can correspond to the first illuminator 231 and the second illuminator 232 being disposed apart from each other.

[0055] Accordingly, when the first charged particle split beam CPB1 and the second charged particle split beam CPB2 are simultaneously irradiated onto the first inspection region I11 and the second inspection region I12, respectively, the first group of secondary electrons E1 and the second group of secondary electrons E2 can be detected by the defect detector 500, respectively.

[0056] In the same manner, the third illuminator 233 and the fourth illuminator 234 can be sufficiently spaced apart from each other in such a manner that interference between the third group of secondary electrons E3 and the fourth group of secondary electrons E4 generated from the third inspection region I21 and the fourth inspection region I22 can be sufficiently prevented or minimized. Also, the third inspection region I21 and the fourth inspection region I22 can also correspond to the third illuminator 233 and the fourth illuminator 234 being disposed apart from each other.

[0057] Accordingly, when the third charged particle split beam CPB3 and the fourth charged particle split beam CPB4 are simultaneously irradiated onto the third inspection region I21 and the fourth inspection region I22, the third group of secondary electrons E3 and the fourth group of secondary electrons E4 can be detected by the defect detector 500, respectively.

[0058] Accordingly, the four charged particle split beams CPB1 to CPB4 can be simultaneously irradiated onto the four inspection regions by the first modified scanner 200a, respectively, and the four groups of secondary electrons E1 to E4 can be detected independently of each other. Accordingly, four inspection processes can be simultaneously performed, and the total inspection time of the inspection processes can be reduced to one fourth of the time.

[0059] Specifically, multiple inspection areas I can be arranged on the same semiconductor device C or on different semiconductor devices C. When multiple semiconductor devices C are arranged on a wafer W and an inspection process is performed on all semiconductor devices C on the wafer W, a single semiconductor device C (e.g., multiple chips) can include a single inspection area I or multiple inspection areas depending on the arrangement of the semiconductor devices on the wafer W and the size of the inspection area I. In this example embodiment, a first semiconductor device C1 and a second semiconductor device C2 can be arranged on the wafer W, and a first inspection area I11 and a second inspection area I12 can be defined on the first semiconductor device C1, and a third inspection area I21 and a fourth inspection area I22 can be defined on the second semiconductor device C2. Therefore, a pair of semiconductor devices C1 and C2 can be inspected simultaneously in the inspection apparatus 1000 by using a first modified beam scanner 200a.

[0060] Although this example embodiment discloses that four beam scanners 200 can be simultaneously provided in the inspection apparatus 1000, the inspection apparatus 1000 may also be provided with more or fewer beam scanners 200 depending on the inspection efficiency and characteristics of the inspection apparatus 1000. The number of inspection areas I may also vary relative to the number of beam scanners 200.

[0061] Figure 4 It shows Figure 1 The diagram shows a second modified version of the beam scanner of the inspection device. Figure 4 In the second modified version 200b of the beam scanner, a single initial beam IB is generated, which is divided into multiple beams that irradiate multiple inspection regions I of the semiconductor device C.

[0062] refer to Figure 4 The second modification of the beam scanner (hereinafter referred to as the second modified scanner 200b) may include: a multi-beam generator 210b for generating a plurality of inspection beams ISB1 to ISB4; a deflector group 220a having a plurality of deflectors 221 to 224 for controlling the paths of the inspection beams ISB1 to ISB4 toward the respective inspection areas I; and an irradiator group 230a including a plurality of irradiators 231 to 234 for irradiating the deflected inspection beams ISB1 to ISB4 (as first charged particle split beams CPB1 to fourth charged particle split beams CPB4) toward the respective inspection areas I.

[0063] For example, the multi-beam generator 210b may include: a single beam source BS for generating an initial beam IB as a charged particle beam CPB; a beam splitting structure 215 that splits the initial beam IB into multiple test beams ISB1 to ISB4; and multiple guide chambers GC1 to GC4 that guide the test beams ISB1 to ISB4 to their respective deflectors in the deflector group 220a.

[0064] For example, the beam source BS can generate the initial beam IB as a single charged particle beam CPB from a beam source material. Since the initial beam IB can be split into the inspection beams ISB1 to ISB4, the inspection beams ISB1 to ISB4 can also be provided as charged particle beams CPB.

[0065] In the present example embodiment, the beam source BS can be set to a single column structure in which a beam generator for generating a charged particle beam CPB from a beam source material and a plurality of structures for controlling radiation of the charged particle beam CPB can be arranged along a path of the charged particle beam CPB. That is, the beam source BS can be set to a single column structure for guiding the initial beam IB toward the beam splitting structure 215.

[0066] The beam splitting structure 215 can split the initial beam IB into a plurality of inspection beams ISB1 to ISB4, which can be provided into respective illuminators of the illuminator group 230a.

[0067] For example, the beam splitting structure 215 can include a plurality of beam splitters 215a for splitting or dividing a beam into a plurality of split beams, and a plurality of reflectors 215b for reflecting the split beams toward a target.

[0068] In the present example embodiment, the initial beam IB generated from the beam source BS can be split into a first split beam SB1 for inspecting a first semiconductor device C1 and a second split beam SB2 for inspecting a second semiconductor device C2. Some of the initial beam IB can be reflected from the first beam splitter BS1 to provide the first split beam SB1, and the remaining initial beam IB can pass through the first beam splitter BS1 to provide the second split beam SB2.

[0069] The first split beam SB1 can be split into a first inspection beam ISB1 and a second inspection beam ISB2 by a second beam splitter BS2, which can be arranged in parallel with the first beam splitter BS1. For example, some of the first split beam SB1 can be reflected from the second beam splitter BS2 into the second guide chamber GC2 as the second inspection beam ISB2. The remaining first split beam SB1 can pass through the second beam splitter BS2 and then be reflected from the second reflector R2 into the first guide chamber GC1 as the first inspection beam ISB1.

[0070] The second split beam SB2 can pass through the first beam splitter BS1 and reflect from a first reflector R1, which can be arranged below the first beam splitter BS1. The second split beam SB2 can then be split into a third inspection beam ISB3 and a fourth inspection beam ISB4 by a third beam splitter BS3, which can be arranged in parallel with the first reflector R1. For example, some of the second split beam SB2 can reflect from the third beam splitter BS3 into a third guide chamber GC3 as the third inspection beam ISB3. The rest of the second split beam SB2 can pass through the third beam splitter BS3 and then reflect from a third reflector R3 into a fourth guide chamber GC4 as the fourth inspection beam ISB4.

[0071] The first inspection beam ISB1 can be deflected by a first deflector 221 and can be illuminated onto a first inspection region II 1 by a first illuminator 231 as a first charged particle split beam CPB1, and the second inspection beam ISB2 can be deflected by a second deflector 222 and can be illuminated onto a second inspection region II 2 by a second illuminator 232 as a second charged particle split beam CPB2. In the same manner, the third inspection beam ISB3 can be deflected by a third deflector 223 and can be illuminated onto a third inspection region 121 by a third illuminator 233 as a third charged particle split beam CPB3, and the fourth inspection beam ISB4 can be deflected by a fourth deflector 224 and can be illuminated onto a fourth inspection region 122 by a fourth illuminator 234 as a fourth charged particle split beam CPB4. Since the beam source BS can be set as a single column structure for guiding the initial beam IB toward the beam splitting structure 215 and can split the initial beam IB into the first to fourth charged particle split beams CPB1 to CPB4 by the beam splitting structure, the second modified beam scanner 200b can be configured as a single column multi-beam structure.

[0072] A first to fourth group of secondary electrons E1 to E4 can be generated from the first to fourth inspection regions II 1, II 2, 121 and 122, respectively, in response to the first to fourth charged particle split beams CPB1 to CPB4, respectively, and the first to fourth group of secondary electrons E1 to E4 can be detected by the defect detector 500 independently from each other. Thus, four inspection processes can be performed simultaneously on the semiconductor device C.

[0073] Although the present example embodiment discloses that the beam splitting structure 215 can be provided with a plurality of beam splitters 215a and a plurality of reflectors 215b, the beam splitting structure 215 can also be provided with any other device or structure together with or instead of the beam splitters 215a and / or the reflectors 215b.

[0074] For example, the beam splitting structure 215 may include an illumination aperture APE for reflecting an initial beam IB toward multiple irradiators, which may be arranged in series along the row or column direction of the wafer W. Therefore, multiple charged particle beams can be simultaneously irradiated onto multiple inspection areas I, which may be arranged along the row or column direction on the wafer W.

[0075] Deflector assembly 220a and illumination assembly 230a can have the same Figure 3 The deflector group 220a and the emitter group 230a of the first modified scanner 200a shown have substantially the same structure. Therefore, any further detailed description of the deflector group 220a and the emitter group 230a of the second modified scanner 200b is omitted.

[0076] Therefore, the second modified scanner 200b may include: a beam source BS for generating an initial beam IB; and a beam splitting structure 215 or an illumination aperture APE for splitting the initial beam IB into a plurality of charged particle split beams CPB1 to CPB4, which individually irradiate a plurality of inspection areas I11, I12, I21 and I22, respectively.

[0077] When each charged particle split beam, CPB1 to CPB4, is irradiated onto the corresponding inspection area I, secondary electrons E can be generated from the corresponding inspection area I and can be detected by the electron detector 510, without any substantial interference between the first group of secondary electrons E1 to the fourth group of secondary electrons E4. The defect detector 500 can generate a detection image corresponding to the inspection area I based on the detection voltage caused by the secondary electrons E.

[0078] The brightness of the inspection image can vary depending on the detection voltage or the amount of secondary electrons E. Therefore, defects in the inspection area I of the semiconductor device C can be detected by comparing the brightness of the inspection image with that of a reference image that indicates the inspection area I when no defects are present in the corresponding inspection area I. Since the brightness of the inspection image can be determined by the detection voltage of the secondary electrons E, the brightness comparison between the inspection image and the reference image is called voltage comparison, and the inspection process using this voltage comparison is called voltage comparison inspection.

[0079] The semiconductor device C on wafer W may include one or more CMOS devices. Each CMOS device includes a PMOS device and an NMOS device. When a charged particle beam CPB is applied to an inspection region I of the semiconductor device C, which has multiple PMOS and NMOS devices, and a voltage comparison inspection is performed on the semiconductor device C, the following problem arises: due to the characteristics of PN junction diodes, the reference image for the PMOS device may differ from that for the NMOS device. That is, when inspecting a CMOS device by voltage comparison inspection, the reference image used for voltage comparison cannot be uniquely determined. Furthermore, since the inspection region I used to perform voltage comparison inspection by using the charged particle beam CPB can be so small and intricate, i.e., a large number of inspection regions I are required to inspect the semiconductor device C on wafer W, the voltage comparison inspection requires a significant amount of inspection time.

[0080] For these reasons, at least one of high-frequency light HL and low-frequency light LL can be irradiated onto the inspection area I of the semiconductor device C to increase the brightness of the reference image for the inspection image used to inspect the NMOS device and to reduce the total inspection time for performing voltage comparison inspection on the CMOS device.

[0081] In an example embodiment, the first light source 300 and the second light source 400 can selectively illuminate the inspection area I of the semiconductor device C, which includes PMOS and NMOS devices, with high-frequency light HL and low-frequency light LL. Figure 1 As shown, the first light source 300 can be arranged above the semiconductor device C in an oblique (e.g., angled) orientation relative to one side of the beam scanner 200. The second light source 400 can be arranged above the semiconductor device C in an oblique (e.g., angled) orientation relative to the other side of the beam scanner 200. In this example embodiment, the charged particle beam CPB can irradiate the semiconductor device C in a vertical direction relative to the semiconductor device C. Considering the orientation of the beam source BS, the first light source 300, and the second light source 400, the high-frequency light HL and the low-frequency light LL can be irradiated onto the CMOS device C in such a way that the irradiation areas of the charged particle beam CPB, the high-frequency light HL, and the low-frequency light LL can have the same irradiation center.

[0082] When high-frequency light HL irradiates the inspection region I of the semiconductor device C, the potential barrier of the PN junction can be lowered in the PMOS device. Therefore, the intensity of the forward current IF increases the secondary electrons E, and thus, the dwell time of the beam scanner 200 can be significantly shortened. For example, although the beam scanner 200 can remain above the inspection region I for a shorter time, the same amount of secondary electrons E can be generated from the inspection region I. Therefore, the irradiation time of the charged particle beam CPB of the beam scanner 200 can be reduced.

[0083] Therefore, high-frequency light (HL) can be used to increase the intensity of the forward current in a PMOS device by providing sufficient light energy. In this example embodiment, the high-frequency light (HL) can have a frequency higher than that of ultraviolet light. For example, the high-frequency light (HL) can include one of alpha rays, beta rays, neutron rays, and X-rays.

[0084] Figure 5 It is a graph showing the relationship between current and voltage in the forward current region of a PN junction diode when high-frequency light HL is shone onto the PN junction diode.

[0085] like Figure 5 As shown, for example, when X-rays are applied to a PN junction diode, the gradient of the forward current IF relative to the voltage increases significantly compared to when X-rays are not applied to the PN junction diode (e.g., when a voltage greater than 0V is applied). The forward current I1 generated when X-rays are applied to the PN junction diode can have a much higher intensity than the forward current I0 when X-rays are not applied to the PN junction diode at the same voltage. Applying X-rays to the PN junction diode sufficiently reduces the potential barrier of the PN junction diode, such that the intensity of the forward current IF increases at the same voltage.

[0086] Figure 6 This is a graph showing the relationship between current and voltage in the reverse current region of a PN junction diode when low-frequency light LL is irradiated onto it. As described below, when low-frequency light LL is irradiated onto the inspection region I of a semiconductor device C and the energy of the low-frequency light LL is sufficiently greater than the bandgap energy of the inspection region I, the kinetic energy of secondary electrons E can be enhanced, and the brightness of the detected image can be significantly improved.

[0087] like Figure 6 As shown, when low-frequency light LL with energy greater than the bandgap energy of a PN junction diode is irradiated onto the inspection region I of a semiconductor device C, the intensity of the reverse current IR in the PN junction diode increases, and therefore, a photoelectromotive force (EMF) can be applied to the boundary surface of the PN junction diode. Thus, the interface potential of the PN junction diode can be enhanced to the same extent as the photoelectromotive force, and secondary electrons E can be accelerated by the photoelectromotive force in the PN junction diode. That is, the secondary electrons E can be enhanced at the boundary surface of the PN junction diode by the low-frequency light LL. Specifically, the greater the energy of the low-frequency light LL, the higher the intensity of the reverse current IR, and the greater the dark current at the boundary surface of the PN junction diode.

[0088] For example, low-frequency light (LL) can include light generated by lasers, ultraviolet light, and visible light.

[0089] Therefore, when high-frequency light HL and low-frequency light LL are irradiated onto the inspection area I of semiconductor device C, secondary electrons E can be generated according to the above reference.Figure 5 and Figure 6 The operating characteristics of the PN junction diode are as described above.

[0090] Figure 7 It shows from Figure 1 The diagram shows a structure illustrating the behavior of secondary electrons generated in the inspection region of a semiconductor device. Figure 7 In the diagram, semiconductor device C includes a CMOS device, which comprises multiple PMOS devices P and multiple NMOS devices N. For ease of comparison, the behavior of secondary electrons in both PMOS devices P and NMOS devices N is shown.

[0091] refer to Figure 7 When a charged particle beam (CPB) is irradiated onto the inspection region I of a semiconductor device C, including a PMOS device P, secondary electrons E are generated from the N-well 10 doped with N-type impurities, and these secondary electrons E flow into the first doped region 20 doped with P-type impurities. The secondary electrons E then diffuse outward through a normal PMOS contact structure 30 that contacts the first doped region 20 in the PMOS device. The diffused secondary electrons E can be detected by a defect detector 500 that can be arranged above the PMOS device P, and a fourth detection image D is generated in the defect detector 500 using the secondary electrons E.

[0092] Specifically, the N-well 10 and the first doped region 20 can be used as a PN junction diode in the PMOS device P, and the secondary electrons E can behave as if a forward bias is applied to the PN junction diode. Therefore, the flow of secondary electrons E from the N-well 10 to the normal PMOS contact structure 30 via the first doped region 20 can generate a forward current in the PMOS device P.

[0093] In contrast to the normal PMOS contact structure 30, the abnormal PMOS contact structure 40 can be separated from the first doped region 20 in the PMOS device P by an insulating interlayer such as a silicon oxide layer, so that the N-well 10 and the abnormal PMOS contact structure 40 do not function as PN junction diodes, and no forward bias is applied to the abnormal PMOS contact structure 40. Therefore, the flow of secondary electrons E from the N-well 10 to the abnormal PMOS contact structure is significantly reduced compared to the flow of secondary electrons E to the normal PMOS contact structure 30.

[0094] Therefore, the amount of secondary electrons E diffusing from the abnormal PMOS contact structure 40 can be much less than the amount of secondary electrons E diffusing from the normal PMOS contact structure 30. The secondary electrons E diffusing from the abnormal PMOS contact structure 40 can be detected by the defect detector 500, and a sixth detection image F can be generated in the defect detector 500.

[0095] Since the amount of secondary electrons E diffusing from the normal PMOS contact structure 30 can be much greater than the amount of secondary electrons E diffusing from the abnormal PMOS contact structure 40, the voltage difference between the fourth detection image D and the sixth detection image F can be significant. Therefore, when performing a voltage comparison check relative to the PMOS device P, the fourth detection image D can be used as a reference image for voltage comparison. That is, since the sixth detection image F is sufficiently dark compared to the fourth detection image D, the abnormal PMOS contact structure 40 can be detected as a defect simply by comparing the sixth detection image F with the fourth detection image D (i.e., the voltage comparison of the detection image with respect to the reference image).

[0096] When a charged particle beam CPB is irradiated onto a semiconductor device C, a reverse bias can be applied between the P-well 50 and the second doped region 60 in the NMOS device N using the same charged particle beam CPB. At the same time, a forward bias can be applied between the N-well 10 and the first doped region 20 in the PMOS device P using the same charged particle beam CPB.

[0097] When a charged particle beam (CPB) is irradiated onto an inspection region I of a semiconductor device C, including an NMOS device N, secondary electrons E are generated from a P-well 50 doped with P-type impurities, and these secondary electrons E flow into a second doped region 60 doped with N-type impurities. The secondary electrons E then diffuse outward through a normal NMOS contact structure 70 that contacts the second doped region 60 in the NMOS device N. A defect detector 500 disposed above the NMOS device N detects the diffused secondary electrons E, and a first detection image A is generated in the defect detector 500 using the secondary electrons E.

[0098] Specifically, the P-well 50 and the second doped region 60 serve as the PN junction diode in the NMOS device N, and the secondary electrons E behave as if a reverse bias is applied to the PN junction diode. Therefore, the flow of secondary electrons E from the P-well 50 to the normal NMOS contact structure 70 via the second doped region 60 generates a reverse current in the NMOS device N.

[0099] Therefore, the amount of secondary electrons E diffusing from the normal NMOS contact structure 70 with reverse bias is less than the amount of secondary electrons E diffusing from the normal PMOS contact structure 30 with forward bias. Consequently, the brightness of the first detection image A is lower than the brightness of the fourth detection image D.

[0100] In contrast to the normal NMOS contact structure 70, the abnormal NMOS contact structure 80 is separated from the second doped region 60 in the NMOS device N by an insulating interlayer such as a silicon oxide layer. Therefore, the flow of secondary electrons E from the P-well 50 to the abnormal NMOS contact structure 80 is significantly reduced compared to the flow of secondary electrons E to the normal NMOS contact structure 70.

[0101] Therefore, the amount of secondary electrons E diffusing from the abnormal NMOS contact structure 80 is much less than the amount of secondary electrons E diffusing from the normal NMOS contact structure 70. The secondary electrons E diffusing from the abnormal NMOS contact structure 80 are detected by the defect detector 500, and a third detection image C is generated in the defect detector 500. The third detection image C may have substantially the same brightness as the sixth detection image F. Terms such as “same” or “equal” as used herein encompass similarity or include near-identical similarity, including variations that may occur due to manufacturing processes. Unless the context or other statements otherwise indicate otherwise, the term “substantially” may be used herein to emphasize this meaning.

[0102] Although the normal PMOS contact structure 30 and the normal NMOS contact structure 70 can make sufficient contact with the first doped region 20 and the second doped region 60, respectively, the brightness of the first detection image A can be lower than that of the fourth detection image D, and therefore the first detection image A can be identified as a defect image. Therefore, when the same charged particle beam CPB is irradiated onto the PMOS device P and the NMOS device N, it may be difficult to detect defects in the NMOS device through voltage comparison inspection.

[0103] Figure 8 It shows Figure 7 The table shows the inspection images of the inspection area of ​​the semiconductor device. Figure 8 In the process, the defect detector 500 generates detection images in normal mode and three enhancement modes. In the three enhancement modes, secondary electrons E are enhanced by high-frequency light HL and / or low-frequency light LL.

[0104] refer to Figure 8 When a voltage contrast check is performed in normal mode (where no high-frequency light HL and no low-frequency light LL illuminate the inspection area I), and therefore the secondary electron E is not enhanced, the fourth detection image D and the sixth detection image F form sufficient contrast based on the brightness contrast, while the first detection image A and the third detection image C do not form sufficient contrast.

[0105] Therefore, the first detection image indicating a normal NMOS contact structure 70 cannot be used as a reference image for determining the third detection image C indicating an abnormal NMOS contact structure 80 as a defect image.

[0106] That is, in the normal mode of voltage comparison inspection, the fourth detection image can be used as a reference image for determining the sixth detection image as a defect image in the PMOS device P, while the first detection image is not used as a reference image for determining the third detection image as a defect image in the NMOS device N.

[0107] In this case, low-frequency light LL is irradiated onto the inspection area I, and the secondary electrons E generated from the P-well 50 of the NMOS device N are enhanced, thereby increasing the brightness of the first detection image A, such as... Figure 8 The enhanced mode 1 is shown in the figure.

[0108] In the enhanced mode 1 of voltage contrast inspection, the brightness of the first detection image A can be close to the brightness of the fourth detection image D. Therefore, based on the brightness contrast, the first detection image A can form a sufficient contrast with the third detection image C.

[0109] Figure 6 The graph shows that the forward current IF is sensitive to the applied voltage in the PN junction diode, while the reverse current IR can be constant until a threshold voltage is applied to the PN junction diode. Therefore, when low-frequency light LL is irradiated onto the semiconductor device C, the reverse bias may be more sensitive to the photoelectromotive force than the forward bias in the PN junction.

[0110] Therefore, the reverse current IR can increase in response to the photoelectromotive force at the boundary between the P-well 50 and the second doped region 60, thereby enhancing or accelerating the secondary electrons E generated from the P-well 50 toward the second doped region 60. Consequently, the voltage of the detected secondary electrons E increases, and the brightness of the first detection image A can be sufficiently increased by the low-frequency light LL.

[0111] Therefore, in the enhanced mode 1 of voltage comparison inspection, the first detection image A indicating a normal NMOS contact structure 70 can be used as a reference image for determining the third detection image C indicating an abnormal NMOS contact structure 80 as a defect image.

[0112] However, the detection current of secondary electrons E can have substantially the same intensity as the detection current of secondary electrons E in normal mode. Since the low-frequency light LL can keep the barrier of the PN junction unchanged, the intensity of the detection current caused by secondary electrons E in enhancement mode 1 can also remain unchanged.

[0113] That is, the amount of secondary electrons E detected by the defect detector 500 in normal mode can be the same as the amount of secondary electrons E detected in enhanced mode 1. Therefore, in both normal mode and enhanced mode 1, the detection of the minimum amount of secondary electrons E required to generate a detection image may require substantially the same time (referred to as dwell time). In other words, the dwell time of the defect detector 500 cannot be improved by irradiating the semiconductor device C with low-frequency light LL.

[0114] In enhanced mode 2 of voltage comparison inspection, high-frequency light HL and charged particle beam CPB are irradiated together onto the inspection region I of semiconductor device C, reducing the potential barrier at the boundary of the PN junction. Therefore, under the same applied voltage, the intensity of the detection current can be increased, and the amount of secondary electrons E detected by defect detector 500 can be increased without increasing the applied voltage.

[0115] Therefore, a minimum amount of secondary electrons E is obtained in a shorter time to generate the detection image, and the dwell time of the defect detector 500 is reduced by irradiating it with high-frequency light HL. That is, the dwell time of the defect detector 500 in enhancement mode 2 is significantly shorter than that of the defect detector 500 in normal mode.

[0116] However, because the low-frequency light LL was not irradiated onto the semiconductor device C, the first detection image A and the third detection image C did not form sufficient contrast. Therefore, in the voltage comparison inspection, the first detection image A cannot be used as a reference image to identify the third detection image C as a defective image.

[0117] Therefore, both high-frequency light HL and low-frequency light LL are irradiated onto the semiconductor device C to increase the brightness of the first detection image A and shorten the dwell time of the defect detector 500 (enhancement mode 3).

[0118] Figure 9 This is a diagram illustrating the irradiation areas of a charged particle beam, high-frequency light HL, and low-frequency light LL, according to an exemplary embodiment of the present invention. Figure 10 This is a graph showing the relationship between the current and voltage of a PN junction diode when high-frequency light HL and low-frequency light LL are simultaneously irradiated onto the PN junction diode.

[0119] refer to Figure 9 The charged particle beam CPB, high-frequency light HL, and low-frequency light LL are irradiated onto the inspection area I of the semiconductor device C in the following manner: the charged particle beam CPB, high-frequency light HL, and low-frequency light LL are irradiated radially from a common irradiation center CC, so that the charged particle beam CPB, high-frequency light HL, and low-frequency light LL can have the same focal point.

[0120] Therefore, although the charged particle beam CPB, high-frequency light HL, and low-frequency light LL can be located at different positions with different installation angles, the irradiation areas of the charged particle beam CPB, high-frequency light HL, and low-frequency light LL can be formed around a common irradiation center CC.

[0121] In this example embodiment, the second irradiation region A2, which can irradiate the low-frequency light LL, can be larger than the first irradiation region A1, which can irradiate the high-frequency light HL. Furthermore, the first irradiation region A1 can be larger than the beam region A0, which can irradiate the charged particle beam CPB. Therefore, the secondary electrons E generated from the beam region A0 can be sufficiently exposed to both the high-frequency light HL and the low-frequency light LL.

[0122] like Figure 10 As shown, when high-frequency light HL is irradiated onto semiconductor device C, the potential barrier of the PN junction in semiconductor device C decreases, and the intensity of the forward current IF can increase under the same applied voltage. Furthermore, when low-frequency light LL is irradiated onto semiconductor device C, the secondary electrons E in NMOS device N can be enhanced or accelerated through photoelectromotive force.

[0123] Therefore, the defect detector 500 can detect a sufficient amount of secondary electrons E on the semiconductor device C in a shorter time, and can enhance the kinetic energy of the secondary electrons E in the NMOS device N through photoelectromotive force.

[0124] Therefore, the dwell time of the defect detector 500 can be reduced, and the first detection image A and the third detection image C can form sufficient contrast. That is, the third detection image C can be accurately and quickly detected as a defect image by comparing its voltage with that of the first detection image A, so that defects in the abnormal NMOS contact structure 80 can be accurately and quickly detected by voltage comparison.

[0125] Specifically, despite the shorter dwell time, the defect detector 500 can adequately detect secondary electrons E within that shorter time and obtain sufficiently high-quality inspection images. Therefore, the total inspection time for voltage contrast inspection can be significantly improved by using high-frequency light HL.

[0126] The defect detector 500 can be positioned above the semiconductor device C and can detect secondary electrons E from the semiconductor device C. Multiple detection images can be generated from the inspection area I of the semiconductor device C.

[0127] For example, such as Figure 1As shown, the defect detector 500 may include: an electronic detector 510 for detecting secondary electrons E and generating an analog detection signal based on the energy spectrum and the amount of secondary electrons E; an image generator 520 for generating detection images based on the detection signal in units of inspection areas I; and a defect image detector 530 for performing voltage comparisons between each detection image and a reference image based on preset defect criteria, and detecting detection images that meet the defect criteria as defect images. The defect detector 500, electronic detector 510, image generator 520, and defect image detector 530 may be implemented using electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. The microprocessor or the like may be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software that may be stored in a storage device. Alternatively, the defect detector 500, electronic detector 510, image generator 520, and defect image detector 530 may be implemented by dedicated hardware or implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

[0128] For example, electron detector 510 may include an electron trapping structure that can surround illuminator 230 above semiconductor device C. Therefore, secondary electrons E generated from inspection region I in response to the charged particle beam CPB can diffuse upwards and be detected by electron detector 510. Electron detector 510 may have a sufficiently large detection surface facing semiconductor device C. In this example embodiment, electron detector 510 may be arranged below beam scanner 200 and surrounding illuminator 230.

[0129] The electronic detector 510 can generate an analog signal based on the electrical characteristics of the secondary electron E, which serves as the detection signal. Therefore, the detection signal can possess various signal characteristics based on the quantity and kinetic energy of the detected secondary electron E. The characteristics of the detection signal can also vary depending on whether the secondary electron E is detected from the PMOS device P or the NMOS device N.

[0130] Although this example embodiment discloses that the electron detector 510 can be arranged around the illuminator 230, the electron detector 510 can be located in various positions and can have various configurations, depending on the behavior of the secondary electron E and the structure of the beam scanner 200, as long as the electron detector 510 can detect the secondary electron E sufficiently well.

[0131] Image generator 520 can generate a detection image with brightness corresponding to the voltage of the detection signal. For example, image generator 520 may include an amplifier 521 for amplifying the detection signal and an analog-to-digital converter (ADC) 522 for converting the analog detection signal into a digital signal. The detection image can be generated in units of inspection area I and can be stored as digital data in storage unit 523.

[0132] Specifically, at least a reference image may also be stored in storage unit 523, and the detected image may be compared with the reference image. The reference image may include a PMOS reference image for voltage comparison with a detected image (PMOS detected image) detected from inspection region I of PMOS device P, and an NMOS reference image for voltage comparison with a detected image (NMOS detected image) detected from inspection region I of NMOS device N. In this example embodiment, the brightness of the NMOS reference image may be controlled within the range of approximately 80% to approximately 100% of the brightness of the PMOS reference image. Terms such as “approximately” or “roughly” may reflect variations in quantity, size, orientation, or layout only in a small relative manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, a range of “approximately 0.1 to approximately 1” may encompass ranges such as 0%–5% deviations of approximately 0.1 and 0%–5% deviations of approximately 1, particularly when such deviations have the same effect as the listed ranges.

[0133] The defect image detector 530 can perform image comparison between each detected image and a reference image based on preset defect criteria, and detect images that meet the defect criteria as defect images. The detected defect images and the location of the inspection area I of the defect images can be stored in the defect image detector 530 as defect information. The defect images can indicate defects that may be located in the inspection area I of the semiconductor device C.

[0134] For example, a PMOS detection image can be compared with a PMOS reference image, and an NMOS detection image can be compared with an NMOS reference image. In this example embodiment, the defect criterion can be set such that the brightness of the detection image is in the range of approximately 5% to approximately 50% of the brightness of the reference image. The defect criterion can vary depending on the inspection precision and the characteristics of the detection image and the reference image.

[0135] The defect detector 500 may further include a map generator 540 for generating a defect map in which multiple defect images can be visually displayed at locations corresponding to inspection areas I of the defect images. For example, a base image can be generated, and multiple semiconductor devices C and multiple inspection areas I for each semiconductor device C can be defined in the base image within the map generator 540. Each defect image can be marked on the base image using color or shading at the corresponding inspection area I, and the distribution of defect images on the base image can be set as the defect map. The defect map can be displayed on a display device D or printed in a catalog.

[0136] Figure 11 This is a structural diagram illustrating a modified inspection apparatus for inspecting semiconductor devices using a charged particle beam, according to another exemplary embodiment of the invention. Figure 11 In the process, the modified inspection device 1001 can have the same characteristics as... Figure 1 The inspection device 1000 shown has the same structure, except that it can perform voltage comparison checks under vacuum conditions. Therefore, in Figure 11 In the figures, the same reference numerals indicate Figure 1 The same elements are described below, and any further detailed description of the same elements will be omitted in the following text.

[0137] refer to Figure 11 The modified inspection apparatus 1001 may include: a vacuum chamber 600; a beam scanner 200 disposed in the vacuum chamber 600, which irradiates an inspection region I of the semiconductor device C with a charged particle beam CPB, such that secondary electrons E can be generated from the inspection region in response to the charged particle beam CPB; a first light source 300 disposed at an oblique orientation relative to the inspection region I on one side of the beam scanner 200, which irradiates the inspection region I with high-frequency light HL; a second light source 400 disposed at an oblique orientation relative to the inspection region I on the other side of the beam scanner 200, which irradiates the inspection region I with low-frequency light LL; and a defect detector 500 that detects the secondary electrons E to generate an inspection image indicating a defect in the semiconductor device C.

[0138] For example, vacuum chamber 600 may include a three-dimensional structure with an enclosed space that can be isolated from the surrounding environment and in which inspection processes can be performed on semiconductor device C. Stage 100 may be disposed at the bottom of vacuum chamber 600, and semiconductor device C may be mounted on stage 100. Therefore, semiconductor device C can be fixed to stage 100 in vacuum chamber 600. Semiconductor device C may, for example, include a semiconductor chip on wafer W. Wafer W may be arranged on stage 100, and multiple semiconductor devices C may be arranged on wafer W. In this example embodiment, semiconductor device C may include a CMOS device having multiple PMOS devices P and multiple NMOS devices N.

[0139] A door 700 for loading / unloading semiconductor device C may be located on one side of vacuum chamber 600, and a vacuum generator 800 may be located at the bottom of vacuum chamber 600. Door 700 may include a valve structure with sealing properties, and vacuum generator 800 may include a vacuum pump and vacuum lines connected to vacuum chamber 600.

[0140] When the inspection process is initiated, door 700 is opened, exposing the interior of vacuum chamber 600 to the outside. Semiconductor device C can then be loaded onto stage 100 through door 700, and door 700 can be closed to isolate the interior of vacuum chamber 600 from the surrounding environment. Subsequently, vacuum generator 800 can bring the interior of vacuum chamber 600 into a vacuum state. Therefore, the voltage comparison inspection process can be performed under vacuum conditions, preventing external interference to secondary electrons E generated during the inspection process.

[0141] As an alternative to a vacuum state, the vacuum chamber 600 can be replaced by a room pressure chamber whose internal space can be at atmospheric pressure.

[0142] The beam scanner 200, the first light source 300, the second light source 400, and the defect detector 500 can have the same characteristics as... Figure 1 The beam scanner 200, the first light source 300, the second light source 400, and the defect detector 500 of the inspection device 1000 shown have the same structure.

[0143] Figure 12 It is shown in Figure 1 The flowchart shows a method for inspecting semiconductor devices using voltage comparison in the inspection apparatus shown.

[0144] refer to Figure 1 and Figure 12 Semiconductor device C can be loaded onto stage 100 and fixed to stage 100 (step S100).

[0145] Semiconductor device C can include various structures depending on the steps of the semiconductor manufacturing process, such that semiconductor device C can include process devices that can be used in the manufacturing process of its execution units. For example, semiconductor device C can include process devices for DRAM devices, flash memory devices, and logic devices. Specifically, semiconductor device C can include CMOS devices, in which multiple NMOS devices and multiple PMOS devices can be arranged.

[0146] Then, high-frequency light HL can be irradiated onto the inspection area I of the semiconductor device C to reduce the potential barrier of the PN junction in the semiconductor device C (step S200).

[0147] The semiconductor device C can include a PN junction between the well region and the doped region, and the high-frequency light HL can reduce the potential barrier at the boundary of the PN junction. Therefore, more secondary electrons E can flow to the contact structure per unit time, and the defect detector 500 can detect more secondary electrons E during this time. That is, the defect detector 500 can detect the minimum amount of secondary electrons E required to generate a detection image in a shorter time, thereby significantly reducing the dwell time of the defect detector 500.

[0148] Then, low-frequency light LL can be irradiated onto the inspection area I of the semiconductor device C to generate a photoelectromotive force at the PN junction of the semiconductor device C (step S300).

[0149] When low-frequency light LL, with energy greater than the bandgap energy of a PN junction diode, is irradiated into the inspection region I, the intensity of the reverse current IR in the PN junction diode increases, and a photoelectromotive force (EMF) can be applied to the boundary surface of the PN junction diode. Therefore, the interface potential of the PN junction diode can be enhanced to the same extent as the photoelectromotive force, and the secondary electrons E can be accelerated by the photoelectromotive force in the PN junction diode. Thus, the kinetic energy of the secondary electrons E at the boundary surface of the PN junction diode can be enhanced by low-frequency light LL.

[0150] Specifically, when a charged particle beam (CPB) irradiates a CMOS device, secondary electrons E can be forward-biased in a PMOS device P and reverse-biased in an NMOS device N. Since the forward current (IF) is sensitive to the applied voltage at the PN junction of the PMOS device P, and the reverse current (IR) remains constant until a threshold voltage is applied to the PN junction of the PMOS device P, the photoelectromotive force (PMF) has a much greater effect on reverse bias than on forward bias when low-frequency light (LL) irradiates the CMOS device. Therefore, low-frequency light (LL) can accelerate secondary electrons E in the NMOS device N, while secondary electrons E in the PMOS device P may not undergo substantial acceleration or enhancement.

[0151] Then, a charged particle beam CPB can be irradiated onto the semiconductor device C, thereby generating multiple secondary electrons E from the semiconductor device C (step S400).

[0152] When a charged particle beam CPB is irradiated onto a semiconductor device C, secondary electrons E can be generated from the well region of the semiconductor device C in response to the charged particle beam CPB. The secondary electrons E can flow into the normal contact structures 30, 70 or the abnormal contact structures 40, 80 and can diffuse outward.

[0153] Specifically, since the potential barrier of the PN junction can be reduced by high-frequency light HL, and the reverse bias can be enhanced at the boundary of the PN junction of the NMOS device N by the photoelectromotive force induced by low-frequency light LL, a large number of secondary electrons E can flow into the contact structures 30, 40, 70, and 80, and can sufficiently enhance the secondary electrons E generated from the NMOS device N.

[0154] Then, the enhanced secondary electrons E can be detected by a defect detector 500 that can be arranged above the semiconductor device C, and multiple detection images can be generated at each inspection area I of the semiconductor device C (step S500).

[0155] When the electron detector 510 detects secondary electrons E, the detection voltage and detection current can be measured, and the detection image can have different brightness (displayed as color or shadow) depending on the detection voltage. Since the potential barrier can be reduced by high-frequency light HL and a large number of secondary electrons E can diffuse outward from contact structures 30, 40, 70, and 80, the time required to detect the minimum amount of secondary electrons E needed to generate the detection image can also be reduced by high-frequency light HL. That is, the dwell time of the defect detector 500 can be significantly reduced by high-frequency light HL, thereby reducing the inspection time of the inspection process.

[0156] Furthermore, when a charged particle beam (CPB) is irradiated onto a CMOS device, since reverse bias and forward bias can be applied to the PN junctions of the NMOS device N and PMOS device P respectively, the amount of diffused secondary electrons E in the NMOS device N can be less than the amount of diffused secondary electrons E in the PMOS device P. However, since the kinetic energy of the secondary electrons E diffused from the normal contact structure 70 in the NMOS device N can be enhanced by low-frequency light LL with energy greater than the bandgap energy of the PN junction diode, the brightness of the detection image corresponding to the normal contact structure 70 can still be sufficiently improved despite the presence of reverse bias in the NMOS device N. Therefore, the detection images corresponding to the normal contact structures 30 and 70 can be used as reference images for voltage comparison checks, regardless of the NMOS device N and PMOS device P.

[0157] Therefore, the detection image corresponding to the normal contact structure 70 can be fully used as an NMOS reference image, and the comparison accuracy between the NMOS detection image and the NMOS reference image can be greatly improved.

[0158] Based on defect criteria, a voltage comparison can be performed between the detection image and the reference image corresponding to each inspection area I, thereby detecting defect images that meet the defect criteria in the detection image (step S600).

[0159] A voltage comparison check can be performed to compare the PMOS detection image generated from the PMOS device P with a PMOS reference image, and the PMOS detection image that meets the defect criteria can be detected as a PMOS defect image. The PMOS defect image and the location of the corresponding inspection area I can be stored in the storage unit of the defect image detector 530.

[0160] A voltage comparison check can be performed to compare the NMOS detection image generated from the NMOS device N with an NMOS reference image, and an NMOS detection image that meets the defect criteria can be detected as an NMOS defect image. The NMOS defect image and the location of the corresponding inspection area I can be stored in the storage unit of the defect image detector 530.

[0161] Therefore, defects in CMOS devices can be detected with sufficiently high accuracy and efficiency through voltage comparison testing, in which a single charged particle beam CPB, high-frequency light HL, and low-frequency light LL are irradiated onto the CMOS device, independent of NMOS devices (N) and PMOS devices (P).

[0162] According to an exemplary embodiment of the present invention, high-frequency light HL can be irradiated onto a semiconductor device to reduce the potential barrier of the PN junction, and low-frequency light LL can be irradiated onto a semiconductor device C to generate a photoelectromotive force in the PN junction. Subsequently, when a charged particle beam CPB is irradiated onto the semiconductor device C and secondary electrons E are generated from the well region of the semiconductor device C, the defect detector 500 can detect a large number of secondary electrons E with enhanced energy.

[0163] A detection image can be generated with sufficiently high contrast based on enhanced secondary electrons within a shorter dwell time of the defect detector 500. Therefore, defects in CMOS devices can be detected with sufficiently high accuracy and efficiency via voltage contrast inspection, regardless of whether they are NMOS or PMOS devices. Due to the reduced dwell time of the defect detector 500 and the high voltage contrast of the detection image, the entire surface of the wafer can be inspected with high precision.

[0164] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the device plus function clause is intended to encompass the structures described herein that perform the functions, and includes not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. An inspection apparatus for inspecting semiconductor devices, comprising: A stage is configured to support semiconductor devices, including multiple PMOS devices and multiple NMOS devices; A first light source is configured to irradiate a high-frequency light onto an inspection area of ​​the semiconductor device to reduce the potential barrier of the PN junction in the semiconductor device. A beam scanner is disposed above the semiconductor device and configured to irradiate an inspection area of ​​the semiconductor device with a beam of charged particles, such that secondary electrons are generated from the inspection area in response to the beam of charged particles. as well as A defect detector is configured to generate a detection image corresponding to the inspection area in response to the voltage of the secondary electrons, and to detect a defect image from the plurality of detection images based on a voltage comparison between a reference image and the plurality of detection images, the defect image indicating a defect in the semiconductor device.

2. The inspection device according to claim 1, wherein, The charged particle beam is irradiated into a first region of the inspection area, and the high-frequency light is irradiated into a second region of the inspection area, wherein the second region is larger than the first region, and the second region and the first region have a common center point.

3. The inspection apparatus according to claim 2 further includes a second light source, the second light source being configured to irradiate the inspection area with low-frequency light having an energy greater than the bandgap energy of the inspection area to generate a photoelectromotive force, thereby enhancing the secondary electrons through the photoelectromotive force.

4. The inspection device according to claim 3, wherein, The low-frequency light is irradiated onto a third region of the inspection area, the third region being larger than the second region, wherein the third region and the second region share a common center point.

5. The inspection device according to claim 3, wherein, The high-frequency light includes one of alpha rays, beta rays, neutron rays, and X-rays, and the low-frequency light includes one of laser-generated light, ultraviolet light, and visible light.

6. The inspection device according to claim 3, wherein, The defect detector includes: An electron detector is disposed above the semiconductor device and configured to detect the secondary electrons in units of the inspection area, and to generate an analog detection signal based on the amount of secondary electrons detected. An image generator, connected to the electronic detector, is configured to generate a plurality of detection images based on the analog detection signal, the plurality of detection images including a first subset of detection images corresponding to the plurality of PMOS devices and a second subset of detection images corresponding to the plurality of NMOS devices; and A defect image detector is configured to perform the voltage comparison between each of the plurality of detected images and a reference image based on a preset defect criterion, and to detect the detected image that meets the defect criterion as a defect image.

7. The inspection device according to claim 6, wherein, Each analog detection signal has a detection voltage that varies with the detected secondary electron, and the detection image that meets the defect criteria has a brightness that is visually represented by one of color and shading according to the detection voltage.

8. The inspection device according to claim 7, wherein, The reference images include a PMOS reference image compared with the first subset of detected images and an NMOS reference image compared with the second subset of detected images.

9. The inspection device according to claim 8, wherein, The brightness of the NMOS reference image is in the range of 80% to 100% of the brightness of the PMOS reference image, and the brightness of the detection image is in the range of 5% to 50% of the brightness of the reference image, and the detection image is detected as meeting the defect criteria.

10. The inspection apparatus according to claim 6, wherein, The defect detector further includes a graph generator configured to generate a defect graph in which the defect image and the positions of the inspection areas corresponding to the defect image are visually displayed on a basic image defining a plurality of semiconductor devices and a plurality of inspection areas.

11. The inspection device according to claim 1, wherein, The beam scanner includes: Beam generator, including: A beam source is configured to generate the charged particle beam; and A guiding chamber through which the charged particle beam is guided from the beam source toward the inspection area of ​​the semiconductor device; A deflector, disposed on one side of the guide chamber, is configured to control the path of the charged particle beam toward the inspection region of the semiconductor device; and An irradiator is disposed at the end of the guide chamber and configured to focus the charged particle beam onto the inspection area of ​​the semiconductor device.

12. The inspection apparatus according to claim 11, wherein, Multiple beam scanners are arranged above the semiconductor device, with multiple irradiators located above multiple inspection areas of the semiconductor device and multiple charged particle beams simultaneously and independently irradiating the respective inspection areas.

13. The inspection device according to claim 1, wherein, The beam scanner includes: A multi-beam generator is configured to generate a single initial beam as the charged particle beam and to split the initial beam into multiple inspection beams; Multiple deflectors are configured to control the path of each of the multiple inspection beams toward a corresponding inspection region among the multiple inspection regions of the semiconductor device; and Multiple irradiators are arranged at the end of the multi-beam generator and configured to focus each of the multiple inspection beams as a charged particle splitting beam onto the corresponding inspection area.

14. The inspection apparatus according to claim 13, wherein, The multi-beam generator includes: A single beam source is configured to generate the initial beam; A beam splitting structure is configured to split the initial beam into the plurality of inspection beams; and Multiple guide chambers are configured to guide each of the multiple inspection bundles toward a corresponding inspection area of ​​the semiconductor device.

15. The inspection apparatus according to claim 14, wherein, At least one of the plurality of deflectors is disposed on one side of a corresponding guide chamber among the plurality of guide chambers, and one of the plurality of irradiators is disposed at the end of a corresponding guide chamber, such that a plurality of charged particle split beams are simultaneously irradiated onto the plurality of inspection areas.

16. The inspection apparatus according to claim 14, wherein, The beam splitting structure includes: a plurality of beam splitters for splitting the initial beam into a plurality of split beams; and a plurality of reflectors for reflecting the plurality of split beams as the plurality of inspection beams into the corresponding guide chambers.

17. A method for inspecting a semiconductor device, comprising: A semiconductor device is fixed onto a stage, the semiconductor device including multiple NMOS devices and multiple PMOS devices; High-frequency light is irradiated onto multiple inspection areas of the semiconductor device, thereby reducing the potential barrier of the PN junction in the semiconductor device. Low-frequency light with energy greater than the bandgap energy of the PN junction is irradiated onto the plurality of inspection regions of the semiconductor device to generate a photoelectromotive force at the PN junction in the semiconductor device. A beam of charged particles is irradiated onto multiple inspection areas of the semiconductor device to generate multiple secondary electrons from the semiconductor device; Secondary electrons enhanced by the photoelectric potential are detected to obtain multiple detection images corresponding to multiple inspection areas of the semiconductor device; as well as The plurality of detected images are compared with reference images to detect images that meet the defect criteria as defect images, the defect images indicating defects in the corresponding inspection areas of the semiconductor device.

18. The method according to claim 17, wherein, The charged particle beam is sequentially irradiated onto each of the plurality of inspection areas along the scanning direction.

19. The method of claim 17, wherein, Multiple charged particle beams are sequentially irradiated onto the inspection area subgroups of the multiple inspection areas along the scanning direction.

20. The method of claim 17, wherein, The charged particle beam is irradiated onto a first region of the plurality of inspection areas, the high-frequency light is irradiated onto a second region of the plurality of inspection areas, and the low-frequency light is irradiated onto a third region of the plurality of inspection areas. The third region is larger than the second region, the second region is larger than the first region, and the first region, the second region, and the third region share a common center point.

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