Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, a gate structure is formed on the substrate, and source-drain doped regions are provided in the substrate on both sides of the gate structure; forming a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer covers the gate structure and the source-drain doped regions; forming a contact hole in the first interlayer dielectric layer, the contact hole exposing the surface of the gate structure and the surface of the source-drain doped regions; forming a barrier layer on the bottom and sidewalls of the contact hole; forming a first metal layer in the contact hole, the top surface of the first metal layer being lower than the top surface of the barrier layer. The method for forming a semiconductor structure provided by an embodiment of the present invention is conducive to reducing RC delay and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In semiconductor devices, reducing RC delay (Resistance Capacitance Delay) can improve the performance of semiconductor devices. With the advancement of semiconductor process technology nodes, the integration of devices is getting higher and higher, and the critical dimension (CD) of devices is getting smaller and smaller. Accordingly, further reducing RC delay has become one of the important measures to improve the performance of semiconductor devices.

[0003] As the size of semiconductor devices continues to decrease, the critical dimensions of metal contacts and interconnect structures in the devices are also getting smaller and smaller. At present, in order to reduce RC delay, the materials used for contact plugs are usually materials with lower resistance, such as cobalt or tungsten, so as to improve the performance of semiconductor devices.

[0004] However, even if the contact plug is made of a material with a relatively small resistance, the performance of the semiconductor structure formed by the current process still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce RC delay and improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, a gate structure is formed on the substrate, and source-drain doped regions are provided in the substrate on both sides of the gate structure; a first interlayer dielectric layer is located on the substrate, and the first interlayer dielectric layer covers the gate structure and the source-drain doped regions; a contact hole is located in the first interlayer dielectric layer, and the contact hole exposes the surface of the gate structure and the surface of the source-drain doped regions; a barrier layer is located at the bottom and sidewall surfaces of the contact hole; a first metal layer is located in the contact hole, and the top surface of the first metal layer is lower than the top surface of the barrier layer.

[0007] Optionally, a top surface of the barrier layer is flush with a top surface of the first interlayer dielectric layer.

[0008] Optionally, it also includes: a second interlayer dielectric layer, the second interlayer dielectric layer is located on the first interlayer dielectric layer; a second metal layer is located on the first metal layer, and the second metal layer is also located in the second interlayer dielectric layer and part of the first interlayer dielectric layer.

[0009] Optionally, the method further includes: a seed layer, wherein the seed layer is located on the surface of the barrier layer, and the top surface of the seed layer is flush with the top surface of the first metal layer.

[0010] Optionally, a height difference between a top surface of the first metal layer and a top surface of the barrier layer is 2 nm to 10 nm.

[0011] Optionally, the material of the first metal layer includes cobalt and ruthenium.

[0012] Optionally, the material of the barrier layer includes TiN, TaN, TiSiN or TaSiN.

[0013] Optionally, the material of the seed layer includes cobalt or ruthenium.

[0014] Correspondingly, an embodiment of the present invention also provides a method for forming the above-mentioned semiconductor structure, including: providing a substrate, a gate structure is formed on the substrate, and source-drain doped regions are provided in the substrate on both sides of the gate structure; forming a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer covering the gate structure and the source-drain doped regions; forming a contact hole in the first interlayer dielectric layer, the contact hole exposing the surface of the gate structure and the surface of the source-drain doped regions; forming a blocking layer on the bottom and sidewalls of the contact hole; and forming a first metal layer in the contact hole, the top surface of the first metal layer being lower than the top surface of the blocking layer.

[0015] Optionally, a top surface of the barrier layer is flush with a top surface of the first interlayer dielectric layer.

[0016] Optionally, the step of forming a first metal layer includes: filling the first metal material layer in the contact hole, the first metal material layer covering the top of the first interlayer dielectric layer; flattening the first metal material layer so that the top surface of the first metal material layer is flush with the top surface of the first interlayer dielectric layer; etching the first metal material layer until the top surface of the first metal material layer is lower than the top surface of the barrier layer to form a first metal layer.

[0017] Optionally, after planarizing the first metal material layer and before etching the first metal material layer, the method further includes: forming a second interlayer dielectric layer on the first interlayer dielectric layer; and forming an opening in the second interlayer dielectric layer, wherein the opening exposes the surface of the first metal material layer.

[0018] Optionally, after etching the first metal material layer to form the first metal layer, the method further includes: forming a second interlayer dielectric layer on the first interlayer dielectric layer; and forming an opening in the second interlayer dielectric layer, wherein the opening exposes the surface of the first metal layer.

[0019] Optionally, the method further includes: forming a second metal layer on the first metal layer, wherein the second metal layer is located in the opening and in a portion of the contact hole.

[0020] Optionally, before filling the contact hole with the first metal material layer, the method further includes: forming a seed layer on the surface of the barrier layer.

[0021] Optionally, when etching the first metal material layer, the seed layer is etched so that the top surface of the seed layer is flush with the top surface of the first metal material layer.

[0022] Optionally, the thickness of the first metal material layer removed by etching is in the range of 2 nm to 10 nm.

[0023] Optionally, the material of the first metal layer includes cobalt and ruthenium.

[0024] Optionally, the material of the barrier layer includes TiN, TaN, TiSiN or TaSiN.

[0025] Optionally, the material of the seed layer includes cobalt or ruthenium.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] The top surface of the first metal layer is lower than the top surface of the barrier layer. When the second metal layer is subsequently formed on the first metal layer, part of the second metal layer is located in the first interlayer dielectric layer, and there is a barrier layer between the second metal layer and the first interlayer dielectric layer. Because the second metal layer and the barrier layer are in close contact and gaps are not easily generated, when the second metal layer is chemically mechanically polished, the polishing liquid cannot flow into the first metal layer through the second metal layer and the barrier layer, thereby avoiding damage to the first metal layer by the polishing liquid. At the same time, during the wet cleaning process after chemical mechanical polishing, the cleaning liquid can be prevented from penetrating into the first metal layer, thereby preventing the cleaning liquid from causing serious damage to the first metal layer, thereby helping to improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 6 is a schematic structural diagram of a semiconductor structure forming process in one embodiment;

[0029] Figures 7 to 14 is a schematic structural diagram corresponding to each step of a semiconductor structure forming process according to an embodiment of the present invention;

[0030] Figure 15 to Figure 16 It is a structural schematic diagram corresponding to each step of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0031] As known from the background art, in order to reduce RC delay, the material used for the contact hole plug is usually a material with a relatively small resistance. Since cobalt material has a relatively small resistance and a relatively good gap filling performance, it is usually used as a contact hole plug material.

[0032] However, the performance of the semiconductor structure still needs to be improved by using cobalt as the contact hole plug material. The reasons why the performance of the semiconductor structure still needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0033] Figures 1 to 6 It is a structural schematic diagram of a semiconductor structure forming process in one embodiment.

[0034] refer to Figure 1 , providing a substrate 10, on which a gate structure 20 is formed, and the substrate 10 has source-drain doping regions 11 on both sides of the gate structure 20;

[0035] A first interlayer dielectric layer 30 is formed on the substrate 10 , and the first interlayer dielectric layer 30 covers the gate structure 20 and the source-drain doped region 11 .

[0036] refer to Figure 2 , a contact hole 31 is formed in the first interlayer dielectric layer 30 , and the contact hole 31 exposes the surface of the gate structure 20 and the surface of the source-drain doped region 11 .

[0037] refer to Figure 3 , forming a barrier layer 32 on the bottom and sidewall surface of the contact hole 31, wherein the top surface of the barrier layer 32 is flush with the top surface of the first interlayer dielectric layer 30;

[0038] A first metal layer 40 is formed in the contact hole 31 , and a top surface of the first metal layer 40 is flush with a top surface of the barrier layer 32 .

[0039] refer to Figure 4 , forming a second interlayer dielectric layer 50 on the first interlayer dielectric layer 30;

[0040] An opening 51 is formed in the second interlayer dielectric layer 50 , and the opening 51 exposes the surface of the first metal layer 40 .

[0041] refer to Figure 5 , a second metal material layer 60 is formed in the opening 51 , and the second metal material layer 60 also covers the top surface of the second interlayer dielectric layer 50 .

[0042] refer to Figure 6, chemical mechanical polishing is performed on the second metal material layer 60 until the top surface of the second metal material layer 60 is flush with the top surface of the second interlayer dielectric layer 50 , so as to form a second metal layer 61 , which is also located on the first metal layer 40 .

[0043] However, in the process of forming the semiconductor structure by the above method, before depositing the second metal material layer 60, in order to reduce the resistance of the interconnection structure, it is chosen not to form a barrier layer on the bottom and side walls of the opening 51. Due to the lack of a barrier layer between the second metal material layer 60 and the second interlayer dielectric layer 50, the second metal material layer 60 is not in close contact with the second interlayer dielectric layer 50 on the side walls of the opening 52. When the second metal material layer 60 is subsequently subjected to chemical mechanical polishing, the polishing liquid will flow down through the gaps in the side walls of the opening 51 and contact the first metal layer 40 at the bottom of the opening 51. When the first metal layer 40 is made of a material that is easily corroded, such as cobalt, the first metal layer 40 will be corroded by the polishing liquid and cause damage. In addition, after the chemical mechanical polishing, wet cleaning is required. The cleaning liquid used in the wet cleaning process will also penetrate from the gaps in the opening 51 to the first metal layer 40. The cleaning liquid will cause more serious damage to the first metal layer 40, thereby affecting the performance of the semiconductor structure.

[0044] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, wherein a first metal layer is formed in the contact hole, and the top surface of the first metal layer is lower than the top surface of the barrier layer. When a second metal layer is subsequently formed on the first metal layer, part of the second metal layer is located in the first interlayer dielectric layer, and there is a barrier layer between the second metal layer and the first interlayer dielectric layer. Because the second metal layer and the barrier layer are in close contact, when the second metal layer is subjected to chemical mechanical polishing and wet cleaning, neither the polishing liquid nor the cleaning liquid can flow into the first metal layer below through the second metal layer and the barrier layer, and will not cause corrosion to the first metal layer, thereby facilitating the improvement of the performance of the semiconductor structure.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 7 to 14 It is a schematic structural diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention.

[0047] refer to Figure 7 , providing a substrate, on which a gate structure 200 is formed, and in which source-drain doped regions 101 are provided on both sides of the gate structure 200 .

[0048] The substrate provides a process platform for subsequently forming a semiconductor structure.

[0049] In this embodiment, taking the formed semiconductor structure as a Fin FET (fin field effect transistor) structure as an example, the base includes: a substrate 100; a discrete fin 110 located on the substrate; an isolation structure (not shown) located on the substrate 100 where the fin 110 is exposed, the isolation structure covering a portion of the side wall of the fin 110, and the top of the isolation structure is lower than the top of the fin 110.

[0050] In other embodiments, the semiconductor device may also be a planar device, and the base may be a planar substrate.

[0051] The material of the substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 can also be a silicon substrate on an insulator or a germanium substrate on an insulator; the material of the fin 110 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the substrate 100 is a silicon substrate, and the material of the fin 110 is silicon.

[0052] The isolation structure serves to electrically isolate adjacent fins 110 , and the material of the isolation structure is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbon nitride oxide. In this embodiment, the material of the isolation structure is silicon oxide.

[0053] In this embodiment, the substrate 100 includes only an NMOS region, and the corresponding FinFET device formed is an NMOS tube; in other embodiments, the substrate may also include an NMOS region and a PMOS region, and the corresponding semiconductor device is a CMOS tube, or may only include a PMOS region, and the corresponding FinFET device formed is a PMOS tube.

[0054] The gate structure 200 is located on the isolation structure and crosses the fin 110 , and the gate structure 200 covers a portion of the top and sidewalls of the fin 110 .

[0055] In this embodiment, the gate structure 200 includes: a gate dielectric layer 210 located on the top and sidewall surfaces of part of the fin 110 ; a work function layer 220 located on the surface of the gate dielectric layer 210 ; and a gate electrode layer 230 located on the surface of the work function layer 220 .

[0056] In this embodiment, the gate electrode layer 230 is made of a metal material, such as copper, aluminum or tungsten.

[0057] In this embodiment, the doping ions of the source / drain doping region 101 are N-type ions, such as P, As or Sb.

[0058] Continue to refer Figure 7, forming a first interlayer dielectric layer 300 on the substrate where the gate structure 200 is exposed, wherein the first interlayer dielectric layer 300 covers the gate structure 200 and the source / drain doped regions 101 .

[0059] In this embodiment, the material of the first interlayer dielectric layer 300 is SiO 2 In other embodiments, the material of the first interlayer dielectric layer may also be SiN, SiON, AlN, Al 2 O 3 , SiC, SiCN, SiOC or SiOCH.

[0060] In this embodiment, the first interlayer dielectric layer 300 is formed by a chemical vapor deposition process; in other embodiments, the first interlayer dielectric layer 300 may also be formed by a physical vapor deposition process or an atomic layer deposition process.

[0061] In this embodiment, the process steps for forming the gate structure 200 and the source-drain doped region 101 include: forming a dummy gate spanning the fin 110; forming a sidewall on the sidewall of the dummy gate (not shown); forming a source-drain doped region 101 in the substrate on both sides of the dummy gate; forming an initial dielectric layer on the substrate exposed by the dummy gate, the initial dielectric layer exposing the top of the dummy gate; removing the dummy gate to form a gate opening in the initial dielectric layer; forming a gate dielectric layer 210, a work function layer 220 and a gate electrode layer 230 in the gate opening in sequence to form a gate structure 200; forming an upper dielectric layer on the initial dielectric layer and on the top of the gate structure 200, the initial dielectric layer and the upper dielectric layer forming the first interlayer dielectric layer 300.

[0062] refer to Figure 8 , a contact hole 310 is formed in the first interlayer dielectric layer 300 , and the contact hole 310 exposes the surface of the gate structure 200 and the source-drain doped region 101 .

[0063] The contact hole 310 provides a process basis for subsequently forming a conductive plug electrically connected to the source and drain doping regions.

[0064] The process steps for forming the contact hole 310 include: forming a first photoresist layer (not shown) on the first interlayer dielectric layer 300, wherein the first photoresist layer defines the position and size of the contact hole 310 to be formed; using the first photoresist layer as a mask, etching the first interlayer dielectric layer 300 to form a contact hole 310 penetrating the first interlayer dielectric layer 300, and the bottom of the contact hole 310 exposes the surface of the gate structure 200 and the surface of the source-drain doped region 101; and removing the first photoresist layer.

[0065] After the contact hole 310 is formed, a barrier layer is formed at the bottom and side wall surfaces of the contact hole 310, and the top surface of the barrier layer is flush with the top surface of the first interlayer dielectric layer 300; then a first metal layer is formed in the contact hole 310, and the top surface of the first metal layer is lower than the top surface of the barrier layer.

[0066] The specific steps of forming the barrier layer and the first metal layer include:

[0067] refer to Figure 8 A barrier material layer 320 is formed on the bottom and sidewall surfaces of the contact hole 310 , and the barrier material layer 320 also covers the top surface of the first interlayer dielectric layer 300 .

[0068] In this embodiment, the method for forming the barrier material layer 320 is physical vapor deposition; in other embodiments, the method for forming the barrier material layer 320 may also be chemical vapor deposition or atomic layer deposition.

[0069] In this embodiment, the material of the barrier material layer 320 is TiN; in other embodiments, the material of the barrier material layer 320 may also be one or more of TaN, TiSiN or TaSiN.

[0070] Continue to refer Figure 8 A seed layer 330 is formed on the surface of the barrier material layer 320 , and the seed layer 330 also covers the surface of the barrier material layer 320 located on the top surface of the first interlayer dielectric layer 300 .

[0071] In this embodiment, the method for forming the seed layer 330 is physical vapor deposition; in other embodiments, the method for forming the seed layer 330 may also be chemical vapor deposition or atomic layer deposition.

[0072] refer to Fig. 9 , a first metal material layer 400 is deposited in the contact hole 310 , and the first metal material layer 400 also covers the seed layer 330 located on the first interlayer dielectric layer 300 .

[0073] In this embodiment, the first metal material layer 400 is made of cobalt material. Cobalt has a relatively low resistance and good filling performance, and can be used as a contact hole plug to reduce contact resistance and RC delay.

[0074] In other embodiments, the first metal material layer 400 may also be ruthenium.

[0075] In this embodiment, the material of the seed layer 330 is the same as that of the first metal material layer 400 , that is, cobalt; in other embodiments, the material of the seed layer may also be ruthenium.

[0076] In this embodiment, the method for depositing the first metal material layer 400 in the contact hole 310 is chemical vapor deposition; in other embodiments, the first metal material layer can also be deposited by electrochemical plating process, atomic layer deposition process or physical vapor deposition method.

[0077] refer to Fig.10 , the first metal material layer 400 is planarized so that the top surface of the first metal material layer 400 is flush with the top surface of the first interlayer dielectric layer 300 .

[0078] In this embodiment, when there is a blocking material layer 320 and a seed layer 330 on the first interlayer dielectric layer 300, the planarization process can remove the blocking material layer 320 and the seed layer 330 on the first interlayer dielectric layer 300 together to form a blocking layer 321, and the top surface of the blocking layer 321 is flush with the top surface of the first interlayer dielectric layer 300.

[0079] In this embodiment, the barrier layer 321 functions to prevent the first metal material from diffusing into the surrounding dielectric layer, thereby preventing the diffusion of the metal from damaging the performance of the semiconductor structure.

[0080] In this embodiment, chemical mechanical polishing is used to planarize the first metal material layer 400 .

[0081] refer to Fig.11 In this embodiment, after the first metal material layer 400 is planarized, a second interlayer dielectric layer 500 is formed on the first interlayer dielectric layer 300 .

[0082] In this embodiment, the material of the second interlayer dielectric layer 500 is SiO 2 In other embodiments, the material of the second interlayer dielectric layer 500 may also be SiN, SiON, AlN, Al 2 O 3 , SiC, SiCN, SiOC or SiOCH.

[0083] In this embodiment, the second interlayer dielectric layer 500 is formed by chemical vapor deposition process; in other embodiments, the second interlayer dielectric layer 500 may also be formed by physical vapor deposition process or atomic layer deposition process.

[0084] Continue to refer Fig.11 , an opening 510 is formed in the second interlayer dielectric layer 500 , and the opening 510 exposes the surface of the first metal material layer 400 .

[0085] The process steps for forming the opening 510 include: forming a second photoresist layer (not shown) on the second interlayer dielectric layer 500, wherein the second photoresist layer defines the position and size of the opening 510 to be formed; using the second photoresist layer as a mask, etching the second interlayer dielectric layer 500 until the surface of the first metal material layer 400 is exposed to form the opening 510 penetrating the second interlayer dielectric layer 500; and removing the second photoresist layer.

[0086] refer to Fig.12 After the opening 510 is formed, the first metal material layer 400 is etched along the opening 510 until the top surface of the first metal material layer 400 is lower than the top surface of the barrier layer 321 , thereby forming a first metal layer 410 .

[0087] The method of etching the first metal material layer 400 includes one or a combination of dry etching and wet etching processes. In this embodiment, the first metal material layer 400 is etched by a dry etching process.

[0088] The thickness of the first metal material layer 400 removed by etching is 2nm to 10nm. If the first metal material layer 400 removed is greater than 10nm, the resistance of the formed first metal layer will increase, causing RC delay; if the first metal material layer 400 removed is less than 2nm, it will not be able to prevent the penetration of the grinding liquid in the subsequent grinding process and the penetration of the cleaning liquid in the wet cleaning process, and will still cause corrosion to the first metal layer; therefore, the thickness of the first metal material layer 400 removed by etching ranges from 2nm to 10nm.

[0089] refer to Fig.13 After forming the first metal layer 410 , a second metal material layer 600 is deposited in the opening 510 , the top of the second metal material layer 600 is higher than the top surface of the second interlayer dielectric layer 500 , and the second metal material layer 600 is located on the first metal layer 410 .

[0090] In this embodiment, the material of the second metal material layer 600 is tungsten.

[0091] In this embodiment, the second metal material layer 600 is deposited by a selective deposition method; in other embodiments, the second metal material layer may also be deposited by an electrochemical plating process, an atomic layer deposition process, a chemical vapor deposition method or a physical vapor deposition method.

[0092] In this embodiment, in order to reduce the resistance, before depositing the second metal material layer 600 , no barrier layer is formed on the bottom and sidewalls of the opening 510 .

[0093] refer to Fig.14, the second metal material layer 600 is planarized until the top surface of the second metal material layer 600 is flush with the top surface of the second interlayer dielectric layer 500 , thereby forming a second metal layer 610 .

[0094] In this embodiment, since the top surface of the first metal layer 410 is lower than the top surface of the barrier layer 321, a portion of the deposited second metal material layer 600 is inside the first interlayer dielectric layer 400, that is, inside the contact hole 310. Since the top surface of the barrier layer 321 is flush with the top surface of the first interlayer dielectric layer 400, there is a barrier layer 321 between the second metal material layer 600 and the first interlayer dielectric layer 400. Due to the presence of the barrier layer 321, the second metal material layer 600 is in close contact with the barrier layer 321, and gaps are not easily generated. When the second metal material layer 600 is subsequently planarized and wet-cleaned, the grinding liquid used for chemical mechanical polishing and the cleaning liquid used for wet cleaning cannot flow through the second metal material layer 600 and the barrier layer 321 to the first metal layer 410, thereby avoiding damage to the first metal layer 410, which is beneficial to the performance of the semiconductor structure.

[0095] Figure 15 to Figure 16 It is a structural schematic diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0096] The difference of another embodiment is that after the first metal material layer 400 is planarized, the first metal material layer 400 is first etched and then a second interlayer dielectric layer 500 is formed. The planarization of the first metal material layer 400 and the previous process steps are the same as those in the previous embodiment and will not be repeated here.

[0097] refer to Fig.15 After the first metal material layer 400 is planarized, the first metal material layer 400 is etched until the top surface of the first metal material layer 400 is lower than the top surface of the barrier layer 321 to form a first metal layer 410 .

[0098] The process and thickness of etching the first metal material layer 400 are the same as those in the previous embodiment and will not be described again herein.

[0099] refer to Fig.16 , a second interlayer dielectric layer 500 is formed on the first interlayer dielectric layer 300 .

[0100] The material and the forming method of the second interlayer dielectric layer 500 are the same as those in the previous embodiment, and will not be described again herein.

[0101] Continue to refer Fig.16, an opening 510 is formed in the second interlayer dielectric layer 500 , and the opening 510 exposes the surface of the first metal layer 410 .

[0102] The steps of forming the opening 510 are the same as those in the previous embodiment and will not be described again.

[0103] After the opening 510 is formed, the second metal layer 610 is formed in the opening 510 .

[0104] The material and formation method of the second metal layer 610 are the same as those in the previous embodiment and will not be described herein again.

[0105] Correspondingly, an embodiment of the present invention further provides a semiconductor structure.

[0106] refer to Fig.14 The semiconductor structure includes: a substrate, a gate structure 200 is formed on the substrate, and source-drain doped regions 101 are provided in the substrate on both sides of the gate structure 200; a first interlayer dielectric layer 300 is located on the substrate, and the first interlayer dielectric layer 300 covers the gate structure 200 and the source-drain doped regions 101; a contact hole 310 is located in the first interlayer dielectric layer 300, and the contact hole 310 exposes the surface of the gate structure 200 and the surface of the source-drain doped regions 101; a barrier layer 321 is located at the bottom and sidewall surfaces of the contact hole 310, and the top surface of the barrier layer 321 is flush with the top surface of the first interlayer dielectric layer 300; a first metal layer 410 is located in the contact hole 310, and the top surface of the first metal layer 410 is lower than the top surface of the barrier layer 321.

[0107] In this embodiment, the base includes: a substrate 100; a discrete fin 110 located on the substrate; an isolation structure (not shown) located on the substrate 100 where the fin 110 is exposed, the isolation structure covering a portion of the side wall of the fin 110, and the top of the isolation structure is lower than the top of the fin 110.

[0108] In this embodiment, the gate structure 200 includes: a gate dielectric layer 210 located on the top and sidewall surfaces of part of the fin 110 ; a work function layer 220 located on the surface of the gate dielectric layer 210 ; and a gate electrode layer 230 located on the surface of the work function layer 220 .

[0109] In this embodiment, the material of the first interlayer dielectric layer 300 is SiO 2 In other embodiments, the material of the first interlayer dielectric layer may also be SiN, SiON, AlN, Al 2 O 3 , SiC, SiCN, SiOC or SiOCH.

[0110] In this embodiment, the material of the barrier layer 321 is TiN; in other embodiments, the material of the barrier layer 321 may also be one or more of TaN, TiSiN or TaSiN.

[0111] In this embodiment, the material of the first metal layer 410 is cobalt. Cobalt has a relatively small resistance and a good filling performance. Using cobalt as the contact hole plug material can reduce RC delay and improve the electrical performance of the semiconductor structure.

[0112] In other embodiments, the material of the first metal layer 410 may also be ruthenium.

[0113] refer to Fig.14 The semiconductor structure further includes: a seed layer 330 located between the barrier layer 321 and the first metal layer 410 .

[0114] In this embodiment, the material of the seed layer 330 is the same as that of the first metal layer 410 , that is, cobalt; in other embodiments, the material of the seed layer 330 may also be ruthenium.

[0115] refer to Fig.14 The semiconductor structure also includes: a second interlayer dielectric layer 500, wherein the second interlayer dielectric layer 500 is located on the first interlayer dielectric layer 300; a second metal layer 610, which is located on the first metal layer 410, and the second metal layer 610 is also located in the second interlayer dielectric layer 500 and in part of the first interlayer dielectric layer 300.

[0116] In this embodiment, the material of the second interlayer dielectric layer 500 is SiO 2 In other embodiments, the material of the second interlayer dielectric layer 500 may also be SiN, SiON, AlN, Al 2 O 3 , SiC, SiCN, SiOC or SiOCH.

[0117] In this embodiment, the material of the second metal layer 610 is tungsten.

[0118] In this embodiment, the top surface of the barrier layer 321 is flush with the top surface of the first interlayer dielectric layer 300, the top surface of the first metal layer 410 is lower than the top surface of the barrier layer 321, the second metal layer 610 located on the first metal layer 410 is partially located in the first interlayer dielectric layer 300, and there is a barrier layer 321 between the second metal layer 610 and the first interlayer dielectric layer 300, and the second metal layer 610 is in close contact with the barrier layer 321. Therefore, during the process of chemical mechanical polishing to form the second metal layer 610, and during the process of wet cleaning after chemical mechanical polishing, the polishing liquid and the cleaning liquid cannot flow through the second metal layer 610 and the barrier layer 321 to the first metal layer 410, thereby avoiding damage to the first metal layer 410, which is beneficial to improving the performance of the semiconductor structure.

[0119] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, a gate structure is formed on the substrate, and source-drain doped regions are provided in the substrate on both sides of the gate structure; A first interlayer dielectric layer is located on the substrate, and the first interlayer dielectric layer covers the gate structure and the source-drain doped region; A contact hole, located in the first interlayer dielectric layer, wherein the contact hole exposes the surface of the gate structure and the surface of the source and drain doped regions; A barrier layer, located at the bottom and sidewall surfaces of the contact hole; A first metal layer is located in the contact hole, wherein a top surface of the first metal layer is lower than a top surface of the barrier layer, and a top surface of the first metal layer is also higher than a surface of the gate structure; a second interlayer dielectric layer, the second interlayer dielectric layer being located on the first interlayer dielectric layer; an opening, wherein the opening is located in the second interlayer dielectric layer and the opening exposes a surface of the first metal layer; The second metal layer is located on the first metal layer, and the second metal layer is also located in the second interlayer dielectric layer and in a portion of the first interlayer dielectric layer.

2. The semiconductor structure according to claim 1, wherein: A top surface of the barrier layer is flush with a top surface of the first interlayer dielectric layer.

3. The semiconductor structure according to claim 2, wherein: Also includes: a second interlayer dielectric layer, the second interlayer dielectric layer being located on the first interlayer dielectric layer; The second metal layer is located on the first metal layer, and the second metal layer is also located in the second interlayer dielectric layer and in a portion of the first interlayer dielectric layer.

4. The semiconductor structure according to claim 1, wherein: Also includes: A seed layer is located on the surface of the barrier layer, and a top surface of the seed layer is flush with a top surface of the first metal layer.

5. The semiconductor structure according to claim 1, wherein: A height difference between a top surface of the first metal layer and a top surface of the barrier layer is 2 nm to 10 nm.

6. The semiconductor structure according to claim 1, wherein: The material of the first metal layer includes cobalt and ruthenium.

7. The semiconductor structure according to claim 1, wherein: The material of the barrier layer includes TiN, TaN, TiSiN or TaSiN.

8. The semiconductor structure according to claim 4, wherein: The material of the seed layer includes cobalt or ruthenium.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a gate structure is formed on the substrate, and source-drain doping regions are provided in the substrate on both sides of the gate structure; forming a first interlayer dielectric layer on the substrate, wherein the first interlayer dielectric layer covers the gate structure and the source-drain doped region; forming a contact hole in the first interlayer dielectric layer, wherein the contact hole exposes the surface of the gate structure and the surface of the source and drain doped regions; forming a barrier layer on the bottom and sidewalls of the contact hole; forming a first metal layer in the contact hole, wherein a top surface of the first metal layer is lower than a top surface of the barrier layer, and a top surface of the first metal layer is also higher than a surface of the gate structure; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming an opening in the second interlayer dielectric layer, wherein the opening is located in the second interlayer dielectric layer and the opening exposes a surface of the first metal layer; A second metal layer is formed on the first metal layer, wherein the second metal layer is located in the opening and in a portion of the contact hole.

10. The method for forming a semiconductor structure according to claim 9, wherein: A top surface of the barrier layer is flush with a top surface of the first interlayer dielectric layer.

11. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the first metal layer comprises: Filling a first metal material layer in the contact hole, wherein the first metal material layer covers the top of the first interlayer dielectric layer; performing a planarization process on the first metal material layer so that a top surface of the first metal material layer is flush with a top surface of the first interlayer dielectric layer; The first metal material layer is etched until a top surface of the first metal material layer is lower than a top surface of the barrier layer, thereby forming a first metal layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: After the first metal material layer is planarized and before the first metal material layer is etched, the method further includes: forming a second interlayer dielectric layer on the first interlayer dielectric layer; An opening is formed in the second interlayer dielectric layer, wherein the opening exposes a surface of the first metal material layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: After etching the first metal material layer to form the first metal layer, the method further includes: forming a second interlayer dielectric layer on the first interlayer dielectric layer; An opening is formed in the second interlayer dielectric layer, wherein the opening exposes a surface of the first metal layer.

14. The method for forming a semiconductor structure according to claim 12 or 13, characterized in that: Also includes: A second metal layer is formed on the first metal layer, wherein the second metal layer is located in the opening and in a portion of the contact hole.

15. The method for forming a semiconductor structure according to claim 11, wherein: Before filling the first metal material layer in the contact hole, the method further includes: forming a seed layer on the surface of the barrier layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: When etching the first metal material layer, the seed layer is etched so that the top surface of the seed layer is flush with the top surface of the first metal material layer.

17. The method for forming a semiconductor structure according to claim 11, wherein: The thickness of the first metal material layer removed by etching is in the range of 2 nm to 10 nm.

18. The method for forming a semiconductor structure according to claim 9, wherein: The material of the first metal layer includes cobalt and ruthenium.

19. The method for forming a semiconductor structure according to claim 9, wherein: The material of the barrier layer includes TiN, TaN, TiSiN or TaSiN.

20. The method for forming a semiconductor structure according to claim 15, wherein: The material of the seed layer includes cobalt or ruthenium.

Images