Motor control device, motor system, and motor control method

Abstract

The present invention provides a motor control device, the motor control device (100-1) comprising an inverter, a current detector, a current detection unit, and a PWM signal generation unit. The PWM signal generation unit extracts a part of the zero vector interval of each of the first PWM signal, the second PWM signal, and the third PWM signal, and allocates the power-on width corresponding to the extracted zero vector interval to the interval outside the zero vector interval of each of the first PWM signal, the second PWM signal, and the third PWM signal, so as to adjust the second power-on time to the power-on width at which the current detection unit can detect the phase current of the two phases, when there is a first power-on time at which the current detection unit can detect the power-on width of the phase current of the one phase, and a second power-on time at which the current detection unit cannot detect the power-on width of the phase current of the two phases.

Description

Technical Field

[0001] The present invention relates to a motor control device, a motor system and a motor control method. Background Art

[0002] Patent document 1 discloses a technique for detecting the current of each phase U, V, and W for controlling a motor by using a shunt resistor inserted into the DC portion of an inverter circuit. In order to detect all currents of the three phases in this manner, it is necessary to generate a three-phase PWM signal pattern in such a manner that currents of two or more phases can be detected within one cycle of a PWM (Pulse Width Modulation) carrier.

[0003] <Prior Art Literature>

[0004] <Patent Documents>

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-84632 Summary of the invention

[0006] <Problems to be Solved by the Invention>

[0007] However, in the conventional technology, when the phase of the PWM signal changes, the current flowing through the DC bus is distorted accordingly, and becomes a waveform with a large noise superimposed. There is a problem that the current distortion becomes a cause of noise, and sometimes causes discomfort to the user depending on the application connected to the motor.

[0008] The present invention is made in view of the above, and its object is to provide a motor control device capable of suppressing noise.

[0009] <Methods used to solve the problem>

[0010] The motor control device of the embodiment of the present invention includes: an inverter unit, which drives the motor based on a first PWM signal, a second PWM signal, and a third PWM signal; a current detection unit, which detects the phase current flowing through each phase of the motor by acquiring the detection signal; a duty ratio setting unit, which sets the duty ratio of the first PWM signal, the second PWM signal, and the third PWM signal based on the detection value of the phase current of each phase; and a PWM signal generating unit, which generates the first PWM signal, the second PWM signal, and the third PWM signal by comparing the setting value of the duty ratio with the level of a carrier whose level increases and decreases periodically. The forming unit extracts a part of each zero vector interval in the first PWM signal, the second PWM signal and the third PWM signal, and allocates the conduction width corresponding to the extracted zero vector interval to the interval outside the respective zero vector interval of the first PWM signal, the second PWM signal and the third PWM signal, so as to adjust the current detection unit to be able to detect the conduction width of the phase current of the phase different from the phase detected in the first PWM signal.

[0011] <Effects of the Invention>

[0012] The motor control device of the present invention has the effect of being able to suppress noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A diagram showing a configuration example of a motor system 1 - 1 according to Embodiment 1 of the present invention.

[0014] Figure 2 It is shown Figure 1 The diagram shows an example of the configuration of the carrier generator 37, the PWM signal generator 32, etc.

[0015] Figure 3 This is a diagram for explaining the principle of generating a triangular wave carrier of each phase.

[0016] Figure 4 The diagram shows waveforms of a plurality of PWM signals U, V, and W, a waveform of a carrier wave C per cycle of these PWM signals, and waveforms of duty ratios Udu, Vdu, and Wdu of each phase.

[0017] Figure 5 This is the first diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0018] Figure 6 This is a second diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0019] Figure 7 This is the third diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0020] Figure 8 This is a fourth diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0021] Fig. 9 1 is a flowchart showing the operation of the motor control device 100 - 1 .

[0022] Fig.10 : is a flowchart showing an example of the first current detection process.

[0023] Fig.11 : is a flowchart showing an example of the second current detection process.

[0024] Fig.12 This is a first flowchart for explaining the operation of the pulse phase adjustment process.

[0025] Fig.13 This is the first diagram showing waveforms of a plurality of PWM signals and a waveform of a carrier wave C per cycle of these PWM signals when the energization rate is high.

[0026] Fig.14 The second diagram shows the waveforms of a plurality of PWM signals and the waveform of the carrier wave C per one cycle of these PWM signals when the energization rate is high.

[0027] Fig.15 The third diagram shows the waveforms of a plurality of PWM signals and the waveform of the carrier C per cycle of these PWM signals when the energization rate is high.

[0028] Fig.16A This is a second flowchart for explaining the operation of the pulse phase adjustment process.

[0029] Fig. 16B This is a third flowchart for explaining the operation of the pulse phase adjustment process. DETAILED DESCRIPTION

[0030] Hereinafter, a motor control device, a motor system, and a motor control method according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0031] [Implementation Method 1]

[0032] Figure 1It is a diagram showing a configuration example of a motor system 1 - 1 according to Embodiment 1 of the present invention. Figure 2 It is shown Figure 1 The diagram shows an example of the configuration of the carrier generator 37, the PWM signal generator 32, etc. Figure 1 The motor system 1-1 shown controls the rotation of the motor 4. The device on which the motor system 1-1 is mounted is, for example, a copy machine, a personal computer, a refrigerator, etc., but the device is not limited thereto. The motor system 1-1 includes at least the motor 4 and the motor control device 100-1.

[0033] The motor 4 has a plurality of windings. The motor 4 has, for example, a three-phase winding including a U-phase winding, a V-phase winding, and a W-phase winding. As a specific example of the motor 4, a three-phase brushless motor or the like can be cited.

[0034] The motor control device 100-1 drives the motor through an inverter, which converts direct current into three-phase alternating current by controlling the on / off (ON, OFF) of a plurality of switching elements connected in a three-phase bridge according to an energization pattern of a PWM signal including three phases. The motor control device 100-1 includes an inverter 23, a current detection unit 27, a current detection timing adjustment unit 34, a drive circuit 33, an energization pattern generation unit 35, a carrier generation unit 37, and a clock pulse generation unit 36.

[0035] The inverter 23, which is an inverter unit, is a circuit that converts the DC supplied from the DC power supply 21 into a three-phase AC by switching a plurality of switching elements, and causes the three-phase AC driving current to flow through the motor 4, thereby rotating the rotor of the motor 4. The inverter 23 drives the motor 4 based on a plurality of energization patterns generated by the energization pattern generation unit 35 (more specifically, a three-phase PWM signal generated by the PWM signal generation unit 32 in the energization pattern generation unit 35).

[0036] The inverter 23 has a plurality of switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- connected in a three-phase bridge. The switching elements 25U+, 25V+, and 25W+ are high-side switching elements (upper bridge arms) connected to the positive side of the DC power supply 21 via the positive bus 22a, respectively. The switching elements 25U-, 25V-, and 25W- are low-side switching elements (lower bridge arms) connected to the negative side (specifically, the ground side) of the DC power supply 21, respectively. The plurality of switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- are turned on or off according to corresponding drive signals among the plurality of drive signals supplied from the drive circuit 33 based on the PWM signal included in the above-mentioned power-on mode. Hereinafter, when no particular distinction is made, the plurality of switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- may be referred to simply as switching elements.

[0037] The connection point of the switching element 25U+ and the switching element 25U- is connected to one end of the U-phase winding of the motor 4. The connection point of the switching element 25V+ and the switching element 25V- is connected to one end of the V-phase winding of the motor 4. The connection point of the switching element 25W+ and the switching element 25W- is connected to one end of the W-phase winding of the motor 4. The other ends of the U-phase winding, the V-phase winding, and the W-phase winding are connected to each other.

[0038] Specific examples of the switching element include N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), etc. However, the switching element is not limited to these.

[0039] The current detector 24 s outputs a detection signal Sd corresponding to the current value of the current flowing through the DC side of the inverter 23 . Figure 1 The current detector 24 shown generates a detection signal Sd corresponding to the current value of the current flowing through the negative bus 22b. The current detector 24 is, for example, a current detection element configured on the negative bus 22b, and more specifically, it is a shunt resistor inserted into the negative bus 22b. The current detection element such as the shunt resistor generates a voltage signal corresponding to the current value of the current flowing through itself as the detection signal Sd. It should be noted that the current detector 24 can be an element that outputs a detection signal corresponding to the current value of the current flowing through the negative bus 22b, and it can be a sensor such as a CT (Current Transformer).

[0040] The current detection unit 27 acquires the detection signal Sd based on the multiple energization patterns (more specifically, the three-phase PWM signals) generated by the energization pattern generation unit 35, thereby detecting the phase currents Iu, Iv, and Iw flowing through the U, V, and W phases of the motor 4. More specifically, the current detection unit 27 acquires the detection signal Sd at an acquisition timing synchronized with the multiple energization patterns (more specifically, the three-phase PWM signals), thereby detecting the phase currents Iu, Iv, and Iw flowing through the U, V, and W phases of the motor 4. The acquisition timing of the detection signal Sd is set by the current detection timing adjustment unit 34.

[0041] For example, the current detection unit 27 introduces the detection signal Sd of the analog voltage generated by the current detector 24 into an AD (Analog to Digital) converter at the acquisition timing set by the current detection timing adjustment unit 34. The AD converter is provided in the current detection unit 27. In addition, the current detection unit 27 detects the phase currents Iu, Iv, and Iw of the U, V, and W phases of the motor 4 by performing AD conversion on the imported analog detection signal Sd to make it a digital detection signal Sd, and digitally processes the digital detection signal Sd after the AD conversion. The detection values ​​of the phase currents Iu, Iv, and Iw of each phase detected by the current detection unit 27 are supplied to the energization pattern generation unit 35. The clock pulse generation unit 36 ​​generates a clock pulse of a predetermined frequency through a built-in oscillation circuit, and outputs the generated clock pulse to the carrier generation unit 37. It should be noted that the clock pulse generation unit 36 ​​starts to operate at the same time as the power supply of the motor control device 100-1 is turned on.

[0042] The energizing pattern generation unit 35 includes a vector control unit 30, a duty ratio setting unit 31, and a PWM signal generation unit 32. The energizing pattern generation unit 35 determines the rotor position of the motor 4 based on the detection values ​​of the phase currents Iu, Iv, and Iw of the motor 4 detected by the current detection unit 27, and generates a pattern for energizing the inverter 23 (energizing pattern of the inverter 23) in such a manner that the rotor of the motor 4 follows the determined rotor position. The energizing pattern of the inverter 23 can be said to be a pattern for energizing the motor 4 (energizing pattern of the motor 4). The energizing pattern of the inverter 23 includes, for example, a three-phase PWM signal for energizing the inverter 23 in such a manner that the motor 4 rotates.

[0043] In addition, when the energization pattern generation unit 35 generates the energization pattern of the inverter 23 by vector control, it has a vector control unit 30 in addition to the duty ratio setting unit 31 and the PWM signal generation unit 32. It should be noted that although the energization pattern of the inverter is generated by vector control in this embodiment, it is not limited to this, and the phase voltage of each phase can also be obtained by VF control or the like.

[0044] After the rotation speed command ωref of the motor 4 is given from the outside, the vector control unit 30 generates a torque current command Iqref and an excitation current command Idref based on the difference between the measured value or estimated value of the rotation speed of the motor 4 and the rotation speed command ωref. The vector control unit 30 calculates the torque current Iq and the excitation current Id based on the phase currents Iu, Iv, and Iw of the U, V, and W phases of the motor 4 by vector control calculation using the rotor position θ. The vector control unit 30 generates a voltage command Vq by, for example, performing a PI control calculation on the difference between the torque current command Iqref and the torque current Iq. The vector control unit 30 generates a voltage command Vd by, for example, performing a PI control calculation on the difference between the excitation current command Idref and the excitation current Id. The vector control unit 30 converts the voltage commands Vq and Vd into phase voltage commands Vu*, Vv*, and Vw* of the U, V, and W phases using the above-mentioned rotor position θ. The phase voltage commands Vu*, Vv*, and Vw* of the respective phases are supplied to the duty ratio setting unit 31 .

[0045] The duty ratio setting unit 31 sets the duty ratios Udu, Vdu, and Wdu for generating three-phase PWM signals (set values ​​of the duty ratios of the phases) based on the input phase voltage commands Vu*, Vv*, and Vw* of the phases.

[0046] A specific example of the method for setting the duty ratio Udu, Vdu, and Wdu of each phase is described. As shown in the following formulas (1) to (3), the duty ratio Udu, Vdu, and Wdu of each phase are set based on the modulation rates modU, modV, and modW. The duty ratios Udu, Vdu, and Wdu of each phase obtained based on the following formulas (1) to (3) are, for example, sinusoidal waveforms with phases that differ by 120 degrees. It should be noted that examples of the waveforms of the duty ratios Udu, Vdu, and Wud of each phase will be described later.

[0047] Udu = modU × (carrier upper limit value) (1)

[0048] Vdu=modV×(carrier upper limit value)···(2)

[0049] Wdu=modW×(carrier upper limit value)···(3)

[0050] The PWM signal generating unit 32 generates a power-on pattern including a 3-phase PWM signal by comparing the duty ratios Udu, Vdu, and Wdu of each phase set by the duty ratio setting unit 31 with the level of the carrier C. The carrier C is a carrier signal whose level increases and decreases periodically. The PWM signal generating unit 32 compares each set value of the duty ratio of each phase with the level of the carrier C. Based on the comparison result, the PWM signal generating unit 32 sets the level of the PWM signal to a high level during a period when the set value of the duty ratio of the PWM signal is greater than the level of the carrier C. On the other hand, based on the comparison result, the PWM signal generating unit 32 sets the level of the PWM signal to a low level during a period when the set value of the duty ratio of the PWM signal is less than the level of the carrier C. The PWM signal generating unit 32 also generates a PWM signal for driving the lower bridge arm by inverting the 3-phase PWM signal for driving the upper bridge arm, and outputs the generated power-on pattern including the PWM signal to the driving circuit 33 after adding a dead time as needed.

[0051] The drive circuit 33 outputs a drive signal for switching the six switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- included in the inverter 23 according to the power-on pattern including the PWM signal given. As a result, a three-phase AC drive current is supplied to the motor 4, and the rotor of the motor 4 rotates.

[0052] The current detection timing adjustment unit 34 determines the acquisition timing for the current detection unit 27 to detect the phase currents of two phases (two phases) among the phase currents of three phases (three phases) within one cycle of the carrier C based on the carrier C supplied from the PWM signal generation unit 32 and the PWM signal generated by the PWM signal generation unit 32.

[0053] It should be noted that the functions of the current detection unit 27, the energization pattern generation unit 35, and the current detection timing adjustment unit 34 are implemented by the CPU (Central Processing Unit) operating a program stored in a storage device (not shown) in a readable manner. For example, these functions are implemented by the cooperation of hardware and software in a microcomputer including a CPU.

[0054] Next, use Figure 2 The carrier generation unit 37 and the PWM signal generation unit 32 will be described in detail.

[0055] The carrier generation unit 37 includes an up-down counter 12 , a comparator 13 , a comparator 14 , and a flip-flop 15 .

[0056] since Figure 1 The clock pulse, count start signal, and count initial value signal outputted from the clock pulse generating section 36 are inputted into the up-down counter 12 .

[0057] After receiving the count start signal, the up-down counter 12 starts counting the clock pulses, and outputs a triangular wave carrier, namely, carrier C, through cumulative addition operation (adding 1 for each input clock pulse) or cumulative subtraction operation (subtracting 1 for each input clock pulse) of the count value.

[0058] In addition, an initial value of the count is set in the up-down counter 12, and the initial value is set by the above-mentioned count initial value signal.

[0059] The comparator 13 compares the count value of the up-down counter 12 with a predetermined upper limit value, and outputs a detection signal INT1 when detecting that the count value reaches the upper limit value.

[0060] The comparator 14 compares the count value of the up-down counter 12 with a predetermined lower limit value, and outputs a detection signal INT2 when detecting that the count value reaches the lower limit value.

[0061] The flip-flop 15 outputs a low-level “L” signal to the up-down counter 12 through the output from the comparator 13 , and outputs a high-level “H” signal to the up-down counter 12 through the output from the comparator 14 .

[0062] The up-down counter 12 performs cumulative addition operation on the count value of the clock pulse after the "H" signal is input from the trigger 15, and performs cumulative subtraction operation on the count value of the clock pulse after the "L" signal is input. Therefore, the "H" signal from the trigger 15 is an addition operation instruction for cumulative addition operation, and the "L" signal is a subtraction operation instruction for cumulative subtraction operation.

[0063] An initial command value signal is given to the flip-flop 15. Whether the initial state of the flip-flop 15 is "H" or "L" is set by the initial command value signal.

[0064] The detection output of the comparator 13, that is, the signal detecting that the count value has reached the upper limit value, is given to the flip-flop 15 as described above, and is output as the detection signal INT1.

[0065] The detection output of the comparator 14 of each phase, that is, the signal detecting that the count value has reached the lower limit value, is given to the trigger 15 as described above and is output as the detection signal INT2. As described later, these interrupt signals become valley interrupt signals in the valley of the triangular wave carrier of each phase.

[0066] The PWM signal generating unit 32 includes three comparators 16 , 17 , and 18 , a PWM circuit 108 , and an interrupt controller 109 .

[0067] The comparator 16 compares the duty cycle Udu of the U phase with the carrier C, and outputs the comparison result as a pulse. Specifically, the comparator 16 compares the value of the duty cycle Udu with the amplitude of the carrier C, and outputs an "H" signal in a range where the amplitude of the carrier C is greater than the duty cycle Udu, and outputs an "L" signal in a range where the amplitude of the carrier C is less than the duty cycle Udu.

[0068] The comparator 17 compares the duty cycle Vdu of the V phase with the carrier C, and outputs the comparison result as a pulse. Specifically, the comparator 17 compares the value of the duty cycle Vdu with the amplitude of the carrier C, and outputs an "H" signal in a section where the amplitude of the carrier C is greater than the duty cycle Vdu, and outputs an "L" signal in a section where the amplitude of the carrier C is less than the duty cycle Vdu.

[0069] The comparator 18 compares the duty cycle Wdu of the W phase with the carrier C, and outputs the comparison result as a pulse. Specifically, the comparator 18 compares the value of the duty cycle Wdu with the amplitude of the carrier C, and outputs an "H" signal in a section where the amplitude of the carrier C is greater than the duty cycle Wdu, and outputs an "L" signal in a section where the amplitude of the carrier C is less than the duty cycle Wdu.

[0070] The PWM circuit 108 outputs six PWM signals having on-off intervals corresponding to the changes in the voltage commands of each phase based on the outputs from the comparators 16, 17, and 18. The six PWM signals include a PWM signal for driving the switch element of the upper bridge arm of the U phase, a PWM signal for driving the switch element of the lower bridge arm of the U phase, a PWM signal for driving the switch element of the upper bridge arm of the V phase, a PWM signal for driving the switch element of the lower bridge arm of the V phase, a PWM signal for driving the switch element of the upper bridge arm of the W phase, and a PWM signal for driving the switch element of the lower bridge arm of the W phase. The six PWM signals are given to the gates of the switch elements of the inverter 23. Under the action of the six PWM signals, the on-off actions of the switch elements are performed. As a result, the voltages of the U phase, the V phase, and the W phase are output from the inverter 23 and applied to the motor 4. It should be noted that, as for the specific power supply method, although the triangle wave comparison method is used in Implementation 1, it is not limited to the triangle wave comparison method, and other methods such as the space vector method can be used to output the voltage of each phase.

[0071] In addition, the PWM circuit 108 generates an interrupt signal at the timing of the rise of the PWM signal, for example, and inputs it to the interrupt controller 109. The interrupt controller 109 receives the interrupt signal from the PWM circuit 108 and gives an A / D conversion instruction to the current detection unit 27. As a result, the current detection unit 27 performs A / D conversion of the detection signal Sd at the timing of the interrupt signal generation.

[0072] Next, use Figure 2 as well as Figure 3 , the principle of generating a triangular wave carrier of each phase is explained. Figure 3 This is a diagram for explaining the principle of generating a triangular wave carrier of each phase. Figure 3 The waveform of carrier C is shown in FIG.

[0073] exist Figure 2 In the embodiment, after the count start signal is input to the up-down counter 12, the up-down counter 12 starts counting the clock pulses from the clock pulse generating unit 36. As described above, an initial value is set in the up-down counter 12, and the initial value is set to 0, for example. Therefore, the up-down counter 12 starts counting from 0. In addition, the output of the trigger 15 that instructs the up-down counter 12 to perform cumulative addition and cumulative subtraction operations is set to "H" in the initial state. The initial state is the output state of the trigger 15 at the moment when the initial instruction value signal is given. Therefore, if the up-down counter 12 starts counting, the cumulative addition operation of the count value is performed. As a result of the above, if Figure 3 As shown, the output of the up-down counter 12 increases with time from the lower limit value (initial value), that is, 0, toward the upper limit value T as indicated by arrow a1.

[0074] And, if the count value reaches the upper limit value T, the comparator 13 detects it and gives the detection signal INT1 to the trigger 15. The trigger 15 is inverted based on the signal, thereby outputting "L". Therefore, the operation of the up-down counter 12 is changed from cumulative addition operation to cumulative subtraction operation, such as Figure 3 As shown, the output decreases with time from the upper limit value T toward the lower limit value 0 as shown by arrow b1.

[0075] And, if the count value reaches the lower limit value 0, the comparator 14 detects it and gives the detection signal INT2 to the trigger 15. The trigger 15 is inverted based on the signal, and outputs "H". Therefore, the action of the up-down counter 12 is changed to cumulative addition operation again, and its output increases from the lower limit value 0 to the upper limit value T as shown by the arrow c1.

[0076] By repeating such cumulative addition and cumulative subtraction operations, the output of the self-up / down counter 12 is Figure 3 The carrier C of the triangle wave shown.

[0077] It should be noted that, in Embodiment 1, although the carrier C is generated from the valley (lower limit), the carrier C may also be generated from the mountain (upper limit). In this case, the initial value of the carrier C is T (upper limit), and the initial command value is "L", which is phase-shifted by 1 / 2 cycle compared to the carrier generated from the valley.

[0078] It should be noted that, in the first embodiment, the carrier wave C is output as a triangular wave, but it may be output as a sawtooth wave or the like using an output comparator.

[0079] Figure 4 The diagram shows waveforms of a plurality of PWM signals U, V, and W, a waveform of a carrier wave C per cycle of these PWM signals, and waveforms of duty ratios Udu, Vdu, and Wdu of each phase.

[0080] like Figure 4 As shown, a plurality of PWM signals U to W are generated in such a manner that the high level and the low level are inverted at the timing consistent with the carrier C at the duty ratios Udu, Vdu, and Wdu of each phase.

[0081] The PWM signal U is a PWM signal for driving the two switching elements of the upper and lower bridge arms constituting the U phase. Figure 4 In the figure, the PWM signal U is expressed as "U-phase PWM signal (U)". When the PWM signal U is at a low level, the switch element of the lower bridge arm of the U phase is turned on (the switch element of the upper bridge arm of the U phase is turned off), and when the PWM signal U is at a high level, the switch element of the lower bridge arm of the U phase is turned off (the switch element of the upper bridge arm of the U phase is turned on). In response to the change in the level of the PWM signal U, the two switch elements constituting the upper and lower bridge arms of the U phase are turned on and off complementarily.

[0082] The PWM signal V is a PWM signal for driving the two switching elements of the upper and lower bridge arms constituting the V phase. Figure 4 In the figure, the PWM signal V is expressed as "V-phase PWM signal (V)". When the PWM signal V is at a low level, the switch element of the lower bridge arm of the V phase is turned on (the switch element of the upper bridge arm of the V phase is turned off), and when the PWM signal V is at a high level, the switch element of the lower bridge arm of the V phase is turned off (the switch element of the upper bridge arm of the V phase is turned on). In response to the change in the level of the PWM signal V, the two switch elements constituting the upper and lower bridge arms of the V phase are turned on and off complementarily.

[0083] The PWM signal W is a PWM signal for driving the two switching elements of the upper and lower bridge arms constituting the W phase. Figure 4 In the figure, the PWM signal W is expressed as "W-phase PWM signal (W)". When the PWM signal W is at a low level, the switch element of the lower bridge arm of the W phase is turned on (the switch element of the upper bridge arm of the W phase is turned off), and when the PWM signal W is at a high level, the switch element of the lower bridge arm of the W phase is turned off (the switch element of the upper bridge arm of the W phase is turned on). With respect to the change in the level of the PWM signal W, the two switch elements constituting the upper and lower bridge arms of the W phase are turned on and off complementarily.

[0084] It should be noted that the timing of the multiple PWM signals U~W changing from low level to high level is slightly later than the timing when the duty ratios Udu, Vdu, and Wdu of each phase are consistent with the carrier C. This is because a dead time is required to prevent short circuits between the upper and lower bridge arms. Figure 4 In the description, the dead time is omitted for convenience of explanation. Hereinafter, when the plurality of PWM signals U to W are not distinguished from each other, they are sometimes referred to as "PWM signals".

[0085] like Figure 4 As shown, in one cycle Tpwm of each of the plurality of PWM signals U to W, the change points (t1 to t6) of each of the plurality of PWM signals U to W are defined as follows.

[0086] The change point t1 is the timing when the lower bridge arm of the W phase changes from being connected to being disconnected (the timing when the upper bridge arm of the W phase changes from being disconnected to being connected). The change point t2 is the timing when the lower bridge arm of the V phase changes from being connected to being disconnected (the timing when the upper bridge arm of the V phase changes from being disconnected to being connected). The change point t3 is the timing when the lower bridge arm of the U phase changes from being connected to being disconnected (the timing when the upper bridge arm of the U phase changes from being disconnected to being connected). The change point t4 is the timing when the lower bridge arm of the U phase changes from being disconnected to being connected (the timing when the upper bridge arm of the U phase changes from being connected to being disconnected). The change point t5 is the timing when the lower bridge arm of the V phase changes from being disconnected to being connected (the timing when the upper bridge arm of the V phase changes from being connected to being disconnected). The change point t6 is the timing when the lower bridge arm of the W phase changes from being disconnected to being connected (the timing when the upper bridge arm of the W phase changes from being connected to being disconnected).

[0087] In the present embodiment, the period from t4 to t5 is defined as the first current detection timing Tm1 and the period from t5 to t6 is defined as the second current detection timing Tm2, ​​but the periods of the first current detection timing Tm1 and the second current detection timing Tm2 are not limited thereto.

[0088] When the inverter 23 is outputting PWM modulated three-phase AC, the current detection unit 27 can detect the current of a specific phase according to the power-on pattern of the switch elements 25U+, 25V+, and 25W+ on the upper bridge arm side. Alternatively, when the inverter 23 is outputting PWM modulated three-phase AC, the current detection unit 27 can detect the current of a specific phase according to the power-on pattern of the switch elements 25U-, 25V-, and 25W on the lower bridge arm side.

[0089] For example Figure 4As shown, during the power-on time T21, the voltage value of the voltage generated at both ends of the current detector 24 corresponds to the current value of the positive phase current Iu+. The power-on time T21 is the time from t4 to t5. The power-on time T21 corresponds to the period of the state in which the switch element of the lower bridge arm of the U phase is turned on, the switch element of the lower bridge arm of the V phase is turned off, and the switch element of the lower bridge arm of the W phase is turned off. Therefore, the current detection unit 27 can detect the current value of the positive phase current Iu+ by obtaining the detection signal Sd at the first current detection timing Tm1 during the power-on time T21.

[0090] The current detection timing adjustment unit 34 sets the first current detection timing Tm1 when a predetermined delay time td has elapsed since one phase of the PWM signal transitions to a logic level different from the other two phases (for example, the timing when the PWM signal of the U phase transitions from a high level that is the same as the V phase and the W phase to a low level that is different from the V phase and the W phase: t4). At this time, the current detection timing adjustment unit 34 sets the first current detection timing Tm1 within the energization time T21.

[0091] The delay time td is expressed by the following equation (4): Tdead is the dead time. Tring is the time required for the damped oscillation generated when the PWM signal changes to converge (damped oscillation convergence time).

[0092] td=Tdead+Tring…(4)

[0093] In addition, for example Figure 4 As shown, during the power-on time T22, the voltage value of the voltage generated at both ends of the current detector 24 corresponds to the current value of the negative phase current Iw-. The power-on time T22 is the time from t5 to t6. The power-on time T22 corresponds to the period when the switch element of the lower bridge arm of the U phase is turned on, the switch element of the lower bridge arm of the V phase is turned on, and the switch element of the lower bridge arm of the W phase is turned off. Therefore, the current detection unit 27 can detect the current value of the negative phase current Iw- by acquiring the detection signal Sd at the second current detection timing Tm2 within the power-on time T22.

[0094] The current detection timing adjustment unit 34 sets the second current detection timing Tm2 when a predetermined delay time td has elapsed since one phase of the PWM signal transitions to a logic level different from the other two phases (for example, the timing at which the PWM signal of the V phase transitions from a high level that is the same as the W phase to a low level that is the same as the U phase, so that the W phase is at a logic level different from the U phase and the V phase: t5). At this time, the current detection timing adjustment unit 34 sets the second current detection timing Tm2 within the energization time T22.

[0095] Similarly, the current detection unit 27 can also detect the current values ​​of other phase currents.

[0096] In this way, if the phase currents of two phases among the phase currents Iu, Iv, and Iw are detected and stored in sequence according to the energization pattern of the PWM signal including the three phases, the currents of the three phases can be detected in time division. Since the sum of the phase currents of the three phases is zero, the current detection unit 27 can detect the phase current of the remaining one phase as long as it can detect the phase currents of two phases among the three phases in the case of three-phase modulation.

[0097] Here, when the magnitude relationship of the duty ratios Udu, Vdu, and Wdu changes, the on-duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal change. A specific example of the case where the magnitude relationship of the duty ratios Udu, Vdu, and Wdu changes will be described later. The first PWM signal is, for example, a PWM signal for driving the lower bridge arm switching element of the U phase. The second PWM signal is, for example, a PWM signal for driving the lower bridge arm switching element of the V phase. The third PWM signal is, for example, a PWM signal for driving the lower bridge arm switching element of the W phase.

[0098] The motor control device 100-1 of the first embodiment is characterized in that, even when the magnitude relationship of the duty ratios Udu, Vdu, and Wdu changes, the pulse phase is adjusted in such a way that the arrangement order of the time series of the timings of the respective changes of the first PWM signal, the second PWM signal, and the third PWM signal does not change. The "timings of the respective changes of the first PWM signal, the second PWM signal, and the third PWM signal" is, for example, Figure 4 The timing of the level change of the U-phase PWM signal (for example, t4), Figure 4 The timing of the level change of the V-phase PWM signal (for example, t5), Figure 4 The pulse phase adjustment is to shift the phases of the first PWM signal, the second PWM signal, and the third PWM signal. Specifically, the pulse phase adjustment is to shift the phases of the first PWM signal, the second PWM signal, and the third PWM signal. Figure 4 The timing of the level change of the U-phase PWM signal (for example, t4), Figure 4 The timing of the level change of the V-phase PWM signal (e.g., t5), and Figure 4 The timing (e.g., t6) of the level change of the W-phase PWM signal shown in FIG. Figure 5 to Figure 7 A specific example of the pulse phase adjustment operation will be described.

[0099] Figure 5 This is the first diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention. Figure 6 This is a second diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention. Figure 7This is the third diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention. Figure 8 This is a fourth diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0100] Figure 5 The duty cycle Udu is shown as a higher value than the duty cycle Vdu. Figure 6 The duty cycle Udu shown is a value lower than the duty cycle Vdu. In this way, when the magnitude relationship between the duty cycle Udu and the duty cycle Vdu changes, it can be known that Figure 6 The timing of the change of the U-phase PWM signal and the V-phase PWM signal is shown in FIG. Figure 5 The timing of the change of the U-phase PWM signal and the V-phase PWM signal is different. Figure 5 In the example, at the change point t4, the PWM signal of the U phase changes, and at the change point t5, the PWM signal of the V phase changes. Figure 6 In the figure, at the changing point t4, the PWM signal of the V phase changes, and at the changing point t5, the PWM signal of the U phase changes.

[0101] Even in this case, since the energization time T21 and the energization time T22 are ensured, the current detection timing adjustment unit 34 sets the first current detection timing Tm1 in the energization time T21 and sets the second current detection timing Tm2 in the energization time T22. Therefore, even when the magnitude relationship between the duty ratio Udu and the duty ratio Vdu changes, current detection is possible.

[0102] However, if Figure 7 As shown in FIG. 1 , the detected current is distorted as the power-on mode changes. This is because the timing of the changes in the multiple PWM signals and the time series arrangement order change. Specifically, Figure 5 In the example, the order of level changes of multiple PWM signals is U, V, W. In contrast, in Figure 6 In the embodiment, since the magnitude relationship of the duty ratios Udu and Vdu is reversed, the order of level changes of the multiple PWM signals is V, U, and W.

[0103] If the timing (phase) of the change of the multiple PWM signals changes, the current flowing through the DC bus (positive bus 22a, negative bus 22b) is distorted accordingly, and becomes a waveform with a large noise superimposed. The distortion of the current becomes the cause of noise, and sometimes gives the user a sense of discomfort depending on the device connected to the motor 4.

[0104] In order to suppress the occurrence of such current distortion, the motor control device 100-1 of this embodiment performs pulse phase adjustment so that even when the magnitude relationship between the duty ratios Udu and Vdu changes, the timing and time series arrangement order of the respective changes of multiple PWM signals are fixed to one arrangement order.

[0105] exist Figure 8 In FIG. 1 , the pulse phase adjustment is performed for multiple PWM signals. Figure 8 In the example, the timing (phase) of the change of the U-phase PWM signal is shifted to the forward side. In addition, the timing (phase) of the change of the V-phase PWM signal is shifted to the delayed side. Moreover, the time width from the phase of the shifted U-phase PWM signal to the phase of the V-phase PWM signal is set to a width that can obtain the detection signal Sd at the first current detection timing Tm1.

[0106] Next, the operation of the motor control device 100 - 1 will be described. Fig. 9 is a flowchart showing the operation of the motor control device 100-1. In this embodiment, at each timing of the phase ta at the bottom of the carrier C, a Fig. 9 PWM counter interrupt processing is shown.

[0107] In step S10, the PWM signal generating unit 32 performs a pulse phase adjustment process. The pulse phase adjustment process will be described in detail later.

[0108] In step S11, the current detection unit 27 detects the phase currents Iu, Iv, and Iw of the U, V, and W phases. The current detection unit 27 obtains the current detection interrupt processing of the detection signal Sd (for example, the interrupt processing of performing AD conversion on the detection signal Sd) and Fig. 9 The treatments shown are separated (see Figure 8 , 9 ), is executed twice within one cycle Tpwm of carrier C.

[0109] Fig.10 1 is a flowchart showing an example of the first current detection process. If the count value of the carrier counter matches the value corresponding to the time when the delay time td has passed since t4, the current detection timing adjustment unit 34 sets (asserts) the setting register of the first current detection timing Tm1. If the setting register of the first current detection timing Tm1 is set, the current detection unit 27 obtains the detection signal Sd through the AD converter (step S41), and stores the obtained value of the detection signal Sd in the first acquisition register.

[0110] Fig.111 is a flowchart showing an example of the second current detection process. If the count value of the up-down counter 12 matches the value corresponding to the time when the delay time td has passed since t5, the current detection timing adjustment unit 34 sets the setting register of the second current detection timing Tm2. If the setting register of the second current detection timing Tm2 is set, the current detection unit 27 obtains the detection signal Sd through the AD converter (step S51), and stores the obtained value of the detection signal Sd in the second acquisition register.

[0111] The current detection unit 27 detects the three-phase currents Iu, Iv, and Iw based on the set values ​​of the detection signal Sd stored in the first acquisition register and the second acquisition register.

[0112] The vector control unit 30 performs current control such as PI control based on the current calculation values ​​of the three-phase currents Iu, Iv, and Iw detected by the current detection unit 27 (step S13), and calculates the phase voltage commands Vu*, Vv*, and Vw* (control amounts) of each phase (step S14).

[0113] In step S15, the duty ratio setting unit 31 sets the duty ratio of each phase based on the phase voltage commands Vu*, Vv*, and Vw* of each phase calculated in step S14. In step S16, the PWM signal generating unit 32 determines which of the plurality of energizing modes is used to control the energization of the inverter 23 based on the duty ratio of each phase set by the duty ratio setting unit 31.

[0114] Next, the operation of the pulse phase adjustment process will be described. Fig.12 1 is a first flowchart for explaining the operation of the pulse phase adjustment process. It is assumed that the following plurality of pulse conditions are given to the PWM signal generation unit 32 .

[0115] The pulse phase conditions shown below are conditions for detecting the change timing of the pulse related to the detection in the order of UVW. When the pulse change timing related to the detection is detected in the order of VUW, for example, the phase is replaced without change in the case of this order, and the phase is replaced with a moving phase in other cases.

[0116] The first pulse phase condition is when the carrier counter is counting down, and the configuration of each PWM signal U, V, W has the relationship of U→V→W in sequence from the advancing side of the phase.

[0117] The second pulse phase condition is when the carrier counter is counting down, and the configuration of each PWM signal U, V, W has the relationship of U→W→V in sequence from the forward side of the phase.

[0118] The third pulse phase condition is when the carrier counter is counting down, and the configuration of each PWM signal U, V, and W has a relationship of V→U→W in sequence from the advancing side of the phase.

[0119] The fourth pulse phase condition is when the carrier counter is counting down, and the configuration of each PWM signal U, V, and W has a relationship of V→W→U in sequence from the advancing side of the phase.

[0120] The fifth pulse phase condition is when the carrier counter is counting down, and the configuration of each PWM signal U, V, W has the relationship of W→U→V in sequence from the advancing side of the phase.

[0121] The sixth pulse phase condition is when the carrier counter is counting down, and the configuration of each PWM signal U, V, W has the relationship of W→V→U in sequence from the advancing side of the phase.

[0122] In step S100 , the PWM signal generating unit 32 determines whether or not the first pulse phase condition is satisfied.

[0123] When the first pulse phase condition is satisfied (step S100, Yes), the count value of the up-down counter 12 changes the timing of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal in the order of U, V, and W when counting down. Therefore, the PWM signal generating unit 32 does not change the phases of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal (step S110), and performs the process of ensuring the current detection interval (power-on time T21, T22) in step S111, and then performs Fig. 9 The process of step S11.

[0124] When the first pulse phase condition is not satisfied (step S100, No), the process of step S101 is executed. In step S101, the PWM signal generating unit 32 determines whether the second pulse phase condition is satisfied.

[0125] When the second pulse phase condition is satisfied (step S101, Yes), the count value of the up-down counter 12 changes the timing of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal in the order of U, W, and V. Therefore, the PWM signal generating unit 32 changes the phases of the W-phase PWM signal and the V-phase PWM signal (step S120), and performs the process of ensuring the current detection interval (power-on time T21, T22) in step S121, and then performs Fig. 9 In step S120, for example, the timing (phase) of the change of the PWM signal of the W phase is shifted to the delay side. In addition, the timing (phase) of the change of the PWM signal of the V phase is shifted to the advance side.

[0126] When the second pulse phase condition is not satisfied (step S101, No), the process of step S102 is executed. In step S102, the PWM signal generating unit 32 determines whether the third pulse phase condition is satisfied.

[0127] When the third pulse phase condition is satisfied (step S102, Yes), the timing of the change of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal during the count down of the up-down counter 12 is V, U, and W. Therefore, the PWM signal generating unit 32 changes the phase of the V-phase PWM signal and the U-phase PWM signal (step S130), performs the process of ensuring the current detection interval (power-on time T21, T22) in step S131, and then performs the process of step S11. In step S130, for example, the timing (phase) of the change of the V-phase PWM signal is shifted to the delay side. In addition, the timing (phase) of the change of the U-phase PWM signal is shifted to the advance side.

[0128] When the third pulse phase condition is not satisfied (step S102, No), the process of step S103 is executed. In step S103, the PWM signal generating unit 32 determines whether the fourth pulse phase condition is satisfied.

[0129] When the fourth pulse phase condition is satisfied (step S103, Yes), the timing of the change of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal when the count value of the up-down counter 12 is counted down is the order of the V-phase PWM signal, the W-phase PWM signal, and the U-phase PWM signal. Therefore, the PWM signal generating unit 32 changes the phases of the V-phase PWM signal, the W-phase PWM signal, and the U-phase PWM signal (step S140), and performs the process of ensuring the current detection interval (power-on time T21, T22) in step S141, and then performs Fig. 9 In step S140, for example, the timing (phase) of the PWM signal change of the V phase is shifted to the delay side. In addition, the timing (phase) of the PWM signal change of the W phase is shifted to the delay side. In addition, the timing (phase) of the PWM signal change of the U phase is shifted to the advance side.

[0130] When the fourth pulse phase condition is not satisfied (step S103, No), the process of step S104 is executed. In step S104, the PWM signal generating unit 32 determines whether the fifth pulse phase condition is satisfied.

[0131] When the fifth pulse phase condition is satisfied (step S104, Yes), the count value of the up-down counter 12 changes the timing of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal in the order of W, U, and V. Therefore, the PWM signal generating unit 32 changes the phase of each PWM signal (step S150), and performs the process of ensuring the current detection interval (power-on time T21, T22) in step S151, and then performs Fig. 9 In step S150, for example, the timing (phase) of the change of the PWM signal of the W phase is shifted to the delay side. In addition, the timing (phase) of the change of the PWM signal of the U phase is shifted to the advance side. In addition, the timing (phase) of the change of the PWM signal of the V phase is shifted to the advance side.

[0132] If the fifth pulse phase condition is not satisfied (step S104, No), the process of step S160 is executed. The remaining pulse phase condition is the sixth pulse phase condition, or two or more phases in each phase have the same pulse change timing, and the count value of the up-down counter 12 changes the timing of the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal in the order of W, V, and U during the count down. Therefore, the PWM signal generating unit 32 changes the phase of each PWM signal (step S160), and the process of ensuring the current detection interval (power-on time T21, T22) is performed in step S161, and then, the process of Fig. 9 In step S160, for example, the timing (phase) of the PWM signal change of the W phase is shifted to the delay side. In addition, the timing (phase) of the PWM signal change of the V phase is shifted to the delay side. In addition, the timing (phase) of the PWM signal change of the U phase is shifted to the advance side, etc., so that the detection sequence becomes the order of U, V, W.

[0133] It should be noted that the PWM signal generating unit 32 of the present embodiment uses a common carrier C in each phase to generate the PWM signal of each phase. That is, the present embodiment is not a method of generating carriers C corresponding to each phase. Moreover, in the present embodiment, since a left-right symmetrical triangle wave centered on phase tb is set as carrier C, the circuit configuration for generating the waveform of the PWM signal of each phase can be simplified. For the up-down counter 12, the counting is down until the phase ta, the counting is up from the phase ta to the phase tb, and the counting is down from the phase tb. In this way, the counting up period and the counting down period are repeated.

[0134] It should be noted that, in this embodiment, an example is given of a case where the first PWM signal is a U-phase PWM signal, the second PWM signal is a V-phase PWM signal, and the third PWM signal is a W-phase PWM signal, but the types of the first PWM signal, the second PWM signal, and the third PWM signal are not limited to this.

[0135] In addition, in the present embodiment, an operation example is described for the case where the first to sixth pulse phase conditions are satisfied when the count value of the up-down counter 12 is a down count, but the PWM signal generating unit 32 can be configured to determine whether the first to sixth pulse phase conditions are satisfied when the count value of the up-down counter 12 is an up count.

[0136] As described above, the motor control device 100-1 of embodiment 1 includes: an inverter, which drives the motor based on the first PWM signal, the second PWM signal and the third PWM signal; a current detection unit, which detects the phase current flowing through each phase of the motor by obtaining the above-mentioned detection signal; a duty ratio setting unit, which sets the duty ratio of the first PWM signal, the second PWM signal and the third PWM signal based on the detection value of the phase current of each phase; and a PWM signal generating unit, which generates the above-mentioned first PWM signal, the second PWM signal and the third PWM signal by comparing the setting value of the above-mentioned duty ratio with the level of the carrier whose level is periodically increased or decreased. A first PWM signal, a second PWM signal and a third PWM signal, wherein the PWM signal generating unit is configured as follows: when the setting value changes, the arrangement order of the time series of the timing changes of the first PWM signal, the second PWM signal and the third PWM signal after the setting value changes is adjusted to the same arrangement order as the arrangement order of the time series of the timing changes of the first PWM signal, the second PWM signal and the third PWM signal before the setting value changes, and the first power-on time (for example, T21) and the second power-on time (for example, T22) within the half cycle of the carrier are ensured.

[0137] With this configuration, the timing of the phase of the PWM signal does not change, and the current flowing through the DC bus (positive bus 22a, negative bus 22b) does not distort. Therefore, the noise that causes the noise is not superimposed on the current, and the generation of noise can be suppressed. In addition, since the current does not distort, higher harmonics can be suppressed, the power factor can be kept high, and the power loss when the motor 4 is driven can be reduced.

[0138] With the above configuration, even when the set value of the duty ratio changes, two current detection phases are always fixed, so that noise that causes noise is not superimposed on the current.

[0139] However, since the conduction rate becomes higher in the high modulation rate region, it may be difficult for the current detection unit 27 to detect the phase current of the two phases. That is, if the conduction rate becomes higher, the ratio of the high level period to the off level period of the PWM signal of each phase becomes larger, so that even if the conduction time of one of the two conduction times (for example, the first conduction time and the second conduction time) that the current detection unit 27 can detect the conduction width of the phase current can be ensured, the conduction time of the other cannot be ensured. Therefore, when the two current detection phases are always fixed, the upper limit of the PWM modulation rate is, for example, about 30%, which cannot be applied to the full modulation rate region, and the voltage utilization rate becomes low.

[0140] Hereinafter, a configuration example will be described in which two energization times are ensured even in a high modulation rate region while suppressing noise that causes noise.

[0141] Fig.13 This is the first diagram showing waveforms of a plurality of PWM signals and a waveform of a carrier wave C per cycle of these PWM signals when the energization rate is high. Fig.14 The second diagram shows the waveforms of a plurality of PWM signals and the waveform of the carrier C per cycle of these PWM signals when the energization rate is high. Fig.15 The third diagram shows the waveforms of a plurality of PWM signals and the waveform of the carrier C per cycle of these PWM signals when the energization rate is high.

[0142] exist Fig.13 In FIG. 1 , the zero vector intervals of the waveforms of multiple PWM signals when the power-on rate is high are shown. The zero vector interval is equivalent to the period when the level of each PWM signal of the U-phase to the W-phase is high, or is equivalent to the period when the level of each PWM signal of the U-phase to the W-phase is low. Fig.13 In FIG. 1 , the period during which the level of each PWM signal of the U-phase to the W-phase is at a high level is exemplified as a zero vector period.

[0143] like Fig.13 As shown in FIG. 1 , when the power-on rate is high, the high level period of each of the plurality of PWM signals is wider than the low level period. Fig.13 As shown, in the interval where the level of the U-phase PWM signal is low, the level of the V-phase PWM signal is high, and the level of the W-phase PWM signal is high, the current detection unit 27 can set the power-on time Tm1 (for example, 4us) in which the current detection unit 27 can detect the power-on width of the phase current.

[0144] However, in Fig.13In the PWM signals of the U-phase to W-phase, since the high-level period is long, the period from the moment when the PWM signal of the V-phase changes from the high level to the low level to the moment when the PWM signal of the U-phase changes from the low level to the high level is short. Therefore, it is sometimes difficult to set the interval in which the level of the PWM signal of the U-phase is low, the level of the PWM signal of the V-phase is low, and the level of the PWM signal of the W-phase is high, that is, to set the power-on time Tm2.

[0145] When the conduction rate becomes high and it is difficult to set the conduction time Tm2 as described above, the PWM signal generation unit 32 of the present embodiment extracts a part of the zero vector interval and allocates the conduction width corresponding to the extracted zero vector interval to the interval outside the zero vector interval (the conduction time during which it is difficult for the current detection unit 27 to detect the conduction width of the two-phase phase current). As a result, the conduction time during which it is difficult to detect the conduction width of the phase current is adjusted to the conduction time Tm2 during which the current detection unit 27 can detect the conduction width of the two-phase phase current.

[0146] like Fig.14 As shown in FIG. 1 , a portion of the zero vector interval (high level period) is extracted, and the interval inversion corresponding to the extracted interval is allocated to the low interval of each phase. As a result, for example, the timing of the PWM signal of each phase U to W changing from high level to low level is shifted to the leading side. As a result, Fig.15 As shown in FIG. 1 , since the low level period of the U-phase PWM signal is extended, the first power-on time and the second power-on time can be set. It should be noted that in the present embodiment, the period during which all phases are at a high level is the period during which all phases are inverted to a low level, but the present invention is not limited thereto, and the power-on time can be adjusted by inverting all phases to a high level during the period during which all phases are at a low level.

[0147] Fig.15 The first power-on time is, for example, the period from when the U-phase PWM signal changes from a high level to a low level until when the V-phase PWM signal changes from a high level to a low level. The second power-on time is, for example, the period from when the V-phase PWM signal changes from a high level to a low level until when the W-phase PWM signal changes from a high level to a low level.

[0148] FIG. 16 is a second flowchart for explaining the operation of the pulse phase adjustment process.

[0149] In step S210, the PWM signal generating unit 32 determines whether the first pulse phase condition is satisfied. The first pulse phase condition is when the count value of the up-down counter 12 is a down count and the duty ratios Udu, Vdu, and Wdu have a relationship of Udu>Vdu>Wdu>.

[0150] When the first pulse phase condition is satisfied (step S210, Yes), the PWM signal generating unit 32 determines whether one of the first energizing time and the second energizing time is a energizing width that is difficult to detect the phase current by the current detecting unit 27 (step S211). This determination is made, for example, by comparing the first energizing time and the delay time td, or by comparing the second energizing time and the delay time td, and when one of the first energizing time and the second energizing time is longer than the delay time td, the first energizing time and the second energizing time are determined to be energizing times of a energizing width that is possible to detect the phase current by the current detecting unit 27.

[0151] When one of the first energization time and the second energization time is shorter than the delay time td, it is determined that one of the first energization time and the second energization time is a energization time of a energization width that makes detection of the phase current by the current detection unit 27 difficult.

[0152] When the PWM signal generating unit 32 determines that the first energizing time and the second energizing time are energizing times of a detectable energizing width based on the phase current of the current detecting unit 27 (step S211, No), it does not extract and allocate the zero vector interval (step S212).

[0153] When the PWM signal generating unit 32 determines that one of the first power-on time and the second power-on time is a power-on time of a power-on width that makes detection of the phase current by the current detecting unit 27 difficult (step S211, Yes), the zero vector interval is extracted and allocated without changing the arrangement order of the time series of the PWM signals of each phase (step S213).

[0154] Through the processing of step S213, even when the modulation rate of the voltage command for generating the respective PWM signals of the U-phase to W-phases satisfying the first pulse phase condition is high, the energization time of the energization width that can be detected based on the phase current of the current detection unit 27 can be set at two locations.

[0155] When the first pulse phase condition is not satisfied (step S210 , No), the PWM signal generating unit 32 performs the process of step S220 .

[0156] In step S220, the PWM signal generating unit 32 determines whether the second pulse phase condition is satisfied. The second pulse phase condition is when the count value of the up-down counter 12 is a down count and the duty ratios Udu, Vdu, and Wdu have a relationship of Udu>Wdu>Vdu>.

[0157] When the second pulse phase condition is satisfied (step S220, Yes), the PWM signal generating unit 32 determines whether one of the first energizing time and the second energizing time is a energizing width that makes it difficult to detect the phase current by the current detecting unit 27 (step S221). This determination is performed in the same manner as the process of step S211.

[0158] When the PWM signal generating unit 32 determines that the first energizing time and the second energizing time are energizing times of a detectable energizing width based on the phase current of the current detecting unit 27 (step S221, No), it does not extract and allocate the zero vector interval (step S222).

[0159] When the PWM signal generating unit 32 determines that one of the first power-on time and the second power-on time is a power-on time of a power-on width that makes detection of the phase current by the current detecting unit 27 difficult (step S221, Yes), the zero vector interval is extracted and allocated without changing the arrangement order of the time series of the PWM signals of each phase (step S223).

[0160] Through the processing of step S223, even when the modulation rate of the voltage command for generating the PWM signals of each of the U-phase to W-phase satisfying the second pulse phase condition is high, the energization time of the energization width that can be detected based on the phase current of the current detection unit 27 can be set at two locations.

[0161] When the second pulse phase condition is not satisfied (step S220 , No), the PWM signal generating unit 32 performs the process of step S230 .

[0162] In step S230, the PWM signal generating unit 32 determines whether the third pulse phase condition is satisfied. The third pulse phase condition is when the count value of the up-down counter 12 is a down count and the duty ratios Udu, Vdu, and Wdu have a relationship of Vdu>Udu>Wdu>.

[0163] When the third pulse phase condition is satisfied (step S230, Yes), the PWM signal generating unit 32 determines whether one of the first energizing time and the second energizing time is a energizing width that makes it difficult to detect the phase current by the current detecting unit 27 (step S231). This determination is performed in the same manner as the process of step S211.

[0164] When the PWM signal generating unit 32 determines that the first energizing time and the second energizing time are energizing times of a energizing width detectable based on the phase current of the current detecting unit 27 (step S231, No), it does not extract and allocate the zero vector interval (step S232).

[0165] When the PWM signal generating unit 32 determines that one of the first power-on time and the second power-on time is a power-on time of a power-on width that is difficult to detect based on the phase current of the current detecting unit 27 (step S231, Yes), the zero vector interval is extracted and allocated without changing the arrangement order of the time series of the PWM signals of each phase (step S233).

[0166] Through the processing of step S233, even when the modulation rate of the voltage command for generating the PWM signals of each of the U-phase to W-phase satisfying the third pulse phase condition is high, the energization time of the energization width that can be detected based on the phase current of the current detection unit 27 can be set at two locations.

[0167] When the third pulse phase condition is not satisfied (step S230 , No), the PWM signal generating unit 32 performs the process of step S240 .

[0168] In step S240, the PWM signal generating unit 32 determines whether the fourth pulse phase condition is satisfied. The fourth pulse phase condition is when the count value of the up-down counter 12 is a down count and the duty ratios Udu, Vdu, and Wdu have a relationship of Vdu>Wdu>Udu>.

[0169] When the fourth pulse phase condition is satisfied (step S240, Yes), the PWM signal generating unit 32 determines whether one of the first energizing time and the second energizing time is a energizing width that makes it difficult to detect the phase current by the current detecting unit 27 (step S241). This determination is performed in the same manner as the process of step S211.

[0170] When the PWM signal generating unit 32 determines that the first energizing time and the second energizing time are energizing times of a detectable energizing width based on the phase current of the current detecting unit 27 (step S241, No), it does not extract and allocate the zero vector interval (step S242).

[0171] When the PWM signal generating unit 32 determines that one of the first power-on time and the second power-on time is a power-on time of a power-on width that is difficult to detect based on the phase current of the current detecting unit 27 (step S241, Yes), the zero vector interval is extracted and allocated without changing the arrangement order of the time series of the PWM signals of each phase (step S243).

[0172] Through the processing of step S243, even when the modulation rate of the voltage command for generating the respective PWM signals of the U-phase to W-phase satisfying the fourth pulse phase condition is high, the conduction time of two places based on the conduction width that can be detected by the current detection unit 27 can be set.

[0173] When the fourth pulse phase condition is not satisfied (step S240 , No), the PWM signal generating unit 32 performs the process of step S250 .

[0174] In step S250, the PWM signal generating unit 32 determines whether the fifth pulse phase condition is satisfied. The fifth pulse phase condition is when the count value of the up-down counter 12 is a down count and the duty ratios Udu, Vdu, and Wdu have a relationship of Wdu>Udu>Vdu>.

[0175] When the fifth pulse phase condition is satisfied (step S250, Yes), the PWM signal generating unit 32 determines whether one of the first energizing time and the second energizing time is a energizing width that makes it difficult to detect the phase current by the current detecting unit 27 (step S251). This determination is performed in the same manner as the process of step S211.

[0176] When the PWM signal generating unit 32 determines that the first energizing time and the second energizing time are energizing times of a energizing width that can be detected based on the phase current of the current detecting unit 27 (step S251, No), it does not extract and allocate the zero vector interval (step S252).

[0177] When the PWM signal generating unit 32 determines that one of the first power-on time and the second power-on time is a power-on time of a power-on width that makes detection of the phase current by the current detecting unit 27 difficult (step S251, Yes), the zero vector interval is extracted and allocated without changing the arrangement order of the time series of the PWM signals of each phase (step S253).

[0178] Through the processing of step S253, even when the modulation rate of the voltage command for generating the respective PWM signals of the U-phase to W-phase satisfying the fifth pulse phase condition is high, the energization time of the energization width that can be detected based on the phase current of the current detection unit 27 can be set at two locations.

[0179] When the fifth pulse phase condition is not satisfied (step S250 , No), the PWM signal generating unit 32 performs the process of step S261 .

[0180] Since the remaining pulse phase condition is the sixth pulse phase condition, in step S261, the PWM signal generating unit 32 determines whether one of the first energizing time and the second energizing time is a energizing width that is difficult to detect the phase current based on the current detecting unit 27 in the sixth pulse phase condition. The sixth pulse phase condition is when the count value of the up-down counter 12 is a down count, and the duty ratios Udu, Vdu, and Wdu have a relationship of Wdu>Vdu>Udu>. This determination is performed in the same manner as the processing of step S211.

[0181] When the PWM signal generating unit 32 determines that the first energizing time and the second energizing time are energizing times of a detectable energizing width based on the phase current of the current detecting unit 27 (step S261, No), it does not extract and allocate the zero vector interval (step S262).

[0182] When the PWM signal generating unit 32 determines that one of the first power-on time and the second power-on time is a power-on time of a power-on width that makes detection of the phase current by the current detecting unit 27 difficult (step S261, Yes), the zero vector interval is extracted and allocated without changing the arrangement order of the time series of the PWM signals of each phase (step S263).

[0183] Through the processing of step S263, even when the modulation rate of the voltage command for generating the respective PWM signals of the U-phase to W-phase satisfying the sixth pulse phase condition is high, the energization time of the energization width that can be detected based on the phase current of the current detection unit 27 can be set at two locations.

[0184] As described above, the PWM signal generating unit of the motor control device 100-1 of the present embodiment is configured as follows: when there is a first energization time in which the current detection unit 27 can detect the energization width of the phase current of at least one phase among the phases of the motor, and a second energization time in which it is difficult for the current detection unit 27 to detect the energization width of the phase current of a phase different from the phase detected in the first energization time (for example, two phases), a part of the zero vector interval of each of the first PWM signal, the second PWM signal, and the third PWM signal is extracted, and the energization width corresponding to the extracted zero vector interval is allocated to the interval outside the zero vector interval of each of the first PWM signal, the second PWM signal, and the third PWM signal, thereby adjusting the second energization time to a energization width in which the current detection unit 27 can detect the phase current of the phase different from the phase detected in the first energization time.

[0185] According to this configuration, even in the high modulation region, two energization times of energization widths that allow detection of the phase current by the current detection unit 27 can be set.

[0186] The motor control device, the motor system, and the motor control method are described above by using the embodiments, but the present invention is not limited to the above embodiments. Various modifications and improvements such as combination and replacement with part or all of other embodiments are possible within the scope of the present invention.

[0187] This international application claims the benefit of priority based on Japanese Patent Application No. 2019-057290 filed on March 25, 2019, and the entire contents of Japanese Patent Application No. 2019-057290 are cited in this international application.

[0188] Description of Reference Numerals

[0189] 1-1 Motor system, 4 Motor, 12 Up / down counter, 13 Comparator, 14 Comparator, 15 Flip-flop, 16 Comparator, 17 Comparator, 18 Comparator, 21 DC power supply, 22a Positive bus, 22b Negative bus, 23 Inverter, 24 Current detector, 25U Switching element, 25V Switching element, 25W Switching element, 27 Current detection unit, 30 Vector control unit, 31 Duty ratio setting unit, 32 PWM signal generation unit, 33 Drive circuit, 34 Current detection timing adjustment unit, 35 Power-on pattern generation unit, 36 Clock pulse generation unit, 37 Carrier generation unit, 100-1 Motor control device, 108 PWM circuit, 109 Interrupt controller

Claims

1. A motor control device, comprising: an inverter unit, which drives the motor based on the first PWM signal, the second PWM signal and the third PWM signal; A current detection unit for detecting a phase current flowing through each phase of the motor; a duty ratio setting unit, which sets the duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal based on the detected values ​​of the phase currents of the phases; and a PWM signal generating unit, which is used to generate the first PWM signal, the second PWM signal and the third PWM signal, In the case where there is a first conduction time during which the current detection unit can detect the conduction width of the phase current flowing through at least one phase of the phases of the motor, and a second conduction time during which it is difficult for the current detection unit to detect the conduction width of the phase current of a phase different from the phase detected in the first conduction time, The PWM signal generating unit extracts a part of each zero vector interval of the first PWM signal, the second PWM signal, and the third PWM signal, and allocates a conduction width corresponding to the extracted zero vector interval to intervals other than the zero vector intervals of the first PWM signal, the second PWM signal, and the third PWM signal, thereby adjusting the second conduction time to a conduction width that enables the current detecting unit to detect a phase current of a phase different from the phase detected in the first conduction time, When the setting value set by the duty ratio setting unit changes, The PWM signal generating unit adjusts the arrangement order of the time series of the timing changes of the first PWM signal, the second PWM signal and the third PWM signal after the setting value changes to the same arrangement order as the arrangement order of the time series of the timing changes of the first PWM signal, the second PWM signal and the third PWM signal before the setting value changes, and ensures the first power-on time and the second power-on time within a half-cycle of the carrier whose level increases and decreases periodically.

2. A motor system, comprising: The motor control device according to claim 1; and The above motor.

3. A motor control method, which is performed in a motor control device for controlling a motor, the motor control method comprising: an output step of outputting a detection signal corresponding to a current value of a current flowing through a DC side of an inverter unit that drives the motor based on the first PWM signal, the second PWM signal, and the third PWM signal, using a current detector; A detection step, which detects the phase current flowing through each phase of the above-mentioned motor; A setting step, which sets the duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal based on the detected values ​​of the phase currents of the phases; A generating step, which generates the first PWM signal, the second PWM signal and the third PWM signal; and an adjustment step of extracting a portion of a zero vector interval in each of the first PWM signal, the second PWM signal, and the third PWM signal, and allocating the conduction width corresponding to the extracted zero vector interval to an interval other than the zero vector interval of each of the first PWM signal, the second PWM signal, and the third PWM signal, when there is a first conduction time in which a current detection unit for detecting a phase current flowing through each phase of the motor can detect a conduction width of a phase current flowing through at least one phase of each phase of the motor, and a second conduction time in which it is difficult for the current detection unit to detect a conduction width of a phase current of a phase different from the phase detected in the first conduction time; Thereby, the second power-on time is adjusted to a power-on width in which the current detection unit can detect a phase current of a phase different from the phase detected in the first power-on time, and when the set value set by the setting step changes, the arrangement order of the timing series of the changes of the first PWM signal, the second PWM signal and the third PWM signal after the set value changes is adjusted to the same arrangement order as the arrangement order of the timing series of the changes of the first PWM signal, the second PWM signal and the third PWM signal before the set value changes, and ensure that the first power-on time and the second power-on time are within a half-cycle of the carrier whose level is periodically increased or decreased.

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