Circuit arrangement of semiconductor switches

Abstract

The invention discloses a circuit arrangement (1) of a semiconductor switch (T1), comprising a gate (G), a collector (C) or a drain and an emitter (E) or a source, wherein the circuit arrangement (1) comprises a capacitor (C1) between the gate (G) and the collector (C) or the drain, wherein a parallel circuit consisting of a resistor (R3) and a diode (V2) is arranged in series with the capacitor (C1).

Description

Technical Field

[0001] The invention discloses a circuit arrangement of a semiconductor switch. Background Art

[0002] Voltage switching edges (du / dt) occur in switches of semiconductors, such as IGBTs, MOSFETs, etc. These voltage switching edges usually extend nonlinearly, so that on the one hand a maximum voltage gradient (du / dt_max) and on the other hand an average voltage gradient (e.g. 10%-90% values) must be taken into account for IGBT tuning (gate resistance tuning).

[0003] For certain applications, the maximum voltage gradient in the power semiconductor must be limited, since excessively high voltage edges cause problems with regard to electromagnetic compatibility (EMC) and, in the case of power electronic switches, can lead to possible damage to the machine connected to the winding.

[0004] In simple control circuits, for example, control circuits with only a gate resistor, the gate resistor is adapted to adjust the maximum voltage gradient. If the maximum voltage gradient is limited by the gate resistor, the average voltage gradient also becomes flat. The flat switching behavior leads to increased switching losses in the semiconductor switch, which has a negative effect on the service life of the semiconductor switch and the converter in the same cooling system.

[0005] The aim is to reduce the maximum value of the voltage gradient during switching without affecting the average voltage gradient, i.e. to linearize the switching edges.

[0006] 1 , it is known to arrange a capacitor C1 between collector C and gate G. Voltage edges in the load circuit induce a displacement current via capacitor C1 which returns to gate G and thereby charges or discharges the gate so that it cancels the switching edge (negative feedback).

[0007] As a result, the voltage edge can be set in a controlled manner approximately to a certain value.

[0008] 1 is used to form two independent gate resistors Rg_on (Rg1 parallel to Rg2) and Rg_off (=Rg1). The decoupling of the gate resistors also affects the diodes in the opposite current direction.

[0009] However, switching on and switching off are influenced in the same way by the additional capacitor C1. In certain semiconductors (e.g. newer IGBTs), the optimized capacitance values ​​for switching on lead to a slowing down of the switching process, which must be compensated by a smaller gate resistor. This results in the same switching edges during switching off in most cases, but does not bring about any improvement in losses and leads to a higher switch-off overvoltage.

[0010] This problem has been solved until now only with complex and expensive driver circuits (eg, driver circuits with regulated current sources). In simple gate driver circuits, the matching between switching on and switching off is disabled. In this case, an optimized setting cannot be achieved. Summary of the invention

[0011] The object of the present invention is to specify an improved circuit arrangement for a semiconductor switch.

[0012] According to the invention, this object is achieved by a circuit arrangement having the features described in the invention.

[0013] Advantageous embodiments of the invention are the subject matter of the dependent claims.

[0014] According to a first aspect of the invention, a circuit arrangement of a semiconductor switch is proposed, comprising a gate, a collector or a drain and an emitter or a source, wherein the circuit arrangement comprises a capacitor between the gate and the collector or the drain, wherein a parallel circuit consisting of a resistor and a diode is arranged in series with the capacitor.

[0015] In one embodiment, the diode is connected in the direction of the current flow away from the gate. Thus, only the switch-on behavior of the semiconductor switch is influenced and / or improved.

[0016] In one embodiment, the diode is connected in the direction of the current flow towards the gate. Thus, only the turn-off behavior of the semiconductor switch is influenced and / or improved.

[0017] In one embodiment, the diode is connected in the direction of the current flow away from the gate, wherein the arrangement consisting of a capacitor, a resistor and a diode is connected in parallel with a further arrangement consisting of a further capacitor, a further resistor and a further diode, wherein a parallel circuit consisting of a further resistor and a further diode is arranged in series with the further capacitor, wherein the further diode is located in the immediate direction of the current flow toward the gate. Thus, the switch-on behavior and the switch-off behavior of the semiconductor switch are influenced and / or improved (independently of one another).

[0018] In one embodiment, an additional capacitor is connected in parallel with the resistor and the diode.

[0019] According to a second aspect of the invention, a circuit arrangement of a semiconductor switch is proposed, comprising a gate, a collector or a drain and an emitter or a source, wherein the circuit arrangement comprises a capacitor between the gate and the collector or the drain, wherein a circuit is arranged in parallel with the capacitor, in which circuit a diode is connected in series with a parallel circuit consisting of a resistor and a further capacitor.

[0020] In this case, the diode can be connected in the direction of current flow away from the gate or towards the gate.

[0021] In one embodiment, a gate resistor arrangement is provided, which includes a first gate resistor connected to the gate and connected in parallel to a series circuit consisting of a second gate resistor and a gate diode, wherein the gate diode is connected such that it allows a current to flow to the gate.

[0022] In one embodiment, a discharge resistor is connected in parallel with the capacitor or the diode.

[0023] In one embodiment, the semiconductor switch is designed as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0024] The advantage of the present invention is that the semiconductor switch is better utilized by:

[0025] Decoupling of switch-on and switch-off behavior and separate adaptation of maximum and average switching edges.

[0026] This results in:

[0027] - Lower cut-off overvoltage of power semiconductors

[0028] - Smaller switching losses

[0029] - Improved electromagnetic compatibility (EMC)

[0030] - Due to the lower power losses of the power semiconductors, a more compact design of the converter is possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above-mentioned characteristics, features and advantages of the present invention and the manner and method of implementation are clearly and understandably explained in conjunction with the following detailed description of the embodiments in connection with the accompanying drawings. It is shown here:

[0032] FIG. 1 is a circuit arrangement of a semiconductor switch known in the prior art,

[0033] Figure 2 is a first embodiment of a circuit arrangement of a semiconductor switch,

[0034] Figure 3is a second embodiment of the circuit arrangement of the semiconductor switch,

[0035] Figure 4 is a third embodiment of the circuit arrangement of the semiconductor switch,

[0036] Figure 5 is a fourth embodiment of the circuit arrangement of the semiconductor switch,

[0037] Figure 6 is a fifth embodiment of the circuit arrangement of the semiconductor switch,

[0038] Figure 7 is a sixth embodiment of the circuit arrangement of the semiconductor switch,

[0039] Figure 8 This is a seventh embodiment of the circuit arrangement of semiconductor switches.

[0040] In all the figures, corresponding parts are provided with the same reference symbols. DETAILED DESCRIPTION

[0041] 1 shows a circuit arrangement 1 of a semiconductor switch T1 known from the prior art. The semiconductor switch T1 is, for example, a field effect transistor, in particular a MOSFET or an IGBT, and has a gate G, a collector C and an emitter E. A capacitor C1 is arranged between the collector C and the gate G. This forms a gate circuit arrangement consisting of a first gate resistor Rg1, a second gate resistor Rg2 and a gate diode V1, which, as explained above in the introduction, symbolizes a gate resistor.

[0042] Figure 2 A first specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0043] The semiconductor switch T1 is, for example, a field effect transistor, in particular a MOSFET or an IGBT, and has a gate G, a collector C and an emitter E. A capacitor C1 is arranged between the collector C and the gate G. This forms a gate circuit arrangement consisting of a first gate resistor Rg1, a second gate resistor Rg2 and a gate diode V1, which, as described above in the introduction, symbolizes a gate resistor. However, in contrast to FIG. 1 , a parallel circuit consisting of a resistor R3 and a diode V2 is arranged in series with the capacitor C1 between the collector C and the gate G, wherein the diode V2 is connected in the direction of the current flowing away from the gate G.

[0044] By adding diode V2, the capacitor C1 can decouple the switching interference from each other. Figure 2 The specific embodiments shown merely influence and / or improve the switch-on behavior.

[0045] The resistor R3 serves to discharge the capacitor C1 when operation in the reverse direction of the diode is not possible via the diode V2 .

[0046] The positioning of the diode V2 determines whether the circuit arrangement 1 is functional when the semiconductor switch T1 is switched on or off.

[0047] Figure 3 A second specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0048] Similar to wiring arrangement 1 Figure 2 The circuit arrangement 1 shown here differs, however, in that the diode V2 is connected in the direction of the current flow towards the gate G.

[0049] By adding diode V2, the capacitor C1 decouples the switching interference from each other. Figure 3 The embodiments shown merely influence and / or improve the switch-off behavior.

[0050] The resistor R3 serves to discharge the capacitor C1 when operation in the reverse direction of the diode is not possible via the diode V2 .

[0051] Figure 4 A third specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0052] Circuit arrangement 1 combines the Figure 2 and Figure 3 The wiring arrangement 1 is shown in FIG.

[0053] Between the collector C and the gate G, a parallel circuit consisting of a resistor R3 and a diode V2 is arranged in series with the capacitor C1, wherein the diode V2 is connected in the direction of the current flowing away from the gate G. The arrangement consisting of the capacitor C1, the resistor R3 and the diode V2 is connected in parallel with a further arrangement consisting of a further capacitor C2, a further resistor R4 and a further diode V3, wherein the further capacitor C2 is, for example, arranged in close proximity to the collector C and in series with the further capacitor C2, wherein the further diode V3 is connected in the direction of the current flowing toward the gate G.

[0054] use Figure 4 The specific embodiments shown influence and / or improve the switching-on behavior and the switching-off behavior separately from one another.

[0055] Figure 5 A fourth specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0056] Similar to wiring arrangement 1 Figure 3The circuit arrangement 1 shown differs in that an additional capacitor C2 is connected in parallel with the resistor R3 and the diode V2.

[0057] Figure 6 A fifth specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0058] Similar to wiring arrangement 1 Figure 2 The circuit arrangement 1 shown differs in that an additional capacitor C2 is connected in parallel with the resistor R3 and the diode V2.

[0059] Figure 7 A sixth specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0060] The circuit arrangement 1 is similar to the circuit arrangement 1 shown in FIG1 . However, it differs in that a circuit is provided in parallel with the capacitor C1 , wherein a diode V2 is connected in series with the parallel circuit consisting of the resistor R3 and the further capacitor C2 . The diode V2 is connected in the current direction toward the gate G in this case.

[0061] Figure 8 A seventh specific embodiment of a circuit arrangement 1 of a semiconductor switch T1 is shown.

[0062] The circuit arrangement 1 is similar to the circuit arrangement 1 shown in FIG1 . However, it differs in that a circuit is provided in parallel with the capacitor C1 , wherein a diode V2 is connected in series with the parallel circuit consisting of the resistor R3 and the further capacitor C2 . In this case, the diode V2 is connected in the direction of the current flowing away from the gate G.

[0063] In one embodiment, the resistor R3 is connected in parallel with the additional capacitor C2 or the diode V2.

[0064] Although the present invention has been illustrated and described in detail through preferred embodiments, the present invention is not limited to the disclosed examples, and other variants can be derived by those skilled in the art without departing from the scope of protection of the present invention.

Claims

1. A circuit arrangement (1) of a semiconductor switch (T1), comprising a gate (G), a collector (C) or a drain and an emitter (E) or a source, wherein: The circuit arrangement (1) comprises a capacitor (C1) between a gate (G) and a collector (C) or a drain, wherein a parallel circuit consisting of a resistor (R3) and a diode (V2) is arranged in series with the capacitor (C1), wherein the diode (V2) is connected in the direction of current flow away from the gate (G), wherein the arrangement consisting of the capacitor (C1), the resistor (R3) and the diode (V2) is connected in parallel with a further arrangement consisting of a further capacitor (C2), a further resistor (R4) and a further diode (V3), wherein a parallel circuit consisting of the further resistor (R4) and the further diode (V3) is arranged in series with the further capacitor (C2) and wherein the further diode (V3) is connected in the direction of current flow toward the gate (G).

2. The circuit arrangement (1) according to claim 1, wherein: A gate resistor circuit arrangement is provided, the gate resistor circuit arrangement comprising a first gate resistor (Rg1) connected at the gate (G), the first gate resistor being connected in parallel with a series circuit consisting of a second gate resistor (Rg2) and a gate diode (V1), wherein the gate diode (V1) is connected in a current direction toward the gate (G).

3. The wiring arrangement (1) according to any one of the preceding claims, wherein: The semiconductor switch (T1) is designed as an IGBT or a MOSFET.

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