Solid-state imaging device

Abstract

The present invention relates to a solid-state imaging device. The solid-state imaging device includes a first substrate, the first substrate includes: four pixels, the four pixels are connected to a floating diffusion portion; and a first part of a differential input circuit, which is shared by the four pixels; a second substrate, stacked on the first substrate, wherein the second substrate includes: a second part of the differential input circuit, which is connected to the first part of the differential input circuit; a feedback circuit, the feedback circuit is connected to the second part of the differential input circuit; and a data storage unit, which is connected to the feedback circuit, and wherein the differential input circuit operates at a first power supply voltage, the feedback circuit operates at a second power supply voltage, and the second power supply voltage is lower than the first power supply voltage.

Description

[0001] This application is a divisional application of a patent application with an application date of August 8, 2017, an invention name of "Comparator, AD converter, solid-state imaging device, electronic device and comparator control method", and an application number of 201780046031.2. Technical Field

[0002] The present invention relates to a comparator, an AD converter, a solid-state imaging device, an electronic device and a control method for a comparator, and more particularly, to a comparator, an AD converter, a solid-state imaging device, an electronic device and a control method for a comparator, which can respectively reduce power consumption while enhancing the determination speed of the comparator. Background Art

[0003] In the case of performing AD conversion in a limited area such as a pixel by, for example, a signal readout system utilizing a solid-state imaging device, the best area efficiency system is an integration type (ramp type) AD conversion system including a comparator and a digital circuit in a subsequent stage of the comparator.

[0004] Non-patent document 1 is proposed as a technology that attempts to realize AD conversion in a limited area by using an integral AD conversion system. For example, the system of non-patent document 1 adopts a circuit structure in which the digital circuit in the rear stage is a DRAM circuit, and the ramp signal is input to the comparator multiple times. For example, in the case of 8-bit AD conversion, the same ramp signal is repeatedly input to the comparator eight times. Then, the operation of storing a code of 0 or 1 at the time point when the output from the comparator is reversed in the DRAM and the operation of outputting the code of interest are repeated eight times. At the time point when the comparison is ended relative to the entire surface, the code of interest is read out to the outside.

[0005] Reference List

[0006] Non-patent literature

[0007] Non-patent document 1: D. Yang, B. Fowler, and A. El Gamal, "A Nyquist rate pixel level ADC for CMOS image sensors," in Proc. IEEE 1998 Custom Integrated circuits Conf., Santa Clara, CA, May 1998, pp. 237-240. Summary of the invention

[0008] Technical issues

[0009] In the case where the AD converter is arranged in the pixel, unlike the case where there is a relative degree of freedom, there is a limitation in the circuit accommodation area in the area such as the column parallel arrangement of the AD converter for each pixel column. Therefore, it is difficult to manufacture a comparator that fully meets the requirements. For example, in some cases, when trying to enhance the performance, the judgment speed of the comparison is reduced, or the power consumption is increased.

[0010] The present invention has been made in view of such circumstances, and can reduce power consumption while enhancing the determination speed of the comparator.

[0011] Technical solutions to the problem

[0012] A comparator according to one aspect of the present invention comprises:

[0013] a differential input circuit that operates at a first power supply voltage and outputs a signal when a voltage of an input signal is higher than a voltage of a reference signal;

[0014] a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and accelerates a switching speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit; and

[0015] a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage,

[0016] Wherein, the source voltage of the differential input circuit is a voltage lower than 0V.

[0017] In the first aspect of the present invention, a differential input circuit operates at a first power supply voltage and outputs a signal when the voltage of an input signal is higher than the voltage of a reference signal. A positive feedback circuit operates at a second power supply voltage lower than the first power supply voltage and speeds up a conversion speed when a comparison result signal representing a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit. A voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage. In this case, a source voltage of the differential input circuit is a voltage lower than 0V.

[0018] The AD converter of the second aspect of the present invention includes a comparator and a data storage unit. The comparator includes: a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal; a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and speeds up the conversion speed when the comparison result signal representing the voltage comparison result between the input signal and the reference signal is inverted based on the output signal from the differential input circuit; and a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage, wherein the source voltage of the differential input circuit is a voltage lower than 0V. The data storage unit stores a time code when the comparison result signal is inverted.

[0019] In a second aspect of the present invention, a differential input circuit operates at a first power supply voltage and outputs a signal when the voltage of an input signal is higher than the voltage of a reference signal. A positive feedback circuit operates at a second power supply voltage lower than the first power supply voltage and speeds up a conversion speed when a comparison result signal representing a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit. A voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage. In addition, a source voltage of the differential input circuit is a voltage lower than 0V. A data storage unit stores a time code when the comparison result signal is inverted.

[0020] A solid-state imaging device according to a third aspect of the present invention includes an AD converter and a pixel circuit. The AD converter includes a comparator and a data storage unit. The comparator includes: a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of an input signal is higher than the voltage of a reference signal; a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and speeds up the conversion speed when a comparison result signal representing a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit; and a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage, wherein the source voltage of the differential input circuit is a voltage lower than 0V. The data storage unit stores a time code when the comparison result signal is inverted. The pixel circuit outputs a charge signal generated by receiving light incident to a pixel and then performing photoelectric conversion on the light as the input signal to the differential input circuit.

[0021] An electronic device according to a fourth aspect of the present invention includes a solid-state imaging device including an AD converter and a pixel circuit. The AD converter includes a comparator and a data storage unit. The comparator includes: a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of an input signal is higher than the voltage of a reference signal; a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and speeds up the conversion speed when a comparison result signal representing a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit; and a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage, wherein the source voltage of the differential input circuit is a voltage lower than 0V. The data storage unit stores a time code when the comparison result signal is inverted. The pixel circuit outputs a charge signal generated by receiving light incident to a pixel and then performing photoelectric conversion on the light as the input signal to the differential input circuit.

[0022] In each of the third and fourth aspects of the present invention, the differential input circuit operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal. The positive feedback circuit operates at a second power supply voltage lower than the first power supply voltage and accelerates the conversion speed when the comparison result signal representing the voltage comparison result between the input signal and the reference signal is inverted based on the output signal from the differential input circuit. The voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage. The source voltage of the differential input circuit is a voltage lower than 0V. The data storage unit stores a time code when the comparison result signal is inverted. In the pixel circuit, a charge signal generated by receiving and photoelectrically converting light incident on a pixel is output as an input signal to the differential input circuit.

[0023] A comparator control method according to a fifth aspect of the present invention, the comparator comprising: a differential input circuit, the differential input circuit operating at a first power supply voltage; a positive feedback circuit, the positive feedback circuit operating at a second power supply voltage lower than the first power supply voltage; and a voltage conversion circuit, the source voltage of the differential input circuit being lower than 0V, the method comprising:

[0024] When the voltage of the input signal is higher than the voltage of the reference signal, the differential input circuit outputs a signal;

[0025] The voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage; and

[0026] The positive feedback circuit speeds up a conversion speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on the output signal from the differential input circuit obtained by conversion in the voltage conversion circuit.

[0027] In a fifth aspect of the present invention, a comparator includes: a differential input circuit, the differential input circuit operates at a first power supply voltage; a positive feedback circuit, the positive feedback circuit operates at a second power supply voltage lower than the first power supply voltage; and a voltage conversion circuit, the source voltage of the differential input circuit is configured to be lower than 0V. In the differential input circuit, a signal is output when the voltage of the input signal is higher than the voltage of the reference signal. In the voltage conversion circuit, an output signal from the differential input circuit is converted into a signal corresponding to the second power supply voltage. In the positive feedback circuit, a conversion speed is accelerated when a comparison result signal representing a voltage comparison result between the input signal and the reference signal is inverted based on the output signal from the differential input circuit obtained by conversion in the voltage conversion circuit.

[0028] The comparator, the AD converter, the solid-state imaging device, the electronic device, and the control method of the comparator may be independent devices, or may be modules included in other devices.

[0029] Advantageous Effects of the Invention

[0030] According to the first to fifth aspects of the present invention, it is possible to reduce power consumption while enhancing the determination speed of the comparator.

[0031] It should be noted that the effects described here are not necessarily limited, and any effects described in the present invention can also be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a diagram depicting a schematic configuration of a solid-state imaging device according to the present invention.

[0033] Figure 2 is a block diagram depicting a detailed configuration example of a pixel.

[0034] Figure 3 is a circuit diagram depicting a first configuration of a comparison circuit.

[0035] Figure 4 is a graph showing signal transitions during the operation period of the comparison circuit.

[0036] Figure 5 is a circuit diagram illustrating the detailed structure of a pixel circuit.

[0037] Figure 6 is a timing chart illustrating a first configuration of a comparison circuit and an operation of a pixel.

[0038] Figure 7 is a circuit diagram depicting a second configuration of the comparison circuit.

[0039] Figure 8 is a circuit diagram depicting a third configuration of the comparison circuit.

[0040] Fig. 9 is a circuit diagram depicting a fourth configuration of the comparison circuit.

[0041] Fig.10 is a circuit diagram depicting a fifth configuration of the comparison circuit.

[0042] Fig.11 is a circuit diagram depicting a sixth configuration of a comparison circuit.

[0043] Fig.12 is a timing chart illustrating the sixth configuration of the comparison circuit and the operation of the pixel.

[0044] Fig.13 is a circuit diagram depicting a configuration example of a comparison circuit in the case of pixel sharing.

[0045] Fig.14 This is a conceptual diagram of a solid-state imaging device configured by stacking two semiconductor substrates.

[0046] Fig.15 is a circuit diagram depicting a circuit configuration example in the case where a solid-state imaging device is configured by using two semiconductor substrates.

[0047] Fig.16 : is a circuit diagram depicting an example of a circuit configuration in the case where a solid-state imaging device is configured by stacking three semiconductor substrates.

[0048] Fig.17 : is a circuit diagram depicting a circuit configuration example in the case where a solid-state imaging device is configured by three semiconductor substrates.

[0049] Fig.18 : is a block diagram depicting a configuration example of an image pickup apparatus as an electronic device according to the present invention. DETAILED DESCRIPTION

[0050] Hereinafter, a mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described. It should be noted that the description will be given in the following order.

[0051] 1. Schematic Configuration Example of Solid-State Imaging Device

[0052] 2. Detailed structure example of a pixel

[0053] 3. First Configuration Example of Comparison Circuit

[0054] 4. Second Configuration Example of Comparison Circuit

[0055] 5. Third Configuration Example of Comparison Circuit

[0056] 6. Fourth Configuration Example of Comparison Circuit

[0057] 7. Fifth Configuration Example of Comparison Circuit

[0058] 8. Sixth Configuration Example of Comparison Circuit

[0059] 9. Example of pixel sharing structure

[0060] 10. Construction of multiple substrates 1

[0061] 11. Construction of multiple substrates 2

[0062] 12. Application examples of electronic devices

[0063] <1. Schematic Configuration Example of Solid-State Imaging Device>

[0064] Figure 1 A schematic configuration of a solid-state imaging device according to the present invention is depicted.

[0065] Figure 1 The solid-state imaging device 1 has a pixel array section 22 in which pixels 21 are arranged in a two-dimensional array on a semiconductor substrate 11 using, for example, silicon (Si) as a semiconductor. The pixel array section 22 is also provided with a time code transmission section 23 for transmitting a time code generated in a time code generation section 26 to each pixel 21. Then, a pixel driving circuit 24, a D / A converter (DAC) 25, a time code generation section 26, a vertical driving circuit 27, an output section 28, and a timing generation circuit 29 are formed in the periphery of the pixel array section 22 on the semiconductor substrate 11.

[0066] As will be referred to later Figure 2 As described, each pixel 21 arranged in a two-dimensional array is provided with a pixel circuit 41 and an ADC 42. The pixel 21 generates a charge signal in response to the amount of light received by a light receiving element (eg, a photodiode) within the pixel and converts the charge signal into a digital pixel signal SIG which is in turn output.

[0067] The pixel driving circuit 24 drives the pixel circuit 41 in the pixel 21 ( Figure 2). The DAC 25 generates a reference signal (reference voltage signal) REF as a ramp signal in which the level (voltage) decreases monotonically with time, and the DAC 25 supplies the reference signal REF to each pixel 21. The time code generation section 26 generates a time code used when the analog pixel signal SIG is converted (AD converted) into a digital signal, and supplies the time code to the corresponding time code transmission section 23. A plurality of time code generation sections 26 are provided in the pixel array section 22. The time code transmission sections 23 are provided in the pixel array section 22 in a number corresponding to the number of the time code generation sections 26. In other words, the time code generation section 26 and the time code transmission section 23 that transmits the time code generated in the time code generation section 26 present a one-to-one correspondence.

[0068] The vertical drive circuit 27 performs control in which the digital pixel signals SIG generated in the pixels 21 are output to the output section 28 in a predetermined order based on the timing signals supplied from the timing generation circuit 29. The digital pixel signals SIG output from the pixels 21 are output from the output section 28 to the outside of the solid-state imaging device 1. The output section 28 performs predetermined digital signal processing, such as black level correction processing for correcting the black level or correlated double sampling (CDS) processing, as required, and then outputs the obtained digital pixel signals to the outside.

[0069] The timing generation circuit 29 includes a timing generator and the like that generates various timing signals, and supplies the generated various timing signals to the pixel driving circuit 24 , the DAC 25 , the vertical driving circuit 27 , and the like.

[0070] The solid-state imaging device 1 is configured as described above. Figure 1 As described above, the description has been given in such a manner that all circuits constituting the solid-state imaging device 1 are formed on one semiconductor substrate 11, but as described later, a construction may be adopted in which the circuits constituting the solid-state imaging device 1 are arranged separately from each other on a plurality of semiconductor substrates 11.

[0071] <2. Detailed Structure Example of Pixel>

[0072] Figure 2 is a block diagram depicting a detailed configuration of the pixel 21 .

[0073] The pixel 21 includes a pixel circuit 41 and an AD converter (ADC) 42 .

[0074] The pixel circuit 41 outputs a charge signal responsive to the amount of received light as an analog pixel signal SIG to the ADC 42. The ADC 42 converts the analog pixel signal supplied from the pixel circuit 41 into a digital signal.

[0075] The ADC 42 includes a comparison circuit 51 and a data storage section 52 .

[0076] The comparison circuit 51 compares the pixel signal SIG with the reference signal REF supplied from the DAC 25 and outputs an output signal VCO as a comparison result signal indicating the comparison result. When the reference signal REF and the pixel signal SIG become the same (voltage) as each other, the comparison circuit 51 inverts the output signal VCO.

[0077] Although the comparison circuit 51 includes a differential input circuit 61, a voltage conversion circuit 62, and a positive feedback (PFB) circuit 63, reference will be made later. Figure 3 Describe its details.

[0078] The output signal VCO is input from the comparison circuit 51 to the data storage section 52. In addition, a WR signal indicating an operation of writing a pixel signal, an RD signal indicating an operation of reading a pixel signal, and a WORD signal for controlling the read timing of the pixel 21 in the operation of reading a pixel signal are all supplied from the vertical drive circuit 27 to the data storage section 52. In addition, the time code generated in the time code generation section 26 is also supplied to the data storage section 52 via the time code transmission section 23.

[0079] The data storage section 52 includes a latch control circuit 71 that controls a write operation and a read operation for a time code based on a WR signal and an RD signal, respectively, and a latch storage section 72 that stores the time code.

[0080] In the writing operation of the time code, while the output signal VCO of high (Hi) is input from the comparison circuit 51, the latch control circuit 71 causes the latch storage section 72 to store the time code supplied from the time code transmission section 23 and updated every unit time. Then, when the reference signal REF and the pixel signal SIG become the same (voltage) as each other, and the output signal VCO supplied from the comparison circuit 51 is inverted to low (Lo), the writing (updating) of the supplied time code is stopped, and the latch storage section 72 is caused to maintain the time code most recently stored in the latch storage section 72. The time code stored in the latch storage section 72 represents the moment when the pixel signal SIG and the reference signal REF are equal to each other. Therefore, the time code represents data indicating that the pixel signal SIG is the reference voltage at this time, that is, the digitized value of the light amount.

[0081] After scanning of the reference signal REF ends and the time code is stored in the latch storage section 72 of all the pixels 21 within the pixel array section 22 , the operation of the pixel 21 changes from the write operation to the read operation.

[0082] In the operation of reading out the time code, when the read timing of the pixel 21 itself is obtained, the latch control circuit 71 outputs the time code (digital pixel signal SIG) stored in the latch storage unit 72 to the time code transmission unit 23 based on the WORD signal, wherein the read timing is controlled according to the WORD signal. The time code transmission unit 23 continuously transmits the supplied time code in the column direction (in the vertical direction) and supplies the time code to the output unit 28.

[0083] Hereinafter, in order to distinguish the time code of interest from the time code written to the latch storage unit 72 in the operation of writing the time code, the digitized pixel data will also be referred to as AD converted pixel data, and the digitized pixel data is the inverted time code when the output signal VCO read out from the latch storage unit 72 in the operation of reading out the time code is inverted, and the digitized pixel data indicates that the pixel signal SIG is the reference voltage at this time.

[0084] <3. First Configuration Example of Comparison Circuit>

[0085] Figure 3 2 is a circuit diagram depicting the detailed configuration of the differential input circuit 61 , the voltage conversion circuit 62 , and the positive feedback circuit 63 constituting the comparison circuit 51 .

[0086] The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 41 within the pixel 21 with the reference signal REF output from the DAC 25 , and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF.

[0087] The differential input circuit 61 includes transistors 81 and 82 that function as a differential pair, transistors 83 and 84 that form a current mirror, and a resistor for supplying a bias current V in response to the input. b A transistor 85 for providing a constant current source of the current IB, and a transistor 86 for outputting the output signal HVO from the differential input circuit 61.

[0088] Each of the transistors 81 , 82 , and 85 includes a negative channel MOS (NMOS) transistor, and each of the transistors 83 , 84 , and 86 includes a positive channel MOS (PMOS) transistor.

[0089] The reference signal REF output from the DAC 25 is input to the gate of the transistor 81 of the transistors 81 and 82 used as a differential pair, and the pixel signal SIG output from the pixel circuit 41 within the pixel 21 is input to the gate of the transistor 82. The sources of the transistors 81 and 82 are connected to the drain of the transistor 85, and the source of the transistor 85 is grounded (GND).

[0090] The drain of transistor 81 is connected to the gates of transistors 83 and 84 constituting a current mirror circuit and the drain of transistor 83, and the drain of transistor 82 is connected to the drain of transistor 84 and the gate of transistor 86. Sources of transistors 83, 84 and 86 are connected to a first power supply voltage VDDH.

[0091] The voltage conversion circuit 62 includes, for example, an NMOS transistor 91. The drain of the transistor 91 is connected to the drain of the transistor 86 in the differential input circuit 61, the source of the transistor 91 is connected to a predetermined connection point in the positive feedback circuit 63, and the gate of the transistor 91 is connected to the bias voltage VBIAS.

[0092] The transistors 81 to 86 constituting the differential input circuit 61 are circuits that operate at a high voltage up to the first power supply voltage VDDH, and the positive feedback circuit 63 is a circuit that operates at a second power supply voltage VDDL lower than the first power supply voltage VDDH. Here, the first power supply voltage VDDH is set to 2.9 [V], for example, and the second power supply voltage VDDL is set to 1.1 [V], for example. The voltage conversion circuit 62 converts the output voltage HVO input from the differential input circuit 61 into a low voltage signal (conversion signal) LVI on which the positive feedback circuit 63 can operate, and outputs the obtained signal LVI to the positive feedback circuit 63.

[0093] It is sufficient that the bias voltage VBIAS is a voltage converted to a voltage that does not damage the transistors 101 to 105 in the positive feedback circuit 63 operating at a low voltage. For example, the bias voltage VBIAS can be set to the same voltage as the second power supply voltage VDDL of the positive feedback circuit 63 (VBIAS=VDDL).

[0094] The positive feedback circuit 63 outputs a comparison result signal which is inverted based on the conversion signal LVI when the pixel signal SIG is higher than the reference signal REF, with which the output signal HVO from the differential input circuit 61 is converted into a signal corresponding to the second power supply voltage VDDL. In addition, the positive feedback circuit 63 accelerates the conversion speed when the output signal VCO output as the comparison result signal is inverted.

[0095] The positive feedback circuit 63 includes five transistors 101 to 105. Here, each of the transistors 101, 102, and 104 includes a PMOS transistor, and each of the transistors 103 and 105 includes an NMOS transistor.

[0096] The source of transistor 91 as the output terminal of voltage conversion circuit 62 is connected to the drain of transistors 102 and 103 and the gate of transistors 104 and 105. The sources of transistors 101 and 104 are connected to the second power supply voltage VDDL, the drain of transistor 101 is connected to the source of transistor 102, and the gate of transistor 102 is connected to the drain of transistors 104 and 105 as the output terminal of the positive feedback circuit. The sources of transistors 103 and 105 are connected to GND, respectively. The initialization signal INI2 is supplied to the gate of transistor 101, and the initialization signal INI1 is supplied to the gate of transistor 103.

[0097] The transistors 104 and 105 constitute an inverter circuit, and a connection point between the drains of the transistors 104 and 105 becomes an output terminal from which the comparison circuit 51 outputs the output signal VCO.

[0098] A description will now be given regarding the operation of the comparison circuit 51 configured in the manner described above. Figure 4 represents the transition of each signal during the operation of the comparison circuit 51. It should be noted that Figure 4 In FIG. 8 , “G86” represents the gate potential of transistor 86 .

[0099] First, the voltage of the reference signal REF is set higher than the voltage of the pixel signal SIG of each pixel 21 , and each of the initialization signals INI1 and INI2 is set to Hi, thereby initializing the comparison circuit 51 .

[0100] More specifically, a reference signal REF is applied to the gate of transistor 81, and a pixel signal SIG is applied to the gate of transistor 82. When the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG, the current output from the transistor 85, which becomes a current source, is almost all flowed into the transistor 83 connected by a diode via the transistor 81. The channel resistance of the transistor 84 having a gate common to the transistor 83 becomes low enough so that the gate of the transistor 86 is roughly maintained at the first power supply voltage VDDH level, thereby turning off the transistor 86. Therefore, even if the transistor 91 of the voltage conversion circuit 62 is turned on, the positive feedback circuit 63 as a charging circuit will not charge the conversion signal LVI with electricity. On the other hand, the Hi signal as the initialization signal INI1 and INI2 is supplied, and the transistor 103 is turned on so that the positive feedback circuit 63 discharges the conversion signal LVI. In addition, since the transistor 101 is turned off, the positive feedback circuit 63 does not charge the conversion signal LVI through the transistor 102. As a result, the conversion signal LVI is discharged to the GND level, and the positive feedback circuit 63 outputs the output signal VCO at Hi by using the transistors 104 and 105 constituting an inverter, thereby initializing the comparison circuit 51.

[0101] After initialization, each of the initialization signals INI1 and INI2 is set to Lo, thereby starting to scan the reference signal REF.

[0102] During a period of time when the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG, the transistor 86 is turned off to be cut off, and since the output signal VCO becomes a signal at Hi, the transistor 102 is also turned off to be cut off. The transistor 103 is also turned off because the initialization signal INI1 is set at Lo. The conversion signal LVI maintains GND while maintaining a high impedance state, and thus the output signal VCO at Hi is output.

[0103] When the voltage of the reference signal REF becomes lower than the voltage of the pixel signal SIG, the output current from the transistor 85 as the current source does not flow through the transistor 81. As a result, each gate potential of the transistors 83 and 84 rises, and thus the channel resistance of the transistor 84 becomes high. Then, the current flowing to the transistor 84 through the transistor 82 causes a voltage drop to reduce the gate potential, thereby turning on the transistor 91. The output signal HVO output from the transistor 86 is converted into the conversion signal LVI by the transistor 91 in the voltage conversion circuit 62, and then supplied to the positive feedback circuit 63. The positive feedback circuit 63 as a charging circuit charges the conversion signal LVI with electricity so that the potential approaches the second power supply voltage VDDL from the GND voltage.

[0104] Then, when the voltage of the conversion signal LVI exceeds the threshold voltage of the inverter composed of the transistors 104 and 105, the output signal VCO becomes Lo, and the transistor 102 is turned on. Since the initialization signal INI2 at Lo is applied to the transistor 101, the transistor 101 is also turned on, and the positive feedback circuit 63 quickly charges the conversion signal LVI through the transistors 101 and 102 to immediately increase the potential to the second power supply voltage VDDL.

[0105] Since the bias voltage VBIAS is applied to the gate of the transistor 91 of the voltage conversion circuit 62, if the voltage of the conversion signal LVI reaches a voltage obtained by subtracting the transistor threshold from the bias voltage VBIAS, the transistor 91 of the voltage conversion circuit 62 is turned off. Even if the transistor 86 remains in the on state, the transistor 86 does not further charge the conversion signal LVI, and therefore, the voltage conversion circuit 62 also functions as a voltage clamping circuit.

[0106] The charging of the conversion signal LVI generated by the conduction of the transistor 102 is a positive feedback operation as follows: at the beginning, the voltage of the conversion signal LVI first rises to the threshold of the inverter and accelerates the movement of interest. Since the number of circuits operating in parallel and simultaneously in the solid-state imaging device 1 is huge, the current of each circuit is set to a very small current in the transistor 85 as the current source of the differential input circuit 61. In addition, since the voltage changed in the unit time when the time code is switched is the LSB step of the AD conversion, the reference signal REF is scanned very slowly. Therefore, the change of the gate potential of the transistor 86 is also slow, and the change of the output current of the transistor 86 driven by the gate potential of the transistor 86 is also slow. However, positive feedback is applied from the rear stage to the conversion signal LVI charged by the output current of the transistor 86, so that the output signal VCO can be converted quickly enough. Preferably, the transition time of the output signal VCO is a part of the unit time of the time code, and as a typical example, the transition time is equal to or less than 1ns. The comparison circuit 51 of the present invention can obtain this output transition time only by setting a small current (eg, 0.1 uA) to the transistor 85 of the current source.

[0107] <Detailed Configuration Example of Pixel Circuit>

[0108] Will refer to Figure 5 A description is given of a detailed configuration of the pixel circuit 41 .

[0109] Figure 5 is a diagram that describes adding details of the pixel circuit 41 to Figure 3 2 is a circuit diagram showing the configuration of the comparison circuit 51.

[0110] The pixel circuit 41 includes a photodiode (PD) 121 as a photoelectric conversion element, a discharge transistor 122 , a transfer transistor 123 , a reset transistor 124 , and a floating diffusion layer (FD) 125 .

[0111] The discharge transistor 122 is used to adjust the exposure period. Specifically, if the discharge transistor 122 is turned on when it is desired to start the exposure period at an arbitrary time, the charge accumulated in the photodiode 121 before this is discharged. Therefore, when the discharge transistor 122 is turned off, the exposure period starts.

[0112] The transfer transistor 123 transfers the charge generated in the photodiode 121 to the FD 125. The reset transistor 124 resets the charge held in the FD 125. The FD 125 is connected to the gate of the transistor 82 in the differential input circuit 61. As a result, the transistor 82 also functions as an amplification transistor of the pixel circuit 41.

[0113] The source of the reset transistor 124 is connected to the gate of the transistor 82 in the differential input circuit 61 and the FD 125, and the drain of the reset transistor 124 is connected to the drain of the transistor 82. Therefore, there is no fixed reset voltage for resetting the charge in the FD 125. This is because, by controlling the circuit state of the differential input circuit 61, the reset voltage for resetting the FD 125 can be arbitrarily set by using the reference signal REF.

[0114] <Timing diagram of pixel unit>

[0115] Will refer to Figure 6 The timing diagram gives the Figure 5 A description of the operation of the pixel 21 is shown.

[0116] First, at time t1, the reference signal REF is switched from the standby voltage V stb The reset voltage V is set to reset the charge in the FD 125. rst , to turn on the reset transistor 124, thereby resetting the charge in the FD 125.

[0117] Next, at time t2, the initialization signal INI2 supplied to the gate of the transistor 101 in the positive feedback circuit 63 is set to Hi, and immediately after this setting operation, the initialization signal INI1 supplied to the gate of the transistor 103 is set to Hi, and the positive feedback circuit 63 is set to the initial state.

[0118] In addition, at time t2, the reference signal REF is raised to a predetermined voltage V u , and comparison between the reference signal REF and the pixel signal SIG is started (scanning of the reference signal REF). At this point in time, since the reference signal REF is greater than the pixel signal SIG, the output signal VCO is Hi.

[0119] At time t3 when it is determined that the reference signal REF and the pixel signal SIG become the same voltage, the output signal VCO is inverted (converted to Low). When the output signal VCO is inverted, as described above, the positive feedback circuit 63 accelerates the inversion of the output signal VCO. In addition, in the data storage unit 52, the time data (N-bit DATA[1] to DATA[N]) at the time point when the output signal VCO is inverted is latched and stored.

[0120] At time t4 when the time period for signal writing ends and the time period for signal reading begins, the voltage of the reference signal REF supplied to the gate of the transistor 81 in the comparison circuit 51 is reduced to a level (standby voltage V stb). As a result, the consumption current of the comparison circuit 51 in the period used for signal reading is suppressed.

[0121] At time t5, the WORD signal for controlling the read timing becomes Hi, and the time data (N-bit DATA[1] to DATA[N]) that has been latched and stored is output from the latch control circuit 71 of the data storage section 52. The time data acquired here becomes P-phase data at a reset level at which a correlated double sampling (CDS) process is performed.

[0122] At time t6, the reference signal REF rises to a predetermined voltage V u , and the initialization signal INI2 supplied to the gate of the transistor 101 is set to Hi. Immediately after this setting operation, the initialization signal INI1 supplied to the gate of the transistor 103 is also set to Hi, and thus the positive feedback circuit 63 is set to the initial state again.

[0123] At time t7 , the transfer transistor 123 of the pixel circuit 41 is turned on by the transfer signal TX being Hi, and the charge generated in the photodiode 121 is transferred to the FD 125 .

[0124] After that, after the initialization signal INI1 returns to Low following the transition of the initialization signal INI2 to Low, the comparison between the reference signal REF and the pixel signal SIG (scanning of the reference signal REF) is started. At this point in time, since the reference signal REF is greater than the pixel signal SIG, the output signal VCO is Hi.

[0125] Then, at time t8 when it is determined that the reference signal REF and the pixel signal SIG become the same voltage, the output signal VCO is inverted (converted to Low). When the output signal VCO is inverted, the positive feedback circuit 63 accelerates the inversion of the output signal VCO. In addition, in the data storage unit 52, the time data (N-bit DATA[1] to DATA[N]) at the time point when the output signal VCO is inverted is latched and stored.

[0126] At time t9 when the time period for signal writing ends and the time period for signal reading begins, the voltage of the reference signal REF supplied to the gate of the transistor 81 in the comparison circuit 51 is reduced to a level at which the transistor 81 is turned off (the standby voltage V stb ). As a result, the consumption current of the comparison circuit 51 in the period used for signal reading is suppressed.

[0127] At time t10, the WORD signal for controlling the read timing becomes Hi, and the latched stored time data (N-bit DATA[1] to DATA[N]) is output from the latch control circuit 71 of the data storage unit 52. The acquired time data here becomes D-phase data at the signal level at which CDS processing is performed. At time t11, the state is the same as that at time t1 above, and the next 1-V (one vertical scan period) drive is performed.

[0128] According to the driving of the above-mentioned pixel 21, first, after obtaining the P-phase data at the reset level, the P-phase data at the reset level is read out to the output section 28. Next, the D-phase data at the signal level is acquired and read out to the output section 28. The output section 28 holds the P-phase data in its internal frame memory, and performs CDS processing of the P-phase data in combination with the D-phase data supplied later. It should be noted that any method can be selected as a method for performing CDS processing. For example, the data storage section 52 can hold the P-phase data therein, and can output the P-phase data and the D-phase data simultaneously or alternately, so that the output section 28 can perform CDS processing.

[0129] By performing the above operation, for the pixel 21 in the pixel array section 22 of the solid-state imaging device 1, a global shutter operation for resetting all pixels at the same time and exposing all pixels at the same time can be performed. Since all pixels can be exposed and read out at the same time, there is no need for a holding section, which is usually set in the pixel and is used to hold the charge while reading out the charge. In addition, with the configuration of the pixel 21, there is no need for a selection transistor, etc., which is necessary for a column parallel reading type solid-state imaging device and selects a pixel that outputs a pixel signal SIG.

[0130] Using reference Figure 6 The driving of the pixel 21 described above usually controls the discharge transistor 122 to be turned off. Figure 6 As shown by the dotted line in , after the discharge signal OFG is set to Hi at a desired timing to temporarily turn on the discharge transistor 122, the discharge transistor 122 is turned off so that an arbitrary time period for exposure can also be set.

[0131] <4. Second Configuration Example of Comparison Circuit>

[0132] Figure 7 is a circuit diagram depicting a second configuration of the comparison circuit 51. Incidentally, Figure 7 The detailed circuit of the pixel circuit 41 and the second configuration of the comparison circuit 51 are also described. The same applies to Figures 8 to 11 .

[0133] The second configuration of the comparison circuit 51 is similar to that of the comparison circuit 51 except that two transistors 161 and 162 are added to the positive feedback circuit 63. Figure 5 The first configuration is shown.

[0134] In the second configuration, the inverter circuit of the positive feedback circuit 63 in the first configuration is replaced with a 2-input NOR circuit. A control signal TEST_VCO as a second input (which is not the conversion signal LVI as the first input) is supplied to each of the gate of the transistor 161 including a PMOS transistor and the gate of the transistor 162 including an NMOS transistor.

[0135] The source of the transistor 161 is connected to the second power supply voltage VDDL, and the drain of the transistor 161 is connected to the source of the transistor 104. The drain of the transistor 162 is connected to the output terminal of the comparison circuit 51, and the source of the transistor 162 is connected to GND.

[0136] In the comparison circuit 51 of the second configuration configured as described above, when the control signal TEST_VCO as the second input is set to Hi, the output signal VCO can be set to Lo regardless of the state of the differential input circuit 61 .

[0137] When the bias voltage VBIAS is controlled to be set to the Lo level to turn off the transistor 91 and thus each of the initialization signals INI1 and INI2 is set to Hi, the output signal VCO becomes Hi regardless of the state of the differential input circuit 61. Therefore, the forced Hi output of the output signal VCO and the forced Lo output of the above-mentioned control signal TEST_VCO are combined with each other, so that the output signal VCO can be set to an arbitrary value regardless of the state of the differential input circuit 61 and the states of the pixel circuit 41 and the DAC 25 in the previous stage of the differential input circuit 61. By using this function, for example, the circuit in the subsequent stage of the pixel 21 can be tested only by using the electric signal input without relying on the light input of the solid-state imaging device 1.

[0138] In addition, for example, when the voltage of the pixel signal SIG is lower than the final voltage of the reference signal REF due to exceeding the expected high brightness (for example, the image of the sun imaged within the viewing angle of the solid-state imaging device 1), the comparison time period ends, and the output signal VCO of the comparison circuit 51 remains at Hi. As a result, the data storage section 52 controlled by the output signal VCO may not be able to fix the value, and the AD conversion function is lost. In order to prevent this from happening, the control signal TEST_VCO of the Hi pulse is input to the end of the scan of the reference signal REF, so that the output signal VCO that has not yet been inverted to Lo is forced to be inverted. Since the data storage section 52 latches and stores the time code before the forced inversion, when using Figure 7In the case of the configuration of , the ADC 42 functions as an AD converter that clamps the output value of the luminance input at a certain level or higher.

[0139] <5. Third Configuration Example of Comparison Circuit>

[0140] Figure 8 is a circuit diagram depicting a third configuration of the comparison circuit 51 .

[0141] The third configuration of the comparison circuit 51 is Figure 7 The second configuration shown is different in that, in the differential input circuit 61, the source of the transistor 85 as a constant current source is not connected to GND but to a negative bias voltage VSS lower than 0 [V]. Figure 7 For example, the negative bias voltage VSS is set to -1.8 [V].

[0142] In the third configuration of the comparison circuit 51, the source potential of the transistor 85 is set to a potential lower than 0 V, thereby expanding the operating range of the comparison circuit 51. In addition, the source potential of the follower transistor 85 is set to negative, and the substrate voltage sides of the photodiode 121 and the FD 125 in the pixel circuit 41 are respectively set to the negative bias voltage VSS. As a result, the saturation charge amount of each pixel 21 (pixel circuit 41) can be increased.

[0143] <6. Fourth Configuration Example of Comparison Circuit>

[0144] Fig. 9 is a circuit diagram depicting a fourth configuration of the comparison circuit 51 .

[0145] In the fourth configuration of the comparison circuit 51, Figure 8 The transistors 83, 84 and 86 of the differential input circuit 61 shown are changed to transistors 83', 84' and 86'. The other components are similar to Figure 7 The constituent elements in the second configuration.

[0146] exist Figure 8 In the third configuration shown, the first power supply voltage VDDH is set to, for example, approximately 2.9 [V], and each of the transistors 83 , 84 , and 86 of the differential input circuit 61 includes a high-voltage system transistor having a large film thickness.

[0147] On the contrary, Fig. 9In the fourth configuration, each of the transistors 83', 84' and 86' includes a low voltage system transistor having a small film thickness, and the low voltage system transistor is driven using a low voltage equal to or less than 2V. More specifically, the source potential of the follower transistor 85 is reduced to the negative bias voltage VSS (-1.8 [V]), and the first power supply voltage VDDH of 2.9 [V] is reduced to the first power supply voltage VDDH of 1.1 [V], thereby enabling the transistors 83, 84 and 86 of the differential input circuit 61 to become low voltage system transistors 83', 84' and 86'. The entire potential difference of the comparison circuit 51 is within the range of 2.9 [V] from -1.8 [V] to 1.1 [V], and is no different from each of the first configuration and the second configuration, in which the entire potential difference of the comparison circuit 51 is within the range of 2.9 [V] from 0 [V] to 2.9 [V].

[0148] In the fourth configuration, the high voltage system transistors 83 , 84 , and 86 each having a large film thickness are changed to low voltage system transistors 83 ′, 84 ′, and 86 ′ each having a small film thickness, so that the circuit area of ​​the comparison circuit 51 can be reduced.

[0149] Although the second power supply voltage VDDL can be maintained at 1.1 [V], which is the same as in the case of each of the first to third configurations, the positive feedback circuit 63 can operate using a voltage lower than the first power supply voltage VDDH' of the differential input circuit 61. Therefore, as the first power supply voltage VDDH decreases to the first power supply voltage VDDH', the second power supply voltage VDDL can be reduced to a voltage lower than the first power supply voltage VDDH'. As a result, power saving can be further promoted. For example, the second power supply voltage VDDL' can be set to approximately 0.6 [V]. Following the decrease in the second power supply voltage VDDL', the bias voltage VBIAS also decreases.

[0150] <7. Fifth Configuration Example of Comparison Circuit>

[0151] Fig.10 is a circuit diagram depicting a fifth configuration of the comparison circuit 51 .

[0152] The fifth embodiment of the comparison circuit 51 is compared with Fig. 9Compared with the fourth configuration of FIG. 1 , transistors 161 and 162 are omitted in the positive feedback circuit 63, and the 2-input NOR circuit is returned to the inverter circuit. In addition, transistor 163, which is a PMOS transistor, is newly added to the positive feedback circuit 63. The source of transistor 163 is connected to the second power supply voltage VDDL', and its drain is connected to the source of transistor 91 together with the drains of transistors 102 and 103 and the gates of transistors 104 and 105. The control signal xTEST_VCO, which is an inverted signal of the control signal TEST_VCO input to the NOR circuit, is supplied to the gate of transistor 163. The other constituent elements are similar to Fig. 9 A constituent element in the fourth construction.

[0153] exist Fig.10 In the fifth configuration of the comparison circuit 51, by supplying the control signal xTEST_VCO in Lo to the gate of the transistor 163, a test function is realized in which the output signal VCO of the comparison circuit 51 is forcibly set to Lo output regardless of the state of the differential input circuit 61.

[0154] In other words, Fig.10 In the fifth configuration of the comparison circuit 51, by using Fig. 9 The method in the fourth configuration shown in the figure realizes the test function in a different method. When the control signal xTEST_VCO at Lo is supplied to the gate of the transistor 163 and the initialization signal INI1 is set to Lo, the comparison circuit 51 outputs the output signal VCO at Lo. On the contrary, when the control signal xTEST_VCO at Hi is supplied to the gate of the transistor 163 and the initialization signal INI1 is set to Hi, the comparison circuit 51 outputs the output signal VCO at Hi.

[0155] according to Fig.10 The fifth configuration of the comparison circuit 51 can realize the following test function: Fig. 9 The number of transistors in the fourth configuration shown is one less.

[0156] In addition, according to Fig.10 The fifth configuration of the comparison circuit 51 can prevent the occurrence of a malfunction that may be caused by reducing the second power supply voltage VDDL of the positive feedback circuit 63 to the second power supply voltage VDDL′.

[0157] <8. Sixth Configuration Example of Comparison Circuit>

[0158] Fig.11 is a circuit diagram depicting a sixth configuration of the comparison circuit 51 .

[0159] The sixth configuration of the comparison circuit 51 is compared with Fig.10Compared with the fifth configuration of FIG. 1 , the configuration of the differential input circuit 61 is different from that in the fifth configuration. Specifically, a transistor 165 is added between the transistors 81 and 83 ′, and a transistor 166 is added between the transistors 82 and 84 ′.

[0160] Each of the transistors 165 and 166 includes an NMOS transistor, and a control signal Vh is supplied to each gate of the transistors 165 and 166. The source of the transistor 165 is connected to the drain of the transistor 81, and the drain of the transistor 165 is connected to the drain of the transistor 83'. The source of the transistor 166 is connected to the drain of the transistor 82, and the drain of the transistor 166 is connected to the drain of the transistor 84'.

[0161] Because in Fig.10 In the fifth configuration shown, each of the transistors 83 ′, 84 ′, and 86 ′ is directly connected to the transistor 81 or 82 , so the negative bias voltage VSS can only be reduced to a voltage that the low voltage system transistors 83 ′, 84 ′, and 86 ′ can withstand.

[0162] So, Fig.11 The comparison circuit 51 is configured in such a manner that the transistor 165 is inserted between the transistors 81 and 83', and the transistor 166 is inserted between the transistors 82 and 84', so that a portion between the transistors 81 and 83' and a portion between the transistors 82 and 84' can be separated from each other as needed. As a result, for example, the negative bias voltage VSS can be reduced to a voltage that the high voltage system transistor can withstand.

[0163] according to Fig.11 In the sixth configuration of the comparison circuit 51, the first power supply voltage VDDH' can be reduced to 1.1 [V], and the negative bias voltage VSS can be reduced to a voltage that the high-voltage system transistor can withstand. Therefore, the power consumption can be reduced while ensuring the saturation charge amount of each pixel 21 (pixel circuit 41). In addition, since the low-voltage system transistors 83', 84' and 86' are used, the circuit area can be reduced and the cost can be suppressed.

[0164] <Timing Diagram>

[0165] Fig.12 Yes Description Fig.11 1 is a timing chart of the operation of the pixel 21 (pixel circuit 41 ) in the sixth configuration of the comparison circuit 51 shown.

[0166] Fig.12 The time period from t31 to t41 in the timing diagram corresponds to Figure 6 The time period from t1 to t11 in the timing diagram of .

[0167] exist Fig.12In the timing diagram of FIG. 1 , a control signal xTEST_VCO for a test function and a control signal Vh supplied to each gate of transistors 165 and 166 as a breakdown voltage relaxation transistor are added. Figure 6 The operations in the timing diagram are the same, so the description of the same operations is omitted here.

[0168] like Fig.12 As shown, the reference signal REF decreases to the standby voltage V std During the period of time, the control signal Vh is set to Lo, and the comparison circuit 51 is controlled in such a way as to prevent the high potential difference from being applied to the transistors 83', 84' and 86'. In contrast, for the reference signal REF to be set to the reset voltage V rst or voltage V u The control signal Vh is set to Hi during the period of time. Meanwhile, the Hi voltage of the control signal Vh is determined by the first power supply voltage VDDH' and the negative bias voltage VSS of the differential input circuit 61. For example, as described above, when the first power supply voltage VDDH' is set to 1.1 [V] and the negative bias voltage VSS is set to -1.8 [V], the voltage of the Hi control signal Vh can be set to 0 [V].

[0169] <9. Example of pixel sharing structure>

[0170] Although the comparison circuit 51 described so far adopts a configuration in which one ADC 42 is arranged within one pixel 21 , a configuration in which one ADC 42 is shared by a plurality of pixels 21 may be adopted.

[0171] Fig.13 is a circuit diagram depicting a configuration example of the comparison circuit 51 in the case where pixel sharing in which a plurality of pixels 21 share one ADC 42 is performed.

[0172] Fig.13 Depicted is a configuration example of the comparison circuit 51 in the case where four pixels 21 , for example, the pixel 21A, the pixel 21B, the pixel 21C, and the pixel 21D share one ADC 42 .

[0173] exist Fig.13 In the embodiment, the differential input circuit 61, the voltage conversion circuit 62 and the positive feedback circuit 63 constituting the comparison circuit 51 are respectively constructed similarly to Fig.11 The sixth configuration shown.

[0174] exist Fig.13In FIG. 1 , four pixels 21A to 21D include pixel circuits 41A to 41D, respectively. Each of the pixel circuits 41A to 41D includes a photodiode 121q, a discharge transistor 122q, and a transfer transistor 123q. On the other hand, a reset transistor 174 and an FD 175 are shared by the four pixels 21A to 21D.

[0175] It should be noted that although Fig.11 The sixth configuration shown can be used as Fig.13 The circuit configuration of the comparison circuit 51 in FIG. 1 is shown, but any configuration among the first configuration to the fifth configuration may be adopted.

[0176] <10. Multiple substrate structure 1>

[0177] Although the description has been given so far in a manner that the solid-state imaging device 1 is formed on one semiconductor substrate 11 , circuits may be formed separately from each other on a plurality of semiconductor substrates to configure the solid-state imaging device 1 .

[0178] Fig.14 A conceptual diagram showing a solid-state imaging device 1 constructed by laminating two semiconductor substrates 11 such as an upper substrate 11A and a lower substrate 11C is shown.

[0179] The pixel circuit 41 including the photodiode 121 is formed at least on the upper substrate 11A. The data storage section 52 storing the time code and the time code transmission section 23 are formed at least on the lower substrate 11C. The upper substrate 11A and the lower substrate 11C are bonded to each other by metal bonding such as Cu-Cu, for example.

[0180] Fig.15 A configuration example of circuits formed on the upper substrate 11A and the lower substrate 11C, respectively, is depicted.

[0181] The pixel circuit 41 and transistors 81, 82, 85, 165 and 166 of the differential input circuit 61 of the ADC 42 are formed on the upper substrate 11A. The circuit of the ADC 42 other than the transistors 81, 82, 85, 165 and 166 and the time code transmission section 23 are formed on the lower substrate 11C.

[0182] <11. Multiple substrate structures 2>

[0183] Despite Fig.14 and Fig.15 In the description, the example in which the solid-state imaging device 1 is configured by using two semiconductor substrates 11 has been given, but the solid-state imaging device 1 may be configured by using three semiconductor substrates 11 .

[0184] Fig.16A conceptual diagram is depicted in which the solid-state imaging device 1 is constructed by stacking three semiconductor substrates 11 such as an upper substrate 11A, an intermediate substrate 11B, and a lower substrate 11C.

[0185] At least a part of the circuits of the pixel circuit 41 including the photodiode 121 and the comparison circuit 51 are formed on the upper substrate 11A. The data storage section 52 storing the time code and the time code transmission section 23 are formed at least on the lower substrate 11C. The remaining circuit of the comparison circuit 51 not arranged on the upper substrate 11A is formed on the intermediate substrate 11B. The upper substrate 11A and the intermediate substrate 11B, and the intermediate substrate 11B and the lower substrate 11C are bonded to each other by metal bonding such as Cu-Cu, for example.

[0186] Fig.17 Described is an example of arrangement of circuits of the semiconductor substrate 11 in the case where the solid-state imaging device 1 is formed by using three sheets of the semiconductor substrate 11 .

[0187] exist Fig.17 In the example of FIG. 1 , the circuits arranged on the upper substrate 11A are Fig.15 The circuits of the upper substrate 11A shown are the same, the remaining circuits of the comparison circuit 51 are arranged on the intermediate substrate 11B, and the data storage section 52 and the time code transfer section 23 are arranged on the lower substrate 11C.

[0188] <12. Application examples of electronic devices>

[0189] The present invention is by no means limited to application to solid-state imaging devices. More specifically, the present invention can also be applied to all electronic devices in which a solid-state imaging device is used for an image capturing section (photoelectric conversion section), for example, an imaging device such as a digital camera or a video camera, a mobile terminal device having an imaging function, or a copier using a solid-state imaging device in an image reading section. The solid-state imaging device may have a form formed as a chip, or may have a modular form with an imaging function, in which the imaging section and the signal processing section or the optical system are collectively packaged.

[0190] Fig.18 : is a block diagram depicting a configuration example of an image pickup apparatus as an electronic device according to the present invention.

[0191] Fig.18 The camera device 800 comprises: an optical part 801 including a lens group, etc.; Figure 1The imaging device 800 includes a solid-state imaging device (imaging apparatus) 802 having a structure of the solid-state imaging device 1; and a digital signal processing (DSP) circuit 803 as a camera signal processing circuit. In addition, the imaging device 800 further includes a frame memory 804, a display unit 805, a recording unit 806, an operation unit 807, and a power supply unit 808. The DSP circuit 803, the frame memory 804, the display unit 805, the recording unit 806, the operation unit 807, and the power supply unit 808 are connected to each other via a bus 809.

[0192] The optical section 801 acquires incident light (image light) from the subject to image the incident light on the imaging surface of the solid-state imaging device 802. The solid-state imaging device 802 converts the light amount of the incident light imaged on the imaging surface by the optical section 801 into an electrical signal in units of pixels, and outputs the obtained electrical signal as a pixel signal. Figure 1 The solid-state imaging device 1 can be used as the solid-state imaging device 802 of interest, that is, the following solid-state imaging device can be used as the solid-state imaging device 802, which has a comparison circuit 51 in which the determination speed when the pixel signal is AD converted is enhanced while the power consumption is reduced.

[0193] The display section 805 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL: electro luminescence) panel, and displays a moving image or a still image captured in the solid-state imaging device 802. The recording section 806 records data associated with the moving image or the still image imaged in the solid-state imaging device 802 in a recording medium such as a hard disk or a semiconductor memory.

[0194] The operation unit 807 issues operation instructions for various functions of the imaging device 800 under user operation. The power supply unit 808 supplies various power sources used as operation power sources for the DSP circuit 803, frame memory 804, display unit 805, recording unit 806 and operation unit 807 to these objects as appropriate.

[0195] As described above, the solid-state imaging device 1 adopting any one of the first to sixth configurations of the above-mentioned comparison circuit 51 is used as the solid-state imaging device 802, so that the power consumption can be reduced while accelerating the determination speed of AD conversion. Therefore, even in the imaging device 800 such as a camera module for a video camera digital camera, a camera module for a mobile device such as a portable phone, etc., high-speed imaging and low power consumption can be achieved.

[0196] Although in the above description, the comparison circuit 51 and the ADC 42 have been described as components included in the solid-state imaging device 1 , products (comparator, AD converter) distributed independently of each other may be used as the comparison circuit 51 and the ADC 42 , respectively.

[0197] Furthermore, the present invention is by no means limited to solid-state imaging devices, and can also be applied to all semiconductor devices having other semiconductor integrated circuits.

[0198] The embodiments of the present invention are by no means limited to the above-described embodiments, and various changes may be made without departing from the gist of the present invention.

[0199] For example, in each of the above-mentioned circuit configurations, a solid-state imaging device can be realized even in a circuit configuration in which the polarities of transistors (NMOS transistors and PMOS transistors) are replaced with each other. In this case, the control signal input to the transistor becomes a signal whose level (Hi and Lo) is inverted.

[0200] Although in each of the above-mentioned embodiments, the reference signal REF is a ramp signal whose level (voltage) decreases monotonically over time, the reference signal REF may also be a ramp signal whose level (voltage) increases monotonically over time.

[0201] In each of the above-described embodiments, an example has been described in which four pixels 21 share the ADC 42. However, the number of pixels 21 shared is not limited to four, and another number (e.g., eight) of pixels 21 may be employed.

[0202] In addition to this, an embodiment obtained by combining all or part of the above-described plural embodiments may be adopted. An embodiment obtained by appropriately combining other embodiments not described in the above-described embodiments may also be adopted.

[0203] It should be noted that the effects described in this specification are merely examples and are not restrictive, and effects other than those described in this specification may also be provided.

[0204] It should be noted that the present invention can also adopt the following configurations.

[0205] (1) A comparator, comprising:

[0206] a differential input circuit that operates at a first power supply voltage and outputs a signal when a voltage of an input signal is higher than a voltage of a reference signal;

[0207] a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and accelerates a switching speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit; and

[0208] a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage,

[0209] Wherein, the source voltage of the differential input circuit is a voltage lower than 0V.

[0210] (2) The comparator according to (1) above, wherein the differential input circuit includes a first transistor and a second transistor that form a current mirror, and the first transistor and the second transistor each include a low voltage system transistor.

[0211] (3) The comparator according to (2) above, wherein the low voltage system transistor is driven by the first power supply voltage equal to or lower than 2V.

[0212] (4) The comparator according to (2) or (3) above, wherein the differential input circuit further comprises:

[0213] a third transistor, the reference signal being input to the third transistor;

[0214] a fourth transistor to which the input signal is input; and

[0215] A fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor turn on or off the connection between the first transistor and the second transistor and between the third transistor and the fourth transistor.

[0216] (5) A comparator according to any one of (1) to (4) above, wherein the positive feedback circuit receives an input of a control signal different from the output signal from the differential input circuit, and inverts the comparison result signal based on the control signal regardless of the output signal from the differential input circuit.

[0217] (6) The comparator according to (5) above, wherein the positive feedback circuit has:

[0218] an inverter circuit that inverts the output signal from the differential input circuit to generate the comparison result signal; and

[0219] A transistor is provided for supplying the second power supply voltage to the inverter circuit based on the control signal.

[0220] (7) The comparator according to (5) above, wherein the positive feedback circuit has a NOR circuit that receives the output signal from the differential input circuit and the control signal as inputs of the NOR circuit.

[0221] (8) an AD converter, comprising:

[0222] A comparator, the comparator comprising:

[0223] a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal,

[0224] a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and accelerates a conversion speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit, and

[0225] a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage,

[0226] wherein the source voltage of the differential input circuit is a voltage lower than 0V; and

[0227] A data storage section stores a time code when the comparison result signal is inverted.

[0228] (9) A solid-state imaging device comprising:

[0229] AD converter, the AD converter comprising:

[0230] A comparator, the comparator comprising:

[0231] a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal,

[0232] a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and accelerates a conversion speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit, and

[0233] a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage, wherein the source voltage of the differential input circuit is a voltage lower than 0V, and

[0234] A data storage section storing a time code when the comparison result signal is inverted; and

[0235] A pixel circuit outputs a charge signal generated by receiving light incident to a pixel and then photoelectrically converting the light to the differential input circuit as the input signal.

[0236] (10) The solid-state imaging device according to (9) above, wherein the AD converter is arranged for each pixel.

[0237] (11) The solid-state imaging device according to (9) above, wherein the AD converter is shared by a plurality of the pixels.

[0238] (12) The solid-state imaging device according to (9) or (10) above, wherein the solid-state imaging device includes a plurality of semiconductor substrates.

[0239] (13) An electronic device comprising a solid-state imaging device, the solid-state imaging device comprising:

[0240] AD converter, the AD converter comprising:

[0241] A comparator, the comparator comprising:

[0242] a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal,

[0243] a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage and accelerates a conversion speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on an output signal from the differential input circuit, and

[0244] a voltage conversion circuit that converts the output signal from the differential input circuit into a signal corresponding to the second power supply voltage,

[0245] wherein the source voltage of the differential input circuit is a voltage lower than 0V, and a data storage section storing a time code when the comparison result signal is inverted; and

[0246] A pixel circuit outputs a charge signal generated by receiving light incident to a pixel and then photoelectrically converting the light to the differential input circuit as the input signal.

[0247] (14) A control method for a comparator, the comparator comprising: a differential input circuit, the differential input circuit operating at a first power supply voltage; a positive feedback circuit, the positive feedback circuit operating at a second power supply voltage lower than the first power supply voltage; and a voltage conversion circuit, the source voltage of the differential input circuit being lower than 0 V, the method comprising:

[0248] When the voltage of the input signal is higher than the voltage of the reference signal, the differential input circuit outputs a signal;

[0249] the voltage conversion circuit converting an output signal from the differential input circuit into a signal corresponding to the second power supply voltage; and

[0250] The positive feedback circuit speeds up a conversion speed when a comparison result signal indicating a voltage comparison result between the input signal and the reference signal is inverted based on the output signal from the differential input circuit obtained by conversion in the voltage conversion circuit.

[0251] Reference numerals list

[0252] 1 solid-state imaging device 11 semiconductor substrate 21 pixel

[0253] 22 Pixel array unit 23 Time code transmission unit 26 Time code generation unit

[0254] 28 output unit 41 pixel circuit 42 ADC 51 comparison circuit

[0255] 52 Data storage unit 61 Differential input circuit 62 Voltage conversion circuit

[0256] 63 positive feedback circuit 71 latch control circuit 72 latch storage unit

[0257] 81 to 86, 91 transistors 101 to 105, 161 to 163, 165, 166 transistors

[0258] 800 imaging device 802 solid-state imaging device

Claims

1. A solid-state imaging device, comprising: A first substrate, the first substrate comprising: four pixels connected to the floating diffusion; and a first portion of a differential input circuit that is shared by the four pixels; A second substrate is stacked on the first substrate, wherein the second substrate comprises: a second portion of the differential input circuit connected to the first portion of the differential input circuit; a feedback circuit connected to the second portion of the differential input circuit; A data storage unit connected to the feedback circuit; and a time code transmission unit configured to provide a time code, and the time code transmission unit extends to the column direction of the four pixels, and Wherein, the differential input circuit operates at a first power supply voltage, The feedback circuit operates at a second power supply voltage, and The second power supply voltage is lower than the first power supply voltage.

2. The solid-state imaging device according to claim 1, wherein The first part of the differential input circuit includes a first input and a second input, the first input is connected to the four pixels, and The second input is connected to a digital-to-analog converter that controls the voltage of the reference signal.

3. The solid-state imaging device according to claim 2, wherein: The reference signal is a ramp signal, and, The level of the reference signal increases monotonically over time.

4. The solid-state imaging device according to claim 3, further comprising: A comparison circuit, the comparison circuit comprising the differential input circuit and the feedback circuit, wherein the comparison circuit is configured as: comparing a first signal received at the first input with a second signal received at the second input; and An output signal is output as a comparison result.

5. The solid-state imaging device according to claim 4, wherein: The feedback circuit is configured to increase a switching speed of the output signal of the comparison circuit.

6. The solid-state imaging device according to claim 5, wherein: The data storage unit includes a latch storage unit, and The latch storage unit is configured to store the time code based on the output signal.

7. The solid-state imaging device according to claim 1, wherein The source voltage of the differential input circuit is a voltage lower than 0V.

8. The solid-state imaging device according to claim 7, wherein: The first substrate and the second substrate are connected by metal bonding.

9. The solid-state imaging device according to claim 8, wherein: The first portion of the differential input circuit and the second portion of the differential input circuit are electrically connected by the metal bond.

10. A solid-state imaging device, comprising: A first substrate, the first substrate comprising: Four pixels; a first portion of a differential input circuit that is shared by the four pixels; A second substrate is stacked on the first substrate, wherein the second substrate comprises: a second portion of the differential input circuit connected to the first portion of the differential input circuit; a feedback circuit connected to the second portion of the differential input circuit; A data storage unit connected to the feedback circuit; and a time code transmission unit configured to provide a time code, and the time code transmission unit extends to the column direction of the four pixels, The first part of the differential input circuit is electrically connected to the second part of the differential input circuit via a metal bond, wherein: The differential input circuit operates at a first power supply voltage, The feedback circuit operates at a second power supply voltage, and The second power supply voltage is lower than the first power supply voltage.

11. The solid-state imaging device according to claim 10, wherein: The first part of the differential input circuit includes a first input and a second input, the first input is connected to the four pixels, and The second input is connected to a digital-to-analog converter that controls the voltage of the reference signal.

12. The solid-state imaging device according to claim 11, wherein The reference signal is a ramp signal, and, The level of the reference signal increases monotonically over time.

13. The solid-state imaging device according to claim 12, further comprising: A comparison circuit, the comparison circuit comprising the differential input circuit and the feedback circuit, wherein the comparison circuit is configured as: comparing a first signal received at the first input with a second signal received at the second input; and An output signal is output as a comparison result.

14. The solid-state imaging device according to claim 13, wherein: The feedback circuit is configured to increase a switching speed of the output signal of the comparison circuit.

15. The solid-state imaging device according to claim 14, wherein The data storage unit includes a latch storage unit, and The latch storage unit is configured to store the time code based on the output signal.

16. The solid-state imaging device according to claim 10, wherein: The first substrate and the second substrate are connected by the metal bond.

17. The solid-state imaging device according to claim 16, wherein: The source voltage of the differential input circuit is a voltage lower than 0V.

18. A solid-state imaging device, comprising: A first substrate, the first substrate comprising: Multiple pixels; a first portion of a differential input circuit, which is shared by the plurality of pixels; and a second substrate, stacked on the first substrate, wherein the second substrate comprises: a second portion of the differential input circuit connected to the first portion of the differential input circuit; a feedback circuit connected to the second portion of the differential input circuit; A data storage unit connected to the feedback circuit; and a time code transmission unit configured to provide a time code, and the time code transmission unit extends to the column direction of the plurality of pixels, The first part of the differential input circuit is electrically connected to the second part of the differential input circuit via a metal bond, wherein: The differential input circuit operates at a first power supply voltage, The feedback circuit operates at a second power supply voltage, and The second power supply voltage is lower than the first power supply voltage.

19. The solid-state imaging device according to claim 18, wherein The first portion of the differential input circuit includes a first input and a second input, the first input being connected to the plurality of pixels, and The second input is connected to a digital-to-analog converter that controls the voltage of the reference signal.

20. The solid-state imaging device according to claim 19, wherein The reference signal is a ramp signal, and, The level of the reference signal increases monotonically over time.

21. The solid-state imaging device according to claim 20, further comprising: A comparison circuit, the comparison circuit comprising the differential input circuit and the feedback circuit, wherein the comparison circuit is configured as: comparing a first signal received at the first input with a second signal received at the second input; and An output signal is output as a comparison result.

22. The solid-state imaging device according to claim 21, wherein The feedback circuit is configured to increase a switching speed of the output signal of the comparison circuit.

23. The solid-state imaging device according to claim 22, wherein: The data storage unit includes a latch storage unit, and The latch storage unit is configured to store the time code based on the output signal.

24. The solid-state imaging device according to claim 18, wherein The first substrate and the second substrate are connected by the metal bond.

25. The solid-state imaging device according to claim 24, wherein The source voltage of the differential input circuit is a voltage lower than 0V.

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