Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure comprises: a substrate; a gate structure located on the substrate; a dielectric layer located on the substrate, the dielectric layer being located on the sidewall of the gate structure; an opening located in the dielectric layer, the opening penetrating the gate structure in a direction perpendicular to the extension direction of the gate structure; a first isolation layer located in the opening, the top surface of the first isolation layer being lower than the top surface of the gate structure. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] The semiconductor manufacturing industry has experienced exponential growth. Technological advances in semiconductor materials and design have produced generations in which each generation has smaller and more complex circuits than the previous generation. In the course of semiconductor technology development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This scaling down process also increases the complexity of processing and manufacturing semiconductor devices, and in order to achieve these advances, more sophisticated process technologies are required. For example, the traditional gate cutting process is greatly limited by the dense packaging of devices required by advanced semiconductor process nodes. Specifically, the gate cutting process usually implements an etching process that completely (or substantially) removes the entire portion of the gate stack (including, for example, at least one gate electrode layer and at least one gate dielectric layer). However, the lateral etching generated during the gate cutting process, or the isolation structure formed after the gate cutting, will affect the performance of the semiconductor device.

[0004] Therefore, the existing gate cutting process needs to be improved to enhance the performance of semiconductor devices. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; a dielectric layer located on the substrate, the dielectric layer covering the side walls of the gate structure; an opening located in the dielectric layer, the opening penetrating the gate structure in a direction perpendicular to the extension direction of the gate structure; a first isolation layer located in the opening, the top surface of the first isolation layer being lower than the top surface of the gate structure.

[0007] Optionally, the material of the first isolation layer includes a dielectric material, and the dielectric material includes silicon nitride.

[0008] Optionally, it further includes: a second isolation layer located in the opening, the second isolation layer is located on the first isolation layer; the material of the second isolation layer is different from the material of the first isolation layer, and the material of the second isolation layer is the same as the material of the dielectric layer.

[0009] Optionally, the substrate includes a base and a plurality of fin structures located on the base; the gate structure spans across the plurality of fin structures; and the first isolation layer is located between adjacent fin structures.

[0010] Optionally, it also includes: source and drain doped regions in the fin structure located on both sides of the gate structure; a metal layer located in the dielectric layer, the metal layer is electrically connected to the source and drain doped regions on one side of the gate structure, and the metal layer is located on the first isolation layer.

[0011] Optionally, the metal layer is parallel to the gate structure.

[0012] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a pseudo gate structure on the substrate; forming a dielectric layer on the substrate, wherein the dielectric layer is located on the side wall of the pseudo gate structure, and the dielectric layer exposes the top surface of the pseudo gate structure; forming an opening in the dielectric layer, wherein the opening passes through the pseudo gate structure in a direction perpendicular to the extension direction of the initial pseudo gate structure; forming a first isolation layer in the opening, wherein the top surface of the first isolation layer is lower than the top surface of the pseudo gate structure.

[0013] Optionally, the material of the first isolation layer includes a dielectric material, and the dielectric material includes silicon nitride.

[0014] Optionally, the method for forming the first isolation layer includes: forming a first isolation material layer in the opening; etching back the first isolation material layer until the side wall of the dummy gate structure is exposed, so that the top surface of the first isolation layer is lower than the top surface of the dummy gate structure.

[0015] Optionally, after forming the first isolation layer, the method further includes: forming a second isolation layer on the first isolation layer, wherein the second isolation layer is located in the opening; a material of the second isolation layer is different from a material of the first isolation layer, and a material of the second isolation layer is the same as a material of the dielectric layer.

[0016] Optionally, the material of the second isolation layer includes a dielectric material, and the dielectric material includes silicon oxide.

[0017] Optionally, the substrate includes a base and a plurality of fin structures located on the base; and the dummy gate structure spans across the plurality of fin structures.

[0018] Optionally, after forming the dummy gate structure and before forming the dielectric layer, the method further includes: forming source and drain doped regions in the fin structure on both sides of the dummy gate structure.

[0019] Optionally, after forming the second isolation layer, it also includes: removing part of the second isolation layer and the dielectric layer, forming a groove in the dielectric layer, wherein the groove exposes the surface of the source and drain doped region on one side of the pseudo gate structure and the surface of the first isolation layer; forming a metal layer in the groove, wherein the metal layer is electrically connected to the source and drain doped region on one side of the pseudo gate structure.

[0020] Optionally, before removing part of the second isolation layer and the dielectric layer to form the groove, the method further includes: removing the dummy gate structure to form a gate opening in the dielectric layer; forming a gate structure in the gate opening, wherein the gate structure includes an effective gate structure and an ineffective gate structure.

[0021] Optionally, before removing a portion of the second isolation layer and the dielectric layer to form the groove, the method further includes: removing the ineffective gate structure.

[0022] Optionally, the process of removing the ineffective gate structure includes a wet etching process.

[0023] Optionally, the metal layer is parallel to the dummy gate structure.

[0024] Optionally, the method for forming the second isolation layer includes: forming a second isolation material layer on the first isolation layer and the dielectric layer; and planarizing the second isolation material layer until a surface of the dielectric layer is exposed to form the second isolation layer.

[0025] Optionally, the process of forming the second isolation material layer includes a chemical vapor deposition process.

[0026] Optionally, the method for forming the opening includes: forming a patterned mask structure on the top surface of the pseudo gate structure and the surface of the dielectric layer, the patterned mask structure exposing a portion of the top surface of the pseudo gate structure and the surface of the dielectric layer; etching the pseudo gate structure and the dielectric layer using the patterned mask structure as a mask to form openings in the dielectric layer and the pseudo gate structure.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the semiconductor structure of the technical solution of the present invention, the dielectric layer has an opening, the opening penetrates the gate structure in a direction perpendicular to the extension direction of the gate structure, and the opening has a first isolation layer, the top surface of the first isolation layer is lower than the top surface of the gate structure. Therefore, in the subsequent process of forming the metal layer, the metal layer spans the first isolation layer, and since the height of the first isolation layer is relatively low, the resistance of the metal layer is relatively small, thereby improving the performance of the semiconductor structure.

[0029] The method for forming a semiconductor structure in the technical solution of the present invention forms an opening in a dielectric layer, the opening penetrates the pseudo gate structure in a direction perpendicular to the extension direction of the initial pseudo gate structure, and then forms a first isolation layer in the opening, the top surface of the first isolation layer is lower than the top surface of the pseudo gate structure. In the subsequent process of forming a metal layer, the metal layer spans the first isolation layer, and since the height of the first isolation layer is relatively low, the resistance of the metal layer is relatively small, thereby improving the performance of the semiconductor structure.

[0030] Furthermore, after forming the first isolation layer, the method further includes: forming a second isolation layer on the first isolation layer, the second isolation layer being located in the opening, the material of the second isolation layer being different from the material of the first isolation layer, and the material of the second isolation layer being the same as the material of the dielectric layer. Thus, when a groove is subsequently formed in the dielectric layer to expose the source and drain doped regions, the second isolation layer can also be removed together, so that the metal layer can be formed on the first isolation layer, so that the resistance of the metal layer is reduced.

[0031] Furthermore, the opening penetrates the pseudo gate structure in a direction perpendicular to the extension direction of the initial pseudo gate structure, so that the size of the opening is larger than the width of the pseudo gate structure. Therefore, when the invalid gate structure is subsequently removed by a wet etching process, the first isolation layer and the second isolation layer located in the opening can protect the effective gate structure, and can prevent the etching solution for removing the invalid gate structure from penetrating from the interface between the first isolation layer and the second isolation layer and the dielectric layer to the effective gate structure, thereby causing damage to the effective gate structure by the etching solution, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1 to 3 is a schematic cross-sectional view and a top view of a semiconductor structure in one embodiment;

[0033] Figures 4 to 14 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the existing gate cutting process needs to be improved. Now, it is analyzed and explained in conjunction with specific embodiments.

[0035] Figures 1 to 3 It is a schematic diagram of the cross-sectional structure and a top view of a semiconductor structure in one embodiment.

[0036] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 for Figure 2 and Figure 3The top view of the first dielectric layer 107 and the second dielectric layer 108 is omitted. Figure 2 for Figure 1 Schematic diagram of the cross-section structure along the section line AA'. Figure 3 for Figure 1 The schematic diagram of the cross-sectional structure along the section line BB' direction includes: a substrate 100, wherein the substrate 100 has a fin structure 101; an isolation layer 102 located on the substrate 100, wherein the isolation layer 102 is located on a portion of the side wall surface of the fin structure 101, and the top surface of the isolation layer 102 is lower than the top surface of the fin structure 101; a gate structure 103 located on the substrate 100, wherein the gate structure 103 spans the fin structure 101; source-drain doped regions 104 located in the fin structure 101 on both sides of the gate structure; a first dielectric layer 107 located on the side wall of the gate structure 103; an isolation structure 105 located in the gate structure 103 and in the first dielectric layer 107; and a metal layer 109 located on the dielectric layer 107, wherein the metal layer 109 is electrically connected to the source-drain doped regions 103 on one side of the gate structure 103.

[0037] During the formation of the semiconductor structure, a dummy gate structure is first formed, and then a portion of the dummy gate structure is removed to form a first groove (not shown) in the dielectric layer 107, and then a portion of the dielectric layer 107 exposed by the first groove is removed, and a second groove (not shown) connected to the first groove is formed in the dielectric layer 107, and an isolation structure 106 is formed in the first groove and the second groove, and the material of the isolation structure 106 includes silicon nitride; then the dummy gate structure is removed to form a gate structure 103.

[0038] However, when forming the metal layer 109 electrically connected to the source-drain doped region 104 on one side of the gate structure 103, in the process of removing the second dielectric layer 108 and the first dielectric layer 107 to expose the surface of the source-drain doped region 104, the removal process causes less loss to the isolation structure 105, so that the formed metal layer 109 spans the isolation structure 105. The height of the isolation structure 105 is relatively high, which, on the one hand, makes the current path through the metal layer 109 longer; on the other hand, makes the height of the metal layer 109 at the top of the isolation structure 105 relatively small, so that the number of electrons passing through the cross-sectional area of ​​the metal layer 109 at the top of the isolation structure 105 is reduced. In summary, the resistance of the metal layer 109 is increased, affecting the performance of the semiconductor structure.

[0039] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, by forming an opening in a dielectric layer and a pseudo gate structure, the opening penetrates the pseudo gate structure in a direction perpendicular to the extension direction of the initial pseudo gate structure, and then forming a first isolation layer in the opening, the top surface of the first isolation layer is lower than the top surface of the pseudo gate structure. In the subsequent process of forming a metal layer, the metal layer spans the first isolation layer, and since the height of the first isolation layer is relatively low, the resistance of the metal layer is relatively small, thereby improving the performance of the semiconductor structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 4 to 14 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0042] Please refer to Figure 4 , providing a substrate.

[0043] The substrate includes a base 200 and a plurality of fin structures 201 located on the base 200 . The substrate also has an isolation layer 202 . The isolation layer 202 is located on a portion of the sidewalls of the fin structure 201 , and the top surface of the isolation layer 202 is lower than the top surface of the fin structure 201 .

[0044] The material of the substrate 200 is single crystal silicon; the material of the fin structure 201 includes single crystal silicon.

[0045] In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator.

[0046] The material of the isolation layer 202 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the isolation layer 202 includes silicon oxide.

[0047] Please refer to Figure 5 and Figure 6 , Figure 6 for Figure 5 A top view of Figure 5 for Figure 6 The cross-sectional structure diagram along the section line CC′ direction shows that a dummy gate structure 203 is formed on the substrate, and the dummy gate structure 203 spans across a number of the fin structures 201 .

[0048] The dummy gate structure 203 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) located on the dummy gate dielectric layer.

[0049] The method for forming the pseudo gate structure 203 includes: forming a pseudo gate dielectric material layer (not shown) on a substrate; forming a pseudo gate material layer (not shown) on the pseudo gate dielectric material layer; forming a patterned mask layer (not shown) on the pseudo gate material layer; and etching the pseudo gate material layer and the pseudo gate dielectric material layer using the patterned mask layer as a mask until the substrate surface is exposed to form the pseudo gate structure 203.

[0050] The material of the dummy gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; the material of the dummy gate layer includes polysilicon.

[0051] Please continue to refer to Figure 5 and Figure 6 , source and drain doped regions (not shown) are formed in the fin structure on both sides of the dummy gate structure 203 .

[0052] The source-drain doping region has doping ions, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions or arsenic ions; and the P-type ions include boron ions or indium ions.

[0053] The process of forming the source-drain doping region includes an epitaxial growth process or an ion implantation process.

[0054] Please continue to refer to Figure 5 and Figure 6 , a dielectric layer 204 is formed on the substrate, wherein the dielectric layer 204 is located on the sidewall of the dummy gate structure 203 , and the dielectric layer 204 exposes the top surface of the dummy gate structure 203 .

[0055] The method for forming the dielectric layer 204 includes: forming a dielectric material layer (not shown) on the substrate, the top surface and the sidewall surface of the dummy gate structure 203; and planarizing the dielectric material layer until the top surface of the dummy gate structure 203 is exposed to form the dielectric layer 204.

[0056] The material of the dielectric layer 204 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon carbon nitride. The process of forming the dielectric material layer includes a chemical vapor deposition process, a heat treatment process, or an atomic layer deposition process.

[0057] In this embodiment, the material of the dielectric layer 204 includes silicon oxide; and the process of forming the dielectric material layer includes a chemical vapor deposition process.

[0058] Please refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 A top view of Figure 7 for Figure 8 The schematic cross-sectional structure diagram along the section line DD′ shows that an opening 205 is formed in the dielectric layer 204 and the dummy gate structure 203 , and the opening 205 penetrates the dummy gate structure 203 in a direction perpendicular to the extension direction of the dummy gate structure 203 .

[0059] The opening 205 penetrates the dummy gate structure 203 in a direction perpendicular to the extension direction of the dummy gate structure 203, so that the size of the opening 205 is greater than the width of the dummy gate structure 203, so that after the first isolation layer and the second isolation layer are subsequently formed in the opening 205, the dummy gate structure is removed to form an effective gate structure and an invalid gate structure, when the invalid gate structure is removed by a wet etching process, the first isolation layer and the second isolation layer can protect the effective gate structure, and can prevent the etching solution for removing the invalid gate structure from penetrating from the interface between the first isolation layer and the second isolation layer and the dielectric layer 204 to the effective gate structure, so that the etching solution causes damage to the effective gate structure, thereby improving the performance of the semiconductor structure.

[0060] The method for forming the opening 205 includes: forming a patterned mask structure (not shown) on the top surface of the dummy gate structure 203 and the surface of the dielectric layer 204, wherein the patterned mask structure exposes a portion of the top surface of the dummy gate structure 203 and the surface of the dielectric layer 204; etching the dummy gate structure 203 and the dielectric layer 204 using the patterned mask structure as a mask to form an opening 205 in the dielectric layer 204 and the dummy gate structure 203.

[0061] In this embodiment, the pseudo gate structure 203 exposed by the patterned mask structure is first removed to form an initial opening (not shown); then the dielectric layer 204 exposed by the initial opening and the patterned mask structure is removed to form the opening 205, so that the pseudo gate structure 203 and the dielectric layer 204 in the opening 205 can be removed cleanly to form an opening 205 with good dimensional accuracy and morphology.

[0062] The process of removing the dummy gate structure 203 exposed by the patterned mask structure includes a combination of one or more dry etching processes and wet etching processes. The process of removing the dielectric layer 204 exposed by the initial opening and the patterned mask structure includes a combination of one or more dry etching processes and wet etching processes.

[0063] In this embodiment, the process of removing the dummy gate structure 203 exposed by the patterned mask structure includes a dry etching process; and the process of removing the dielectric layer 204 exposed by the initial opening and the patterned mask structure includes a dry etching process.

[0064] Please refer to Fig. 9 and Fig.10 , Fig.10 for Fig. 9 A top view of Fig. 9 for Fig.10 The schematic cross-sectional structure diagram along the section line EE′ direction shows that a first isolation layer 206 is formed in the opening 205 , and a top surface of the first isolation layer 206 is lower than a top surface of the dummy gate structure 203 .

[0065] The top surface of the first isolation layer 206 is lower than the top surface of the pseudo gate structure 203, so that in the subsequent process of forming a metal layer, the metal layer spans the first isolation layer 206. Since the height of the first isolation layer 206 is reduced, the resistance of the metal layer is smaller, thereby improving the performance of the semiconductor structure.

[0066] In this embodiment, the top surface of the first isolation layer 206 is slightly higher than the top surface of the fin structure 201, so that the first isolation layer 206 and the subsequently formed second isolation layer have a better blocking effect on the etching solution for removing the invalid gate structure while reducing the resistance of the metal layer, so that an effective gate structure with less damage can be obtained subsequently, thereby making the effective gate structure have better performance.

[0067] In other embodiments, the top surface of the first isolation layer may be lower than or flush with the top surface of the fin structure.

[0068] The method for forming the first isolation layer 206 includes: forming a first isolation material layer (not shown) in the opening 205; etching back the first isolation material layer until the side wall of the dummy gate structure 203 is exposed, so that the top surface of the first isolation layer 206 is lower than the top surface of the dummy gate structure 203.

[0069] The material of the first isolation layer 206 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride. The process of forming the first isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0070] In this embodiment, the material of the first isolation layer 206 includes silicon nitride; and the process of forming the first isolation material layer includes a chemical vapor deposition process.

[0071] Please continue to refer to Fig. 9 and Fig.10 , a second isolation layer 207 is formed on the first isolation layer 206 , and the second isolation layer 207 is located in the opening 205 .

[0072] The material of the second isolation layer 207 is different from that of the first isolation layer 206, and the material of the second isolation layer 207 is the same as that of the dielectric layer 204. Therefore, when a groove is subsequently formed in the dielectric layer 204 to expose the source and drain doping regions, the second isolation layer 207 can also be removed together, so that the metal layer can be formed on the first isolation layer 206, so that the resistance of the metal layer is reduced.

[0073] A second isolation layer 207 is formed on the first isolation layer 206. The material of the second isolation layer 207 is different from that of the first isolation layer 206. Therefore, while the first isolation layer 206 and the second isolation layer 207 play a good isolation role, the threshold voltage of the formed semiconductor device (such as a transistor) is small.

[0074] The method for forming the second isolation layer 207 includes: forming a second isolation material layer (not shown) on the first isolation layer 206 and the dielectric layer 204 ; and planarizing the second isolation material layer to expose the top surface of the dielectric layer 204 to form the second isolation layer 207 .

[0075] The material of the second isolation layer 207 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride. The process of forming the second isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0076] In this embodiment, the material of the second isolation layer 207 includes silicon nitride; and the process of forming the second isolation material layer includes a chemical vapor deposition process.

[0077] Please refer to Fig.11 and Fig.12 , Fig.12 for Fig.11 A top view of Fig.11 for Fig.12 In the schematic cross-sectional structure diagram along the section line FF′, the dummy gate structure 203 is removed, a gate opening (not shown) is formed in the dielectric layer 204 , and a gate structure is formed in the gate opening.

[0078] In this embodiment, the gate structure includes an effective gate structure 210 and an ineffective gate structure (not shown), and the effective gate structure 210 and the ineffective gate structure are located on both sides of the first isolation layer 206 and the second isolation layer 207 .

[0079] The effective gate structure 210 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0080] In this embodiment, the effective gate structure 210 further includes a work function layer (not shown), and the work function layer is located between the gate dielectric layer and the gate layer.

[0081] The material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0082] Please continue to refer to Fig.11 and Fig.12 After forming the gate structure, the ineffective gate structure is removed.

[0083] In this embodiment, the process of removing the ineffective gate structure includes a wet etching process.

[0084] Since the opening 205 penetrates the dummy gate structure 203 in a direction perpendicular to the extension direction of the dummy gate structure 203, the size of the opening 205 is greater than the width of the dummy gate structure 203. Therefore, when the invalid gate structure is removed by a wet etching process, the first isolation layer 206 and the second isolation layer 207 located in the opening 205 can protect the effective gate structure 210, and can prevent the etching solution for removing the invalid gate structure from penetrating from the interface between the first isolation layer 206 and the second isolation layer 207 and the dielectric layer 204 to the effective gate structure 210, thereby causing damage to the effective gate structure 210 by the etching solution, thereby improving the performance of the semiconductor structure.

[0085] In other embodiments, the inactive gate structure may not be removed.

[0086] Please continue to refer to Fig.11 and Fig.12 An interlayer dielectric layer (not shown) is formed on the top surface of the gate structure, the surface of the dielectric layer 204 and the surface of the second isolation layer 207; a portion of the interlayer dielectric layer, the second isolation layer 207 and the dielectric layer 204 are removed to form a groove 208 in the dielectric layer 204, wherein the groove 208 exposes the surface of the source / drain doped region on one side of the gate structure 210 and the surface of the first isolation layer 206.

[0087] The method for forming the groove 208 includes: forming a patterned mask layer (not shown) on the dielectric layer 204, the second isolation layer 207 and the gate structure 210, wherein the patterned mask layer exposes a portion of the surface of the second isolation layer 207 and a portion of the surface of the dielectric layer 204 on the source and drain doped regions; etching the second isolation layer 207 and the dielectric layer 204 using the patterned mask layer as a mask until the surface of the source and drain doped regions is exposed to form the groove 208.

[0088] Since the material of the second isolation layer 207 is the same as that of the dielectric layer 204, when a groove 208 exposing the source and drain doping regions is formed in the dielectric layer 204, the second isolation layer 207 can also be removed together, so that the subsequent metal layer can be formed on the first isolation layer 206, thereby reducing the resistance of the metal layer.

[0089] Please refer to Fig.13 and Fig.14 , Fig.14 for Fig.13 A top view of Fig.13 for Fig.14 The schematic cross-sectional structure diagram along the section line GG′ shows that a metal layer 209 is formed in the groove 208 , and the metal layer 209 is electrically connected to the source-drain doped region on one side of the gate structure 210 .

[0090] The metal layer 209 is parallel to the gate structure 210 , and a top surface of the metal layer 209 is higher than a top surface of the gate structure 210 .

[0091] The method for forming the metal layer 209 includes: forming a metal material layer (not shown) in the groove 208 and on the dielectric layer 204 ; and planarizing the metal material layer until the surface of the dielectric layer 204 is exposed to form the metal layer 209 .

[0092] The material of the metal layer 209 includes: one or more combinations of copper, aluminum, tungsten, cobalt and titanium nitride. The process of forming the metal material layer includes chemical vapor deposition process, physical vapor deposition process or electroplating process.

[0093] In this embodiment, the material of the metal layer 209 includes copper; and the process of forming the metal material layer includes a physical vapor deposition process.

[0094] At this point, a metal layer 209 electrically connected to the source and drain doping regions is formed, and the metal layer 209 spans the first isolation layer 206. The top surface of the first isolation layer 206 is lower than the top surface of the gate structure 210. The height of the first isolation layer 206 is relatively low, so that the resistance of the metal layer 209 is relatively small, thereby improving the performance of the semiconductor structure.

[0095] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.13 and Fig.14 , including: a substrate; a gate structure 210 located on the substrate; a dielectric layer 204 located on the substrate, the dielectric layer 204 is located on the sidewall of the gate structure 210; an opening (not shown) located in the gate structure 210 and in the dielectric layer 204, the opening penetrating the gate structure 210 along a direction perpendicular to the extension direction of the gate structure 210; a first isolation layer 206 located in the opening, the top surface of the first isolation layer 206 is lower than the top surface of the gate structure 210.

[0096] In this embodiment, the material of the first isolation layer 206 includes a dielectric material, and the dielectric material includes silicon nitride.

[0097] In this embodiment, it also includes: a second isolation layer 207 located in the opening, the second isolation layer 207 is located on the first isolation layer 206, and the second isolation layer 207 is located in the opening; the material of the second isolation layer 207 is different from the material of the first isolation layer 206, and the material of the second isolation layer 207 is the same as the material of the dielectric layer 204.

[0098] In this embodiment, the substrate includes a base 200 and a plurality of fin structures 201 located on the base 200 ; the gate structure 210 spans across the plurality of fin structures 201 ; and the first isolation layer 206 is located between adjacent fin structures 201 .

[0099] In this embodiment, it also includes: source and drain doped regions (not shown) within the fin structure 201 located on both sides of the gate structure 210; a metal layer 209 located in the dielectric layer 204, the metal layer 209 is electrically connected to the source and drain doped regions on one side of the gate structure 210, and the metal layer 209 is located on the first isolation layer 206.

[0100] In this embodiment, the metal layer 209 is parallel to the gate structure 210 .

[0101] The semiconductor structure has an opening in the gate structure 210 and in the dielectric layer 204, the opening penetrates the gate structure 210 in a direction perpendicular to the extension direction of the gate structure 210, and the opening has a first isolation layer 206, the top surface of the first isolation layer 206 is lower than the top surface of the gate structure 210. Therefore, in the process of forming the metal layer 209, the metal layer 209 spans the first isolation layer 206, and since the height of the first isolation layer 206 is relatively low, the resistance of the metal layer 209 is relatively low, thereby improving the performance of the semiconductor structure.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a gate structure located on the substrate; A dielectric layer located on the substrate, wherein the dielectric layer covers the sidewall of the gate structure; An opening located in the dielectric layer, wherein the opening penetrates the gate structure in a direction perpendicular to an extension direction of the gate structure; A first isolation layer is located in the opening, wherein a top surface of the first isolation layer is lower than a top surface of the gate structure; source-drain doped regions within the fin structure located on both sides of the gate structure; A metal layer located in the dielectric layer, the metal layer is located on the first isolation layer, the metal layer is parallel to the gate structure, the metal layer is electrically connected to the source and drain doped regions, the upper portion of the first isolation layer is embedded in the metal layer, and the height of the portion of the first isolation layer embedded in the metal layer relative to the lower surface of the metal layer is H1; if the top surface of the first isolation layer is flush with the top surface of the gate structure, the height of the portion of the first isolation layer embedded in the metal layer relative to the lower surface of the metal layer is H2, then H1 <H2。 2. The semiconductor structure according to claim 1, wherein: The material of the first isolation layer includes a dielectric material, and the dielectric material includes silicon nitride.

3. The semiconductor structure according to claim 1, wherein: Also includes: a second isolation layer located in the opening, and the second isolation layer is located on the first isolation layer; The material of the second isolation layer is different from that of the first isolation layer, and the material of the second isolation layer is the same as that of the dielectric layer.

4. The semiconductor structure according to claim 1, wherein: The substrate includes a base and a plurality of fin structures located on the base; the gate structure spans across the plurality of fin structures; and the first isolation layer is located between adjacent fin structures.

5. The semiconductor structure according to claim 4, characterized in that The metal layer is electrically connected to the source-drain doped region on one side of the gate structure.

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dummy gate structure on the substrate; forming source-drain doped regions in the fin structure on both sides of the dummy gate structure; Forming a dielectric layer on the substrate, wherein the dielectric layer is located on the sidewall of the dummy gate structure, and the dielectric layer exposes the top surface of the dummy gate structure; forming an opening in the dielectric layer, wherein the opening penetrates the dummy gate structure in a direction perpendicular to an extension direction of the dummy gate structure; forming a first isolation layer in the opening, wherein a top surface of the first isolation layer is lower than a top surface of the dummy gate structure; forming a second isolation layer on the first isolation layer, wherein the second isolation layer is located in the opening; removing a portion of the second isolation layer and the dielectric layer to form a groove in the dielectric layer; A metal layer is formed in the groove, the metal layer is located on the first isolation layer, the metal layer is parallel to the pseudo gate structure, the metal layer is electrically connected to the source and drain doped regions, the upper portion of the first isolation layer is embedded in the metal layer, and the height of the portion of the first isolation layer embedded in the metal layer relative to the lower surface of the metal layer is H1; if the top surface of the first isolation layer is flush with the top surface of the gate structure, the height of the portion of the first isolation layer embedded in the metal layer relative to the lower surface of the metal layer is H2, then H1 <H2。 7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first isolation layer includes a dielectric material, and the dielectric material includes silicon nitride.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first isolation layer includes: forming a first isolation material layer in the opening; etching back the first isolation material layer until the side wall of the dummy gate structure is exposed, so that the top surface of the first isolation layer is lower than the top surface of the dummy gate structure.

9. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second isolation layer is different from that of the first isolation layer, and the material of the second isolation layer is the same as that of the dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the second isolation layer includes a dielectric material, and the dielectric material includes silicon oxide.

11. The method for forming a semiconductor structure according to claim 9, wherein: The substrate includes a base and a plurality of fin structures located on the base; the dummy gate structure spans across the plurality of fin structures.

12. The method for forming a semiconductor structure according to claim 6, wherein: The groove exposes the surface of the source-drain doped region on one side of the dummy gate structure and the surface of the first isolation layer; the metal layer is electrically connected to the source-drain doped region on one side of the dummy gate structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: Before removing part of the second isolation layer and the dielectric layer to form the groove, the method further includes: removing the dummy gate structure to form a gate opening in the dielectric layer; forming a gate structure in the gate opening, wherein the gate structure includes an effective gate structure and an ineffective gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: Before removing a portion of the second isolation layer and the dielectric layer to form the groove, the method further includes: removing the ineffective gate structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The process of removing the ineffective gate structure includes a wet etching process.

16. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the second isolation layer includes: forming a second isolation material layer on the first isolation layer and the dielectric layer; and planarizing the second isolation material layer until the surface of the dielectric layer is exposed to form the second isolation layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process of forming the second isolation material layer includes a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the opening comprises: forming a patterned mask structure on the top surface of the pseudo gate structure and the surface of the dielectric layer, wherein the patterned mask structure exposes a portion of the top surface of the pseudo gate structure and the surface of the dielectric layer; etching the pseudo gate structure and the dielectric layer using the patterned mask structure as a mask to form an opening in the dielectric layer and the pseudo gate structure.

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