Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device. The semiconductor memory device includes a stacked structure and a slit structure. The stacked structure includes an insulating layer and a conductive layer alternately stacked with the insulating layer. The slit structure is configured to divide the stacked structure into memory blocks. A portion of the slit structure configured to define one memory block has a dotted line shape including a slit region and a bridge region.

Description

Technical Field

[0001] Various embodiments relate generally to a three-dimensional semiconductor memory device, and more particularly, to a slit structure configured to partition blocks of a nonvolatile memory device. Background Art

[0002] In order to provide a semiconductor memory device with good performance at a low price, it may be necessary to increase the integration degree of the semiconductor memory device. The integration degree of the semiconductor memory device is an important factor in determining the cost of a product including the semiconductor memory device.

[0003] In a two-dimensional or planar semiconductor memory device, the integration of the two-dimensional or planar semiconductor memory device may be determined by the area of ​​the unit memory cell, so that the integration may be affected by the technology used to form fine patterns. However, since expensive equipment may be used to form fine patterns, although the integration is slightly improved, the integration of the two-dimensional semiconductor memory device may be limited. In order to overcome this limitation, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell may be considered. In addition, in order to increase the integration density, the number of stacks of the three-dimensional semiconductor memory device may be increased. Therefore, when a slit is formed to divide a block of a semiconductor memory device, the shape of the block structure may change due to the high aspect ratio. Summary of the invention

[0004] Some embodiments are directed to a three-dimensional semiconductor memory device capable of maintaining the shape of a memory block.

[0005] In an example embodiment of the present disclosure, a semiconductor memory device may include a stacked structure and a slit structure. The stacked structure may include an insulating layer and a conductive layer alternately stacked with the insulating layer. The slit structure may be configured to divide the stacked structure into memory blocks. A portion of the slit structure is configured to define a memory block and is configured to have a dotted line shape including a slit region and a bridge region.

[0006] In an example embodiment of the present disclosure, a semiconductor memory device may include a plurality of memory blocks. Each memory block may include a line structure. The memory blocks may be divided by a slit structure. The line structure of any one of the plurality of memory blocks may be electrically connected to a line structure of a selected memory block among the plurality of memory blocks via at least one bridging region.

[0007] In example embodiments, the memory block may include a cell array region and a slimming region. The slimming region may include a plurality of contact regions. The contact regions may be located on both sides of the cell array region. The contact regions may be configured to contact the electrical signal line.

[0008] In example embodiments, the bridge region may be formed in the cell array region and the thinning region. Alternatively, the bridge region may be formed only in the thinning region.

[0009] In an example embodiment of the present disclosure, a semiconductor memory device may include a plurality of memory blocks. The memory blocks may be divided by a slit structure. The slit structure may include a first slit portion and a second slit portion and a third slit portion and a fourth slit portion. The first slit portion and the second slit portion may extend in a first direction. The first slit portion and the second slit portion may be alternately arranged in parallel with each other. The third slit portion and the fourth slit portion may extend in a second direction substantially perpendicular to the first direction. The third slit portion and the fourth slit portion may be alternately arranged in parallel with each other. The third slit portion may be connected between a first end of the first slit portion and a first end of the second slit portion. The fourth slit portion may be connected between a second end of the first slit portion and a second end of the second slit portion. The first slit portion may have a slit area. The second slit portion may have a dotted line shape including a slit area and at least one bridging area.

[0010] In an example embodiment of the present disclosure, a semiconductor memory device may include a memory block and a slit structure. The memory block may include a cell array region and a thinning region. The thinning region may include a plurality of contact regions. The memory block may be divided by the slit structure. The contact regions may be arranged in a stepped manner along a first direction and a second direction in the thinning region to divide the thinning region into a high-step region and a low-step region relative to the second direction. The slit structure may include a first slit portion and a second slit portion, the first slit portion being configured to divide a portion including a high-step region, and the second slit portion being configured to divide a portion including a low-step region. The second slit portion may include a slit region and a bridging region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a nonvolatile memory device according to an example embodiment;

[0013] Figure 2 is an equivalent circuit diagram showing a memory block according to an example embodiment;

[0014] Figure 3 is a plan view showing a semiconductor memory device according to an example embodiment;

[0015] Figure 4 is a perspective view showing arrangement of word lines in a thinned region according to example embodiments;

[0016] Figure 5 is along Figure 4 A cross-sectional view taken along line V-V';

[0017] Figure 6 is a perspective view showing adjacent word lines along the z direction in a first stepped region according to example embodiments;

[0018] Figure 7 is a perspective view showing a first line structure of a thinning area according to an example embodiment;

[0019] Figure 8 is along Figure 7 A cross-sectional view taken along line VII-VII';

[0020] Fig. 9 is a perspective view showing a first line structure of a thinning area according to an example embodiment;

[0021] Fig.10 is along Fig. 9 A cross-sectional view taken along line XI-XI';

[0022] Fig.11 is a plan view showing a memory block of a semiconductor memory device according to an example embodiment;

[0023] Fig.12 is a plan view showing a slit structure for defining a memory block according to an example embodiment;

[0024] Fig.13A and Fig. 13B is a plan view showing a slit structure for partitioning a cell array region of a memory block according to an example embodiment;

[0025] Fig.14A It is shown Fig.13A A stereogram of the cell array region in FIG.

[0026] Fig. 14B It is shown Fig. 13B A stereogram of a cell array region;

[0027] Fig.15 is a plan view showing a slit structure for dividing a thinning area of ​​a memory block according to an example embodiment;

[0028] Fig.16 It is shown Fig.15 A stereogram of the thinned area;

[0029] Fig.17 is a plan view showing a slit structure for dividing a thinning area of ​​a memory block according to an example embodiment;

[0030] Fig.18 It is shown Fig.17 A stereogram of the thinned area in FIG.

[0031] Fig.19 is a plan view showing a plurality of memory blocks according to example embodiments;

[0032] Fig. 20 is a block diagram illustrating a memory system according to an example embodiment;

[0033] Fig.21 is a block diagram illustrating a memory system according to an example embodiment;

[0034] Fig. 22 is a block diagram illustrating a computing system according to an example implementation; and

[0035] Fig.23 is a block diagram illustrating a computing system according to an example implementation. DETAILED DESCRIPTION

[0036] Various embodiments of the present teachings will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments (and intermediate structures). Therefore, deviations in the illustrated configurations and shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present teachings as defined by the appended claims.

[0037] The present teaching is described herein with reference to the cross-section and / or plan views of idealized embodiments. However, the manner in which the present teaching is presented should not be construed as a limitation of the present teaching. Although some embodiments of the present teaching will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be changed without departing from the principles and spirit of the present teaching.

[0038] Figure 1 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

[0039] Reference Figure 1 , a nonvolatile memory device 100 of example embodiments may include a memory cell array 110 , a row decoder 120 , a page buffer circuit 130 , and a peripheral circuit 140 .

[0040] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKn. Figure 1Although not shown in the figure, each of the memory blocks BLK1 to BLKn may include a plurality of memory cells. The memory cells may be accessed through word lines and bit lines. The memory cells may include nonvolatile memory cells configured to retain stored data without power supply. However, the memory cells are not limited to nonvolatile memory cells.

[0041] Furthermore, in the following, a nonvolatile memory device may include a vertical NAND flash memory device (not limited to a specific type).

[0042] The memory cell array 110 may include a plurality of first line structures L1 and a plurality of second line structures L2 configured to define memory cells. The first line structure L1 may include a word line. The second line structure L2 may include a bit line intersecting the first line structure L1. In example embodiments, each of the memory blocks BLK1 to BLKn may include one first line structure L1.

[0043] The first line structure L1 may extend to the row decoder 120. The first line structure L1 may be electrically connected to the row decoder 120. Each first line structure L1 may include at least one drain selection line, a plurality of word lines, and at least one source selection line. For example, one first line structure L1 may form a memory block BLK. The row decoder 120 may select any one of the memory blocks BLK1 to BLKn of the memory cell array 110 according to the address information. The row decoder 120 may send the operation voltage Vop to the selected memory block through the first line structure L1. For example, the operation voltage Vop may include a programming voltage, a pass voltage, and a read voltage. The operation voltage Vop may be received from the peripheral circuit 140. Although not shown in the drawings, in order to selectively provide the operation voltage Vop to the selected memory blocks BLK1 to BLKn, the row decoder 120 may include a pass switch element.

[0044] The page buffer circuit 130 may be electrically connected to the second line structure L2. The page buffer circuit 130 may include a plurality of page buffers PB connected to the respective second line structures L2. The page buffer circuit 130 may receive a page buffer control signal PB_C from the peripheral circuit 140. Data may be transmitted between the page buffer circuit 130 and the peripheral circuit 140.

[0045] The page buffer circuit 130 may control the second line structure L2 (i.e., the bit line) connected to the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 130 may sense the voltage level of the bit line in the memory cell array 110 in response to the page buffer control signal PB_C to detect the data in the memory cell. The page buffer circuit 130 may send the detected data to the peripheral circuit 140. The page buffer circuit 130 may apply a voltage that may correspond to the data to the bit line based on the page buffer control signal PB_C and the data to perform a programming operation. The page buffer circuit 130 may program the data into the memory cell connected to the word line that may be activated by the row decoder 120, or may read the data in the memory cell.

[0046] The peripheral circuit 140 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from an external device (e.g., a controller) of the semiconductor memory device 100. Data may be transmitted between the peripheral circuit 140 and the controller. The peripheral circuit 140 may program data into a selected memory cell of the memory cell array based on the command signal CMD, the address signal ADD, and the control signal CTRL. The peripheral circuit 140 may output a signal for reading data in a memory cell, such as a row address signal X-add, a page buffer control signal PB_C, etc. The peripheral circuit 140 may generate various voltages required in the semiconductor memory device 100, such as an operating voltage Vop.

[0047] Figure 2 is an equivalent circuit diagram illustrating a memory block according to example embodiments.

[0048] Reference Figure 2 , the memory block BLKi may include a second line structure L2 (ie, a bit line BL), and a plurality of cell strings CSTR connected between the bit line BL and a common source line CSL.

[0049] The second line structures L2 may extend parallel to each other in the y-direction. The cell strings CSTR may be connected in parallel between the second line structures L2 and the common source line CSL.

[0050] Each cell string CSTR may include a drain select transistor DST connected to a second line structure L2 (i.e., a bit line BL), a source select transistor SST connected to a common source line CSL, and a plurality of memory cells MC connected between the drain select transistor DST and the source select transistor SST. The drain select transistor DST, the memory cells MC, and the source select transistor SST may be connected in series to each other in the z direction.

[0051] The drain selection line DSL, the plurality of word lines WL, and the source selection line SSL may be stacked in the space between the second line structure L2 and the common source line CSL. The drain selection line DSL, the word lines WL, and the source selection line SSL may extend in the x direction. The drain selection line DSL may be connected to the gate of each corresponding drain selection transistor DST. The word line WL may be connected to the gate of each corresponding memory cell MC. The source selection line SSL may be connected to the gate of each corresponding source selection transistor SST.

[0052] Figure 3 is a plan view illustrating a semiconductor memory device according to example embodiments.

[0053] Reference Figure 3 , four memory cell arrays 110-1 to 110-4 may be arranged in a matrix shape along the x-direction and the y-direction on the semiconductor substrate. The memory cell arrays 110-1 to 110-4 may correspond to a plane of the nonvolatile memory device.

[0054] The row decoders 120-1 to 120-4 may be arranged at a first edge portion of the memory cell arrays 110-1 to 110-4. For example, the row decoders 120-1 to 120-4 may be arranged at a first edge portion among edge portions of the memory cell arrays 110-1 to 110-4 parallel to the y direction.

[0055] The page buffer circuits 130-1 to 130-4 may be arranged at a second edge portion of the memory cell arrays 110-1 to 110-4 adjacent to the first edge portion. For example, the page buffer circuits 130-1 to 130-4 may be arranged at a second edge portion of the edge portions of the memory cell arrays 110-1 to 110-4 parallel to the x direction.

[0056] The peripheral circuits 140 may be dispersedly arranged between the memory cell arrays 110 - 1 to 110 - 4 . Figure 3 The memory cell arrays 110-1 to 110-4, the row decoders 120-1 to 120-4, the page buffer circuits 130-1 to 130-4, and the peripheral circuit 140 are shown on the same plane. However, the memory cell arrays 110-1 to 110-4, the row decoders 120-1 to 120-4, the page buffer circuits 130-1 to 130-4, and the peripheral circuit 140 may be located on different planes on the surface of the semiconductor substrate.

[0057] The first line structure L1 of the memory cell arrays 110-1 to 110-4 may be electrically connected to the row decoders 120-1 to 120-4 (particularly, to the transfer transistors (not shown) of the row decoder 120-1). In order to effectively connect the conductive wires of the first line structure L1 to the transfer transistors, the first line structure L1 may need to be thinned.

[0058] For example, the first line structure L1 in one memory block BLKi may include a source selection line SSL, a word line WL, and a drain selection line DSL stacked in sequence. In order to provide an electrical signal from a pass transistor to the source selection line SSL, the word line WL, and the drain selection line DSL, a thinning process may be performed to provide different extension lengths for the source selection line SSL, the word line WL, and the drain selection line DSL. Portions of the source selection line SSL, the word line WL, and the drain selection line DSL having different extension lengths may be referred to as a thinning region 150.

[0059] Since the integration degree of the semiconductor memory device may have been increased, the number of memory cells on one memory block BLKi may be greatly increased. Therefore, the number of word lines WL in the first line structure L1 may also be significantly increased. Therefore, it is difficult to form a contact area for supplying voltage to the source selection line SSL, the word line WL, and the drain selection line DSL in the defined thinning area 150.

[0060] Recently, a portion of the width of the conductive layers SSL, WL, and DSL in the first line structure L1 may be used for the contact region.

[0061] Figure 4 is a perspective view showing an arrangement of word lines in a thinned region according to example embodiments, Figure 5 is along Figure 4 A cross-sectional view taken along line V-V' in FIG. Figure 6 is a perspective view illustrating adjacent word lines in a z-direction in a first stepped region according to example embodiments.

[0062] For ease of explanation, word lines WL1 to WL36 in the conductive lines in the first line structure may be shown. Figures 4 to 6 The arrangement of word lines in a unit memory block divided by slits is shown.

[0063] Reference Figures 4 to 6 , the word lines WL1 to WL36 in the first line structure L1 may be sequentially stacked in the z direction. The word lines WL1 to WL36 in the thinning region 150 may have a changed length and a changed width to make the word lines WL1 to WL36 electrically contact the row decoders 120-1 to 120-4, thereby forming word line contact regions WC1 to WC36.

[0064] For example, the word lines WL1 to WL36 in the thinning region 150 may be divided into four classes (layers) so that each class has the same length and a different width (ie, word line contact area). However, the word lines WL1 to WL36 in the memory cell arrays 110-1 to 110-4 may include the same width and the same length.

[0065] For example, the thirty-sixth to thirty-third word lines WL36 to WL33 may have substantially the same length in the x-direction of the thinning region 150. The original width of the thirty-sixth word line WL36 in the thinning region 150 may be thinned to provide the thirty-sixth word line WL36 with a width of about 1 / 4 times the original width. The original width of the thirty-fifth word line WL35 in the thinning region 150 may be thinned to provide the thirty-fifth word line WL35 with a width of about 2 / 4 times the original width. The original width of the thirty-fourth word line WL34 in the thinning region 150 may be thinned to provide the thirty-fourth word line WL34 with a width of about 3 / 4 times the original width. The thirty-third word line WL33 may have an original width. Because the upper word line in the thinning region 150 may have a reduced width, a portion of the lower word line in the thinning region 150 that may have an area of ​​about 1 / 4 times the original area of ​​the lower word line may be exposed. As a result, the width of the word line contact regions WC36 to WC33 may be approximately 1 / 4 times the original width of the word line. Figure 4 From the VV′ direction in FIG. 1 , the word lines WL1 to WL36 may be divided into first to fourth stepped regions r1 to r4 .

[0066] In addition, the length of the thirty-second word line WL32 to the twenty-ninth word line WL29 may be longer by "d" than the length of the thirty-sixth word line WL36 to the thirty-third word line WL33. In the thinning region 150, the thirty-second word line WL32 to the twenty-ninth word line WL29 may form the word line contact regions WC32 to WC29 with a rule substantially the same as the rule of the thirty-sixth word line WL36 to the thirty-third word line WL33 for forming the word line contact regions WC36 to WC33. Therefore, the remaining word lines WL28 to WL1 and the remaining word line contact regions WC28 to WC1 may be arranged with the rule. Therefore, the first line structure L1 including the stacked word lines WL1 to WL36 in the thinning region 150 may have a stepped structure along the length direction and the lateral direction (i.e., the x direction and the y direction) of the word lines.

[0067] The word line contact region of example embodiments may have a structure different from that described above.

[0068] Figure 7 is a perspective view showing a first line structure of a thinning area according to an example embodiment, and Figure 8 is along Figure 7 A cross-sectional view taken along line VII-VII'.

[0069] Figure 7 FIG. 4 shows word line contact regions WC1 to WC36 of two adjacent memory blocks BLK before being divided into memory blocks by slits Sx. Figure 7 and Figure 8 In the embodiment, an insulating layer may be interposed between the word line contact regions WC1 to WC36.

[0070] Reference Figure 7 and Figure 8 , the word lines WL1 to WL36 in the first line structure L1 may be divided into four stepped regions r1, r2, r3, and r4 to control the length and width of the word lines WL1 to WL36. Each of the stepped regions r1, r2, r3, and r4 includes 9 word lines.

[0071] For example, the thirty-sixth to twenty-eighth word lines WL36 to WL28 in the thinning region 150 may be thinned to provide the thirty-sixth to twenty-eighth word lines WL36 to WL28 with a width of about 1 / 4 times the original width of the thirty-sixth to twenty-eighth word lines WL36 to WL28. Therefore, the thirty-sixth to twenty-eighth word lines WL36 to WL28 may define thirty-sixth to twenty-eighth word line contact regions WC36 to WC28 in the first stepped region r1. The thirty-sixth to twenty-eighth word lines WL36 to WL28 in the first stepped region r1 may have a length that gradually increases from the upper portion to the lower portion in the thirty-sixth to twenty-eighth word lines WL36 to WL28 by a length d.

[0072] The 27th to 19th word lines WL27 to WL19 in the thinning region 150 may be thinned to provide the 27th to 19th word lines WL27 to WL19 with a width of about 2 / 4 times the original width of the 27th to 19th word lines WL27 to WL19. Therefore, the 27th to 19th word lines WL27 to WL19 may define 27th to 19th word line contact regions WC27 to WC19 in the second step region r2. The 27th to 19th word lines WL27 to WL19 in the first and second step regions r1 and r2 of the thinning region 150 may have a length that gradually increases by a length d from the upper portion to the lower portion in the 27th to 19th word lines WL27 to WL19.

[0073] The eighteenth word lines WL18 to the cross lines WL10 in the thinning region 150 may be thinned to provide the eighteenth word lines WL18 to the cross lines WL10 with a width of about 3 / 4 times the original width of the eighteenth word lines WL18 to the cross lines WL10. Therefore, the eighteenth word lines WL18 to the cross lines WL10 may define eighteenth word line contact regions WC18 to the cross line contact regions WC10 in the third step region r3. The eighteenth word lines WL18 to the cross lines WL10 in the first to third step regions r1, r2, and r3 of the thinning region 150 may have a length that gradually increases from the upper portion to the lower portion in the eighteenth word lines WL18 to the cross lines WL10 by a length d.

[0074] The ninth word line WL9 to the first word line WL1 may have an original width. The ninth word line WL9 to the first word line WL1 may define the ninth word line contact area WC9 to the first word line contact area WC1 in the fourth step region r4 by the tenth contact area WC10 to the thirty-sixth contact area WC36 above the ninth word line WL9 to the first word line WL1. The ninth word line WL9 to the first word line WL1 in the first to fourth step regions r1, r2, r3, and r4 of the thinning region 150 may have a length that gradually increases from the upper portion to the lower portion in the ninth word line WL9 to the first word line WL1 by a length d.

[0075] The structure may also have a relatively high stepped portion between the first to fourth stepped regions r1 , r2 , r3 , and r4 of the first line structure L1 .

[0076] Fig. 9 is a perspective view showing a first line structure of a thinning area according to an example embodiment, and Fig.10 is along Fig. 9 A cross-sectional view taken along line XI-XI'.

[0077] Fig. 9 Word line contact regions WC1 to WC20 of two adjacent memory blocks BLK before being divided into memory blocks by the slits Sx are shown.

[0078] Reference Fig. 9 and Fig.10 , the word lines in the first line structure L1 may be divided into a plurality of categories to control the length and width of the word lines. In example embodiments, the word line contact regions WC20 to WC1 may have two stepped regions r1 and r2.

[0079] A method of forming a structure having a thinned region is disclosed in U.S. Patent Application Publication 2020 / 0020714A1 filed on December 14, 2018, the entire contents of which are incorporated herein by reference. In addition, the thinned structure of the first line structure L1 according to example embodiments should not be limited to the above-described example embodiments.

[0080] Fig.11 is a plan view illustrating a memory block of a semiconductor memory device according to example embodiments.

[0081] Reference Fig.11 , the source selection line SSL, the word line WL, and the drain selection line DSL in the first line structure L1 may be formed to have a step shape in the thinning area 150. In addition, the source selection line SSL, the word line WL, and the drain selection line DSL may be divided into the memory block BLK by the slit S. The slit S may play a role in dividing the sacrificial layer (rather than the conductive layer in the first line structure L1) used to form the first line structure L1. That is, the alternately stacked sacrificial layer and the insulating layer may be divided into the memory block BLK by the slit S. The sacrificial layer may then be removed. A conductive layer may be formed in the space formed by removing the sacrificial layer to form the first line structure L1 of the memory block BLK. In example embodiments, defining the first line structure L1 by the slit S may be interpreted as including the above-described process.

[0082] The memory block BLK may be divided into a cell array region CA and a thinning region 150. The thinning region 150 may be located between the cell array region CA and the row decoder 120. Figures 4 to 10 As shown, the thinning region 150 may have first to fourth step regions r1, r2, r3, and r4 in the y direction with the step portion in the x direction. Figure 7 and 9 As shown, in order to easily form the step regions r1, r2, r3, and r4, the step regions r1, r2, r3, and r4 of the thinning region 150 may be symmetrically arranged with the step regions r1, r2, r3, and r4 of the adjacent memory block BLK. Therefore, in the thinning region 150 of the adjacent memory block BLK, the relatively lower step regions r4 or the relatively higher step regions r1 may face each other.

[0083] As a result, the slits S extending along the x-direction in the thinning region 150 may have different heights. For example, the first slit S1 configured to divide the relatively lower step region r4 may have a relatively lower height. Conversely, the second slit S2 configured to divide the relatively higher step region r1 may have a relatively higher height. The height difference between the first slit S1 and the second slit S2 in the thinning region 150 may cause the first slit S1 to lean toward the memory block BLK. That is, the center of gravity of the thinning region 150 may lean toward the relatively higher step region (e.g., the first step region r1). Therefore, due to the structural difference between the first slit S1 and the second slit S2, the memory block BLK may bend in the thinning region 150. As Figure 5 , Figure 8 and Fig.10 As shown, reference numeral "B" may represent a bending force of the memory block BLK. The bending of the memory block BLK may cause the first slit S1 and the second slit S2 to have different sizes. When a material may be formed in the first slit S1 and the second slit S2 to form a slit structure, the different sizes of the first slit S1 and the second slit S2 may cause unevenness of the slit structure and different sizes of seams in the slit structure, thereby degrading the electrical characteristics of the nonvolatile memory device.

[0084] In example embodiments, in order to address unevenness in the width of the slits caused by the bending of the memory block BLK, the shapes of the slits and the memory blocks may be changed.

[0085] Fig.12 is a plan view illustrating a slit structure for defining a memory block according to example embodiments.

[0086] Reference Fig.12 , a portion of the slit structure Sa configured to define the memory block BLK may have a dotted line shape.

[0087] For example, the slit structure Sa may include a first slit portion Sx1 and a second slit portion Sx2 and a third slit portion Sy1 and a fourth slit portion Sy2. The first slit portion Sx1 and the second slit portion Sx2 may extend parallel to each other in the x direction (e.g., the extension direction of the word line). The third slit portion Sy1 and the fourth slit portion Sy2 may extend parallel to each other in the y direction (e.g., the extension direction of the bit line). The first slit portion Sx1 and the second slit portion Sx2 may be spaced apart from each other by a gap substantially the same as the width of the memory block BLK. The third slit portion Sy1 and the fourth slit portion Sy2 may be spaced apart from each other by a gap substantially the same as the length of the first line structure L1.

[0088] The first slit portion Sx1 may have a solid line shape. The second slit portion Sx2 may have a dotted line shape including a slit region SR and a bridge region BR. The slit region SR may correspond to a space configured to divide the memory block BLK. The slit region SR may have a length or size that allows an etchant capable of completely removing a sacrificial layer of the memory block BLK to pass through.

[0089] As described above, the positions of the source selection line, the word line, and the drain selection line in the first line structure L1 may be determined by the sacrificial layer. Since the sacrificial layer may be removed by an etchant provided through the sidewall of the slit region SR, the size of the slit region SR may be determined in consideration of removing the sacrificial layer. Therefore, the length or size of the bridge region BR may be set according to the length of the slit region SR. The first slit portion Sx1 of the solid line may include only the slit region SR without the bridge region BR.

[0090] In example embodiments, before forming the first line structure L1, the slit region SR may be an empty space. After forming the first line structure L1, the slit region SR may be filled with a filling material, so that the slit region SR may be interpreted as a slit structure. Therefore, according to the corresponding state, the slit, the slit structure, and the slit region may be interpreted as a space or structure including an insulating material.

[0091] In addition, the third and fourth slit portions Sy1 and Sy2 may divide a space between the slimming region 150 and the row decoder 120. Alternatively, the third and fourth slit portions Sy1 and Sy2 may include only a solid line region without a bridge region BR.

[0092] As described above, the memory block BLK may be divided into the cell array region CA and the thinning region 150. The second slit portion Sx2 of a dotted line shape may be formed in the cell array region CA and the thinning region 150 or in at least one of the cell array region CA and the thinning region 150.

[0093] Fig.13A and Fig. 13B is a plan view showing a slit structure for partitioning a cell array region of a memory block according to an example embodiment, Fig.14A It is shown Fig.13A A stereogram of the cell array region in FIG. 1 , and Fig. 14B It is shown Fig. 13B A stereogram of the cell array area in FIG.

[0094] Reference Fig.13A and Fig. 13B , the cell array area CA of the memory block BLK may include a plurality of channel plugs CH and a plurality of support members. The channel plugs CH and the support members may be arranged in a uniform regular pattern.

[0095] Each channel plug CH may include a channel layer and a gate insulating layer. The channel layer may include a polysilicon layer, a single crystal silicon layer, etc. At least a portion of the channel layer may be doped with conductive impurities. The channel layer may have a columnar shape formed vertically through the memory block BLK relative to the substrate. Alternatively, the channel layer may have a tubular shape of an opening formed vertically through the substrate.

[0096] The gate insulating layer may be configured to surround the outer surface of the channel plug. The gate insulating layer may include a tunnel insulating layer, a charge storage layer, and a blocking layer. The gate insulating layer may be interposed between the channel plug CH and the conductive layer in the first line structure L1.

[0097] Supporters may be disposed between the channel plugs CH to fix the memory blocks BLK.

[0098] The cell array area CA may be divided into memory blocks BLK by a slit structure Sb. The slit structure Sb may include a solid line-shaped first slit portion Sx1 and a dotted line-shaped second slit portion Sx2. The first slit portion Sx1 and the second slit portion Sx2 may extend in the x-direction.

[0099] For example, Fig.13A As shown, the first slit portion Sx1 and the second slit portion Sx2 may be alternately arranged to define a cell array area CA of the memory block BLK. The second slit portion Sx2 may include at least one slit region SR and at least one bridge region BR.

[0100] like Fig.14A As shown, the adjacent cell array regions CA along the y direction may be partially electrically connected by the bridging region BR and may be separated by the slit region SR. In other words, the first line structures L1 of the first memory block BLK1 and the second memory block BLK2 may be electrically connected to each other through the bridging region BR. Therefore, the effective width EWB of the first memory block BLK1 and / or the second memory block BLK2 may be increased to about twice the width w of the original memory block BLK through the bridging region BR. As a result, the memory block BLK may have an improved aspect ratio to prevent or mitigate the bending of the memory block BLK, thereby obtaining a uniform slit structure Sb.

[0101] Alternatively, if Fig. 13B As shown, the cell array area CA of the memory block BLK may be defined only by the solid line-shaped first slit portion Sx1 .

[0102] When the cell array region CA includes only the first slit portion Sx1 of the solid line, as shown in FIG. Fig. 14BAs shown, the bridge region may not be used to completely separate the memory blocks BLK1 and BLK2. Therefore, the effective width EWB' of the cell array region CA may be substantially the same as the width w of the memory blocks BLK1 and BLK2.

[0103] Fig.15 is a plan view showing a slit structure for partitioning a thinning area of ​​a memory block according to an example embodiment, and Fig.16 It is shown Fig.15 Stereoscopic image of the thinned area in .

[0104] Reference Fig.15 and Fig.16 , the thinning region 150 may include a plurality of contact structures CT. The contact structures CT may be arranged in a uniform regular pattern to provide an operating voltage to the conductive line of the first line structure L1. For ease of explanation, Fig.15 and Fig.16 A portion of the contact structure CT is shown. For example, each contact structure CT may be electrically connected to Figures 4 to 10 The contact areas WC1 to WC36 in FIG.

[0105] The thinning region 150 may be divided by the slit structure Sb to define the memory block BLK. In order to divide the thinning region 150 of the adjacent memory block BLK into memory block units in the y direction, the solid line first slit portion Sx1 and the dotted line second slit portion Sx2 may be alternately arranged. Fig.16 As shown, the bridge region BR may be partially formed in the thinning region 150 of the memory block BLK divided by the second slit portion Sx2. The first line structure L1 may be partially connected between the thinning regions 150 of the adjacent memory blocks BLK through the bridge region BR.

[0106] Therefore, the effective width EWB of the memory block BLK may be increased by the bridge region BR formed in the thinning region 150. As a result, the memory block BLK may have an improved aspect ratio.

[0107] Fig.17 is a plan view showing a slit structure for partitioning a thinning area of ​​a memory block according to an example embodiment, and Fig.18 It is shown Fig.17 Stereoscopic image of the thinned area in .

[0108] Reference Fig.17 and Fig.18 , the thinned region 150 may be divided into memory blocks BLK by the slit structure Sd.

[0109] The thinning region 150 may include step regions r1, r2, r3, and r4 extending in the x-direction and the y-direction to ensure a plurality of contact regions. In addition, as described above, for ease of formation, the step regions r1, r2, r3, and r4 in the thinning region 150 may be arranged symmetrically with the adjacent step regions r1, r2, r3, and r4 in the y-direction in the thinning region 150. The step regions r1, r2, r3, and r4 may have a height that gradually increases from the step region r1 to the step region r4.

[0110] The slit structure Sd may include first slit portions Sx1 and second slit portions Sx2 arranged alternately. The slit structure Sd may further include third slit portions Sy1 and fourth slit portions Sy2 extending in the y direction. The first slit portion Sx1, the third slit portion Sy1, and the fourth slit portion Sy2 may have a solid line shape. The second slit portion Sx2 may include at least one slit region SR and at least one bridge region BR.

[0111] In example embodiments, the first slit portion Sx1 may be located between the first stepped regions r1 , and the second slit portion Sx2 may be located between the fourth stepped regions r4 .

[0112] In example embodiments, since the fourth stepped region r4 having a relatively low step may be divided by the second slit portion Sx2 of a dotted line, a bridge region BR may be formed between the thinning regions 150 of adjacent memory blocks BLK.

[0113] Because the bridge region BR of the first line structure L1 can be formed between the thinning regions 150 of the memory block BLK facing each other, the memory block BLK can be firmly fixed without bending. In addition, the effective width EWB of the thinning region 150 of the memory block BLK can be increased by the bridge region BR. Therefore, the aspect ratio of the memory block BLK can be improved to prevent or reduce the bending of the memory block BLK.

[0114] Fig.19 is a plan view illustrating a plurality of memory blocks according to example embodiments.

[0115] Reference Fig.19 In order to divide the memory blocks BLK1 to BLK9 of the semiconductor memory device along the y direction (e.g., the extending direction of the bit lines), the slit Se may include a plurality of solid line slit portions Sx1, Sx3, Sx5... and a plurality of dotted line slit portions Sx2, Sx4, Sx6...

[0116] In example embodiments, the solid line slit portions Sx1, Sx3, Sx5 ... and the dotted line slit portions Sx2, Sx4, Sx6 ... may be arranged alternately. In addition, the dotted line slit portions Sx2, Sx4, Sx6 ... may include different numbers of bridge regions BR. The dotted line slit portions Sx2, Sx4, Sx6 ... may be configured to divide a relatively lower step region of the memory block BLK.

[0117] For example, the first dotted slit portion Sx2 may have one bridge region BR. The second dotted slit portion Sx4 may have two bridge regions BR. Therefore, the nth dotted slit portion Sx2n may have n bridge regions BR. The length and / or number of the bridge regions BR may be set within a range that allows the sacrificial layer to be removed by an etchant provided through the slit region SR.

[0118] In example embodiments, the bridging regions BR may have a sequentially increasing shape. However, the bridging regions BR may be randomly arranged.

[0119] also, Fig.19 The memory blocks BLK1 to BLK9 in FIG. 1 may correspond to the cell array area CA or the thinning area 150 .

[0120] According to example embodiments, the slit region SR and the bridge region BR may have various shapes so that the memory block BLK having a high aspect ratio may be firmly fixed without being bent.

[0121] When a portion of the slits configured to divide the memory blocks may include a dotted line shape, the slits on the wafer may have a uniform width.

[0122] In example embodiments, the lines, word lines, and sacrificial layers in the first line structure L1 may have substantially the same shape. Although the lines may be illustrated as being mixed with each other, they may indicate the same structure.

[0123] In addition, the contact region of the line in the first line structure L1 (eg, the word line contact region) may have various structures without being limited to Figures 4 to 10 The structure in .

[0124] Fig. 20 is a block diagram of a configuration of a memory system 1000 according to an embodiment of the present disclosure.

[0125] like Fig. 20 As shown, the memory system 1000 may include a memory device 1200 and a controller 1100 .

[0126] The memory device 1200 may be used to store various data types such as text, graphics, and software code. The memory device 1200 may be a non-volatile memory. The memory device 1200 may be a memory device as described above with reference to FIG. Figures 1 to 19 Semiconductor device described. In addition, the memory device 1200 may include: an electrode structure, the electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a second direction, wherein each of the plurality of channel pillars includes a first pillar having a first shape on the uppermost plane and a second pillar having a second shape on the uppermost plane, and N (N is a natural number greater than or equal to 1) first pillars and N second pillars are alternately arranged in a first direction intersecting the second direction. In addition, the memory device 1200 may include: an electrode structure, the electrode structure including a plurality of gate conductive films stacked on a substrate; and a channel array, wherein a plurality of channel pillars passing through the electrode structure are arranged in a zigzag manner in the second direction, wherein the plurality of channel pillars include a first pillar having a first shape on the uppermost plane and a second pillar having a second shape different from the first shape on the uppermost plane, and in any one row of the channel array, N (N is a natural number greater than or equal to 1) first pillars and M (M is a natural number greater than or equal to 2) second pillars are alternately arranged in a first direction intersecting the second direction. Since the memory device 1200 is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

[0127] The controller 1100 may be coupled to the host and the memory device 1200, and may access the memory device 1200 in response to a request from the host. For example, the controller 1100 may control read, write, erase, and background operations of the memory device 1200.

[0128] The controller 1100 may include a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , and a memory interface 1150 .

[0129] The RAM 1110 may be used as a working memory of the CPU 1120, a cache memory between the memory device 1200 and the host, and a buffer memory between the memory device 1200 and the host. The RAM 1110 may be replaced by a static random access memory (SRAM) or a read only memory (ROM).

[0130] The host interface 1130 can interface with the host. For example, the controller 1100 can communicate with the host through one of various interface protocols including a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, an express PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a dedicated protocol.

[0131] The ECC circuit 1140 may detect and correct an error included in data read from the memory device 1200 by using an error correction code (ECC).

[0132] The memory interface 1150 may interface with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface.

[0133] For example, the controller 1100 may further include a buffer memory (not shown) configured to temporarily store data. The buffer memory may temporarily store data transmitted from the outside through the host interface 1130, or temporarily store data transmitted from the memory device 1200 through the memory interface 1150. In addition, the controller 1100 may further include a ROM storing code data for interfacing with the host.

[0134] As described above, since the memory system 1000 according to the embodiment of the present disclosure may be reliably manufactured and include the memory device 1200 having a stable structure and improved characteristics, the characteristics of the memory system 1000 may also be improved.

[0135] Fig.21 1 is a block diagram of a configuration of a memory system 1000 ′ according to an embodiment of the present disclosure. Hereinafter, description of common contents with the previously described embodiments is omitted.

[0136] like Fig.21 As shown, the memory system 1000' may include a memory device 1200' and a controller 1100. In addition, the controller 1100 may include a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, and a memory interface 1150.

[0137] The memory device 1200' may be a non-volatile memory device. The memory device 1200' may be the above reference Figures 1 to 19 Since the memory device 1200' is formed and manufactured in the above-described manner, a detailed description thereof will be omitted.

[0138] In addition, the memory device 1200' may be a multi-chip package consisting of a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups. The plurality of groups may communicate with the controller 1100 through the first channel CH1 to the kth channel CHk. In addition, the memory chips included in a single group may be suitable for communicating with the controller 1100 through a common channel. The memory system 1000' may be modified so that a single memory chip may be connected to a single channel.

[0139] As described above, since the memory system 1000' according to the embodiment of the present disclosure can be reliably manufactured and includes the memory device 1200' having a stable structure and improved characteristics, the characteristics of the memory system 1000' can also be improved. In addition, by forming the memory device 1200' using a multi-chip package, the data storage capacity of the memory system 1000' can be further increased.

[0140] Fig. 22 2 is a block diagram of a configuration of a computing system 2000 according to an embodiment of the present disclosure. Hereinafter, description of common contents with the previously described embodiments is omitted.

[0141] like Fig. 22 As shown, the computing system 2000 may include a memory device 2100 , a CPU 2200 , a random access memory (RAM) 2300 , a user interface 2400 , a power supply 2500 , and a system bus 2600 .

[0142] The memory device 2100 may store data input through the user interface 2400 and data processed by the CPU 2200. In addition, the memory device 2100 may be electrically coupled to the CPU 2200, the RAM 2300, the user interface 2400, and the power supply 2500. For example, the memory device 2100 may be coupled to the system bus 2600 through a controller (not shown), or may be directly coupled to the system bus 2600. When the memory device 2100 is directly coupled to the system bus 2600, the function of the controller may be performed by the CPU 2200 and the RAM 2300.

[0143] The memory device 2100 may be a non-volatile memory. Figures 1 to 19 The semiconductor memory device described above. Fig.21 As described above, the memory device 2100 may be a multi-chip package consisting of a plurality of memory chips.

[0144] The computing system 2000 having the above configuration may be one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional (3D) television, a digital recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a device for sending / receiving information in a wireless environment, one of various electronic devices for a home network, one of various electronic devices for a computer network, one of various electronic devices for a telematics network, an RFID device, and / or one of various devices for a computing system, and the like.

[0145] As described above, since the computing system 2000 according to the embodiment of the present disclosure can be reliably manufactured and includes the memory device 2100 having a stable structure and improved characteristics, the characteristics of the computing system 2000 are also improved.

[0146] Fig.23 is a block diagram of a computing system 3000 according to an embodiment of the present disclosure.

[0147] like Fig.23 As shown, computing system 3000 may include software layers including operating system 3100, application 3200, file system 3300, and translation layer 3400. In addition, computing system 3000 may include hardware layers such as memory system 3500.

[0148] The operating system 3100 manages software and hardware resources of the computing system 3000. The operating system 3100 may control program execution of the central processing unit. The application 3200 may include various application programs executed by the computing system 3000. The application 3200 may be a utility program executed by the operating system 3100.

[0149] The file system 3300 may refer to a logical structure configured to manage data and files present in the computing system 3000. The file system 3300 may organize files or data to be stored in the memory device 3500 according to rules. The file system 3300 may be determined according to the operating system 3100 used in the computing system 3000. For example, when the operating system 3100 is a system based on Microsoft Windows, the file system 3300 may be a file allocation table (FAT) or an NT file system (NTFS). In addition, when the operating system 3100 is a system based on Unix / Linux, the file system 3300 may be an extended file system (EXT), a Unix file system (UFS), or a journaled file system (JFS).

[0150] Fig.23 The operating system 3100, the application 3200, and the file system 3300 are shown as separate blocks. However, the application 3200 and the file system 3300 may be included in the operating system 3100.

[0151] In response to a request from the file system 3300, the translation layer 3400 may translate an address suitable for the memory device 3500. For example, the translation layer 3400 may translate a logical address generated by the file system 3300 into a physical address of the memory device 3500. Mapping information of the logical address and the physical address may be stored in an address translation table. For example, the translation layer 3400 may be a flash translation layer (FTL) or a universal flash storage link layer (ULL), etc.

[0152] The memory device 3500 may be a non-volatile memory. The memory device 3500 may be the memory device described above with reference to Figures 1 to 19 The semiconductor memory device described above. The computing system 3000 having the above configuration may be divided into an operating system layer operating in an upper layer area and a controller layer operating in a lower layer area. The operating system 3100, the application 3200, and the file system 3300 may be included in the operating system layer and driven by the working memory. In addition, the conversion layer 3400 may be included in the operating system layer or the controller layer.

[0153] The above embodiments of the present teachings are intended to illustrate rather than limit the present teachings. Various alternatives and equivalents are possible. The present teachings are not limited to the embodiments described herein. The present teachings are also not limited to any particular type of semiconductor device. Other additions, reductions, or modifications based on the present disclosure are possible and are intended to fall within the scope of the appended claims.

[0154] CROSS-REFERENCE TO RELATED APPLICATIONS

[0155] This application claims the benefit of Korean Application No. 10-2020-0059681 filed on May 19, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: A stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of conductive layers alternately stacked with the plurality of insulating layers; as well as a slit structure configured to divide the stack structure into a plurality of memory blocks, wherein a portion of the slit structure configured to define one of the plurality of memory blocks has a dotted line shape, the dotted line shape including a slit region and a bridge region, The one memory block includes a line structure, and the line structure includes a plurality of word lines. wherein the one memory block comprises a contact region for each of the plurality of word lines, wherein the line structure of the selected memory block among the plurality of memory blocks is electrically connected to the line structure of a memory block adjacent to the selected memory block among the plurality of memory blocks through at least one bridge region, wherein the memory block is divided into a cell array region and a thinning region, wherein the line structure in the thinned region includes a high-step region and a low-step region in a direction parallel to a direction in which the bit line extends, and wherein a slit portion formed between the low-step region of the one memory block and the low-step region of the adjacent memory block has the dotted line shape.

2. The semiconductor memory device according to claim 1, wherein The line structure also includes a source selection line and a drain selection line, and Wherein, the line structure constitutes the stacking structure.

3. The semiconductor memory device according to claim 2, wherein: The slit structure defining the one memory block includes: a first slit portion and a second slit portion, the first slit portion and the second slit portion extending in a direction parallel to an extending direction of the word line; and a third slit portion and a fourth slit portion, the third slit portion and the fourth slit portion extending in a direction parallel to a direction in which a bit line extends, the direction in which the bit line extends being perpendicular to a direction in which the word line extends, the third slit portion and the fourth slit portion being configured to connect both ends of the first slit portion and both ends of the second slit portion to each other, Wherein, a selected slit portion among the first slit portion and the second slit portion has the dotted line shape.

4. The semiconductor memory device according to claim 2, wherein: The thinned region is located between the cell array region and a row decoder configured to provide an electrical signal to the cell array region.

5. The semiconductor memory device according to claim 4, wherein: The source selection line, the word line and the drain selection line of the line structure in the thinned area include contact areas configured to receive the electrical signals, and wherein the line structure in the thinned area has a step area extending in a direction in which the multiple word lines extend and a direction in which the bit lines extend to define the contact areas.

6. The semiconductor memory device according to claim 5, wherein: The high-step region or the low-step region in the thinned region of the one memory block faces a high-step region or a low-step region of an adjacent memory block of the one memory block.

7. A semiconductor memory device comprising a plurality of memory blocks, wherein: Each of the plurality of memory blocks includes a line structure; The plurality of memory blocks are divided by a slit structure; and A line structure of a selected memory block among the plurality of memory blocks is electrically connected to a line structure of a first memory block adjacent to the selected memory block among the plurality of memory blocks through at least one bridge region, Wherein, the line structure includes a plurality of word lines, wherein each of the plurality of memory blocks comprises a contact region for each of the plurality of word lines, Each of the plurality of memory blocks includes a cell array region and a thinning region, wherein the thinning region is located on both sides of the cell array region. wherein the line structure in the thinned region of the selected memory block is divided into a high-step region and a low-step region in a direction in which the bit lines extend, and The at least one bridge region is located between the low-step region of the selected memory block and the low-step region of the first memory block.

8. The semiconductor memory device according to claim 7, wherein: The line structure of the selected memory block includes a source select line, the plurality of word lines, and a drain select line stacked in sequence, and wherein an insulating layer is interposed between the source select line, the plurality of word lines, and the drain select line.

9. The semiconductor memory device according to claim 7, wherein: The thinned region includes a plurality of contact areas for receiving electrical signals.

10. The semiconductor memory device according to claim 9, wherein: The at least one bridge region is arranged in the cell array region and the thinning region.

11. The semiconductor memory device according to claim 9, wherein: The at least one bridging region is arranged in the thinned region.

12. The semiconductor memory device according to claim 9, wherein: The line structure in the thinned region of the selected memory block is divided into the high-step region and the low-step region to expose the contact region.

13. The semiconductor memory device according to claim 12, wherein: One end of the selected memory block faces a low-step region of the first memory block, and the other end of the selected memory block faces a high-step region of a second memory block adjacent to the selected memory block among the plurality of memory blocks.

14. A semiconductor memory device, comprising: a slit structure configured to divide a plurality of memory blocks, The slit structure includes: a first slit portion and a second slit portion, the first slit portion and the second slit portion are alternately arranged and extend parallel to each other in a first direction; and a third slit portion and a fourth slit portion, the third slit portion and the fourth slit portion extend parallel to each other in a second direction perpendicular to the first direction, the third slit portion is configured to connect a first end of the first slit portion and a first end of the second slit portion to each other, and the fourth slit portion is configured to connect a second end of the first slit portion and a second end of the second slit portion to each other, wherein the first slit portion includes a slit region, wherein the second slit portion has a dotted line shape, the dotted line shape including the slit area and at least one bridge area, Each of the plurality of memory blocks comprises a line structure, wherein the line structure comprises a plurality of word lines, wherein each of the plurality of memory blocks comprises a contact region for each of the plurality of word lines, wherein the line structure of the selected memory block among the plurality of memory blocks is electrically connected to the line structure of a memory block adjacent to the selected memory block among the plurality of memory blocks through at least one bridge region, wherein the selected memory block includes a cell array region and a thinning region, wherein the line structure in the thinned region of the selected memory block is divided into a high-step region and a low-step region with respect to the second direction, and The first slit portion is located between high-step regions, and the second slit portion is located between low-step regions.

15. The semiconductor memory device according to claim 14, wherein: A plurality of the second slit portions include different numbers of the bridging regions.

16. The semiconductor memory device according to claim 14, wherein: The bridging regions of different second slit portions have different sizes.

17. The semiconductor memory device according to claim 14, wherein: The thinning region is arranged between the cell array region and the third slit portion and between the cell array region and the fourth slit portion, and Wherein, the bridge region of the second slit portion is located in at least one of the cell array region and the thinning region.

18. The semiconductor memory device according to claim 17, wherein: The line structure in the thinned region of the selected memory block includes a plurality of contact regions configured to contact electrical signal lines, and The high-step region and the low-step region extend along the first direction and the second direction to expose the contact region.

19. A semiconductor memory device, comprising: a memory block including a cell array region and a thinning region including a plurality of contact regions for each of word lines included in the memory block; as well as a slit structure configured to divide the memory block, The thinned region is divided into a high-step region and a low-step region relative to the second direction, and the high-step region and the low-step region extend in the first direction and in the second direction perpendicular to the first direction. wherein the slit structure includes a first slit portion and a second slit portion, the first slit portion is configured to divide a portion including the high-step region, and the second slit portion is configured to divide a portion including the low-step region, the second slit portion includes a slit region and a bridge region, and The line structure of the selected memory block among the memory blocks is electrically connected to the line structure of the memory block adjacent to the selected memory block in the second direction among the memory blocks through at least one bridge region.

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