Semiconductor device and method for manufacturing semiconductor structure

Abstract

The semiconductor device includes a fin structure protruding vertically from a substrate, wherein the fin structure includes silicon germanium (SiGe). An epitaxial silicon layer is disposed on a sidewall of the fin structure. The epitaxial silicon layer includes nitrogen. One or more dielectric liner layers are disposed on the epitaxial silicon layer. A dielectric isolation structure is disposed above the one or more dielectric liner layers. Embodiments of the present application also relate to a method for manufacturing a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of manufacturing semiconductor structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while their geometry (i.e., the smallest component or line that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of IC processing and manufacturing.

[0003] For example, as semiconductor devices continue to scale down, silicon germanium has been used to form the channel region of a P-type transistor. However, a silicon germanium channel oxidizes faster than a silicon channel. Conventional semiconductor manufacturing methods do not adequately account for this difference. As a result, conventional methods of manufacturing semiconductor devices with silicon germanium channels may experience performance degradation or reduced yield.

[0004] Thus, while conventional methods of fabricating semiconductor devices are generally adequate, they have not been satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes: forming a fin structure protruding vertically from a substrate; epitaxially growing a silicon layer on the surface of the fin structure; performing a first rapid thermal nitridation (RTN) process, wherein the first rapid thermal nitridation process injects nitrogen into the epitaxially grown silicon layer; after the first rapid thermal nitridation process has been performed, forming a dielectric liner layer above the epitaxially grown silicon layer; and forming a dielectric isolation structure above the dielectric liner layer.

[0006] Other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: patterning a silicon germanium material into a p-type fin structure, wherein the patterning comprises one or more etching processes; growing an epitaxial layer on the p-type fin structure; injecting nitrogen into the epitaxial layer; after the nitrogen has been injected into the epitaxial layer, depositing a silicon oxide liner layer on the epitaxial layer; injecting nitrogen into the silicon oxide liner layer; and after the nitrogen has been injected into the silicon oxide liner layer, forming a shallow trench isolation (STI) structure above the silicon oxide liner layer.

[0007] Still other embodiments of the present application provide a semiconductor device, comprising: a fin structure protruding vertically from a substrate, wherein the fin structure contains silicon germanium (SiGe); an epitaxial silicon layer disposed on a sidewall of the fin structure, wherein the epitaxial silicon layer contains nitrogen; one or more dielectric liner layers disposed on the epitaxial silicon layer; and a dielectric isolation structure disposed above the one or more dielectric liner layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A is a perspective view of an IC device in the form of a fin field effect transistor (FinFET) according to various aspects of the present invention.

[0010] Figure 1B is a top plan view of a FinFET-format IC device according to various aspects of the present invention.

[0011] Figure 1C is a perspective view of an IC device in the form of a GAA device according to various aspects of the present invention.

[0012] Figure 2-Figure 10 are cross-sectional side views of various embodiments of IC devices at various stages of fabrication according to various aspects of the present invention.

[0013] Fig.11 is a circuit diagram of an SRAM cell according to various aspects of the present invention.

[0014] Fig.12 is a block diagram of a manufacturing system according to various aspects of the present invention.

[0015] Fig.13 is a flowchart illustrating a method of manufacturing a semiconductor device according to various aspects of the present invention.

[0016] Fig.14A , Fig. 14B and Fig. 14C are various 3D and cross-sectional views of the results of an etching step according to some embodiments.

[0017] Fig.15A , Fig. 15B and Fig. 15C According to some embodiments, FIG. 14A to FIG. 14C Various 3D and cross-sectional views of the structures formed by the etching steps. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed. Moreover, in the subsequent description of the present invention, forming a component on another component, connecting a component to and / or coupling it to another component may include embodiments in which the components are directly contacted, and may also include additional components that can form an inserted component, so that the components may not be directly contacted. In addition, in order to facilitate understanding of the relationship between one component of the present invention and another component, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above...", "above...", "below...", "below...", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used. Spatial relative terms are intended to include different orientations of the device in use or operation. Further, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a numerical value within a reasonable range including the described numerical value (such as, within + / -10% of the described numerical value or other value), as understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0020] The present invention relates generally to semiconductor devices, and more particularly to field effect transistors (FETs) such as planar FETs, three-dimensional fin-line FETs (FinFETs), or gate-all-around (GAA) devices. One aspect of the present invention relates to forming an STI liner to protect a semiconductor channel (e.g., a silicon germanium channel), wherein the STI liner contains silicon nitride. In some embodiments, multiple STI liners having different material compositions may be formed above the semiconductor channel for its protection. Thus, device performance and / or yield may be improved, as discussed in more detail below.

[0021] Figure 1A and Figure 1B A three-dimensional stereogram and a top view of a portion of an integrated circuit (IC) device 90 are shown, respectively. The IC device 90 may be an intermediate device or a portion thereof during IC processing, which may include static random access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and / or other memory cells. Unless otherwise required, the present invention is not limited to any particular number of devices or device regions or any particular device configuration. For example, although the illustrated IC device 90 is a three-dimensional FinFET device, the concepts of the present invention may also be applied to planar FET devices or GAA devices.

[0022] refer to Figure 1A , the IC device 90 includes a substrate 110. The substrate 110 may include an element (single element) semiconductor such as silicon, germanium and / or other suitable materials; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide and / or other suitable materials; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP and / or other suitable materials. The substrate 110 may be a single layer of material having a uniform composition. Alternatively, the substrate 110 may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions such as source / drain regions may be formed in or on the substrate 110. Depending on the design requirements, the doped region may be doped with an n-type dopant such as phosphorus or arsenic and / or a p-type dopant such as boron. The doped region may be directly formed on the substrate 110 in a p-type well structure, an n-type well structure, a double well structure, or a structure using a protrusion. The doped region may be formed by implanting dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques.

[0023] A three-dimensional active area 120 is formed on the substrate 110. The active area 120 is an elongated fin-shaped structure that protrudes upward beyond the substrate 110. As such, the active area 120 is interchangeably referred to as the fin structure 120 or the fin structure 120 hereinafter. The fin structure 120 may be manufactured using a suitable process (including photolithography and etching processes). The photolithography process may include forming a photoresist layer covering the substrate 110, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element (not shown) including a resist. Then, a recess is etched in the substrate 110 using the mask element, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography with a self-aligned process, thereby allowing the creation of a pattern having, for example, a pitch smaller than that obtained using a single direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers may be formed next to the patterned layer using a self-aligned process. The layer is then removed and the remaining spacers or mandrels may then be used to pattern the fin structure 120.

[0024] The IC device 90 also includes source / drain features 122 formed above the fin structure 120. The source / drain features 122 may include an epitaxial layer epitaxially grown on the fin structure 120. As device dimensions continue to shrink, these source / drain features 122 may merge with each other, even when they were intended to remain separate. This is a problem that the present invention overcomes, as discussed in more detail below.

[0025] The IC device 90 also includes an isolation structure 130 formed above the substrate 110. The isolation structure 130 electrically separates the various components of the IC device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 130 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 130 is formed by etching a trench in the substrate 110 during the formation of the fin structure 120. The trench may then be filled with the above-mentioned isolation material, followed by a chemical mechanical planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as the isolation structure 130. Optionally, the isolation structure 130 may include, for example, a multilayer structure having one or more thermal oxide liner layers.

[0026] The IC device 90 also includes a gate structure 140 formed over and bonded to the fin structure 120 on three sides in the channel region of each fin 120. The gate structures 140 may be dummy gate structures (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or they may be HKMG structures including a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not depicted here, the gate structure 140 may include additional material layers such as an interface layer, a protective layer, other suitable layers, or combinations thereof over the fin structure 120.

[0027] refer to Figure 1B , the plurality of fin structures 120 are oriented longitudinally along the X direction, and the plurality of gate structures 140 are oriented longitudinally along the Y direction (i.e., substantially perpendicular to the fin structures 120). In many embodiments, the IC device 90 includes additional features such as gate spacers disposed along sidewalls of the gate structures 140, a hard mask layer disposed over the gate structures 140, and many other features.

[0028] It should also be understood that various aspects of the present invention discussed below may be applied to multi-channel devices such as gate-all-around (GAA) devices. Figure 1C A three-dimensional perspective view of an exemplary GAA device 150 is shown. For consistency and clarity, Figure 1C and Figure 1A-1B 1 and 2. Similar components in the drawings will be labeled the same. For example, active areas such as fin structures 120 protrude vertically upward from substrate 110 in the Z direction. Isolation structures 130 provide electrical separation between fin structures 120. Gate structures 140 are located above fin structures 120 and above isolation structures 130. Mask 155 is located above gate structures 140, and gate spacers 160 are located on sidewalls of gate structures 140. A capping layer 165 is formed over fin structures 120 to protect fin structures 120 from oxidation during formation of isolation structures 130.

[0029] A plurality of nanostructures 170 are disposed above each of the fin structures 120. The nanostructures 170 may include nanosheets, nanotubes, or nanowires extending horizontally in the X direction, or some other type of nanostructure. The portion of the nanostructure 170 below the gate structure 140 may be used as a channel of the GAA device 150. A dielectric internal spacer 175 may be disposed between the nanostructures 170. In addition, although not shown for simplicity, each of the nanostructures 170 may be circumferentially wound by a gate dielectric and a gate electrode. In the illustrated embodiment, the portion of the nanostructure 170 outside the gate structure 140 may be used as a source / drain component of the GAA device 150. However, in some embodiments, a continuous source / drain component may be epitaxially grown above the portion of the fin structure 120 outside the gate structure 140. In any case, a conductive source / drain contact 180 is formed above the conductive source / drain component to provide electrical connectivity thereto. An interlayer dielectric (ILD) 185 is formed over the isolation structure 130 and around the gate structure 140 and the source / drain contacts 180 .

[0030] Additional details related to GAA device fabrication are disclosed in U.S. Pat. No. 10,164,012, entitled “Semiconductor Device and Manufacturing Method Thereof,” published on Dec. 25, 2018, and U.S. Pat. No. 10,361,278, entitled “Method of Manufacturing a Semiconductor Device and a Semiconductor Device,” published on Jul. 23, 2019, and also in U.S. Pat. No. 9,887,269, entitled “Multi-Gate Device and Method of Fabrication Thereof,” published on Feb. 6, 2018, the disclosures of each of which are incorporated herein by reference in their respective entities. To the extent the present invention relates to fin structures or FinFET devices, such discussion may be equally applicable to GAA devices.

[0031] The following is an example of additional details related to GAA device manufacturing using No. 10,361,278.

[0032] exist Fig.14A , Fig. 14B and Fig. 14CIn the embodiment, substantially only the second layer 28 of the superlattice 24 is etched. Due to this etching step, the sidewalls of the etched second layer 28d are offset inwardly toward the fin from the sidewalls of the first layer 26 on the corresponding side. This etching produces a fourth modified superlattice 24d. In some embodiments, as Fig.14A , Fig. 14B and Fig. 14C The results of the etching shown may be a function of the material of the first layer 26 and the second layer 28, the orientation of the sidewalls, and the etchant used for etching. For example, continuing with this specific example, where each first layer 26 is Si 0.50 Ge 0.50 The buffer layer 22, the first layer 26 and the second layer 28 are each a layer of Si, the buffer layer 22, the first layer 26 and the second layer 28 are epitaxially grown on the (110) surface of the bulk Si substrate, and the sidewalls of the first layer 26 and the second layer 28 are (111) crystal surfaces. In addition, the etchant can be a wet etchant, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) and the like, which are selective to the (111) crystal surface of the Si second layer 28. These conditions can produce a etchant from Si. 0.50 Ge 0.50 The (111) crystal side wall surfaces of the first layer 26 are shifted inwardly toward the (111) crystal side wall surfaces of the etched Si second layer 28d.

[0033] Fig.15A , Fig. 15B and Fig. 15C Shown in undergoing Fig.14A , Fig. 14B and Fig. 14C 4 and after continuing with other processing steps (such as forming a gate dielectric 42 and a gate electrode 44 in the opening through ILD0 40, depositing an ILD (ILD1) 46 over ILD0 40 and gate electrode 44, and forming a contact 48 through ILD1 46 and ILD0 40 to the epitaxial source / drain region 38). Fig. 15C As shown, gate dielectric 42 conforms to the etched sidewalls in fourth modified superlattice 24d. In addition, since etched second layer 28d has been etched, gate electrode 44 may at least partially extend between or closer to the surface of first layer 26.

[0034] Figure 2-Figure 10 2 shows a cross-sectional side view of an IC device 200 at different stages of manufacture. Specifically, Figure 2-Figure 10 Corresponding to along the Y direction, for example along Figure 1A or Figure 1C The cross-sectional view taken along the cutting line A-A' in FIG. Figure 2-Figure 10 It can be called a Y-cut diagram. For consistency and clarity, Figure 2-Figure 10Similar parts appearing in the drawings will be marked as identical.

[0035] refer to Figure 2 , the IC device 200 includes an NMOS (also referred to as NFET) region 200A and a PMOS (also referred to as PFET) region 200B. It should be understood that the NMOS region 200A and the PMOS region 200B may or may not be disposed adjacent to each other, but for simplicity of description, the NMOS region 200A and the PMOS region 200B are disposed adjacent to each other. Figure 2 The voltage divider 210 shown herein (not corresponding to a physical structure in the IC device 200 ) represents the separation between the NMOS region 200A and the PMOS region 200B.

[0036] The IC device 200 includes a substrate 110 in both the NMOS region 200A and the PMOS region 200B. The substrate 110 may be formed using the substrate 110 of FIG. Figure 1A-Figure 1C The substrate discussed, such as a silicon substrate, can be implemented. Doped regions or doped wells can be formed in the substrate 110. For example, the substrate 110 in the NMOS region 200A may include a P-type well, and the substrate 110 in the PMOS region 200B may include an N-type well. Therefore, transistors with different types of conductivity can be formed in the NMOS region 200A and the PMOS region 200B. The doped wells can be formed using one or more ion implantation processes. In some embodiments, the dopant ions may include n-type materials, such as arsenic (As) or phosphorus (P), or in some other embodiments, the dopant ions may include p-type materials, such as boron (B), depending on whether NFET or PFET is required.

[0037] An epitaxial semiconductor layer 230 is formed over the substrate 110 in the NMOS region 200A, and an epitaxial semiconductor layer 240 is formed over the substrate 110 in the PMOS region 200B. In some embodiments, the epitaxial semiconductor layer 230 includes silicon (Si), and the epitaxial semiconductor layer 240 includes silicon germanium (SiGe). The epitaxial semiconductor layers 230 and 240 may be formed using one or more epitaxial growth processes in combination with one or more patterning processes. For example, in some embodiments, the epitaxial semiconductor layer 230 may be epitaxially grown over the substrate 110 in both the NMOS region 200A and the PMOS region 200B. Thereafter, a patterning process may be performed to remove a portion of the epitaxial semiconductor layer 230 formed in the PMOS region 200B, and the epitaxial semiconductor layer 240 may be epitaxially grown over the substrate 110 only in the PMOS region 200B. The epitaxial semiconductor layers 230 and 240 will undergo a patterning process to form fin structures of the NMOS region 200A and the PMOS region 200B, wherein portions of the fin structures will serve as channel regions of transistors of the NMOS region 200A and the PMOS region 200B.

[0038] A buffer layer 250 (also referred to as a capping layer) may be formed over the epitaxial semiconductor layers 230 and 240 in both the NMOS region 200A and the PMOS region 200B. In some embodiments, the buffer layer 250 may include a semiconductor material, such as silicon, and it may be formed using one or more deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. The buffer layer 250 protects the epitaxial semiconductor layers 230 and 240 from undesirable oxidation. For example, if exposed to ambient air (which contains oxygen), the silicon germanium material in the epitaxial semiconductor layer 240 may be easily oxidized, which is undesirable because it may adversely affect the intended function of the silicon germanium material (e.g., use as a semiconductor material). Forming the buffer layer 250 helps prevent the epitaxial semiconductor layers 230 and 240 from being exposed to air, and thus prevents potential oxidation of the silicon or silicon germanium material of the epitaxial semiconductor layers 230 and 240. The buffer layer 250 may be removed in a later process.

[0039] A dielectric layer 270 is formed over the buffer layer 250. In some embodiments, the dielectric layer 270 includes silicon oxide and may be referred to as a pad oxide layer. A dielectric layer 280 is then formed over the dielectric layer 270. In some embodiments, the dielectric layer 280 includes silicon nitride and may be referred to as a pad nitride layer. The dielectric layers 270 and 280 may be used as materials for a hard mask for a subsequent photolithography patterning process.

[0040] Reference Figure 3 , an OD (active area) patterning process 290 is performed to form an NMOS fin structure 300 protruding upward (e.g., upward in the Z direction) in the NMOS region 200A and a PMOS fin structure 310 in the PMOS region 200B. As part of the OD patterning process 290, the dielectric layers 270 and 280 may be patterned (e.g., using a patterned photoresist layer) to form a patterned hard mask that defines lateral dimensions of the NMOS fin structure 300 and the PMOS fin structure 310.

[0041] The patterned hard mask 270 / 280 is then used to pattern the layers below it. For example, portions of the layers 250, 240, and 230 that are not protected by the patterned mask 270 / 280 are etched away in one or more etching processes. Figure 3As shown, the epitaxial semiconductor layer 230 is etched so that the remaining portion thereof protrudes upward from the substrate 110 as part of the NMOS fin structure 300, and the epitaxial semiconductor layer 240 is etched so that the remaining portion thereof protrudes upward from the substrate 110 as part of the PMOS fin structure 310. Channels and source / drain regions of transistors in the NMOS region 200A and transistors in the PMOS region 200B may be formed in the NMOS fin structure 300 and the PMOS fin structure 310, respectively, such as in the epitaxial semiconductor layers 230 and 240. In some embodiments, an n-type fully strained channel (NFSC) is formed using the NMOS fin structure 300, and a p-type fully strained channel (PFSC) is formed using the PMOS fin structure 310.

[0042] The patterning process 290 may cause damage to the NMOS fin structure 300 and the PMOS fin structure 310. For example, the etching process performed during the patterning process 290 may roughen the surface of the NMOS fin structure 300 and the PMOS fin structure 310. For example, the surface of the NMOS fin structure 300 and the PMOS fin structure 310 (e.g., the epitaxial semiconductor layers 230 and 240) may have a first surface roughness at this manufacturing stage, wherein the first roughness is greater than a desired first roughness. In addition, the NMOS fin structure 300 and the PMOS fin structure 310 may be exposed to oxygen or moisture (e.g., ambient air or steam), such as due to the formation of silicon oxide material during the manufacture of the IC device 200. This may also be undesirable because such exposure may oxidize the NMOS fin structure 300 and the PMOS fin structure 310. Even worse, silicon germanium (e.g., silicon germanium of the PMOS fin structure 310) is oxidized at a much faster rate than silicon (e.g., silicon of the NMOS fin structure 300). Conventional semiconductor manufacturing does not take into account the differences in oxidation rates, and therefore does not pay special attention to addressing the undesirable faster oxidation of silicon germanium. As discussed in more detail below, the present invention forms a nitride-containing liner to alleviate these problems.

[0043] Reference now Figure 4, an epitaxial layer formation process 320 is performed on the IC device 200 to form an epitaxial liner 330 on the NMOS fin structure 300 and an epitaxial layer 340 on the PMOS fin structure 310, including forming on the exposed surfaces of each layer 230, 240, 250, 270 and 280. In some embodiments, the epitaxial liner formation process 320 includes an epitaxial growth process, and the epitaxial liners 330 and 340 each include epitaxially grown silicon. For example, the portions of the epitaxial liners 330 and 340 grown on the epitaxial semiconductor layers 230 and 240 include crystalline silicon. In contrast, because the dielectric layers 270 and 280 include dielectric materials rather than crystalline semiconductor materials, the portions of the epitaxial liners 330 and 340 grown on the layers 270 and 280 include amorphous silicon. Note that, at least in part due to differences in material composition (e.g., crystalline silicon versus amorphous silicon), portions of epitaxial liners 330 and 340 formed over side surfaces of epitaxial semiconductor layers 230 and 240 are substantially thinner than portions of epitaxial liners 330 and 340 formed over side surfaces of dielectric layers 270 and 280. Additional description regarding the formation of epitaxial liners 330 and 340 is disclosed in U.S. patent application Ser. No. 17 / 109,895, filed on Dec. 20, 2020, entitled “Method of Manufacturing A Semiconductor Device and A Semiconductor Device,” the entire disclosure of which is incorporated herein by reference.

[0044] Epitaxial liners 330 and 340, respectively, help smooth the surfaces of epitaxial semiconductor layers 230 and 240 that have been roughened or damaged by previous etching processes and / or other processes. For example, epitaxial liners 330 and 340 may have a second surface roughness that is less than the first surface roughness of epitaxial semiconductor layers 230 and 240. Epitaxial layer 340 may also help prevent or reduce oxidation of epitaxial semiconductor layers 230 and 240, which may occur in previous or subsequent processing steps. However, the presence of epitaxial layers alone may not be sufficient to achieve these goals. As such, additional processing is performed to further protect epitaxial semiconductor layers 230 and 240.

[0045] For example, now refer to Figure 5According to the first embodiment of the present invention, a nitridation process 370 is performed on the IC device 200. In some embodiments, the nitridation process 370 includes a rapid thermal nitridation process performed in a chamber at a temperature range between about 600 degrees Celsius and about 800 degrees Celsius for a duration between about 30 seconds and about 180 seconds. The nitridation process 370 injects nitrogen into the epitaxial liners 330 and 340, which helps to repair surface damage of the epitaxial liners 330 and 340. For example, due to the nitridation process 370, the epitaxial liners 330 and 340 can be smoother.

[0046] Reference now Figure 6 , a liner formation process 390 is performed on the IC device 200 to form a liner layer 400 above the NMOS fin structure 300 and the PMOS fin structure 310, for example, on the upper surface and side surfaces of the epitaxial liners 330 and 340. In some embodiments, the liner layer 400 is formed to include silicon oxide. The liner layer 400 can be formed by an atomic layer deposition (ALD) process so that the thickness 410 of the liner layer 400 can be precisely controlled. In some embodiments, the thickness 410 is formed to be within a range between about 20nm and about 40nm. This range of thickness 410 is not arbitrarily selected, but is actually specifically configured to ensure that the liner layer 400 is thick enough to adequately protect the underlying layers from oxidation or other damage, but not too thick to interfere with subsequent manufacturing processing steps.

[0047] In some embodiments, the formation of the liner layer 400 may involve processes such as wet oxidation (e.g., in-situ steam production) and / or plasma enhanced oxidation. These processes can be performed in a processing chamber where hydrogen and oxygen are introduced. The temperature of the wafer may be high enough to trigger the conversion of hydrogen and oxygen into water, and / or cause the presence of atomic oxygen and hydroxyl radicals (OH) on the wafer surface, which is unintentional and undesirable. However, the present invention has injected nitrogen into the epitaxial pads 330 and 340, which makes the epitaxial pads 330 and 340 more hydrophobic. Therefore, even if water is unexpectedly formed, the nitrogen-containing epitaxial pads 330 and 340 will be able to protect the underlying layers (e.g., epitaxial semiconductor layers 230 and 240) from the effects of water and / or atomic oxygen and hydroxyl radicals (OH), which is one of the advantages of the present invention.

[0048] Reference now Figure 7, a deposition process 440 is performed on the IC device 200 to form a dielectric isolation structure 450 directly on the liner layer 400. In some embodiments, the deposition process 440 may include a furnace chemical vapor deposition (FCVD) process. The dielectric isolation structure 450 is formed to fill the gap or trench between the NMOS fin structures 300 and 310. In some embodiments, the dielectric isolation structure 450 may include a shallow trench isolation (STI). Since the STI is formed on the liner layer 400, the liner layer 400 may also be referred to as an STI liner. In some embodiments, the dielectric isolation structure 450 may include an oxide material, such as silicon oxide. Before or after the dielectric isolation structure 450 is formed, a polishing process such as a CMP process may be performed to remove the dielectric layers 270 and 280 (and portions of the dielectric isolation structure 450). In some embodiments, the polishing process may also remove the buffer layer 250.

[0049] Figure 2-Figure 7 Corresponding to the first embodiment of the present invention. In other words, according to the first embodiment, a nitridation process is performed to implant nitrogen into the epitaxial liners 330 and 340, then an oxide-containing liner layer 400 is deposited on the epitaxial liners 330 and 340, and then a dielectric isolation structure 450 is formed directly on the liner layer 400. However, the present invention is not limited to such an embodiment. Figure 8-Figure 10 The second, third and fourth embodiments of the present invention are shown and discussed. For consistency and clarity, the same components in the first, second, third and fourth embodiments are labeled the same.

[0050] refer to Figure 8 The IC device 200 in the second embodiment also undergoes the above reference Figure 5 The nitridation process 370 discussed. That is, nitrogen has been injected into the epitaxial liners 330 and 340 to repair surface damage of the epitaxial liners, and to better protect the epitaxial liners 330 and 340 in subsequent manufacturing process steps. However, unlike the first embodiment, the IC device 200 in the second embodiment does not undergo the liner formation process 390, but rather undergoes the liner formation process 490. The liner formation process 490 forms a liner layer 500 above the NMOS fin structure 300 and the PMOS fin structure 310, for example, on the upper surface and side surfaces of the epitaxial liners 330 and 340. In some embodiments, the liner layer 500 is formed to include silicon nitride, which, as described above, can provide certain advantages over other types of materials. For example, silicon nitride has good hydrophobicity (e.g., compared to oxide materials). In this way, the liner layer 500 can fully protect the underlying layers (e.g., silicon germanium of the epitaxial semiconductor layer 340) from water or other oxidizing elements. Silicon nitride is also a good candidate material for restoring surface damage of the epitaxial liner 330 or 340 .

[0051] The liner layer 500 may be formed by an atomic layer deposition (ALD) process, so that the thickness 510 of the liner layer 500 may be precisely controlled. In some embodiments, the thickness 510 is formed to be within a range between about 20 nm and about 40 nm. This range of thickness 510 is not arbitrarily selected, but is in fact specifically configured to ensure that the liner layer 500 is thick enough to adequately protect the underlying layers from oxidation or other damage, but not too thick to interfere with subsequent manufacturing processing steps.

[0052] Reference now Fig. 9 , showing a third embodiment of the present invention. According to the third embodiment, a nitridation process 370 has been performed to implant nitrogen into the epitaxial pads 330 and 340, and a pad layer 400 has also been formed. Thereafter, another nitridation process 540 is also performed on the IC device 200 to implant nitrogen into the pad layer 400. In some embodiments, the nitridation process 540 is substantially similar to the nitridation process 370, for example, the nitridation process 540 may also include a rapid thermal nitridation process performed in a chamber at a temperature range of about 600 degrees Celsius to about 800 degrees Celsius for a duration between about 30 seconds and about 180 seconds. Nitrogen implantation into the pad layer 400 may also help repair surface damage to the pad layer 400 and help it withstand subsequent manufacturing processes. For example, due to the nitridation process 540, the pad layer 400 may be smoother and may be better able to withstand the undesirable effects of water and / or oxygen.

[0053] Reference now Fig.10, showing a fourth embodiment of the present invention. According to the fourth embodiment, the IC device 200 has undergone the same manufacturing process as performed in the third embodiment, such as the nitridation process 370 of injecting nitrogen into the epitaxial liners 330 and 340, the formation of the liner layer 400, and the nitridation process 540 of then injecting nitrogen into the liner layer 400. Thereafter, the IC device 200 is subjected to a liner formation process 590 to form a liner layer 600 over the liner layer 400. In some embodiments, the liner layer 600 is formed to include silicon nitride, which, as described above, can provide certain benefits over other types of materials, such as enhanced hydrophobicity and better ability to protect the underlying layers (including the epitaxial semiconductor layer 240) from water or other oxidizing elements. The liner layer 600 can be formed by an atomic layer deposition (ALD) process, so that the thickness 610 of the liner layer 600 can be precisely controlled. In some embodiments, the thickness 610 is formed to be in a range between about 20nm and about 40nm. This range of thickness 610 is not arbitrarily selected, but is in fact specifically configured to ensure that the liner layer 600 is thick enough to adequately protect the underlying layers from oxidation or other damage, but not too thick to interfere with subsequent manufacturing processing steps. In some embodiments, thickness 610 is thinner than thickness 410. For example, the ratio between thickness 610 and thickness 410 can be in the range of about 50% to about 200%. Such a ratio range helps the liner layers 600 and 400 perform their respective functions of protecting the underlying components.

[0054] Regardless of the embodiment of the STI liner used to implement the present invention, it should be understood that the above referenced STI liner will still need to be performed. Figure 7 Other fabrication processes are discussed, such as the formation of the STI structure 450, the removal of the dielectric layers 270 and 280, and planarization steps.

[0055] It should also be understood that additional manufacturing processes may be performed to complete the manufacturing of the IC device 200. For example, the layers surrounding the NMOS fin structures 300 and 310 may be partially etched to expose the side surfaces of the upper portions of the NMOS fin structures 300 and 310. This may be referred to as a fin recessing process. Thereafter, a high-k metal gate (HKMG) structure (e.g., such as Figure 1AThe HKMG structure 140 is formed to surround the NMOS fin structures 300 and 310. The formation of the HKMG structure may include a gate replacement process, in which a dummy gate structure (e.g., including a dummy polysilicon gate electrode and a dummy gate dielectric or a high-k gate dielectric) is first formed above the NMOS fin structures 300 and 310. The source / drain region may then be defined, and the dummy gate structure is then removed and replaced by the HKMG structure. In some embodiments, if the dummy gate structure includes a dummy gate dielectric (e.g., a silicon oxide gate dielectric), the dummy gate dielectric will be replaced by a high-k gate dielectric layer that is part of the KHMG structure. The HKMG structures may each include a high-k gate dielectric and a metal gate electrode. Example materials for the high-k gate dielectric include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or a combination thereof. The metal gate electrode may include one or more work function metal layers and one or more fill metal layers. The work function metal layer may be configured to adjust the work function of each transistor. Example materials for the work function metal layer may include titanium nitride (TiN), titanium aluminide (TiAl), tantalum nitride (TaN), titanium carbide (Tic), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum nitride (TiAlN), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or a combination thereof. The fill metal layer may be used as the main conductive portion of the gate electrode layer. In some embodiments, the HKMG structure may include additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer or other applicable layers. Other manufacturing processes may also be performed after the HKMG structure is formed, such as forming conductive contacts for the source / drain region and the HKMG structure and a multilayer interconnect structure comprising metal lines and vias. For simplicity, these additional processes are not discussed in detail here.

[0056] IC device 200 may be implemented in a variety of IC applications, including memory devices such as static random access memory (SRAM) devices. In this regard, Fig.11 An exemplary circuit schematic diagram of a single-port SRAM cell (e.g., a 1-bit SRAM cell) 800 is shown. The single-port SRAM cell 800 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass-gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, and transistors PG1, PG2, PD1, and PD2 are n-type transistors. According to various aspects of the present invention, the PG1, PG2, PD1, and PD2 transistors are implemented with thinner spacers than the PU1 and PU2 transistors. Since the SRAM cell 800 includes six transistors in the illustrated embodiment, it may also be referred to as a 6T SRAM cell.

[0057] The drains of the pull-up transistor PU1 and the pull-down transistor PD1 are coupled together, and the drains of the pull-up transistor PU2 and the pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and coupled with the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and coupled with the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to a power supply voltage Vcc (also referred to as Vdd), and the sources of the pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be electrically grounded.

[0058] The first storage node SN1 of the first data latch is coupled to the bit line BL through the pass gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through the pass gate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are usually at opposite logic levels (logic high or logic low). The gates of the pass gate transistors PG1 and PG2 are coupled to the word line WL. SRAM devices such as the SRAM cell 800 can be implemented using "planar" transistor devices, FinFET devices, and / or GAA devices.

[0059] Fig.12 An integrated circuit manufacturing system 900 according to an embodiment of the present invention is illustrated. The manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916 ..., N connected by a communication network 918. The network 918 can be a single network, or can be a variety of different networks such as an intranet and the Internet, and can include both wired and wireless communication channels.

[0060] In an embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer who controls processes and related protocols, or an equipment engineer who monitors or adjusts conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor process tool, such as an EUV tool for performing a lithography process to define various layers of the IC device 200; entity 912 represents a virtual metrology module associated with the process tool 910; entity 914 represents an advanced process control module associated with the process tool 910 and other process tools; and entity 916 represents a sampling module associated with the process tool 910.

[0061] Each entity can interact with other entities and can provide integrated circuit manufacturing, process control and / or computing capabilities to receive such capabilities from other entities. Each entity can also include one or more computer systems for performing calculations and performing automation. For example, the high-level process control module of entity 914 can include a plurality of computer hardware in which software instructions are encoded. The computer hardware can include a hard drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0062] The integrated circuit manufacturing system 900 enables interaction between entities for the purpose of integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In an embodiment, advanced process control includes adjusting process conditions, settings and / or recipes of a processing tool applicable to an associated wafer based on metrology results.

[0063] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0064] One of the capabilities provided by the IC manufacturing system 900 can enable collaboration and information access in areas such as design, engineering and processing, metrology and advanced process control. Another capability provided by the IC manufacturing system 900 can be system integration between facilities (such as, between metrology tools and processing tools). Such integration enables facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable manufacturing information to be more effectively incorporated into manufacturing processes or APC modules, and can enable wafer data from online or field measurements using metrology tools integrated in associated processing tools.

[0065] Fig.13 1 is a flow chart showing a method 1000 for manufacturing a semiconductor device according to an embodiment of the present invention. The method 1000 includes step 1010 to form a fin structure protruding vertically from a substrate.

[0066] The method 1000 includes step 1020 of epitaxially growing a silicon layer on a surface of the fin structure.

[0067] The method 1000 includes step 1030 of performing a first rapid thermal nitridation (RTN) process. The first RTN process implants nitrogen into the epitaxially grown silicon layer.

[0068] The method 1000 includes step 1040 of forming a dielectric liner layer on the epitaxially grown silicon layer after the first RTN process has been performed.

[0069] The method 1000 includes step 1050 of forming a dielectric isolation structure over the dielectric liner layer.

[0070] In some embodiments, the fin structure is formed by performing one or more etching processes to pattern the fin structure. After performing the one or more etching processes, the fin structure has a first surface roughness. The silicon layer epitaxially grown on the fin structure has a second surface roughness less than the first surface roughness.

[0071] In some embodiments, the fin structure is a P-type fin structure including a silicon germanium material. In some embodiments, one or more mask layers are formed over the silicon germanium material of the fin structure. A silicon layer is epitaxially grown on the silicon germanium material and the one or more mask layers. A first portion of the silicon layer grown on the one or more mask layers is thicker than a second portion of the silicon layer grown on the silicon germanium material.

[0072] In some embodiments, a silicon oxide liner is formed on the silicon layer after the first RTN process has been performed, and then an isolation structure is formed over the silicon oxide liner.

[0073] In some embodiments, forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer. Forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer.

[0074] In some embodiments, forming the dielectric liner layer further comprises forming a silicon nitride liner layer on the epitaxially grown silicon layer. Forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer.

[0075] In some embodiments, forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer. Performing a second RTN process to implant nitrogen into the silicon oxide liner layer. Forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer.

[0076] In some embodiments, forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer. In some embodiments, the method further comprises: performing a second RTN process to implant nitrogen into the silicon oxide liner layer; and forming a silicon nitride liner layer directly on the silicon oxide liner layer. In some embodiments, forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer.

[0077] In some embodiments, the silicon oxide liner layer is formed to have a first thickness; the silicon nitride liner layer is formed to have a second thickness; and the first thickness is greater than the second thickness.

[0078] It should be understood that method 1000 may include other steps performed before, during, or after steps 1010-1050. For example, method 1000 may include steps of forming a dummy gate structure, forming source / drain features, replacing the dummy gate structure with a high-k metal gate structure, forming a metallization layer, etc. For simplicity, these additional steps will not be discussed in detail herein.

[0079] The above-described advanced lithography processes, methods, and materials can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between components, and the above disclosure is well suited for this. In addition, spacers, also referred to as mandrels, for forming the fins of a FinFET can be processed according to the above disclosure. It should also be understood that the various aspects of the present invention discussed above can be applied to multi-channel devices such as full-all-around gate (GAA) devices. To the extent that the present invention relates to fin structures or FinFET devices, such discussion can be equally applied to GAA devices.

[0080] In summary, the present invention forms a nitride-containing STI liner above a p-type fully strained channel (PFSC) comprising silicon germanium. In a first embodiment, an epitaxial liner is formed above a fin structure comprising a PFSC. A rapid thermal nitridation (RTN) process is performed to implant nitrogen into the epitaxial liner. An oxide-containing STI liner is then formed on the epitaxial liner. In a second embodiment, an epitaxial liner is formed above a fin structure comprising a PFSC, and an RTN process is performed to implant nitrogen into the epitaxial liner. Thereafter, a nitride-containing STI liner is formed above the epitaxial liner. In a third embodiment, an epitaxial liner is formed above a fin structure comprising a PFSC, and an RTN process is performed to implant nitrogen into the epitaxial liner. Thereafter, an oxide-containing STI liner is formed above the epitaxial liner, and a nitride-containing STI liner is formed above the oxide-containing STI liner. In a fourth embodiment, an epitaxial liner is formed above a fin structure comprising a PFSC, and a first RTN process is performed to implant nitrogen into the epitaxial liner. Thereafter, an STI liner containing oxide is formed over the epitaxial liner, and then a second RTN process is performed to implant nitrogen into the STI liner containing oxide, and then a STI liner containing nitride is formed over the STI liner containing oxide.

[0081] Forming an STI liner in the manner of the present invention can provide advantages over conventional devices. However, it should be understood that not all advantages are discussed herein, different embodiments can provide different advantages, and no specific advantages are required for all embodiments. One advantage is that damage to the PFSC can be mitigated. In more detail, the fin patterning process and / or the oxide layer formation process can result in a roughened fin surface, which can reduce device performance. Nitrogen treatment (e.g., RTN) of the epitaxial liner and / or the oxide-containing STI liner formed above the epitaxial liner helps to smooth the roughened surface and thus restore fin surface damage. In addition, the silicon germanium material of the PFSC is oxidized at a different rate (e.g., substantially faster rate) than the silicon material of the n-type channel. Therefore, the PFSC is more susceptible to or more susceptible to oxygen-containing environments (e.g., ambient air or water) than the n-type channel. In order to better protect the PFSC from future manufacturing steps that may introduce oxygen, the present invention forms a nitride-containing STI liner on the PFSC because the nitride-containing STI liner is a better candidate than the oxide-containing liner in terms of protecting the PFSC. For example, a nitride-containing STI liner is more hydrophobic than an oxide-containing STI liner. Other advantages may include compatibility with existing manufacturing processes (including FinFET and GAA processes) and simplicity and low cost of implementation.

[0082] One aspect of the present invention relates to a method for manufacturing a semiconductor structure. The method includes forming a fin structure protruding vertically from a substrate. The method includes epitaxially growing a silicon layer on a surface of the fin structure. The method includes performing a first rapid thermal nitridation (RTN) process. The first RTN process injects nitrogen into the epitaxially grown silicon layer. The method includes forming a dielectric liner layer on the epitaxially grown silicon layer after the first RTN process has been performed. The method includes forming a dielectric isolation structure above the dielectric liner layer.

[0083] Another aspect of the present invention relates to a method for manufacturing a semiconductor structure. The method includes patterning a silicon germanium material into a p-type fin structure. The patterning includes one or more etching processes. The method includes growing an epitaxial layer on the p-type fin structure. The method includes injecting nitrogen into the epitaxial layer. The method includes depositing a silicon oxide liner layer on the epitaxial layer after the nitrogen has been injected into the epitaxial layer. The method includes injecting nitrogen into the silicon oxide liner layer. The method includes forming a shallow trench isolation (STI) structure above the silicon oxide liner layer after the nitrogen has been injected into the silicon oxide liner layer.

[0084] Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes a fin structure protruding vertically from a substrate, wherein the fin structure includes silicon germanium (SiGe). An epitaxial silicon layer is disposed on a sidewall of the fin structure. The epitaxial silicon layer includes nitrogen. One or more dielectric liner layers are disposed on the epitaxial silicon layer. A dielectric isolation structure is disposed above the one or more dielectric liner layers.

[0085] Some embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes: forming a fin structure protruding vertically from a substrate; epitaxially growing a silicon layer on the surface of the fin structure; performing a first rapid thermal nitridation (RTN) process, wherein the first rapid thermal nitridation process injects nitrogen into the epitaxially grown silicon layer; after the first rapid thermal nitridation process has been performed, forming a dielectric liner layer above the epitaxially grown silicon layer; and forming a dielectric isolation structure above the dielectric liner layer.

[0086] In some embodiments, forming the fin structure includes performing one or more etching processes to pattern the fin structure, wherein after performing the one or more etching processes, the fin structure has a first surface roughness; and the silicon layer epitaxially grown on the fin structure has a second surface roughness less than the first surface roughness. In some embodiments, forming the fin structure includes forming a P-type fin structure including a silicon germanium material. In some embodiments, one or more mask layers are formed over the silicon germanium material of the fin structure; and the silicon layer is epitaxially grown over the silicon germanium material and the one or more mask layers. In some embodiments, a first portion of the silicon layer grown over the one or more mask layers is thicker than a second portion of the silicon layer grown over the silicon germanium material. In some embodiments, the method further includes: forming a silicon oxide liner over the silicon layer after the first rapid thermal nitridation process has been performed; and forming an isolation structure over the silicon oxide liner. In some embodiments, forming the dielectric liner layer also includes forming a silicon oxide liner layer over the epitaxially grown silicon layer; and forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly over the silicon oxide liner layer. In some embodiments, forming the dielectric liner layer further comprises forming a silicon nitride liner layer on the epitaxially grown silicon layer; and forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer. In some embodiments, forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer; the method further comprises performing a second rapid thermal nitridation process to implant nitrogen into the silicon oxide liner layer; and forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer. In some embodiments, forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer; the method further comprises performing a second rapid thermal nitridation process to implant nitrogen into the silicon oxide liner layer; and forming a silicon nitride liner layer directly on the silicon oxide liner layer; and forming the dielectric isolation structure comprises forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer. In some embodiments, the silicon oxide liner layer is formed to have a first thickness; the silicon nitride liner layer is formed to have a second thickness; and the first thickness is greater than the second thickness.

[0087] Other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: patterning a silicon germanium material into a p-type fin structure, wherein the patterning comprises one or more etching processes; growing an epitaxial layer on the p-type fin structure; injecting nitrogen into the epitaxial layer; after the nitrogen has been injected into the epitaxial layer, depositing a silicon oxide liner layer on the epitaxial layer; injecting nitrogen into the silicon oxide liner layer; and after the nitrogen has been injected into the silicon oxide liner layer, forming a shallow trench isolation (STI) structure above the silicon oxide liner layer.

[0088] In some embodiments, the method further comprises, after said injecting said nitrogen into said silicon oxide liner layer but before said forming said shallow trench isolation structure, depositing a silicon nitride liner layer on said silicon oxide liner layer, wherein said shallow trench isolation structure is formed above said silicon nitride liner layer. In some embodiments, said silicon nitride liner layer is formed to be thinner than said silicon oxide liner layer. In some embodiments, said injecting said nitrogen into said epitaxial layer comprises performing a first thermal nitridation process; and said injecting said nitrogen into said silicon oxide liner layer comprises performing a second thermal nitridation process.

[0089] Still other embodiments of the present application provide a semiconductor device, comprising: a fin structure protruding vertically from a substrate, wherein the fin structure contains silicon germanium (SiGe); an epitaxial silicon layer disposed on a sidewall of the fin structure, wherein the epitaxial silicon layer contains nitrogen; one or more dielectric liner layers disposed on the epitaxial silicon layer; and a dielectric isolation structure disposed above the one or more dielectric liner layers.

[0090] In some embodiments, the one or more dielectric liner layers include a silicon oxide layer; and the dielectric isolation structure includes a shallow trench isolation (STI) formed directly on the silicon oxide layer. In some embodiments, the silicon oxide layer contains nitrogen. In some embodiments, the one or more dielectric liner layers include a silicon nitride layer; and the dielectric isolation structure includes a shallow trench isolation (STI) formed directly on the silicon nitride layer. In some embodiments, the one or more dielectric liner layers include a silicon oxide layer formed on the epitaxial silicon layer and a silicon nitride layer formed on the silicon oxide layer; and the dielectric isolation structure includes a shallow trench isolation (STI) formed directly on the silicon oxide layer.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a fin structure protruding vertically from the substrate, wherein the fin structure includes a first segment and a second segment different from the first segment and located below the first segment; epitaxially growing a silicon layer on a surface of the fin structure, wherein a first portion of the silicon layer grown in the first segment is thicker than a second portion of the silicon layer grown in the second segment; performing a first rapid thermal nitridation (RTN) process, wherein the first rapid thermal nitridation process implants nitrogen into the epitaxially grown silicon layer; forming a dielectric liner layer over the epitaxially grown silicon layer after the first rapid thermal nitridation process has been performed; and A dielectric isolation structure is formed over the dielectric liner layer.

2. The method according to claim 1, wherein: Forming the fin structure includes performing one or more etching processes to pattern the fin structure, wherein after performing the one or more etching processes, the fin structure has a first surface roughness; and The silicon layer epitaxially grown on the fin structure has a second surface roughness less than the first surface roughness.

3. The method according to claim 1, wherein: Forming the fin structure includes forming a P-type fin structure including a silicon germanium material.

4. The method according to claim 3, wherein: The first segment of the fin structure includes one or more masking layers, wherein the second segment of the fin structure includes the silicon germanium material; and epitaxially growing the first portion of the silicon layer on the one or more mask layers; The second portion of the silicon layer is epitaxially grown on the silicon germanium material.

5. The method according to claim 1, wherein: The silicon layer includes polysilicon.

6. The method according to claim 1, further comprising: forming a silicon oxide liner on the silicon layer after the first rapid thermal nitridation process has been performed; as well as An isolation structure is formed over the silicon oxide liner.

7. The method according to claim 1, wherein: Forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer; and Forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer.

8. The method according to claim 1, wherein: Forming the dielectric liner layer further comprises forming a silicon nitride liner layer on the epitaxially grown silicon layer; and Forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer.

9. The method according to claim 1, wherein: Forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer; The method further includes performing a second rapid thermal nitridation process to implant nitrogen into the silicon oxide liner layer; and Forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon oxide liner layer.

10. The method of claim 1, wherein: Forming the dielectric liner layer further comprises forming a silicon oxide liner layer on the epitaxially grown silicon layer; The method further comprises: performing a second rapid thermal nitridation process to implant nitrogen into the silicon oxide liner layer; and forming a silicon nitride liner layer directly on the silicon oxide liner layer; and Forming the dielectric isolation structure includes forming a shallow trench isolation (STI) structure directly on the silicon nitride liner layer.

11. The method according to claim 10, wherein: The silicon oxide liner layer is formed to have a first thickness; The silicon nitride liner layer is formed to have a second thickness; and The first thickness is greater than the second thickness.

12. A method for manufacturing a semiconductor structure, comprising: patterning a silicon germanium material into a p-type fin structure, wherein the patterning includes performing one or more etching processes while using a mask structure formed over the silicon germanium material; Growing a first portion of an epitaxial layer on the patterned silicon germanium material and growing a second portion of the epitaxial layer over the mask structure, wherein the first portion of the epitaxial layer is grown thinner than the second portion of the epitaxial layer and the second portion of the epitaxial layer is located on the first portion of the epitaxial layer; implanting nitrogen into the epitaxial layer; depositing a silicon oxide liner layer on the epitaxial layer after nitrogen has been implanted into the epitaxial layer; implanting nitrogen into the silicon oxide liner layer; and After nitrogen has been implanted into the silicon oxide liner layer, a shallow trench isolation (STI) structure is formed over the silicon oxide liner layer.

13. The method according to claim 12, further comprising, after said injecting said nitrogen into said silicon oxide liner layer but before forming said shallow trench isolation structure, depositing a silicon nitride liner layer on said silicon oxide liner layer, wherein: The shallow trench isolation structure is formed above the silicon nitride liner layer.

14. The method according to claim 13, wherein: The silicon nitride liner layer is formed to be thinner than the silicon oxide liner layer.

15. The method of claim 12, wherein: Implanting the nitrogen into the epitaxial layer includes performing a first thermal nitridation process; and Implanting the nitrogen into the silicon oxide liner layer includes performing a second thermal nitridation process.

16. A semiconductor device comprising: a fin structure protruding vertically from the substrate, wherein the fin structure comprises silicon germanium (SiGe); An epitaxial silicon layer, disposed on a sidewall of the fin structure, wherein the epitaxial silicon layer contains nitrogen; one or more dielectric liner layers disposed on the epitaxial silicon layer; and a dielectric isolation structure disposed above the one or more dielectric liner layers, At least a portion of the one or more dielectric liner layers is in direct contact with the substrate on one side and in direct contact with the dielectric isolation structure on another side.

17. The semiconductor device according to claim 16, wherein: The one or more dielectric liner layers include a silicon oxide layer; and The dielectric isolation structure includes a shallow trench isolation (STI) formed directly on the silicon oxide layer.

18. The semiconductor device according to claim 17, wherein: The silicon oxide layer contains nitrogen.

19. The semiconductor device according to claim 17, wherein: The one or more dielectric liner layers include a silicon nitride layer; and The dielectric isolation structure includes a shallow trench isolation (STI) formed directly on the silicon nitride layer.

20. The semiconductor device according to claim 16, wherein: The one or more dielectric liner layers include a silicon oxide layer formed on the epitaxial silicon layer and a silicon nitride layer formed on the silicon oxide layer; and The dielectric isolation structure includes a shallow trench isolation (STI) formed directly on the silicon oxide layer.

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