Bandgap reference circuit using heterogeneous power supply and electronic device having the same

Abstract

The present invention discloses a bandgap reference circuit, comprising: a first current generator configured to generate a first current proportional to temperature; a second current generator configured to output a second current obtained by mirroring the first current to a first node forming a reference voltage; a first resistor connected to the first node and provided with the second current; and a first bipolar junction transistor (BJT), the first BJT comprising an emitter node connected to the first resistor, a base node provided with a first power supply, and a collector node provided with a second power supply different from the first power supply.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2020-0067576 filed on June 4, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments of the present disclosure relate to a bandgap reference circuit, and more particularly, to a bandgap reference circuit for driving a transistor based on heterogeneous power supplies (two or more different types of power supplies) and an electronic device including the bandgap reference circuit. Background Art

[0004] Semiconductor devices may include various circuits for generating, processing or storing data. The circuits of semiconductor devices may operate based on a reference voltage provided from an external power supply or any other circuit. For example, the reference voltage may vary depending on external factors such as temperature. Semiconductor devices may include a bandgap reference circuit for reducing or preventing abnormal operation of the circuits of semiconductor devices and ensuring their reliability. A bandgap reference circuit is a circuit that generates a reference voltage that is insensitive to process-voltage-temperature (PVT) (or PVT variation).

[0005] In a semiconductor chip, when a circuit and a bandgap reference circuit share the same substrate, the bandgap reference circuit may be affected by noise from the circuit. In particular, as semiconductor chips become more highly integrated and miniaturized, the impact of noise on the bandgap reference circuit increases. Therefore, a method for improving the reliability of the bandgap reference circuit is needed. Summary of the invention

[0006] Example embodiments of the present disclosure provide a bandgap reference circuit and an electronic device including the bandgap reference circuit, which is insensitive to PVT, reduces noise, and improves the reliability of the reference voltage by applying heterogeneous power supplies (e.g., analog and digital power supplies) to transistors of the bandgap reference circuit.

[0007] According to example embodiments, a bandgap reference circuit includes: a first current generator that generates a first current proportional to temperature; a second current generator that outputs a second current obtained by mirroring the first current to a first node that forms a reference voltage; a first resistor that is connected to the first node and is provided with the second current; and a first bipolar junction transistor (BJT) that includes an emitter node connected to the first resistor, a base node provided with a first power supply, and a collector node provided with a second power supply different from the first power supply.

[0008] According to an example embodiment, an electronic device includes: a bipolar junction transistor (BJT) formed at a semiconductor substrate; and a digital circuit formed at the semiconductor substrate and operating in a digital domain. The BJT includes: a collector node connected to the semiconductor substrate and sharing a first power supply with a digital node of the digital circuit; a base node connected to a first conductive region formed by injecting a first impurity into the semiconductor substrate and provided with a second power supply different from the first power supply; and an emitter node connected to a second conductive region formed by injecting a second impurity into the first conductive region and connected to a resistor provided with a current proportional to a temperature from a mirror current generator.

[0009] According to an example embodiment, an electronic device includes: a first circuit that operates based on a first power supply; a second circuit that operates based on a second power supply different from the first power supply; and a bandgap reference circuit that generates a reference voltage for operation of the first circuit and the second circuit based on the first power supply and the second power supply. The bandgap reference circuit includes: a first current generator that generates a first current proportional to temperature; a second current generator that outputs a second current obtained by mirroring the first current to a first node that forms a reference voltage; a first resistor that is connected to the first node and is provided with a second current; and a bipolar junction transistor (BJT) that includes an emitter node connected to the first resistor, a base node provided with the first power supply, and a collector node provided with the second power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating an electronic device according to an example embodiment of the present disclosure.

[0012] Figure 2 It is shown in detail including Figure 1 Block diagram of the electronic system of an electronic device.

[0013] Figure 3 It is shown in detail Figure 1 Block diagram of the bandgap reference circuit.

[0014] Figure 4 It is shown in detail Figure 3 Circuit diagram of the bandgap reference circuit.

[0015] Figure 5 is a diagram for describing an electronic device to which a heterogeneous power source is applied from a setting module.

[0016] Figure 6 It is shown in detail Figure 5Illustration of an electronic device.

[0017] Figure 7 is a diagram illustrating in detail an electronic device according to an example embodiment.

[0018] Figure 8 is a diagram illustrating in detail an electronic device according to an example embodiment.

[0019] Fig. 9 is a block diagram illustrating in detail an electronic system according to an example embodiment of the present disclosure.

[0020] Fig.10 It is shown in detail Fig. 9 Circuit diagram of the bandgap reference circuit.

[0021] Fig.11 It is shown in detail Fig. 9 Illustration of an electronic device.

[0022] Fig.12 is a graph showing the PTAT current measured at a bandgap reference circuit with DC noise introduced.

[0023] Fig.13 is a graph showing the distribution of a reference voltage at a bandgap reference circuit into which DC noise is introduced.

[0024] Fig.14 is a graph showing the standard deviation of a reference voltage at a bandgap reference circuit into which DC noise is introduced.

[0025] Fig.15 is a graph showing gain and phase at a bandgap reference circuit with AC noise introduced.

[0026] Fig.16A and 16B is a graph showing a waveform of a reference voltage at a bandgap reference circuit into which AC noise is introduced.

[0027] Fig.17 is a block diagram illustrating an image sensor device according to an example embodiment of the present disclosure.

[0028] Fig.18 is a block diagram illustrating an electronic system according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Below, exemplary embodiments of the present disclosure may be described in detail and clearly so that a person skilled in the art can easily implement the present disclosure. Below, for ease of description, similar components are represented by using the same or similar reference numerals.

[0030] In the following figures or detailed description, a module may be shown in the figures or may be connected to any other components other than the components in the specific embodiments. The modules or components may be connected directly or indirectly. The modules or components may be connected by communication or may be physically connected.

[0031] Figure 1 is a block diagram showing an electronic device ED according to an exemplary embodiment of the present disclosure. Figure 1 , showing an electronic device ED generating a data signal based on power provided from an external module (not shown). For example, the electronic device ED may be an electronic device included in a device such as a computer, a laptop computer, a smart phone, a digital camera, or a tablet computer.

[0032] The electronic device ED may include a bandgap reference circuit 10, an analog circuit 20, a digital circuit 30, and / or an analog and digital circuit 40. The electronic device ED may be provided with an analog ground AGND, a digital ground DGND, and a power supply voltage V by an external module. SS The electronic device ED may output a data signal based on the operation of the internal circuits 10, 20, 30, and / or 40. For example, the data signal may include at least one of the following various information: such as an image, a video, a sound, a text, a position, and a distance.

[0033] For example, the analog ground AGND may be a signal used for signal processing in the analog domain. For example, the analog ground AGND may be a ground voltage in the analog domain. The digital ground DGND may be a signal used for signal processing in the digital domain. For example, the digital ground DGND may be a ground voltage in the digital domain.

[0034] In an example embodiment, the noise of the digital ground DGND may be different from the noise of the analog ground AGND. For example, the digital ground DGND may be connected to a circuit of a digital domain; since noise from the operation of the circuit of the digital domain is introduced into the digital ground DGND, the noise of the digital ground DGND may be generated more frequently or larger than the noise of the analog ground AGND. For example, the noise of the digital ground DGND may be noise of a DC component or noise of an AC component.

[0035] The bandgap reference circuit 10 can generate a reference voltage V REF The reference voltage V REF It can be a bandgap reference voltage. The reference voltage V REF The reference voltage V may be a voltage used for the operation of at least one of the analog circuit 20, the digital circuit 30, and the analog and digital circuit 40. For example, in the case where the analog circuit 20 is a comparator that determines whether an input value exceeds a reference value, the reference voltage V REF Can be a reference value provided to the comparator.

[0036] At the reference voltage V REF In the case of a value different from the expected value at the time of design, the electronic device ED may operate abnormally or may output an incorrect data signal. In order to ensure the reliability of the data signal output from the electronic device ED, the bandgap reference circuit 10 needs to have strong characteristics in terms of external factors (e.g., temperature changes, noise, or leakage current). That is, the bandgap reference circuit 10 may need to generate a reference voltage V that is insensitive to process-voltage-temperature (PVT) (or PVT changes). REF . This will refer to Figure 3 Describe more fully.

[0037] The analog circuit 20 may be a circuit that operates in the analog domain. For example, the analog circuit 20 may be based on a power supply voltage V SS and analog ground AGND. The digital circuit 30 may be a circuit that operates in the digital domain. For example, the digital circuit 30 may be based on a power supply voltage V SS The analog and digital circuit 40 may be a circuit that operates in the analog domain and the digital domain. For example, the analog and digital circuit 40 may be based on a power supply voltage V SS , analog ground AGND and digital ground DGND. For example, the analog and digital circuit 40 may be a circuit such as an analog-to-digital converter (ADC) circuit and a digital-to-analog converter (DAC) circuit.

[0038] In an example embodiment, the electronic device ED may output a data signal based on the operation of at least one of the analog circuit 20, the digital circuit 30, and the analog and digital circuit 40. For example, the reference voltage V REF To output the data signal. In order to ensure the reliability of the data signal output from the electronic device ED, it is necessary to generate a reference voltage V that is insensitive to PVT. REF Bandgap reference circuit 10.

[0039] Figure 2 A detailed description includes Figure 1 Block diagram of the electronic system ES of the electronic device ED. Figure 2 The electronic system ES can be connected to the setting module SM through a pin connection. The electronic system ES can be a system that performs a specific operation. For example, the electronic system ES can be a device such as a computer, a laptop computer, a smart phone, a digital camera, or a tablet computer.

[0040] The electronic system ES may include an electronic device ED and an interface module IM. The electronic device ED may include a bandgap reference circuit 10, an analog circuit 20, a digital circuit 30, an analog and digital circuit 40, a first pad (pad 1) and / or a second pad (pad 2). Since the bandgap reference circuit 10, the analog circuit 20, the digital circuit 30, and the analog and digital circuit 40 have been described with reference to Figure 1 The above has been explained, so I will not repeat it here.

[0041] The electronic device ED may be connected to the interface module IM through a first pad and a second pad. The electronic device ED may receive a first power source through the first pad and may receive a second power source through the second pad.

[0042] In example embodiments, the first power source received through the first pad may be applied to the bandgap reference circuit 10, the analog circuit 20, and the analog and digital circuit 40. For example, the first power source may be the analog ground AGND.

[0043] In example embodiments, the second power source received through the second pad may be applied to the digital circuit 30 and the analog and digital circuit 40. For example, the second power source may be the digital ground DGND.

[0044] The interface module IM may include a first pin and a second pin. The first pin may be connected to a first pad of the electronic device ED via a first pad bond. The second pin may be connected to a second pad of the electronic device ED via a second pad bond. That is, in the electronic system ES, the analog ground AGND and the digital ground DGND may be sent via separate paths.

[0045] However, the interface module IM according to the exemplary embodiment of the present disclosure is not limited thereto. For example, the interface module IM may also include a Figure 1 The power supply voltage V SS That is, the interface module IM may be a module that receives a signal such as power or data from outside the electronic system ES or outputs a signal such as power or data to outside the electronic system ES.

[0046] The setting module SM may be a module that provides a common ground CGND to the electronic system ES. The common ground CGND may be a power supply used in the electronic system ES. For example, the common ground CGND may be a voltage used as a reference for generating grounds AGND and DGND within the electronic system ES.

[0047] In an example embodiment, a first pin of the interface module IM may be connected to a common ground CGND of the setting module SM via a first pin connection. A second pin of the interface module IM may be connected to a common ground CGND of the setting module SM via a second pin connection. That is, the electronic system ES may receive a power supply corresponding to the analog ground AGND and a power supply corresponding to the digital ground DGND via different paths.

[0048] Figure 3 It is shown in detail Figure 1 A block diagram of a bandgap reference circuit 10 is shown in FIG. Figure 3 The bandgap reference circuit 10 may include a proportional to absolute temperature (PTAT) current generator 11 , a mirror current generator 12 , and / or a reference voltage generator 13 .

[0049] The PTAT current generator 11 can generate a PTAT current I PTAT PTAT current I PTAT The mirror current generator 12 may be electrically connected to the PTAT current generator 11. The current generator 12 may be a current whose magnitude increases in proportion to the absolute temperature. PTAT That is, the mirror current generator 12 can generate a mirror PTAT current I PTAT .

[0050] The reference voltage generator 13 can receive the mirror PTAT current I from the mirror current generator 12. PTAT , the reference voltage generator 13 may include a semiconductor device having a voltage inversely proportional to the absolute temperature. The reference voltage generator 13 may be based on the mirrored PTAT current I PTAT and the characteristics of semiconductor devices to generate a reference voltage V that is insensitive to absolute temperature REF .

[0051] For example, as the absolute temperature increases, the mirror PTAT current I PTAT The magnitude of the PTAT current I can be increased, while the voltage of the semiconductor device can be decreased. Therefore, the effect caused by the increase in absolute temperature can be offset. Conversely, in the case of a decrease in absolute temperature, the voltage of the semiconductor device can be increased, while the mirror PTAT current I PTAT The magnitude of can be reduced. Therefore, the effect caused by the decrease in absolute temperature can be offset. This will refer to Figure 4 Describe more fully.

[0052] Figure 4 It is shown in detail Figure 3 A circuit diagram of a bandgap reference circuit 10 is shown. Figure 4The bandgap reference circuit 10 may include a PTAT current generator 11 , a mirror current generator 12 , and a reference voltage generator 13 .

[0053] The PTAT current generator 11 may include a first resistor R1, transistors Q1, Q2, M1 and M2, and / or an amplifier AMP. A power supply voltage V SS and ground GND to the PTAT current generator 11. In an example embodiment, each of the transistors Q1 and Q2 may be a bipolar junction transistor (BJT). For example, the transistors Q1 and Q2 may be a PNP-type BJT, but the present disclosure is not limited thereto. For example, the transistors Q1 and Q2 may be an NPN-type BJT.

[0054] The transistor Q1 can be connected to the first input node N 11 and ground GND, and can operate in response to the ground GND. For example, the transistor Q1 may include a first input node N 11 The emitter node is connected to GND and the base and collector nodes are connected to ground GND.

[0055] The transistor Q2 may be connected between the first resistor R1 and the ground GND and may operate in response to the ground GND. For example, the transistor Q2 may include an emitter node connected to the first resistor R1 and a base node and a collector node connected to the ground GND.

[0056] The first resistor R1 may be connected to the second input node N 12 and transistor Q2. The amplifier AMP can amplify the first input node N 11 The voltage of the second input node N 12 The voltage difference between the output node N O The transistor M1 can be connected to a power supply voltage V SS The power supply node and the first input node N 11 between, and can respond to the output node N O The transistor M2 can be connected to a power supply voltage V SS The power supply node and the second input node N 12 between, and can respond to the output node N O For example, transistor M2 can operate in response to the voltage of output node N O The voltage generates the PTAT current I PTAT . Transistor M2 can convert the PTAT current I PTAT Output to the second input node N12.

[0057] The mirror current generator 12 may include a transistor M3. The power supply voltage V SS and output node N O The voltage of the output node N can be provided to the mirror current generator 12. The transistor M3 can respond to the output node N O The voltage generates the mirror PTAT current I PTAT . Transistor M3 can mirror the PTAT current I PTAT Output to reference node N REF . Reference node N REF Can be formed reference voltage V REF Node.

[0058] The reference voltage generator 13 may include a second resistor R2 and a transistor Q3. The reference voltage generator 13 may be configured to generate a voltage at a reference node N REF is provided with a mirrored PTAT current I PTAT The reference voltage generator 13 may be provided with a ground GND. In an example embodiment, the transistor Q3 may be a BJT. For example, the transistor Q3 may be a PNP type BJT.

[0059] The second resistor R2 can be connected to the reference node N REF The second resistor R2 can provide a mirror current I PTAT The transistor Q3 may be connected between the second resistor R2 and the ground GND, and may operate in response to the ground GND. For example, the transistor Q3 may include an emitter node connected to the second resistor R2, and a base node and a collector node connected to the ground GND.

[0060] The reference voltage generator 13 can be based on the mirror PTAT current I PTAT and the voltage V across transistor Q3 BE3 Generates a reference voltage V that is insensitive to absolute temperature REF . Reference voltage V REF The characteristic of being insensitive to absolute temperature will be more fully described with reference to Equation 1 below.

[0061] V REF =I PTAT R2+V BE3

[0062] [Equation 1]

[0063] The above equation 1 represents the reference voltage V REF Equation I PTAT is the mirror PTAT current I output from the mirror current generator 12 PTAT R2 is the resistance value of the second resistor R2. V BE3is the voltage value between the emitter node and the base node of transistor Q3. V BE3 May have a value that is inversely proportional to absolute temperature based on device characteristics.

[0064] Because the mirrored PTAT current I PTAT Based on the PTAT current I generated by the PTAT current generator 11 PTAT , so assuming "A" is the gain of transistor Q1 and n*A is the gain of transistor Q2, the PTAT current I PTAT It can be expressed by the following equation 2.

[0065]

[0066] Equation 2 above is the PTAT current I PTAT Equation. V BE1 is the voltage value between the emitter node and the base node of transistor Q1. V BE2 is the voltage value between the emitter node and the base node of transistor Q2. R1 is the resistance value of the first resistor R1. “n” is the ratio of the gain of transistor Q2 to the gain of transistor Q1. V T is the thermal voltage. Since the thermal voltage is proportional to the absolute temperature, the PTAT current I PTAT Can have a magnitude proportional to absolute temperature.

[0067] Returning to equation 1 above, since I PTAT has a value proportional to absolute temperature, and V BE3 has a value that decreases as the absolute temperature increases, so it can offset the fluctuation of absolute temperature. For example, when the absolute temperature increases, because I PTAT Increase V BE3 The effect of the absolute temperature increase on the reference voltage V REF On the contrary, when the absolute temperature decreases, because I PTAT Lowering V BE3 increase, so it can offset the increase in absolute temperature on the reference voltage V REF That is, the reference voltage V REF Can have a value that is insensitive to changes in absolute temperature.

[0068] Figure 5 is a diagram for describing an electronic device ED to which a heterogeneous power source is applied from a setting module SM. Figure 5, shows an electronic device ED to which a heterogeneous power supply is applied through pad bonding and pin connection and a setting module SM. The setting module SM may have a common ground CGND. The setting module SM may provide grounds AGND and DGND to the electronic device ED through separate pin connections and separate pad bonding.

[0069] The analog ground AGND of the electronic device ED can be connected by including a series resistor R X1 , R X2 and R X3 The first path is connected to the common ground CGND. The digital ground DGND of the electronic device ED can be connected by a series resistor R X1 , R X2 and R X3 The second path is connected to the common ground CGND. Here, the resistor R X1 It can be an internal resistor of the electronic device ED. Resistor R X2 It can be a resistor corresponding to the pad bond. Resistor R X3 Can be a resistor corresponding to the pin connection.

[0070] In an example embodiment, the electronic device ED may be a semiconductor chip including a plurality of circuits formed on a semiconductor substrate. The terminals of the ground terminals AGND and DGND of the electronic device ED may be used as separate terminals when designed. However, when the electronic device ED is manufactured on a semiconductor substrate, an unwanted resistance connection may occur between the terminals of the analog ground AGND and the digital ground DGND.

[0071] In an example embodiment, the digital ground DGND may be a power source that generates noise compared to the analog ground AGND. The noise of the digital ground DGND may be transferred to the analog ground AGND through an unwanted resistance connection. The effect of the noise of the digital ground DGND on the analog ground AGND may be represented by the following equation 3.

[0072]

[0073] Equation 3 above indicates the effect of noise from the digital ground DGND on the analog ground AGND. n DGND N is the noise of the random assumed digital ground DGND. X1 Is the internal resistance of the electronic device ED. X2 is the resistance value corresponding to the pad junction. R X3 is the resistance value corresponding to the pin connection. R X4 It is a value corresponding to the resistance connection occurring between the terminal of the analog ground AGND and the terminal of the digital ground DGND.

[0074] For example, when DGND n 100mV, R X1 , R X2 and R X3 When each of RX4 is 100mΩ and RX4 is 10Ω, the AGND calculated using Equation 3 above is N It can be 2.9mV.

[0075] As described above, in the electronic device ED, an unwanted resistance connection may occur between the terminal of the analog ground AGND and the terminal of the digital ground DGND. Figure 4 The bandgap reference circuit 10 may operate abnormally due to the resistance connection (for example, a reference voltage V may be generated that exceeds the value expected in the design). REF ). Therefore, a method may be needed to reduce the effect of noise from the digital ground DGND on the analog ground AGND.

[0076] Figure 6 It is shown in detail Figure 5 Schematic diagram of an electronic device ED. Figure 6 , showing a manufacturing process diagram corresponding to a portion of an electronic device ED formed on a semiconductor substrate. The electronic device ED may include a transistor "Q" and a digital circuit 30. The transistor "Q" may include a collector node CC, a base node BB, and an emitter node EE. The digital circuit 30 may include a digital node XX. The transistor "Q" may be a portion of a bandgap reference circuit 10 included in the electronic device ED. For example, the transistor "Q" may be Figure 4 One of the transistors Q1, Q2 and Q3.

[0077] The transistor "Q" of the electronic device ED and the digital circuit 30 may be formed on the same semiconductor substrate. The semiconductor substrate may be connected to the digital node XX of the digital circuit 30 and the collector node CC of the transistor "Q". The digital node XX may be provided with a digital ground DGND. The collector node CC may be provided with an analog ground AGND.

[0078] The first conductive region may be formed by implanting a first impurity into a semiconductor substrate. The first conductive region may be connected to a base node BB of transistor "Q". The base node may be provided with an analog ground AGND. The base node BB may be connected to a collector node CC.

[0079] The second conductive region may be formed by implanting a second impurity into the first conductive region. The second conductive region may be connected to the emitter node EE of the transistor "Q". The emitter node EE may be connected to any other node or element. For example, in the case where the transistor "Q" is Figure 4 In the case of transistor Q1, the emitter node EE can be connected to the node N 11 For example, in transistor "Q" is Figure 4 In the case of transistor Q2, the emitter node EE can be connected to the first resistor R1. For example, in the case of transistor "Q" is Figure 4 In the case of the transistor Q3, the emitter node EE may be connected with the second resistor R2.

[0080] In example embodiments, the semiconductor substrate may be a P-type semiconductor substrate. The first impurity may be an N-type impurity. The first conductive region may be an N-type region. The second impurity may be a P-type impurity. The second conductive region may be a P-type region.

[0081] like Figure 6 As shown, an unwanted resistive connection (e.g., R X4 ). Since noise of the digital ground DGND is introduced into the analog ground AGND through the unnecessary resistance connection, a method of reducing the influence according to the unnecessary resistance connection (for example, a method of increasing a value corresponding to the unnecessary resistance connection) is required.

[0082] Figure 7 Detailed description of the electronic device ED according to the exemplary embodiment. Figure 7 An exemplary embodiment is described in which the influence of the unwanted resistance connection is reduced. The transistor "Q" and the digital circuit 30 formed at the semiconductor substrate are similar to the reference Figure 6 The transistor “Q” is described similarly to the digital circuit 30 , and thus, additional description will be omitted to avoid redundancy.

[0083] In an example embodiment, a resistant barrier may be inserted into a semiconductor substrate of an electronic device ED. When the resistant barrier is inserted, a resistive connection (eg, R X4 ) can be increased. Therefore, the influence of the noise of the digital ground DGND on the analog ground AGND can be reduced.

[0084] Figure 8 Detailed description of the electronic device ED according to the exemplary embodiment. Figure 8An example embodiment is described in which the influence of the unwanted resistance connection is reduced, the common ground CGND and the resistor R X1 , R X2 and R X3 Similar to reference Figure 5 The common ground CGND and resistor R X1 , R X2 and R X3 , therefore, additional description will be omitted to avoid redundancy.

[0085] according to Figure 8 In an exemplary embodiment, a resistive barrier layer may be inserted into a semiconductor substrate of an electronic device ED and different pad bonds may be added. Figure 7 Compared to the exemplary embodiment, Figure 8 The electronic device ED may correspond to a digital ground DGND and may be connected to a pin corresponding to an analog ground AGND through a different pad.

[0086] In an example embodiment, when a resistive barrier layer is inserted into the electronic device ED and different pad bonds are added, the influence of the noise of the digital ground DGND on the analog ground AGND can be reduced. X5 It may be a resistor corresponding to a resistive barrier layer inserted into a semiconductor substrate of the electronic device ED. For example, the resistor R X2 It can be a resistor corresponding to the added pad bond.

[0087] Since the resistor R X2 and R X5 As well as the connection path between the grounds AGND and DGND, the influence of the noise of the digital ground DGND on the analog ground AGND can be expressed by the following Equation 4.

[0088]

[0089] Equation 4 above indicates the effect of noise from the digital ground DGND on the analog ground AGND. n DGND N is the noise of the random assumed digital ground DGND. X1 Is the internal resistance of the electronic device ED. X2 is the resistance value corresponding to the pad junction. R X3 is the resistance value corresponding to the pin connection. R X5 It is the resistance value of the resistance barrier layer corresponding to the semiconductor substrate inserted into the electronic device ED.

[0090] For example, when DGND n 100mV, RX1 , R X2 and R X3 When each of RX5 is 500Ω and RX5 is 100mΩ, the AGND calculated using Equation 4 above is N It can be 20μV.

[0091] As mentioned above, according to Figure 8 An example embodiment in which a resistive barrier layer is inserted and different pad bonds are added can reduce the effect of the noise of the digital ground DGND on the analog ground AGND. However, a process of adding a resistive barrier layer is required, a pad for pad bonding is added, and the noise introduced into the analog ground AGND is not sufficiently reduced. Therefore, another method is needed to reduce the noise introduced into the analog ground AGND at the electronic device ED.

[0092] Fig. 9 Detailed description of the electronic system ES according to an exemplary embodiment of the present invention. Fig. 9 , showing an electronic system ES according to an exemplary embodiment of the present disclosure. The first pad, the second pad, the interface module IM and the setting module SM are connected to the reference Figure 2 The described first pad, second pad, interface module IM and setting module SM are similar, and therefore, additional description will be omitted to avoid redundancy.

[0093] The electronic device ED may include a bandgap reference circuit 100, an analog circuit 200, a digital circuit 300, and / or an analog and digital circuit 400. Figure 2 Different from the electronic device ED, the bandgap reference circuit 100 of the electronic device ED may also be connected to the digital ground DGND and the analog ground AGND.

[0094] In example embodiments, the first power source received through the first pad may be applied to the bandgap reference circuit 100, the analog circuit 200, and the analog and digital circuit 400. For example, the first power source may be an analog ground AGND.

[0095] In example embodiments, the second power source received through the second pad may be applied to the bandgap reference circuit 100, the digital circuit 300, and the analog and digital circuit 400. For example, the second power source may be a digital ground DGND.

[0096] The bandgap reference circuit 100 according to an example embodiment of the present disclosure may operate based on a first power supply and a second power supply. When the bandgap reference circuit 100 operates based on both the first power supply and the second power supply, the bandgap reference circuit 100 may generate a response to PVT (e.g., Figure 2 Example embodiment) is less sensitive to the reference voltage V REF The bandgap reference circuit 100 will refer to Fig.10Describe more completely.

[0097] Fig.10 It is shown in detail Fig. 9 The circuit diagram of the bandgap reference circuit. Fig.10 , a bandgap reference circuit 100 including a PTAT current generator 110, a mirror current generator 120 and / or a reference voltage generator 130 is shown. Figure 4 Unlike the bandgap reference circuit 10 of FIG. 1 , the bandgap reference circuit 100 can also be operated based on the digital ground DGND. The transistors M1, M2, and M3, the amplifier AMP, and the resistors R1 and R2 are similar to the reference circuit 100. Figure 4 The transistors M1, M2, and M3, the amplifier AMP, and the resistors R1 and R2 are described, and thus additional description will be omitted to avoid redundancy.

[0098] The transistor Q1 can be connected to the first input node N 11 and ground GND, and can operate in response to analog ground AGND. For example, transistor Q1 may include a first input node N 11 An emitter node connected to AGND, a base node provided with an analog ground AGND, and a collector node connected to a digital ground DGND. In an example embodiment, the transistor Q1 may be a PNP type BJT.

[0099] The transistor Q2 may be connected between the first resistor R1 and the digital ground DGND, and may operate in response to the analog ground AGND. For example, the transistor Q2 may include an emitter node connected to the first resistor R1, a base node provided with the analog ground AGND, and a collector node connected to the digital ground DGND. In an example embodiment, the transistor Q2 may be a PNP-type BJT.

[0100] The transistor Q3 may be connected between the second resistor R2 and the digital ground DGND, and may operate in response to the analog ground AGND. For example, the transistor Q3 may include an emitter node connected to the second resistor R2, a base node provided with the analog ground AGND, and a collector node connected to the digital ground DGND. In an example embodiment, the transistor Q3 may be a PNP-type BJT.

[0101] In an example embodiment, the base node and the collector node of each of the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 may be electrically separated from each other. For example, the digital ground DGND may be provided to the collector node of at least one of the transistors Q1, Q2, and Q3, and the analog ground AGND may be provided to the base node thereof. The ground AGND and the DGND in the electronic device ED or the electronic system ES may be electrically separated from each other. The ground AGND and the DGND being electrically separated from each other may mean that a resistance value (e.g., R) corresponding to an unwanted resistance connection between the ground AGND and the DGND may be removed. X4 ) has increased greatly.

[0102] For example, the noise of the digital ground DGND affects the analog ground AGND. n can be calculated by using Equation 3 above. For example, when the resistor R X1 , R X2 and R X3 Each of them is 100mΩ, the experimentally measured R X4 Can be about 500kΩ. n For a voltage of 100mV, the AGND calculated using Equation 3 above is n The value of is about 60nV. n The value may be smaller than in other example embodiments (e.g., Figure 5 and 8 AGND calculated in the example embodiment of n value.

[0103] As described above, according to an exemplary embodiment of the present disclosure, a bandgap reference circuit 100 is provided that provides a heterogeneous power supply to a transistor (e.g., at least one of Q1, Q2, and Q3). As the influence of the noise of the digital ground DGND on the analog ground AGND is greatly reduced, the bandgap reference circuit 100 can generate a reference voltage V that is less sensitive to PVT. REF .

[0104] Fig.11 It is shown in detail Fig. 9 Schematic diagram of an electronic device ED. Fig.11 An example embodiment of providing a heterogeneous power supply to transistor "Q" is described. Transistor "Q" may be Fig.10 The transistor "Q" and the digital circuit 300 formed on the semiconductor substrate are connected to the reference Figure 6 The transistor “Q” is described similarly to the digital circuit 30 , and thus, additional description will be omitted to avoid redundancy.

[0105] The transistor "Q" of the bandgap reference circuit 100 may include a collector node CC provided with a digital ground DGND, a base node BB provided with an analog ground AGND, and an emitter node EE connected to any other node or element. Figure 6 Unlike the collector node CC of the digital circuit 300 or the collector node CC of the digital circuit 300, the digital ground DGND may be provided to the collector node CC. The collector node CC may be connected to the digital node XX of the digital circuit 300.

[0106] Instead of providing the same ground (e.g., AGND) to all nodes CC and BB of the bandgap reference circuit 100, an electronic device ED in which the resistance connection between the analog ground AGND and the digital ground DGND is increased may be provided by providing the digital ground DGND to the collector node CC of the bandgap reference circuit 100 and providing the analog ground AGND to the base node BB thereof. For example, the increase in the resistance connection between the analog ground AGND and the digital ground DGND may indicate an increase in the resistance between the analog ground AGND and the digital ground DGND, and thus the leakage current between the analog ground AGND and the digital ground DGND may be reduced.

[0107] Fig.12 1 is a graph showing the PTAT current I measured at the bandgap reference circuits 10 and 100 with DC noise introduced. PTAT Refer to the curve diagram of Fig.12 , showing a graph showing the DC noise of the digital ground DGND, showing that when the same ground is applied to the Figure 4 The example embodiment of the bandgap reference circuit 10 measures the PTAT current I PTAT The graph shows that when different grounding is applied to the Fig.10 The example embodiment of the bandgap reference circuit 100 measures the PTAT current I PTAT Graph of the curve. Fig.12 The graphs shown in share the same time axis.

[0108] Referring to the graph showing the DC noise of the digital ground DGND, the horizontal axis represents time and the vertical axis represents the voltage amplitude of the digital ground DGND. In an example embodiment, the amplitude of the digital ground DGND may increase from -2V to 0.7V over time. The digital ground DGND may be provided to the transistors Q1, Q2, and Q3 of the bandgap reference circuit 10 or the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100.

[0109] Referring to the PTAT current I measured when the same ground is applied to the bandgap reference circuit 10 PTATThe horizontal axis represents time, and the vertical axis represents the magnitude of the current. The solid line represents the PTAT current I output from the transistor M2. PTAT The dotted line indicates the mirrored PTAT current I output from transistor M3. PTAT .

[0110] In the exemplary embodiment, in the bandgap reference circuit 10 to which the digital ground DGND is applied increasing from -2V to 0.7V, the PTAT current I PTAT can be almost uniform, while the mirror PTAT current I PTAT It can be changed between about -43 μA and about -39 μA. That is, the bandgap reference circuit 10 with the same ground applied is less sensitive to PVT.

[0111] Referring to FIG. 1 , the PTAT current I measured when different grounds are applied to the bandgap reference circuit 100 is shown. PTAT The horizontal axis represents time, and the vertical axis represents the magnitude of the current. The solid line indicates the PTAT current I output from the transistor M2. PTAT The dotted line indicates the mirrored PTAT current I output from transistor M3. PTAT .

[0112] In an exemplary embodiment, in the bandgap reference circuit 100 to which the digital ground DGND is applied increasing from -2V to 0.7V, the PTAT current I PTAT can be almost uniform, and the mirror PTAT current I of transistor M3 PTAT That is, the bandgap reference circuit 100 with different grounds applied is less sensitive to PVT than the bandgap reference circuit 10 with the same ground applied.

[0113] Fig.13 is a diagram showing the reference voltage V at the bandgap reference circuit 100 with DC noise introduced. REF The distribution curve of . Fig.13 , when any DC noise of the digital ground DGND is introduced according to Fig.10 1. When the bandgap reference circuit 100 of an example embodiment is shown, the reference voltage V measured at the bandgap reference circuit 100 is shown. REF The horizontal axis represents the reference voltage V REF The vertical axis represents the reference voltage V REF The density of the distribution.

[0114] In an example embodiment, the reference voltage V measured at the bandgap reference circuit 100 is REF Can have a normal distribution. Reference voltage V REFCan have minimum, maximum, mean, and standard deviation.

[0115] In an example embodiment, the following Table 1 shows the reference voltage V measured when the DC noise of the digital ground DGND is introduced into the bandgap reference circuit 100 in the range of -0.3V to 0.3V. REF The standard deviation, minimum and maximum values ​​of

[0116] [Table 1]

[0117] DGND[V] -0.3 -0.2 -0.1 0 0.1 0.2 0.3 STDEV[V] 0.012732 0.012730 0.012729 0.012729 0.012729 0.012724 0.012733 <![CDATA[V REF_Min ]]> 1.1949 1.1949 1.1949 1.1949 1.1949 1.1949 1.1949 <![CDATA[V REF_Max ]]> 1.2304 1.2304 1.2304 1.2304 1.2304 1.2304 1.2304

[0118] The reference voltage V measured at the bandgap reference circuit 100 into which the DC noise of the digital ground DGND is introduced will be described with reference to Table 1. REF The DGND provided to the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 may be increased from -0.3V to 0.3V in units of 0.1V. STDEV is the reference voltage V measured at the corresponding DGND. REF The standard deviation of V REF_Min is the reference voltage V measured at the corresponding DGND REF Minimum value of V REF_Max is the reference voltage V measured at the corresponding DGND REF Referring to the measured values ​​in Table 1, even in the fluctuation of the digital ground DGND, the bandgap reference circuit 100 to which a heterogeneous power supply is applied can generate a reference voltage V that is insensitive to PVT. REF .

[0119] Fig.14 is a diagram showing the reference voltage V at the bandgap reference circuit 100 with DC noise introduced. REF A graph of the standard deviation of Fig.14 , a graph showing a standard deviation STDEV in the bandgap reference circuit 100 is shown, which corresponds to the digital ground DGND of Table 1 above.

[0120] The horizontal axis represents the magnitude of the digital ground DGND provided to the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100, and the vertical axis represents the measured reference voltage V REF The standard deviation of Fig.14 In the curve graph, the standard deviation STDEV has a relatively uniform value.

[0121] As mentioned above, the digital ground DGND may be a power supply that is often noisy or generates a lot of noise compared to the analog ground AGND. Fig.12 , 13As described in FIG. 14 , even if DC noise of the digital ground DGND is introduced into the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 operating based on a heterogeneous power supply, the bandgap reference circuit 100 can generate a reference voltage V of uniform amplitude. REF That is, the bandgap reference circuit 100 according to the example embodiment of the present disclosure may have a strong influence on the DC noise of the digital ground DGND.

[0122] Fig.15 is a graph showing gain and phase at the bandgap reference circuit 100 with AC noise introduced. Fig.10 and Fig.15 , the AC noise introduced into the digital ground DGND Fig.10 The bandgap reference circuit 100 is shown showing the measured reference voltage V REF The graph of the gain ACG1 to the digital ground DGND and shows the measured reference voltage V REF A graph of the phase ACG2 to the digital ground DGND.

[0123] Referring to the graph ACG1, the horizontal axis represents the frequency on a logarithmic scale and the vertical axis represents the gain. In the exemplary embodiment, the measured reference voltage V REF The gain to the digital ground DGND may have a value within a specific range at the operating frequency. The operating frequency may be a frequency within the range in which the bandgap reference circuit 100 operates. For example, at the operating frequency of the bandgap reference circuit 100, the measured reference voltage V REF The gain to the digital ground DGND may be approximately -77.6 dB. Thus, even if AC noise of the digital ground DGND is introduced into the bandgap reference circuit 100, the bandgap reference circuit 100 may still generate a reference voltage V of uniform amplitude. REF .

[0124] Referring to graph ACG2, the horizontal axis represents the frequency on a logarithmic scale and the vertical axis represents the phase. In the exemplary embodiment, the measured reference voltage V REF The phase to the digital ground DGND may have a value within a specific range at the operating frequency. In this way, the bandgap reference circuit 100 does not cause abnormal operation such as oscillation.

[0125] Fig.16A and 16B is a diagram showing the reference voltage V at the bandgap reference circuit 100 with AC noise introduced REF The waveform of the curve. Fig.10 and Fig.16A , in an example embodiment where the AC noise of the digital ground DGND has a frequency of 100 kHz, a graph showing a waveform of the digital ground DGND and a graph showing a measured reference voltage VREF The horizontal axis represents time and the vertical axis represents voltage.

[0126] In an example embodiment, when the AC noise of the digital ground DGND having a frequency of 100 kHz has a first peak-to-peak voltage Vpp1, the reference voltage V measured at the bandgap reference circuit 100 is REF The second peak-to-peak voltage Vpp2 may have a second peak-to-peak voltage Vpp2. The second peak-to-peak voltage Vpp2 may be less than the first peak-to-peak voltage Vpp1. That is, even if AC noise of the digital ground DGND having a frequency of 100 kHz is introduced, the bandgap reference circuit 100 may still operate normally.

[0127] Reference Fig.10 and Fig. 16B , in an example embodiment in which the AC noise of the digital ground DGND has a frequency of 1 MHz, a graph showing a waveform of the digital ground DGND and a graph showing a measured reference voltage V REF The horizontal axis represents time and the vertical axis represents voltage.

[0128] In an example embodiment, when the AC noise of the digital ground DGND having a frequency of 1 MHz has a third peak-to-peak voltage Vpp3, the reference voltage V measured at the bandgap reference circuit 100 is REF The fourth peak-to-peak voltage Vpp4 may have a fourth peak-to-peak voltage Vpp4. The fourth peak-to-peak voltage Vpp4 may be less than the third peak-to-peak voltage Vpp3. That is, even if AC noise of the digital ground DGND having a frequency of 1 MHz is introduced, the bandgap reference circuit 100 may still operate normally.

[0129] As mentioned above, the digital ground DGND may be a power supply that is often noisy or generates a lot of noise compared to the analog ground AGND. Fig.15 , Fig.16A and Fig. 16B As described above, even if AC noise of the digital ground DGND is introduced into the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 operating based on a heterogeneous power supply, the bandgap reference circuit 100 can generate a reference voltage V of uniform amplitude. REF In addition, abnormal operations such as oscillation may be reduced at the bandgap reference circuit 100. That is, the bandgap reference circuit 100 according to the example embodiment of the present disclosure may have a strong influence on the AC noise of the digital ground DGND.

[0130] Fig.17 is a block diagram illustrating an image sensor device ISD according to an example embodiment of the present disclosure. Fig.17 An image sensor device ISD according to an example embodiment of the present disclosure is shown. The image sensor device ISD may be Fig. 9 The image sensor device ISD is an implementation example of an electronic device ED. The image sensor device ISD may be a semiconductor chip included in a digital camera, a smart phone, a tablet computer, a laptop computer, etc. The image sensor device ISD may operate in an analog domain, a digital domain, and both analog and digital domains.

[0131] For example, analog signals such as analog ground AGND can be used in the analog domain. Digital signals such as digital ground DGND can be used in the digital domain. Both analog signals such as analog ground AGND and digital signals such as digital ground DGND can be used in the analog and digital domains.

[0132] The connection lines are omitted to prevent the drawing from being complicated. However, the analog ground AGND received from the first pin may be provided to at least one circuit included in the analog domain, and may be provided to at least one circuit included in the analog and digital domains. In addition, the digital ground DGND received from the second pin may be provided to at least one circuit included in the digital domain, and may be provided to at least one circuit included in the analog and digital domains.

[0133] The image sensor device ISD may include circuits in the analog domain, circuits in the digital domain, and circuits in the analog and digital domains. For example, the image sensor device ISD may include a pixel array 210, a capacitor and switch network, and a comparator used in the analog domain. The image sensor device ISD may include a counter, a memory cell, a second decoder 310, and a sense amplifier used in the digital domain. The image sensor device ISD may include a bandgap reference circuit 100, a device interface circuit 410, a ramp generator 420, a pixel voltage generator 430, and / or a first driver and a first decoder 440 used in the analog and digital domains.

[0134] The device interface circuit 410 may include a first pad and a second pad. The analog ground AGND may be formed at the first pad based on the power received from the first pin. The digital ground DGND may be formed at the second pad based on the power received from the second pin. The device interface circuit 410 may receive a power supply voltage V from a separate power module (not shown). SS The device interface circuit 410 can transmit power (eg, AGND, DGND, and V SS ) is sent to the bandgap reference circuit 100.

[0135] The bandgap reference circuit 100 can be based on the power supplies (eg, AGND, DGND, and V SS ) to generate the reference voltage V REFIn an example embodiment, the bandgap reference circuit 100 may further include a current source configured to generate a current based on the reference voltage V REF Output reference current.

[0136] For example, the bandgap reference circuit 100 may further include a first current source CS1, wherein the first current source CS1 is configured to be based on the reference voltage V REF Output the first reference current I REF1 The first reference current I REF1 For example, the bandgap reference circuit 100 may further include a second current source CS2 configured to be based on the reference voltage V REF Output the second reference current I REF2 The second reference current I REF2 The second reference current I REF2 can be in conjunction with the use of a first reference current I REF1 The current used in different circuits.

[0137] In an example embodiment, the bandgap reference circuit 100 may be configured to generate a reference voltage V REF and the first reference current I REF1 The bandgap reference circuit 100 can output the second reference current I REF2 Output to ramp generator 420.

[0138] The ramp generator 420 can be based on the second reference current I REF2 Generate a ramp power supply. The ramp generator 420 can output the ramp power supply to the comparator in the analog domain. The ramp power supply can be a power supply signal used in the comparison operation of the comparator.

[0139] The pixel voltage generator 430 may be based on the reference voltage V REF and the first reference current I REF1 Generate pixel voltage. The pixel voltage generator 430 may output the pixel voltage to the first driver and the first decoder 440. The pixel voltage may be a power supply signal for the first driver and the first decoder 440 to control the pixels of the pixel array 210. The first driver and the first decoder 440 may control the pixels of the pixel array 210 based on the pixel voltage received from the pixel voltage generator 430.

[0140] The pixel array 210 may include a plurality of pixels arranged along a first direction and a second direction. Each of the pixels may generate an image signal under the control of the first driver and the first decoder 440. Each of the pixels may output an image signal to a corresponding capacitor and a switch network. That is, the pixel array 210 may be a circuit driven based on a pixel voltage of the pixel voltage generator 430 and configured to output a plurality of image signals.

[0141] The capacitor and switch network may be connected to a corresponding comparator. The capacitor and switch network may output an image signal received from a corresponding pixel of the pixel array 210 to the comparator.

[0142] The comparator may perform a comparison operation based on the image signal received from the capacitor and switch network and the ramp voltage received from the ramp generator 420. The comparator may output a comparison signal as a result of performing the comparison operation to the counter. For example, when the amplitude of the image signal is greater than the amplitude of the ramp voltage, the comparator may output a comparison signal of a first voltage level. When the amplitude of the image signal is less than the amplitude of the ramp voltage, the comparator may output a comparison signal of a second voltage level.

[0143] The counter may receive a comparison signal from a corresponding comparator. The counter may determine a count value based on the received comparison signal. For example, the counter may count comparison signals having a first voltage level among the comparison signals received from the comparator within a specific time. The counter may output a signal indicating the determined count value to a corresponding storage unit.

[0144] The storage unit may store data based on a signal received from the counter. The storage unit may be connected to the sense amplifier 320. The second decoder 310 may control a plurality of storage units. For example, the second decoder 310 may control the storage unit so that the data signal is output to the sense amplifier 320 corresponding to the storage unit.

[0145] As described above, the bandgap reference circuit 100 according to an example embodiment of the present disclosure may be a circuit included in the image sensor device ISD. Also, the bandgap reference circuit 100 may be based on the reference voltage V REF Generate a current that is not sensitive to PVT (eg, a first reference current I REF1 Or the second reference current I REF2 ).

[0146] Fig.18 is a block diagram showing in detail an electronic system ES according to an exemplary embodiment of the present disclosure. Fig.18, an electronic system ES including a semiconductor chip implemented on a printed circuit board (PCB) is shown. The electronic system ES may include an interface module IM, an electronic device ED, an analog chip and / or a digital chip. The electronic device ED may include a bandgap reference circuit 100, an analog circuit 200, a digital circuit 300 and / or an analog and digital circuit 400.

[0147] The analog chip may be a semiconductor chip that operates based on an analog signal such as an analog ground AGND. The digital chip may be a semiconductor chip that operates based on a digital signal such as a digital ground DGND. Unlike the analog circuit 200 and the digital circuit 300 formed on the semiconductor substrate of the electronic device ED, the analog chip and the digital chip may be semiconductor chips that are manufactured or used independently of the electronic device ED.

[0148] In an example embodiment, the electronic system ES may include an interface module IM, an electronic device ED, an analog chip, and / or a digital chip implemented at a PCB. For example, the analog chip may be deposited on an analog plane of the PCB. The digital chip may be deposited at a digital plane of the PCB. The electronic device ED may be deposited at both the analog plane and the digital plane of the PCB.

[0149] The interface module IM may include a first pin and a second pin. The first pin may receive a common ground CGND from the setting module SM through the first pin connection. The second pin may receive a common ground CGND from the setting module SM through the second pin connection. The first pin may be connected to the electronic device ED and the analog chip. The common ground CGND input to the first pin may be used as the analog ground AGND of the electronic device ED and the analog chip. The second pin may be connected to the electronic device ED and the digital chip. The common ground CGND input to the second pin may be used as the digital ground DGND at the electronic device ED and the digital chip.

[0150] In an example embodiment, a pad bond can be achieved by connecting a pad of a semiconductor device such as an electronic device ED and a pad of a PCB. For example, with reference to a pad bond providing an analog ground AGND of the electronic device ED, the electronic device ED may include a first pad. The first pad may be an on-chip pad. The analog plane of the PCB may include a third pad. The third pad may be a PCB pad. The first pad and the third pad may be connected by a wire. The wire may be formed of a conductive material. The third pad may be connected to a first pin of the interface module IM. For example, the first pad, the corresponding wire, and the third pad may be referred to as a "first pad bond".

[0151] For example, the electronic device ED may include a second pad that is an on-chip pad. The digital plane of the PCB may include a fourth pad that is a PCB pad. The second pad and the fourth pad may be connected by a wire. The fourth pad may be connected to a second pin of the interface module IM. For example, the second pad, the corresponding wire, and the fourth pad may be referred to as "second pad bonding".

[0152] However, the present disclosure is not limited thereto. Fig.18 Unlike the example described in , the electronic system ES may include semiconductor chips connected by using through silicon vias (TSVs). For example, the pad bonding may indicate a through silicon via connecting the semiconductor chips.

[0153] Any of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0154] According to the present disclosure, a bandgap reference circuit and an electronic device including the bandgap reference circuit are provided, in which the reliability of a reference voltage is improved by using a heterogeneous power supply.

[0155] In addition, a bandgap reference circuit that reduces the influence due to noise introduced from any other circuit and is less sensitive to PVT and an electronic device including the same are provided.

[0156] While the present disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A bandgap reference circuit in a semiconductor device, comprising: a first current generator configured to generate a first current proportional to temperature; a second current generator configured to output a second current obtained by mirroring the first current to a first node forming a reference voltage; a first resistor connected to the first node and supplied with a second current; and a first bipolar junction transistor (BJT), the first BJT including an emitter node connected to the first resistor, a base node supplied with a first power source, and a collector node supplied with a second power source different from the first power source, wherein the first power supply is provided via a first pad and the first power supply is an analog ground for signal processing in an analog domain, and the second power supply is provided via a second pad and the second power supply is a digital ground for signal processing in a digital domain, The first pad is separated from the second pad so that the analog ground and the digital ground in the semiconductor device are electrically separated. 2 . The bandgap reference circuit of claim 1 , wherein a base node of the first BJT is connected to a first pad, and a collector node of the first BJT is connected to a second pad.

3. The bandgap reference circuit according to claim 2, wherein the first pad is connected to the first pin of the interface module through a first pad bond, The second pad is connected to the second pin of the interface module through the second pad bonding, wherein the first pin is connected to a common ground of the setting module through the first pin connection, and The second pin is connected to the common ground of the setting module through the second pin connection.

4. The bandgap reference circuit according to claim 1, wherein the first current generator comprises: a second BJT including an emitter node connected to the second node; a second resistor connected to a third node; a third BJT including an emitter node connected to the second resistor; an amplifier configured to amplify a difference between a voltage of the second node and a voltage of the third node, and output the amplified result to a fourth node; a first transistor connected between a power supply node and the second node and configured to operate in response to a voltage of the fourth node; as well as A second transistor is connected between the power supply node and the third node and is configured to output the first current in response to a voltage of the fourth node.

5. The bandgap reference circuit according to claim 4, wherein the second current generator comprises: a third transistor connected between the power supply node and the first node and configured to output the second current in response to a voltage of the fourth node.

6. The bandgap reference circuit of claim 4, wherein the second BJT includes a base node supplied with the first power supply and a collector node supplied with the second power supply, and The third BJT includes a base node supplied with the first power supply and a collector node supplied with the second power supply. 7 . The bandgap reference circuit according to claim 6 , wherein the first to third BJTs are PNP type BJTs.

8. The bandgap reference circuit according to claim 1, further comprising: A current source is configured to output a reference current based on a reference voltage at the first node.

9. An electronic device, comprising: A bipolar junction transistor (BJT), wherein the BJT is formed at a semiconductor substrate; as well as a digital circuit formed at the semiconductor substrate and configured to operate in a digital domain, The BJTs include: a collector node connected to the semiconductor substrate and sharing a first power supply with a digital node of the digital circuit; a base node connected to a first conductive region formed by implanting a first impurity into the semiconductor substrate and supplied with a second power source different from the first power source; and an emitter node connected to a second conductive region formed by implanting a second impurity into the first conductive region and to a resistor supplied with a current proportional to the temperature from the mirror current generator, wherein the first power supply is provided via a first pad and the first power supply is an analog ground for signal processing in an analog domain, and the second power supply is provided via a second pad and the second power supply is a digital ground for signal processing in a digital domain, The first pad is separated from the second pad so that the analog ground and the digital ground in the semiconductor device are electrically separated.

10. The electronic device according to claim 9, further comprising: a first pad connected to a collector node of the BJT and configured to receive the first power supply from a first pin; as well as A second pad is connected to a base node of the BJT and is configured to receive the second power supply from a second pin. 11 . The electronic device according to claim 9 , wherein the semiconductor substrate is a P-type semiconductor substrate, the first impurity is an N-type impurity, and the second impurity is a P-type impurity.

12. An electronic device comprising: a first circuit configured to operate based on a first power source; a second circuit configured to operate based on a second power supply different from the first power supply; as well as a bandgap reference circuit configured to generate a reference voltage for operation of the first circuit and the second circuit based on the first power supply and the second power supply, The bandgap reference circuit comprises: a first current generator configured to generate a first current proportional to temperature; a second current generator configured to output a second current obtained by mirroring the first current to a first node forming a reference voltage; a first resistor connected to the first node and supplied with a second current; and a bipolar junction transistor (BJT), the BJT including an emitter node connected to the first resistor, a base node supplied with the first power supply, and a collector node supplied with the second power supply, wherein the first power supply is provided via a first pad and the first power supply is an analog ground for signal processing in an analog domain, and the second power supply is provided via a second pad and the second power supply is a digital ground for signal processing in a digital domain, The first pad is separated from the second pad so that the analog ground and the digital ground in the semiconductor device are electrically separated.

13. The electronic device according to claim 12, further comprising: A third circuit is configured to operate based on the first power supply, the second power supply, and the reference voltage.

14. The electronic device according to claim 12, further comprising: a first pad connected to a base node of the BJT and the first circuit and configured to receive the first power supply from a first pin of an interface module; as well as A second pad is connected to a collector node of the BJT and the second circuit and is configured to receive the second power supply from a second pin of the interface module.

15. The electronic device of claim 12, wherein the bandgap reference circuit further comprises: A first current source is configured to output a first reference current based on the reference voltage; as well as The second current source is configured to output a second reference current based on the reference voltage.

16. The electronic device according to claim 15, further comprising: a pixel voltage generator configured to output a pixel voltage based on the reference voltage and the first reference current; a ramp generator configured to output a ramp power supply based on the second reference current; a pixel array driven based on the pixel voltage and configured to output a plurality of image signals; as well as A plurality of comparators are configured to compare the plurality of image signals with the ramp power supply respectively, so as to output a plurality of comparison signals respectively.

Images