Semiconductor structure and method for forming the same

Abstract

The technical solution of the present application provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate, the substrate comprising an epitaxial layer; a first doped region, discretely located in the epitaxial layer; a first JFET region, located on a partial surface of the first doped region; a second JFET region, located on a partial surface of the epitaxial layer between adjacent first doped regions; a well region, located on the first JFET region and the second JFET region; a source region, extending from the surface of the well region to the well region; a second doped region, located on the surface of the first doped region between adjacent source regions, and the second doped region is coplanar with the surface of the source region; a gate structure, located in the source region and the well region and extending between the first JFET region and the second JFET region, and the entire or partial bottom of the gate structure is adjacent to the first doped region. The technical solution of the present application can reduce the electric field at the bottom of the gate structure and reduce the gate-drain charge.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of power MOSFET technology, trench MOSFET has emerged. The biggest advantage of trench MOSFET is that it can increase the channel density of planar devices to improve the current handling capability of the device. However, the bottom of the gate structure of current trench MOSFET is subjected to a high electric field and the gate-drain charge (Qgd) is large. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a semiconductor structure and a method for forming the same, which can reduce the electric field at the bottom of the gate structure and reduce the gate leakage charge.

[0004] To solve the above technical problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising an epitaxial layer; a first doped region, discretely located in the epitaxial layer; a first JFET region, located on a partial surface of the first doped region; a second JFET region, located on a partial surface of the epitaxial layer between adjacent first doped regions; a well region, located on the first JFET region and the second JFET region; a source region, extending from the surface of the well region to the well region; a second doped region, located on the surface of the first doped region between adjacent source regions, and the second doped region is coplanar with the surface of the source region; a gate structure, located in the source region and the well region and extending between the first JFET region and the second JFET region, and the entire or partial bottom of the gate structure is adjacent to the first doped region.

[0005] In an embodiment of the present application, the first doped region is distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region spans or does not span the first doped region in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

[0006] In the embodiment of the present application, surfaces of the first JFET region and the second JFET region are coplanar.

[0007] In an embodiment of the present application, the depth of the source region is 0.2μm-0.4μm; the depth of the second doping region is 1.2μm-1.5μm; the depth of the well region is 0.8μm-1.0μm; the thickness of the first JFET region and the second JFET region is 0.3μm-0.4μm; the thickness of the first doping region is 0.4μm-0.8μm.

[0008] In an embodiment of the present application, the gate structure includes a gate oxide layer and a gate layer located on a surface of the gate oxide layer.

[0009] In the embodiment of the present application, the depth of the gate layer is 1.1 μm-1.5 μm.

[0010] In an embodiment of the present application, the epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the first doping region, the second doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

[0011] In the embodiment of the present application, the doping concentration of the first doping region is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 , the doping concentration of the first JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 , the doping concentration of the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

[0012] In an embodiment of the present application, the semiconductor structure also includes: an interlayer dielectric layer, located on the surface of the gate structure and a portion of the source region; a source contact layer, located on the surface of the source region and the second doped region between the interlayer dielectric layers, and the surface of the source contact layer and the interlayer dielectric layer are coplanar; a source metal, located on the surface of the interlayer dielectric layer and the source contact layer.

[0013] The present application also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an epitaxial layer, wherein a discrete first doped region is formed in the epitaxial layer; forming a first JFET region on a portion of the surface of the first doped region; forming a second JFET region on the surface of the epitaxial layer between adjacent first doped regions; forming a well region in the epitaxial layer higher than the second JFET region; forming a source region extending from the surface of the well region on the first JFET region and the second JFET region to the well region; forming a second doped region extending from the surface of the well region between adjacent source regions to the surface of the first doped region; etching a portion of the source region, the well region, the first JFET region and the second JFET region, and forming a gate structure at a corresponding position, wherein the entire or partial bottom of the gate structure is adjacent to the first doped region.

[0014] In an embodiment of the present application, the first doped region is distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region spans or does not span the first doped region in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

[0015] In the embodiment of the present application, surfaces of the first JFET region and the second JFET region are coplanar.

[0016] In an embodiment of the present application, an ion implantation process is used to form the first doped region, the first JFET region, the second JFET region, the well region, the source region and the second doped region; wherein the temperature of the ion implantation process for forming the first doped region, the well region, the source region and the second doped region is 500°C-600°C, and the temperature of the ion implantation process for forming the first JFET region and the second JFET region is 20°C-40°C or 500°C-600°C.

[0017] In an embodiment of the present application, the epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the first doping region, the second doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

[0018] In the embodiment of the present application, the doping concentration of the first doping region is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 , the doping concentration of the first JFET region and the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

[0019] In an embodiment of the present application, before forming the gate structure, it also includes: forming a carbon layer on the surface of the source region and the second doping region; performing annealing to activate doped ions under the protection of the carbon layer; and removing the carbon layer.

[0020] In an embodiment of the present application, the method for forming the gate structure includes: etching part of the source region, the well region, the first JFET region and the second JFET region, stopping on the surface of the epitaxial layer and the first doped region, to form a trench; forming a gate oxide layer on the sidewall and bottom of the trench; and forming a gate layer filling the trench on the surface of the gate oxide layer.

[0021] In an embodiment of the present application, the method for forming the semiconductor structure also includes: forming an interlayer dielectric layer on the surface of the gate structure and a portion of the source region; forming a source contact layer on the surface of the source region and the second doped region between the interlayer dielectric layer, and the surface of the source contact layer and the interlayer dielectric layer are coplanar; forming a source metal on the surface of the interlayer dielectric layer and the source contact layer.

[0022] The technical solution of the present application forms a first doped region in the epitaxial layer, and a first JFET region is formed on a portion of the surface of the first doped region, a second JFET region is formed on a portion of the surface of the epitaxial layer between adjacent first doped regions, a second doped region extending to the surface of the first doped region is formed between adjacent source regions, and the first doped region is adjacent to the entire or partial bottom of the gate structure, wherein the first JFET region and the second JFET region can improve the drain-source on-resistance RDS(on), and the first doped region can reduce the electric field of the gate oxide layer, thereby improving the reliability of the gate oxide layer and reducing the gate-drain charge. Furthermore, the first doped region is discrete and distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, which can prevent the diffusion of basal plane dislocation defects and improve conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0024] Figure 1 A schematic diagram of the structure of a trench MOSFET;

[0025] Figures 2 to 20 Schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0027] refer to Figure 1A trench MOSFET includes an epitaxial layer 10, a gate structure 20 is formed in the epitaxial layer 10, a well region 30 is formed between adjacent gate structures 20, an active region 40 is formed in the well region 30, the source region 40 is adjacent to the sidewall of the gate structure 20, and a doping region 50 is formed in the source region 40 and the well region 30, and both the source region 40 and the doping region 50 extend from the surface of the well region 30 to the well region 30. Although this trench MOSFET can improve the current handling capability of the device, it has a higher electric field at the bottom of the gate structure 20, and the gate-drain charge Qgd is large.

[0028] Based on this, the semiconductor structure of the technical solution of the present application and the method for forming the same form a first doped region in the epitaxial layer, and form a first JFET region on a partial surface of the first doped region, and form a second JFET region on a partial surface of the epitaxial layer between adjacent first doped regions, and the first doped region is adjacent to the entire or partial bottom of the gate structure, wherein the first JFET region and the second JFET region can further improve the drain-source on-resistance RDS(on); the first doped region can reduce the electric field of the gate oxide layer, thereby improving the reliability of the gate oxide layer, and at the same time, the first doped region can also prevent the diffusion of basal plane dislocation (BPD) defects and improve conductivity.

[0029] The semiconductor structure of the technical solution of the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] refer to Fig.17 The present invention provides a semiconductor structure, comprising: a substrate, wherein the substrate comprises an epitaxial layer 100. The epitaxial layer 100 may be doped with impurity ions. For example, ions of nitrogen, arsenic, antimony or phosphorus may be implanted. As an example, the epitaxial layer 100 is lightly doped with N-type, and the doping concentration may be 10 14 / cm 3 -10 16 / cm 3 In some embodiments, the substrate may further include other substrate layers located below the epitaxial layer 100. In some embodiments, the epitaxial layer 100 further includes an N-type heavily doped layer, for example, by ion implantation of nitrogen, arsenic, antimony or phosphorus, with a doping concentration of 10 16 / cm 3 -10 19 / cm 3 within the range.

[0031] The first doping region 210 is separately located in the epitaxial layer 100. The doping type of the first doping region 210 is different from the doping type of the epitaxial layer 100. In some embodiments, the epitaxial layer 100 is N-type doped, and the first doping region 210 is P-type doped. The doping concentration of the first doping region 210 is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 The thickness of the first doping region 210 is 0.4 μm-0.8 μm. Figure 2 and 17 The first doped region 210 is distributed along the extension direction of the gate structure (y direction) and perpendicular to the extension direction of the gate structure (x direction). This distribution method can prevent the expansion of BPD defects and thus improve the conductivity of the device.

[0032] refer to Fig.17 and Fig.18 , Fig.17 is a cross-sectional view along a direction perpendicular to the extension direction of the gate structure, Fig.18 for Fig.17 The cross-sectional view at HH, that is, Fig.18 is a cross-sectional view along the extension direction of the gate structure. The semiconductor structure further includes a first JFET region 220, which is located on a portion of the surface of the first doping region 210. The first JFET region 220 is a continuous structure and crosses the first doping region 210 in the extension direction of the gate structure, that is, part of the first JFET region 220 is located on a portion of the surface of the first doping region 210, and the rest is located on the surface of the epitaxial layer 100 between adjacent first doping regions 210. At this time, the first JFET region 220 is adjacent to the epitaxial layer 100 through the bottom.

[0033] refer to Fig.19 In some other embodiments, the first JFET region 220 is a discontinuous discrete structure and is only located on a portion of the surface of the first doping region 210. The widths of the first JFET region 220 and the first doping region 210 in the extension direction of the gate structure are equal. At this time, the first JFET region 220 is adjacent to the epitaxial layer 100 through the sidewall.

[0034] The first JFET region 220 has the same doping type as the epitaxial layer 100 and is opposite to the doping type of the first doping region 210. As an example, the first JFET region 220 is N-type doped and has a doping concentration of 3×10 16 / cm 3 Up to 2×10 17 / cm 3In some embodiments, the thickness of the first JFET region 220 may be 0.3 μm-0.4 μm. Fig.17 , a second JFET region 230 is further included on the surface of the epitaxial layer 100 between the adjacent first doping regions 210. The arrangement of the first JFET region 220 and the second JFET region 230 can further improve RDS(on). The extension direction of the second JFET region 230 is the same as the extension direction of the gate structure. The second JFET region 230 is a continuous structure, for example, in the shape of a long strip. The surfaces of the first JFET region 220 and the second JFET region 230 are coplanar. As an example, the thickness of the second JFET region 230 is 0.3μm-0.4μm. The second JFET region 230 has the same doping type as the first JFET region 220, and the doping concentration of the first JFET region 220 can be equal to the doping concentration of the second JFET region 230. Since the first JFET region 220 and the epitaxial layer 100 are blocked by the first doping region 210, the doping of the first JFET region 220 can also be greater than the doping concentration of the second JFET region 230, so as to further improve the improvement effect on RDS(on). As an example, the second JFET region 230 is N-type doped, and the doping concentration of the second JFET region 230 is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

[0035] The first JFET region 220 and the second JFET region 230 include a well region 240. The depth of the well region 240 may be 0.8 μm-1.0 μm. The well region 240 may be lightly doped with a P-type. For example, the well region 240 may be doped with aluminum ions to make the doping concentration of the well region 240 be 5×10 16 / cm 3 Up to 5×10 20 / cm 3 .

[0036] The source region 250 extends from the surface of the well region 240 into the well region 240, and the doping type of the source region 250 is opposite to that of the well region 240, and the doping type of the first JFET region 220 and the second JFET region 230 is the same. As an example, the source region 250 is N-type doped, and the doping concentration is 1×10 18 / cm 3 Up to 1×10 21 / cm 3In some embodiments, the depth of the source region 250 is 0.2 μm-0.4 μm, wherein the depth of the source region 250 refers to the distance from the surface of the well region 240 to the bottom of the source region 250. Since the surfaces of the source region 250 and the well region 240 are coplanar, the depth of the source region 250 is also the distance from the surface of the source region 250 to the bottom of the source region 250, and the depth of the well region 240 may also refer to the distance from the surface of the source region 250 to the bottom of the well region 240.

[0037] The semiconductor structure of the embodiment of the present application further includes a second doping region 260. The second doping region 260 is located on the surface of the first doping region 210 between the adjacent source regions 250, and the second doping region 260 is coplanar with the surface of the source region 250. Extending the second doping region 260 to the surface of the first doping region 210 can prevent the first doping region 210 from becoming a floating junction. The second doping region 260 has the same doping type as the first doping region 210 and the well region 240, for example, P-type doping. In some embodiments, the doping concentration of the second doping region 260 is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 The depth of the second doping region 260 is 1.2 μm-1.5 μm, wherein the depth of the second doping region 260 refers to the distance from the surface of the second doping region 260 to the bottom of the second doping region 260 , that is, the distance from the surface of the second doping region 260 to the surface of the first doping region 210 .

[0038] Continue to refer Fig.17 , the semiconductor structure further includes a gate structure, the gate structure is located in the source region 240 and the well region 240 and extends between the first JFET region 220 and the second JFET region 230, and the entire bottom of the gate structure is adjacent to the first doping region 210, or part of the bottom of the gate structure is adjacent to the first doping region 210. The gate structure may include a gate oxide layer 310 and a gate layer 320 located on the surface of the gate oxide layer 310. The material of the gate oxide layer 310 may include oxide, oxynitride, etc. The thickness of the gate oxide layer 310 may be between 350 angstroms and 550 angstroms. The material of the gate layer 320 may include polysilicon, and the depth of the gate layer 320 may be 1.1 μm-1.5 μm. The depth of the gate layer 320 refers to the distance from the surface of the gate layer 320 to the bottom surface of the gate layer 320.

[0039] In the embodiment of the present application, since the first doping region 210 covers part or all of the bottom of the gate structure, the electric field of the gate oxide layer is reduced, thereby significantly improving the reliability of the gate oxide layer.

[0040] refer to Fig. 20 The semiconductor structure may further include: an interlayer dielectric layer 330, wherein the interlayer dielectric layer 330 is located on the surface of the gate structure and a portion of the source region 250; a source contact layer 410, located on the surface of the source region 250 and the second doped region 260 between the interlayer dielectric layer 330, and the surface of the source contact layer 410 and the interlayer dielectric layer 330 are coplanar; and a source metal 420, located on the surface of the interlayer dielectric layer 330 and the source contact layer 410.

[0041] The method for forming a semiconductor structure according to an embodiment of the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0042] The method for forming a semiconductor structure according to an embodiment of the present application comprises the following steps:

[0043] Step S1: providing a substrate, wherein the substrate comprises an epitaxial layer, and a discrete first doped region is formed in the epitaxial layer;

[0044] Step S2: forming a first JFET region on a portion of the surface of the first doped region;

[0045] Step S3: forming a second JFET region on the surface of the epitaxial layer between adjacent first doped regions;

[0046] Step S4: forming a well region in the epitaxial layer higher than the second JFET region;

[0047] Step S5: forming a source region extending from the surface of the well region on the first JFET region and the second JFET region to the well region;

[0048] Step S6: forming a second doped region extending from the surface of the well region between the adjacent source regions to the surface of the first doped region;

[0049] Step S7: etching a portion of the source region, the well region, the first JFET region and the second JFET region, and forming a gate structure at a corresponding position, wherein the entire or a portion of the bottom of the gate structure is adjacent to the first doped region.

[0050] refer to Figure 2 and Figure 3 ,in Figure 2 This is a top view of the semiconductor structure obtained in step S1. In order to clearly illustrate the distribution of the first doped region 210 in the epitaxial layer 100, the epitaxial layer 100 covering the first doped region 210 is removed. Figure 3 for Figure 2 Schematic diagram of the cross section at AA, Figure 3 2 shows an epitaxial layer 100 covering the first doped region 210. In step S1, a substrate is provided including an epitaxial layer 100. The epitaxial layer 100 may be lightly doped with an N-type, for example, formed by ion implantation of nitrogen, arsenic, antimony or phosphorus. In some embodiments, an N-type heavily doped layer is also formed below the epitaxial layer 100.

[0051] The first doping region 210 is formed by an ion implantation process. The process of forming the first doping region 210 may include: forming a first oxide layer (not shown) on the surface of the epitaxial layer 100, the first oxide layer may act as a mask, and the thickness of the first oxide layer may be 1.6 μm-2 μm; then performing an ion implantation process. Since the first doping region 210 is deep, a channel effect ion implantation process may be used, and the temperature of the channel effect ion implantation process is 500° C.-600° C., the doping ions are, for example, aluminum ions, and the doping concentration is, for example, 3×10 17 / cm 3 Up to 1×10 21 / cm 3 ; After the channel effect ion implantation process is completed, the first oxide layer is removed.

[0052] The first doped regions 210 are formed to be distributed along the extension direction (y direction) of the gate structure and perpendicular to the extension direction (x direction) of the gate structure. Compared with a continuous structure, this discrete structure can prevent the diffusion of BPD defects and improve conductivity.

[0053] In step S2 , a first JFET region 220 is formed on a portion of the surface of the first doped region 210 . Figure 4 and Figure 5 is Figure 3 The schematic diagram of the structure obtained by adding the first JFET region 220 on the basis of Figure 6 yes Figure 4 The cross-sectional view at BB shows the first JFET region 220 and the epitaxial layer 100 on the first doped region 210 .

[0054] refer to Figure 4 In some embodiments, the first JFET region 220 crosses the first doped region 210 in the extension direction (y direction) of the gate structure, that is, part of the first JFET region 220 is located on the surface of the first doped region 210, and the rest of the first JFET region 220 is located on the surface of the epitaxial layer 100 between adjacent first doped regions 210. Figure 5In other embodiments, the first JFET region 220 does not cross the first doping region 210 in the extension direction (y direction) of the gate structure, that is, the first JFET region 220 is separately located on the surface of the first doping region 210, and the first JFET region 220 and the first doping region 210 have the same width in the extension direction (y direction) of the gate structure. The sidewalls of one side of the first JFET region 220 and the first doping region 210 may be coplanar or non-coplanar.

[0055] The formation process of the first JFET region 220 may include: forming a patterned second oxide layer (not shown) on the surface of the epitaxial layer 100, wherein the second oxide layer exposes the area where ion implantation is required, and the thickness of the second oxide layer may be 1.2 μm-1.6 μm; performing an ion implantation process, wherein the ion implantation temperature may be controlled at 20° C.-40° C. or 500° C.-600° C., and the implanted ion type may be the same as the doping ion type of the epitaxial layer 100, for example, N-type ions may be implanted, and the doping concentration may be 3×10 16 / cm 3 Up to 2×10 17 / cm 3 ; removing the second oxide layer.

[0056] Figure 7 is Figure 4 The schematic diagram of the structure obtained by adding the second JFET region 230 on the basis of Figure 8 yes Figure 7 The cross-sectional view at CC in FIG. 2 shows the epitaxial layer 100 on the first doping region 210, the first JFET region 220 and the second JFET region 230. The process of forming the second JFET region 230 on the surface of the epitaxial layer 100 between the adjacent first doping regions 210 may include: forming a patterned third oxide layer (not shown) on the surface of the epitaxial layer 100, wherein the third oxide layer exposes an ion implantation region, and the third oxide layer may have the same thickness as the second oxide layer; performing ion implantation, wherein the ion implantation temperature may be 20°C-40°C or 500°C-600°C, and the implanted ion type may be the same as the doping ion type of the epitaxial layer 100, for example, N-type ions may be implanted, and the doping concentration may be lower than the doping concentration of the first JFET region 220, for example, 3×10 16 / cm 3 Up to 2×10 17 / cm 3 ; removing the third oxide layer.

[0057] The second JFET region 230 is formed in the same extension direction as the gate structure and is coplanar with the surface of the first JFET region 220 .

[0058] refer to Fig. 9 and Fig.10 ,in Fig.10 for Fig. 9 The epitaxial layer 100 higher than the second JFET region 230 forms a well region 240. The process of forming the well region 240 may include: forming a fourth oxide layer (not shown) on the surface of the epitaxial layer 100, the thickness of the fourth oxide layer is 1.6 μm-2.0 μm; performing ion implantation on the surface of the fourth oxide layer, the temperature during ion implantation may be 500°C-600°C, the type of implanted ions is the same as the doping type of the first doping region 210, for example, the type of implanted ions is P type, the doping ions are, for example, aluminum ions, and the doping concentration may be 3×10 17 / cm 3 Up to 1×10 21 / cm 3 ; removing the fourth oxide layer.

[0059] refer to Fig.11 and Fig.12 ,in Fig.12 for Fig.11 A cross-sectional view at EE in FIG. A source region 250 is formed extending from the surface of the well region 240 on the first JFET region 220 and the second JFET region 230 to the well region 240. The process of forming the source region 250 includes: forming a patterned fifth oxide layer (not shown) on the surface of the well region 240, wherein the fifth oxide layer exposes the ion implantation area, and the thickness of the fifth oxide layer may be, for example, 1 μm; performing ion implantation, wherein the temperature during ion implantation may be 500° C.-600° C., and the type of implanted ions is the same as the type of doped ions of the epitaxial layer 100, the first JFET region 220, and the second JFET region 230, and the concentration of the ion implantation is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 ; removing the fifth oxide layer.

[0060] refer to Fig.13 and Fig.14 ,in Fig.14 for Fig.13A cross-sectional view at FF in the middle. A second doping region 260 is formed extending from the surface of the well region 240 between the adjacent source regions 250 to the surface of the first doping region 210. The formation process of the second doping region 260 may include: forming a sixth oxide layer (not shown) on the surface of the source region 250, the thickness of the sixth oxide layer may be 1.2μm-1.6μm; using the sixth oxide layer as a mask, ion implantation is performed, the ion implantation temperature may be 500℃-600℃, the type of ion implantation may be the same as the doping type of the first doping region 210 and the well region 260, the doping ions may be, for example, aluminum ions, and the doping concentration may be 3×10 17 / cm 3 Up to 1×10 21 / cm 3 ; removing the sixth oxide layer.

[0061] Before forming the gate structure, the following process can also be performed: forming a carbon layer on the surface of the source region 250 and the second doping region 260 by processes such as carbonizing photoresist or depositing carbon powder; annealing is performed at 1600°C-1800°C in an argon atmosphere to activate all previously doped ions. Since the surfaces of the source region 250 and the second doping region 260 will react with trace oxygen or nitrogen oxides in the atmosphere during the annealing process, the carbon layer can play an isolation and protection role; and then the carbon layer is removed.

[0062] refer to Fig.15 and Fig.16 ,in Fig.16 for Fig.15 The source region 250, the well region 240, the first JFET region 220 and the second JFET region 230 are partially etched, and the etching stops at the surface of the epitaxial layer 100 and the first doping region 210 to form a trench 301. In some embodiments, the inner wall of the trench 301 may be repaired, for example, a dielectric layer may be deposited on the inner wall of the trench 301 for repair.

[0063] refer to Fig.17, a gate oxide layer 310 is formed on the sidewall and bottom of the trench 301, and the process of forming the gate oxide layer 310 may be a deposition process such as high temperature oxidation, chemical vapor deposition, physical vapor deposition, etc. The material of the gate oxide layer 310 may include at least one of silicon oxide, silicon nitride and oxynitride, such as a combination of SiO2, Si3N4, etc. After forming the gate oxide layer 310, a high temperature annealing may be performed at 1200°C-1350°C in a gas such as NO or N2O. Then, a gate layer 310 filling the trench 301 is formed on the surface of the gate oxide layer 310. The process of forming the gate layer 320 may include: forming a gate material layer in the trench 301 and on the surface of the source region 250 and the second doping region 260 by a deposition process; grinding the gate material layer by a process such as chemical mechanical grinding or physical mechanical grinding, so that the gate material layer is coplanar with the surface of the source region 250 and the second doping region 260 to form the gate layer 320.

[0064] refer to Fig. 20 , the method for forming the semiconductor structure may further include: forming an interlayer dielectric layer 330 on the surface of the gate structure and part of the source region 250. The process of forming the interlayer dielectric layer 330 may include: depositing an interlayer dielectric material on the surface of the gate structure, the source region 250 and the second doping region 260 by a deposition process such as chemical vapor deposition, physical vapor deposition or atomic layer deposition; etching the interlayer dielectric material to expose the surface of the second doping region 260 and part of the source region 250 adjacent to the second doping region 260, so as to form the interlayer dielectric layer 330. The material of the interlayer dielectric layer 330 may include phosphosilicate glass material (PSG), plasma enhanced tetraethyl orthosilicate material (PE-TEOS) or borophosphosilicate glass material (BPSG), etc. The thickness of the interlayer dielectric layer 330 may be 0.5μm-1.5μm.

[0065] In some embodiments, the method for forming the semiconductor structure may further include: forming a source contact layer 410 on the surface of the source region 250 and the second doping region 260 between the interlayer dielectric layer 330. The source contact layer 410 may form an ohmic contact. The method for forming the source contact region 410 may include: forming a source contact material layer on the surface of the interlayer dielectric layer 330, the source region 250 and the second doping region 260 by a deposition process such as physical vapor deposition, chemical vapor deposition or atomic layer deposition; then performing a first annealing treatment at 700°C-850°C; etching and removing the source contact material layer on the surface of the interlayer dielectric layer 330, leaving only the source contact material layer on the surface of the source region 250 and the second doping region 260; performing a second annealing treatment at 1000°C-1100°C to form the source contact layer 410, and the surface of the source contact layer 410 is coplanar with the top surface of the interlayer dielectric layer 330. The material of the source contact layer 410 may include nickel. The source contact layer 410 may have a thickness of 500 angstroms to 1000 angstroms.

[0066] In some embodiments, after forming the source contact layer 410 , a contact hole may be further formed.

[0067] Continue to refer Fig. 20 The method for forming the semiconductor structure may further include: forming a source metal 420 on the surface of the interlayer dielectric layer 330 and the source contact layer 410. The source metal 420 includes aluminum, for example. The thickness of the source metal 420 may be 2.5 μm-4.5 μm.

[0068] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0069] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0070] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0071] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0072] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising an epitaxial layer; A first doping region is separately located in the epitaxial layer, and a doping type of the first doping region is different from a doping type of the epitaxial layer; A first JFET region, located on a portion of the surface of the first doped region; A second JFET region is located in a portion of the epitaxial layer between adjacent first doped regions, and surfaces of the first JFET region and the second JFET region are coplanar; a well region located on the first JFET region and the second JFET region; A source region extending from the surface of the well region into the well region; A second doping region is located on the surface of the first doping region between adjacent source regions, and the second doping region is coplanar with the surface of the source region; A gate structure is located in the source region and the well region and extends between the first JFET region and the second JFET region, and the entire or a portion of the bottom of the gate structure is adjacent to the first doped region.

2. The semiconductor structure according to claim 1, characterized in that: The first doped region is distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region crosses or does not cross the first doped region in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

3. The semiconductor structure according to claim 1, characterized in that: The depth of the source region is 0.2μm-0.4μm; the depth of the second doping region is 1.2μm-1.5μm; the depth of the well region is 0.8μm-1.0μm; the thickness of the first JFET region and the second JFET region is 0.3μm-0.4μm; the thickness of the first doping region is 0.4μm-0.8μm.

4. The semiconductor structure according to claim 1, characterized in that: The gate structure includes a gate oxide layer and a gate layer located on the surface of the gate oxide layer.

5. The semiconductor structure according to claim 4, characterized in that: The depth of the gate layer is 1.1 μm-1.5 μm.

6. The semiconductor structure according to claim 1, characterized in that The epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the first doping region, the second doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

7. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the first doping region is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 , the doping concentration of the first JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 , the doping concentration of the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

8. The semiconductor structure according to claim 1, characterized in that: Also includes: An interlayer dielectric layer, located on the surface of the gate structure and part of the source region; A source contact layer, located on the surface of the source region and the second doping region between the interlayer dielectric layers, and the surface of the source contact layer and the interlayer dielectric layer are coplanar; The source metal is located on the surface of the interlayer dielectric layer and the source contact layer.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an epitaxial layer, wherein a discrete first doping region is formed in the epitaxial layer, and a doping type of the first doping region is different from a doping type of the epitaxial layer; forming a first JFET region on a portion of the surface of the first doped region; forming a second JFET region in the epitaxial layer between adjacent first doped regions, wherein surfaces of the first JFET region and the second JFET region are coplanar; Forming a well region in the epitaxial layer higher than the first JFET region and the second JFET region; A source region formed extending from a surface of a well region on the first JFET region and the second JFET region to the well region; A second doped region is formed extending from the surface of the well region between the adjacent source regions to the surface of the first doped region; Part of the source region, the well region, the first JFET region and the second JFET region are etched, and a gate structure is formed at a corresponding position, and the entire or a part of the bottom of the gate structure is adjacent to the first doped region.

10. The method for forming a semiconductor structure according to claim 9, characterized in that: The first doped region is distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region crosses or does not cross the first doped region in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

11. The method for forming a semiconductor structure according to claim 9, wherein: The first doped region, the first JFET region, the second JFET region, the well region, the source region and the second doped region are formed by an ion implantation process; wherein the temperature of the ion implantation process for forming the first doped region, the well region, the source region and the second doped region is 500°C-600°C, and the temperature of the ion implantation process for forming the first JFET region and the second JFET region is 20°C-40°C or 500°C-600°C.

12. The method for forming a semiconductor structure according to claim 9, wherein: The epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the first doping region, the second doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

13. The method for forming a semiconductor structure according to claim 12, wherein: The doping concentration of the first doping region is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 , the doping concentration of the first JFET region and the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

14. The method for forming a semiconductor structure according to claim 9, wherein: Before forming the gate structure, the method further includes: forming a carbon layer on surfaces of the source region and the second doping region; Under the protection of the carbon layer, annealing is performed to activate doping ions; The carbon layer is removed.

15. The method for forming a semiconductor structure according to claim 9, wherein: The method of forming the gate structure includes: Etching a portion of the source region, the well region, the first JFET region, and the second JFET region, stopping at the surfaces of the epitaxial layer and the first doped region, to form a trench; forming a gate oxide layer on the sidewalls and bottom of the trench; A gate layer filling the trench is formed on the surface of the gate oxide layer.

16. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: forming an interlayer dielectric layer on the surface of the gate structure and a portion of the source region; forming a source contact layer on the surface of the source region between the interlayer dielectric layers and the second doped region, wherein the surface of the source contact layer and the surface of the interlayer dielectric layer are coplanar; A source metal is formed on surfaces of the interlayer dielectric layer and the source contact layer.

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