Narrow bandgap semiconductor transistor and preparation method thereof

Abstract

The present invention provides a narrow-bandgap semiconductor transistor with a high-κ or heterogeneous buried oxide layer and a method for fabricating the same. The transistor comprises a substrate, a high-κ or heterogeneous buried oxide layer thereon, a narrow-bandgap semiconductor channel layer thereon, and a gate structure. The gate structure comprises two sidewalls and a gate located therein, with a source and a drain located on either side of the gate structure. The transistor of the present invention optimizes the energy band distribution of semiconductor transistors, particularly narrow-bandgap semiconductor transistors. By regulating the energy band at the drain end, the off-state current and static energy consumption are suppressed. Furthermore, the transistor is compatible with industrial semiconductor processes and can be fabricated using large-scale integrated circuits.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, in particular to a carbon nanotube field effect transistor with a buried oxide layer and a manufacturing method thereof. Background Art

[0002] As semiconductor integrated circuit technology continues to scale down to nodes below 3nm, silicon-based integrated circuits are likely to reach the limits of silicon materials and quantum mechanics. The continued development of the electronics industry necessitates the search for new, more promising and advantageous materials to extend silicon and break the limits of Moore's Law. Carbon nanotubes (CNTs), with their high carrier mobility, long mean free path, and nanometer-scale diameters, can be used to construct nanoscale field-effect transistors that are faster, more power-efficient, and smaller in size. Therefore, CNT electronics are considered one of the future information technologies with the potential to extend silicon-based CMOS devices and continue to support Moore's Law.

[0003] Low-dimensional materials like carbon nanotubes, graphene, and black phosphorus generally have smaller band gaps than silicon. The typical band gap of carbon nanotubes is approximately 0.8 eV, compared to about 1.12 eV for silicon. Due to the narrow band gap, the drain barrier width is significantly compressed in the off-state, resulting in larger tunneling currents and increased static energy consumption. The off-state tunneling effect in narrow-bandgap channel transistors is more pronounced than in silicon-based transistors. Furthermore, currently, there is a lack of stable doping methods for high-performance low-dimensional channel materials. The mainstream approach uses metal as source-drain contacts, resulting in excessively strong drain-side electric fields and thin Schottky barriers near the drain end of the channel, causing severe reverse tunneling. Furthermore, the transistor fabrication process lacks ion implantation and doping, making it impossible to achieve the lightly doped source / drain (LDD) method used in silicon-based transistors to finely control the spatial distribution of drain-side doping concentrations, thereby mitigating negative effects such as short-channel effects, junction leakage, and parasitic currents.

[0004] Existing solutions to this problem involve the use of an asymmetric gate stack or feedback gate structure. Asymmetric gate structures are generally based on bottom gates and are complex to manufacture, hindering device miniaturization and large-scale fabrication. The feedback gate connects a feedback gate near the drain end of the channel, short-circuiting the feedback gate to the metal electrode at the drain end. This clamps the channel barrier at the drain end to the drain potential, maintaining a large barrier width. This large barrier width significantly suppresses reverse tunneling current, reduces static power consumption, and improves the on / off ratio. In feedback gate transistors, the introduction of a secondary gate also requires additional device area, limiting device miniaturization.

[0005] Therefore, there is a need to design a device structure that can optimize the energy band distribution of semiconductor transistors, suppress off-state current and static energy consumption, be compatible with industrial semiconductor processes, and achieve large-scale integrated production. Summary of the Invention

[0006] The present invention addresses the problems existing in the above prior art and proposes a semiconductor transistor with a buried oxide layer and a method for preparing the same in order to suppress the bipolarity of a narrow-bandgap channel Schottky barrier transistor, thereby suppressing the off-state current and static energy consumption. The technical solutions of the present invention are as follows:

[0007] A long channel narrow bandgap semiconductor transistor, wherein the long channel generally has a channel length greater than 100nm, comprises a substrate having a high-κ buried oxide layer on the substrate, a narrow bandgap semiconductor channel layer on the high-κ buried oxide layer, a gate structure on the narrow bandgap semiconductor channel layer, the gate structure comprising two side walls and a gate dielectric layer and a gate located between the side walls, and a source and a drain on both sides of the gate structure.

[0008] Preferably, the high-κ buried oxide layer is selected from hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

[0009] Preferably, the typical band gap of the narrow-bandgap semiconductor channel layer is less than 1 eV, and is preferably selected from carbon nanotubes, graphene, germanium, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or in different stacks.

[0010] Preferably, the width of the narrow-bandgap semiconductor channel layer is the same as the width of the gate structure, and the source and drain are in contact with side surfaces of the narrow-bandgap semiconductor channel layer.

[0011] Preferably, the width of the narrow-bandgap semiconductor channel layer exceeds the width of the gate structure, and the source and drain cover the exceeding portion of the narrow-bandgap semiconductor channel layer to form source-drain contacts.

[0012] Preferably, the substrate is selected from hard insulating materials such as silicon oxide, quartz, glass, aluminum oxide, or high-temperature resistant flexible insulating materials such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate), polyimide, and is preferably a silicon substrate.

[0013] Preferably, the source and drain are selected from any one of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), and erbium (Er), or different alloys or stacked combinations of the above materials.

[0014] Another aspect of the present invention provides a method for preparing the long-channel narrow-bandgap semiconductor transistor, comprising the following steps:

[0015] S1: providing a substrate, growing a high-κ buried oxide layer thereon, and planarizing the layer;

[0016] S2: forming a narrow bandgap semiconductor channel layer on the high-κ buried oxide layer, and forming a gate structure including a gate dielectric layer and a gate electrode thereon by using a photolithography process and a deposition process;

[0017] S3: removing the narrow bandgap semiconductor channel layer on both sides of the gate structure using the gate structure as a pattern, and then depositing a source electrode and a drain electrode on both sides of the gate structure.

[0018] Preferably, in step S3 , the narrow bandgap semiconductor channel layer on both sides of the gate structure is not removed, and a source electrode and a drain electrode covering the narrow bandgap semiconductor channel layer are directly formed on both sides of the gate structure.

[0019] Preferably, the high-κ buried oxide layer is hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

[0020] Preferably, the typical band gap of the narrow-bandgap semiconductor channel layer is less than 1 eV, and is preferably selected from carbon nanotubes, graphene, germanium, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or in different stacks.

[0021] Another aspect of the present invention further provides a short channel narrow bandgap semiconductor transistor, wherein the semiconductor channel length of the short channel is generally less than 100nm, and the transistor comprises a substrate, a heterogeneous buried oxide layer on the substrate, a narrow bandgap semiconductor channel layer on the heterogeneous buried oxide layer, a gate structure on the narrow bandgap semiconductor channel layer, the gate structure comprising two side walls and a gate dielectric and a gate located between the side walls, and a source and a drain on both sides of the gate structure, wherein the heterogeneous buried oxide layer comprises a low-κ buried oxide layer with a width of L1 and a high-κ buried oxide layer with a width of L2, wherein L1>L2, and the high-κ buried oxide layer is located on one side of the drain and has an overlapping width L with the narrow bandgap semiconductor channel layer. ov .

[0022] Preferably, the low-κ buried oxide layer is silicon dioxide (SiO2), and the high-κ buried oxide layer (102) is hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

[0023] Preferably, the typical band gap of the narrow-bandgap semiconductor channel layer is less than 1 eV, and can be selected from carbon nanotubes, graphene, germanium, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or in different stacks.

[0024] Preferably, the width of the narrow bandgap semiconductor channel layer is the same as the width of the gate structure, and the source and drain are in contact with the side surfaces of the low-dimensional semiconductor channel layer.

[0025] Preferably, the width of the narrow-bandgap semiconductor channel layer exceeds the width of the gate structure, and the source and drain cover the exceeding portion of the narrow-bandgap semiconductor channel layer to form contact.

[0026] Preferably, the substrate is selected from hard insulating materials such as silicon oxide, quartz, glass, aluminum oxide, or selected from high-temperature resistant flexible insulating materials such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate), polyimide, and is preferably a silicon substrate.

[0027] Preferably, the source and drain are selected from any one of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y), and erbium (Er), or different alloys or stacked combinations of the above materials.

[0028] Another aspect of the present invention further provides a method for preparing the above-mentioned short-channel narrow-bandgap semiconductor transistor, which comprises the following steps:

[0029] S1: providing a substrate, growing a low-κ buried oxide layer thereon, and simultaneously forming a high-κ buried oxide layer pattern by a photolithography process;

[0030] S2: etching the low-κ buried oxide layer corresponding to the high-κ buried oxide layer pattern to form a low-κ buried oxide layer with a width of L1, further depositing a high-κ buried oxide layer with a width of L2 in the groove formed after etching, and then performing chemical mechanical polishing to form a heterogeneous buried oxide layer;

[0031] S3: forming a narrow bandgap semiconductor channel layer on the heterogeneous buried oxide layer, and forming a gate structure including a gate dielectric layer and a gate electrode thereon by using a photolithography process and a deposition process;

[0032] S4: removing the narrow bandgap semiconductor channel layer on both sides of the gate structure using the gate structure as a pattern, and then depositing a source electrode and a drain electrode on both sides of the gate structure.

[0033] Preferably, the high-κ buried oxide layer is hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

[0034] Preferably, the typical band gap of the narrow-bandgap semiconductor channel layer is less than 1 eV, and is preferably selected from carbon nanotubes, graphene, germanium, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or in different stacks.

[0035] Preferably, in step S4 , the narrow bandgap semiconductor channel layer on both sides of the gate structure may not be removed, and a source electrode and a drain electrode covering the narrow bandgap semiconductor channel layer may be directly formed on both sides of the gate structure.

[0036] The present invention adopts a high-κ buried oxide layer design. For long-channel transistors, the high-κ buried oxide layer can achieve strong electrostatic coupling between the drain electrode and the channel drain end energy band, so that the drain end potential clamps the Schottky barrier thickness. For short-channel transistors, a heterogeneous buried oxide layer is used to reduce the short channel effect and enhance the electrostatic coupling between the drain electrode and the channel drain end energy band, thereby solving the static power consumption problem caused by the off-state tunneling current. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the technical solutions of the present invention with reference to the accompanying drawings, in which:

[0038] FIG1 is a schematic diagram of the structure of a long-channel narrow-bandgap semiconductor transistor according to the present invention;

[0039] FIG2 is a flow chart of the preparation of a long-channel narrow-bandgap semiconductor transistor according to the present invention;

[0040] FIG3 is a transfer characteristic curve of a long-channel narrow-bandgap semiconductor transistor according to the present invention;

[0041] FIG4 is an off-state energy band diagram of the present long-channel narrow-bandgap semiconductor transistor;

[0042] FIG5 is a schematic diagram of the structure of a short-channel narrow-bandgap semiconductor transistor according to the present invention;

[0043] FIG6 compares various performance indices of 50 nm gate length transistors based on different buried oxide layers according to the present invention;

[0044] Figure 7 A flow chart for preparing a short-channel, narrow-bandgap semiconductor transistor according to the present invention; DETAILED DESCRIPTION

[0045] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the various drawings, identical elements are denoted by identical reference numerals, and parts in the drawings are not drawn to scale. Furthermore, certain well-known components may not be shown. For the sake of clarity, a semiconductor structure obtained after several steps may be depicted in a single figure.

[0046] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0047] To describe a situation where an element is directly located on another layer or region, this document uses the expression "A is directly on B" or "A is on and adjacent to B." In this application, "A is directly located in B" means that A is located in B and is directly adjacent to B, rather than that A is located in a doped region formed in B.

[0048] The following Figure 1-Figure 7 The present invention is described in detail.

[0049] The long-channel, narrow-bandgap semiconductor transistor of this embodiment is shown in FIG1 . The semiconductor transistor comprises a silicon substrate 101, on which a high-κ buried oxide layer 102 of hafnium dioxide (HfO2) is formed. In other embodiments, the high-κ buried oxide layer 102 may also be made of materials such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), or titanium oxide (TiO2). A carbon nanotube channel layer 103 is formed on the high-κ buried oxide layer 102 of hafnium dioxide (HfO2). In other embodiments, the channel layer may be made of graphene, germanium, a two-dimensional material such as molybdenum disulfide, tungsten disulfide, or black phosphorus, or various combinations of these materials on the same plane or in different layers. A gate structure is provided on the carbon nanotube channel layer 103, and the gate structure includes two sidewalls 104 and 104', a gate dielectric layer 105 between the sidewalls, and a gate 106 located thereon, with a source 107 and a drain 108 on either side of the gate structure. FIG2 is a transfer characteristic curve of this embodiment, from which it can be seen that the off-state current of the transistor device using a high-κ buried oxide layer is reduced by an order of magnitude compared to the traditional low-κ buried oxide layer. FIG3 is a simulated off-state energy band diagram of the device of this embodiment, from which it can be seen that the transistor device using a high-κ buried oxide layer can improve gate efficiency and enhance the electrostatic coupling between the drain electrode and the drain end energy band, thereby clamping the drain end Schottky barrier thickness to a certain extent.

[0050] In this embodiment, the width of the carbon nanotube channel layer 103 is the same as the width of the gate structure, and the source electrode 107 and the drain electrode 108 form contact with the side surfaces of the carbon nanotube channel layer 103. In another embodiment, the width of the carbon nanotube channel layer 103 exceeds the width of the gate structure, and the source electrode 107 and the drain electrode 108 respectively cover the excess portion of the carbon nanotube channel layer 103 to form source-drain contacts.

[0051] In this embodiment, the source 107 and the drain 108 are respectively made of metal palladium (Pd). In other embodiments, the source 107 and the drain 108 are respectively selected from any one of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), scandium (Sc), platinum (Pt), scandium (Sc), yttrium (Y), and erbium (Er), or different alloys or stacked combinations of the above materials.

[0052] FIG4 is a flow chart of the method for preparing the long-channel narrow-bandgap semiconductor transistor, which mainly includes the following steps:

[0053] S1: A silicon substrate 101 is provided, and a hafnium dioxide buried oxide layer 102 is grown thereon and planarized. In other embodiments, the buried oxide layer may also be made of aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), or titanium oxide (TiO2).

[0054] S2: A carbon nanotube channel layer 103 is formed on the hafnium dioxide buried oxide layer 102, and a gate structure including a gate dielectric layer 105 and a gate electrode 106 is formed thereon using conventional photolithography and deposition processes in the art; in other embodiments, the semiconductor channel layer can use a semiconductor material with a band gap less than 1eV, such as graphene, germanium, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or in different stacks.

[0055] S3: Using the gate structure as a pattern, the carbon nanotube channel layer on both sides of the gate structure is removed, and then metal Pd is deposited on both sides of the gate structure to form a source 107 and a drain 108.

[0056] In other embodiments, the carbon nanotube channel layer on both sides of the gate structure may not be removed in step S3 , and the source electrode 107 and the drain electrode 108 covering the carbon nanotube channel layer may be directly formed on both sides of the gate structure.

[0057] The short-channel, narrow-bandgap semiconductor transistor of this embodiment is shown in FIG5 . The semiconductor transistor comprises a silicon substrate 201 on which a heterogeneous buried oxide layer is formed. The heterogeneous buried oxide layer comprises a low-κ silicon dioxide buried oxide layer 202 having a width L1 and a high-κ hafnium dioxide buried oxide layer 202′ having a width L2, wherein L1>L2. A carbon nanotube channel layer 203 is formed on the heterogeneous buried oxide layer, and a gate structure is formed thereon. The gate structure comprises two sidewalls 204 and 204′, a gate dielectric layer 205 between the sidewalls, and a gate 206 located thereon. A metal Pd source 207 and a drain 208 are formed on both sides of the gate structure. The high-κ hafnium dioxide buried oxide layer 202′ is located on one side of the drain 208 and overlaps with the carbon nanotube channel layer 203 by a width L. ov By adjusting the overlap width, the optimal current on / off ratio can be achieved to ensure that the static power consumption design requirements of the transistor are met. Figure 6 shows a comparison of various simulation performance indicators of 50 nm gate length transistors based on different buried oxide layers in this embodiment, including source-induced barrier lowering (DIBL), subthreshold swing (SS), and on / off ratio. Compared with SiO2 buried oxide layer devices, HfO2 buried oxide layer devices have poor off-state performance and significant short channel effect, namely DIBL = 222 mV / V, SS = 177 mV / dec, on / off ratio = 8.9×10 3 For the heterogeneous buried oxide device, DIBL = 25 mV / V and SS = 80 mV / dec, while the on / off ratio is improved by an order of magnitude compared to the SiO2 buried oxide device. These results demonstrate the advantages and application potential of the heterogeneous buried oxide structure in short-channel devices.

[0058] In other embodiments, the high-κ buried oxide layer 202' may also be selected from materials such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), or titanium oxide (TiO2). The semiconductor channel layer typically has a band gap of less than 1 eV and may be selected from carbon nanotubes, graphene, germanium, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, and black phosphorus, or various combinations of these materials on the same plane or in different layers.

[0059] In this embodiment, the width of the carbon nanotube channel layer 203 is the same as the width of the gate structure, and the source electrode 207 and the drain electrode 208 contact the side of the carbon nanotube channel layer 203. In another embodiment, the width of the carbon nanotube channel layer 203 exceeds the width of the gate structure, and the source electrode 207 and the drain electrode 208 cover the excess portion of the carbon nanotube channel layer 203 to form a contact.

[0060] In another embodiment, the source 207 and the drain 208 may also be selected from any one of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), scandium (Sc), platinum (Pt), scandium (Sc), yttrium (Y), erbium (Er), or different alloys or stacked combinations of the above materials.

[0061] FIG6 is a method for preparing a short-channel narrow-bandgap semiconductor transistor, which includes the following steps:

[0062] S1: providing a substrate 201, growing a low-κ silicon dioxide buried oxide layer 202 thereon, and simultaneously forming a high-κ buried oxide layer pattern by conventional photolithography processes in the art;

[0063] S2: Etching the low-κ silicon dioxide buried oxide layer corresponding to the high-κ buried oxide layer pattern to form a low-κ silicon dioxide buried oxide layer 202 with a width of L1, and further depositing a high-κ hafnium dioxide buried oxide layer 202' with a width of L2 in the groove formed after etching, and then performing chemical mechanical polishing to form a heterogeneous buried oxide layer; in other embodiments, the high-κ buried oxide layer can also be made of aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

[0064] S3: forming a carbon nanotube channel layer 203 on the heterogeneous buried oxide layer, and forming a gate structure including a gate dielectric layer 205 and a gate electrode 206 thereon by using conventional photolithography and deposition processes in the art;

[0065] S4: The carbon nanotube channel layer on both sides of the gate structure is removed using the gate structure as a pattern, and then a source electrode 207 and a drain electrode 208 are deposited on both sides of the gate structure. In another embodiment, the carbon nanotube channel layer on both sides of the gate structure may not be removed, and the source electrode 207 and the drain electrode 208 covering the carbon nanotube channel layer may be directly formed on both sides of the gate structure.

[0066] In other embodiments, other narrow bandgap semiconductors with a typical bandgap less than 1 eV may be used, such as germanium, graphene, two-dimensional materials such as molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of these materials on the same plane or in different stacks.

[0067] The above-mentioned semiconductor transistor structure adjusts the thickness of the low-κ sidewall between the transistor gate electrode and the source and drain electrodes, extends the overlapping width between the transistor semiconductor channel and the high-κ gate dielectric, increases the channel area regulated by the drain electrode, and further increases the width of the drain barrier, thereby solving the static power consumption problem caused by the off-state tunneling current.

[0068] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made based on the present invention. Therefore, such modifications and improvements, which do not depart from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. A short-channel narrow-bandgap semiconductor transistor comprising a substrate, characterized in that: A heterogeneous buried oxide layer is provided on the substrate, wherein the heterogeneous buried oxide layer comprises a low-κ buried oxide layer with a width L1 and a high-κ buried oxide layer with a width L2, wherein L1>L2; A narrow bandgap semiconductor channel layer is provided on the low-κ buried oxide layer and the high-κ buried oxide layer, and a gate structure is provided on the narrow bandgap semiconductor channel layer, wherein the gate structure includes two sidewalls and a gate dielectric layer and a gate located between the sidewalls, and a source and a drain are provided on both sides of the gate structure, and the drain is located on one side of the high-κ buried oxide layer; The width of the narrow bandgap semiconductor channel layer is greater than or equal to the width of the gate structure, and the source and drain electrodes contact the side surfaces of the narrow bandgap semiconductor channel layer or cover the excess portion of the narrow bandgap semiconductor channel layer to form source-drain contacts.

2. The short-channel narrow-bandgap semiconductor transistor according to claim 1, wherein: The high-κ buried oxide layer is selected from hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

3. The short-channel narrow-bandgap semiconductor transistor according to claim 1, wherein: The band gap of the narrow band gap semiconductor channel layer is less than 1 eV.

4. The short-channel narrow-bandgap semiconductor transistor according to claim 3, wherein: The narrow bandgap semiconductor channel layer is selected from carbon nanotubes, graphene, germanium, molybdenum disulfide, tungsten disulfide, black phosphorus, or various combinations of the above materials on the same plane or in different stacks.

5. The short-channel narrow-bandgap semiconductor transistor according to claim 1, wherein: The substrate is a hard insulating material or a high-temperature resistant flexible insulating material.

6. The short-channel narrow-bandgap semiconductor transistor according to claim 5, wherein: The hard insulating material is silicon oxide, quartz, glass or aluminum oxide, and the high-temperature resistant flexible insulating material is PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or polyimide high-temperature resistant flexible insulating material.

7. The short-channel narrow-bandgap semiconductor transistor according to claim 1, wherein: The source and drain are selected from any one of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), molybdenum (Mo), tungsten (W), palladium (Pd), platinum (Pt), scandium (Sc), yttrium (Y) or erbium (Er), or different types of alloys or stacked combinations of the above materials.

8. A method for preparing a short-channel narrow-bandgap semiconductor transistor according to claims 1 to 7, comprising the following steps: S1: providing a substrate, growing a low-κ buried oxide layer thereon, and then forming a high-κ buried oxide layer pattern; S2: etching the low-κ buried oxide layer corresponding to the high-κ buried oxide layer pattern to form a low-κ buried oxide layer with a width of L1, further depositing a high-κ buried oxide layer with a width of L2 in the groove formed after etching, and then performing chemical mechanical polishing to form a heterogeneous buried oxide layer; S3: forming a narrow bandgap semiconductor channel layer on the heterogeneous buried oxide layer, and forming a gate structure including two sidewalls, a gate dielectric layer and a gate thereon by using a photolithography process and a deposition process; S4: removing the narrow bandgap semiconductor channel layer on both sides of the gate structure using the gate structure as a pattern, and then depositing a source electrode and a drain electrode on both sides of the gate structure.

9. The short-channel narrow-bandgap semiconductor transistor according to claim 8, wherein: In step S3 , the narrow bandgap semiconductor channel layer on both sides of the gate structure is not removed, and a source electrode and a drain electrode covering the narrow bandgap semiconductor channel layer are directly formed on both sides of the gate structure.

10. The short-channel narrow-bandgap semiconductor transistor according to claim 8, wherein: The high-κ buried oxide layer is hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3) or titanium oxide (TiO2).

Images