Data transmission method and device, circuit board, storage medium, and electronic device

Abstract

The embodiments of the present invention provide a data transmission method and device, a circuit board, a storage medium, and an electronic device, which utilize invalid bits in a second transmission channel for transmitting second data to transmit first data, without the need to deploy multiple additional interconnection lines to transmit the first data. Therefore, the problem of a large number of interconnection lines on a single board is solved and the wiring of the single board is simplified.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular, to a data transmission method and device, a circuit board, a storage medium, and an electronic device. Background Art

[0002] In the related art, artificial intelligence (AI) chips and analog-to-digital / digital-to-analog conversion (AD / DA) devices (also called analog-to-digital / digital-to-analog conversion devices) can exchange data through interface protocols, such as the JESD204 protocol. JESD204 is an industry-wide interface protocol for data exchange between AI chips (such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs)) and AD / DA devices. Figure 1 This is a schematic diagram of the interaction between the chip and the AD / DA device in the related technology, such as Figure 1 As shown, in actual use, in addition to data transmission, the communication between the AI ​​chip and the analog-to-digital / digital-to-analog conversion device also requires a large number of other signal interactions, such as control signal interactions. Currently, these other signals (such as control signals) are interconnected through the input and output (IO) pins on the chip.

[0003] Currently, the number of devices integrated on PCBs is increasing, and the number of integrated channels in a single device is also increasing, resulting in the following design problems:

[0004] From the perspective of chip development: more single-ended or differential pins are needed to transmit IO pin signals, resulting in a large number of interconnect lines;

[0005] From the perspective of single board design: the routing is more dense, and more signal layers are needed on the PCB to support the design, which not only increases the pressure on wiring layout, but also leads to an increase in overall cost.

[0006] Therefore, for the current design, how to reduce the number of interconnection lines on a single board has become an important issue, and there is no technical solution to solve the problem of a large number of interconnection lines on a single board in the related art. Summary of the invention

[0007] The embodiments of the present invention provide a data transmission method and device, a circuit board, a storage medium, and an electronic device, so as to at least solve the problem of a large number of interconnection lines on a single board in the related art.

[0008] According to one embodiment of the present invention, there is provided a data transmission method, which is applied between a chip and an analog-to-digital to digital-to-analog conversion device, and includes: transmitting first data through a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data includes custom data, and the second data includes business data.

[0009] According to one embodiment of the present invention, a circuit board is also provided, comprising: a chip and an analog-to-digital / digital-to-analog converter; wherein first data is transmitted between the chip and the analog-to-digital / digital-to-analog converter via a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, and the second transmission channel is a transmission channel for transmitting second data between the chip and the analog-to-digital / digital-to-analog converter, wherein the first data includes custom data, and the second data includes business data.

[0010] According to another embodiment of the present invention, a data transmission device is also provided, including: a transmission module, used to transmit first data through a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data includes custom data, and the second data includes business data.

[0011] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0012] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0013] According to the embodiment of the present invention, since the first data is transmitted by utilizing the invalid bits in the second transmission channel for transmitting the second data, there is no need to deploy multiple additional interconnection lines to transmit the first data. Therefore, the problem of a large number of interconnection lines on a single board is solved and the wiring of the single board is simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the interaction between the chip and the AD / DA device in the related technology;

[0015] Figure 2 is a flow chart of a data transmission method according to an embodiment of the present invention;

[0016] Figure 3is a structural block diagram of a data transmission device according to an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of the structure of a transmission channel in an example implementation mode 1 according to an embodiment of the present invention;

[0018] Figure 5 is a schematic diagram of the structure of a data packet in an example implementation mode 1 of an embodiment of the present invention;

[0019] Figure 6 is a schematic diagram of the structure of a transmission channel in an example implementation mode 2 according to an embodiment of the present invention;

[0020] Figure 7 is a schematic diagram of the structure of a data packet in an example implementation mode 2 of an embodiment of the present invention;

[0021] Figure 8 is a schematic diagram of the structure of a transmission channel in a third exemplary implementation manner according to an embodiment of the present invention;

[0022] Fig. 9 1 is a schematic diagram of the structure of a data packet in example implementation mode 3 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] In this embodiment, a data transmission method is provided, which is applied between a chip and an analog-to-digital digital-to-analog conversion device. Figure 2 is a flow chart of a data transmission method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0026] Step S202, transmitting first data through a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data includes custom data, and the second data includes business data.

[0027] Through the above steps, the first data can be transmitted by utilizing the invalid bits in the second transmission channel for transmitting the second data, without deploying multiple additional interconnection lines to transmit the first data. Therefore, the problem of a large number of interconnection lines on a single board is solved and the wiring of the single board is simplified.

[0028] It should be noted that the method provided in the embodiment of the present invention can be applied between any AI chip and AD / DA device. In an example implementation, the second data is transmitted between the AI ​​chip and the AD / DA device through a second transmission channel, wherein the second data may be business data originally transmitted between a serializer / deserializer (SERializer / DESerializer, SERDES for short), or the first data may be transmitted through a first transmission channel, and the first data may be custom data. The first transmission channel and the second transmission channel may be transmission channels between serializers / deserializers (SERializer / DESerializer, SERDES for short).

[0029] Exemplarily, the custom data may include data originally transmitted between IO pins, such as data originally required to be transmitted through additional wiring or through IO pins, such as a control signal.

[0030] For example, assuming that the system needs to transmit the data of one antenna through the JESD204C protocol (assuming a 32-bit bit width), then the channel for transmitting the data of this antenna is the service data channel (i.e., the second transmission channel realizes the transmission), and the transmission bit width is 32 bits. Although 32 bits of data are transmitted on the service data channel, some of these 32 bits are actually meaningless. These meaningless bits do not carry any useful information. However, due to the requirements of the 204C protocol itself, although some bits are meaningless, they are still transmitted on the channel. Then these meaningless bits are the "invalid bits" stated in this embodiment, that is, invalid bits (i.e., meaningless bits) on the service data channel (equivalent to the "second transmission channel" described above). In this embodiment, these meaningless bits form the first transmission channel, in which custom information is transmitted.

[0031] In this embodiment, the transmission bit width generally refers to the bit width of the service data channel, such as the 32 bits mentioned above, and the transmission bit width carries meaningful data and meaningless data. The method provided in this embodiment regards these invalid bits as a new transmission channel (that is, the first transmission channel described above), and then in this first transmission channel, all invalid bits within a period of time can be used (because only from a certain point in time, there are very few invalid bits and custom information cannot be transmitted) to form a data packet, and the custom information is placed in the data packet, and this data packet is transmitted to the other side through the first transmission channel.

[0032] In an exemplary embodiment, before transmitting the first data through the first transmission channel, the method further includes: forming the first transmission channel with the invalid bit in the second transmission channel, wherein the invalid bit includes at least one of the following:

[0033] a fixed invalid bit in the second transmission channel, wherein the fixed invalid bit is an invalid bit preset in the second transmission channel, and the fixed invalid bit does not carry the second data;

[0034] The remaining invalid bits in the second transmission channel are invalid bits other than the bit width required by the second data in the second transmission channel.

[0035] In an exemplary embodiment, the first transmission channel includes one or more invalid bits in the second transmission channel, or the first transmission channel includes one or more invalid bits in a plurality of second transmission channels respectively.

[0036] In an exemplary implementation, transmitting the first information through the first transmission channel includes: transmitting the first data through a first data transmission unit in the first transmission channel.

[0037] In an example embodiment, the first data transmission unit includes at least one of the following: a type bit, a payload bit, and a check bit; wherein the type bit is used to indicate the type of the first data transmission unit, the payload bit is used to transmit the first data, and the check bit is used to check the first data transmission unit.

[0038] In an example embodiment, the first data transmission unit also includes at least one of the following: a start bit, an end bit, a transmission valid time start bit, and a transmission valid time end bit; wherein the start bit is used to indicate the start boundary of the first data transmission unit, the end bit is used to indicate the end boundary of the first data transmission unit, the transmission valid time start bit is used to indicate the start of the transmission valid time, and the transmission valid time end bit is used to indicate the end of the transmission valid time.

[0039] In an exemplary implementation, the transmitting the first data through the first transmission channel includes: transmitting the first data through one of the first transmission channels; or transmitting the first data through multiple of the first transmission channels. It should be noted that, exemplarily, in some cases, the first data may be relatively large and cannot be transmitted all at once through one transmission channel, so it can be split into multiple transmission channels and transmitted through the multiple transmission channels.

[0040] In an exemplary implementation, when the first transmission channel does not transmit the first data, an idle state indication is transmitted in the first transmission channel. It should be noted that, exemplarily, the idle state indication may be a fixed coding format.

[0041] In an exemplary implementation, a clock of the first transmission channel is the same as a clock of the second transmission channel.

[0042] In an exemplary implementation, the first transmission channel and the second transmission channel are transmission channels that are connected in parallel between the same chip and the analog-to-digital / digital-to-analog converter.

[0043] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0044] In the present embodiment, a data transmission device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0045] Figure 3 is a structural block diagram of a data transmission device according to an embodiment of the present invention. Figure 3 As shown, the device comprises:

[0046] The transmission module 31 is used to transmit first data through a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data includes custom data, and the second data includes business data.

[0047] Through the above steps, the first data can be transmitted by utilizing the invalid bits in the second transmission channel for transmitting the second data, without deploying multiple additional interconnection lines to transmit the first data. Therefore, the problem of a large number of interconnection lines on a single board is solved and the wiring of the single board is simplified.

[0048] In an exemplary embodiment, the transmission module 31 is further configured to, before transmitting the first data through the first transmission channel, form the first transmission channel with the invalid bits in the second transmission channel, wherein the invalid bits include at least one of the following:

[0049] a fixed invalid bit in the second transmission channel, wherein the fixed invalid bit is an invalid bit preset in the second transmission channel, and the fixed invalid bit does not carry the second data;

[0050] The remaining invalid bits in the second transmission channel are invalid bits other than the bit width required by the second data in the second transmission channel.

[0051] In an exemplary embodiment, the first transmission channel includes one or more invalid bits in the second transmission channel, or the first transmission channel includes one or more invalid bits in a plurality of second transmission channels respectively.

[0052] In an exemplary embodiment, the first data is transmitted in the first transmission channel via a first data transmission unit.

[0053] In an exemplary embodiment, the first data transmission unit includes at least one of the following: a type bit, a payload bit, and a check bit; wherein the type bit is used to indicate the type of the first data transmission unit, the payload bit is used to transmit the first data, and the check bit is used to check the first data transmission unit.

[0054] In an exemplary embodiment, the first data transmission unit also includes at least one of the following: a start bit, an end bit, a transmission valid time start bit, and a transmission valid time end bit; wherein the start bit is used to indicate the start boundary of the first data transmission unit, the end bit is used to indicate the end boundary of the first data transmission unit, the transmission valid time start bit is used to indicate the start of the transmission valid time, and the transmission valid time end bit is used to indicate the end of the transmission valid time.

[0055] In an exemplary embodiment, transmitting the first data through the first transmission channel includes: transmitting the first data through one of the first transmission channels; or transmitting the first data through a plurality of the first transmission channels.

[0056] In an exemplary implementation, when the first transmission channel does not transmit the first data, an idle state indication is transmitted in the first transmission channel.

[0057] In an exemplary embodiment, a clock of the first transmission channel is the same as a clock of the second transmission channel.

[0058] In an exemplary embodiment, the first transmission channel and the second transmission channel are transmission channels connected in parallel between the same chip and the analog-to-digital / digital-to-analog converter.

[0059] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0060] An embodiment of the present invention also provides a circuit board, comprising a chip and an analog-to-digital / digital-to-analog converter; wherein first data is transmitted between the chip and the analog-to-digital / digital-to-analog converter via a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, and the second transmission channel is a transmission channel for transmitting second data between the chip and the analog-to-digital / digital-to-analog converter, wherein the first data includes custom data, and the second data includes business data.

[0061] Through the above steps, the first data can be transmitted by utilizing the invalid bits in the second transmission channel for transmitting the second data, without deploying multiple additional interconnection lines to transmit the first data. Therefore, the problem of a large number of interconnection lines on a single board is solved and the wiring of the single board is simplified.

[0062] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0063] Example Implementations

[0064] The following further explains the embodiment of the present invention in conjunction with an exemplary scenario. It should be noted that the technical solution provided in this embodiment is applicable to any interaction protocol between an AI chip and an AD / DA device, and this implementation only uses the JESD204 protocol as an example for explanation.

[0065] The JESD204 protocol is a universal interface standard for data interaction between Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) and analog-to-digital / digital-to-analog conversion (AD / DA) devices. The protocol itself focuses more on data transmission and the realization of deterministic latency.

[0066] This example implementation provides an implementation solution that can rely on the JESD204 interface, but does not use the frame structure of the protocol itself. Control signals are transmitted in the data stream by self-assembling frames, which can be compatible with the limitations caused by the evolution of the protocol itself.

[0067] The data transmission bit width (indicated by parameter N') in the JESD204 protocol is user-definable. In actual use, for the convenience of assembling and deframing, it is usually defined as an integer multiple of 4 bits or 8 bits. The protocol uses N' to represent the transmission bit width of the JESD204 interface during deframing, indicating the actual transmission bit width of a certain sampled data. For example, N'=16 means that a certain sampled data is ultimately transmitted in the form of 16 bits on the JESD204 interface, and N'=12 means that a certain sampled data is ultimately transmitted in the form of 12 bits on the JESD204 interface.

[0068] However, in actual use, the bit width required by the data itself is related to the system requirements. It does not necessarily need to be as large as the bit width ultimately presented on the JESD204 interface, or not all time periods require such a large bit width. However, in order to meet the transmission requirements of the JESD204 protocol, the value of the parameter N' is often greater than the actual bit width requirement.

[0069] Example 1: The data required bit width is smaller than the definition of parameter N', and more redundant bits are added to the data to meet the transmission framing requirements, that is, N' = data required bit width + redundant bits (redundant bits can also be called "invalid bits");

[0070] Example 2: Only in certain time periods (such as when a large signal appears), the required data bit width is equal to the definition of parameter N'. In other time periods (such as when a small signal appears), the required data bit width is smaller than the definition of parameter N'. Generally, for the sake of design simplicity, the required data bit width of each time period is uniformly defined to be the same as parameter N'. However, in some time periods, there are redundant bits in the data.

[0071] These redundant bits occupy transmission resources but cannot transmit any valid information. The solution provided in this example implementation is to use these redundant bits to form an independent transmission channel, and transmit the signal originally transmitted through the IO pin in the form of a data packet. For example, it can be one or more contents of control information, alarm information, status indication, interactive instructions, etc., wherein the control information can be switch control information, gain control information and other information.

[0072] This example implementation provides a method of transmitting user-defined information by using invalid bits in data in a data intercommunication protocol between an AI chip and an AD / DA device, such as the JESD204 protocol, with flexible definition and various implementation methods. For example, this implementation uses some data bits (such as invalid bits) in the JESD204 interface protocol to establish an independent transmission channel, and can use a serializer / deserializer (SERializer / DESerializer, referred to as SERDES) to transmit customized information, such as user-defined information, or, for example, control information that originally needs to be implemented through IO pins, saving chip IO resources and single-board wiring pressure.

[0073] In an exemplary implementation, the user-defined information is incorporated at the user side of the JESD204 protocol transport layer and is not affected by the JESD204 protocol version.

[0074] In an exemplary implementation, the user's customized information is stored in invalid bits of the data. These invalid bits may be certain fixed bits in the data that are set as long-term invalid bits, or certain bits in the data within a certain period of time.

[0075] In an exemplary embodiment, these invalid bits are used to form a transmission channel without occupying normal valid data.

[0076] In an exemplary embodiment, a transmission channel may be composed of a single sampled data (1 M) or a plurality of sampled data (multiple M), wherein M is a special term of the JESD204 protocol and is described in the protocol as a digital-to-analog / analog-to-digital converter. For example, 1 M refers to 1 ADC or DAC.

[0077] In an exemplary implementation, the clock of the transmission channel is the working clock for sampling data, and no additional clock resources need to be provided.

[0078] In an exemplary embodiment, the transmission content of each transmission channel can be customized. For a chip-to-chip interconnection system with multiple transmission channels, you can choose to use only one transmission channel to transmit user-defined information, or you can use multiple transmission channels to share the transmission of user-defined information.

[0079] In an exemplary implementation, in a transmission channel, user-defined information is transmitted in the form of a data packet, and the present solution uses a variety of basic structures to define the data packet.

[0080] In an exemplary embodiment, 1 bit in the invalid bits can be used to specify the boundary of the data packet, and 1 or more bits in the invalid bits can be used to transmit information. When the bit specifying the boundary is in an invalid state, it indicates that the current data packet is not valid and the transmitted information is invalid.

[0081] In an exemplary embodiment, multiple states can be used to specify the boundaries of data packets. When there is no user information to be transmitted, the transmission channel is in an idle state. When user information transmission is required, user-defined data packets are transmitted. It should be noted that the "state" here refers to the current state of the transmission channel, because the transmission channel does not necessarily need to send valid data packets all the time. So when there is no need to transmit valid data packets, illustratively, the transmission channel does not transmit nothing, but transmits an IDLE code to tell the receiver that the current state is idle. Once there is a data packet to be transmitted, the transmission channel will change from an idle state to a valid data packet format. When the receiver finds that a valid data packet format has been received, it believes that the system has left the idle state and starts receiving data packets.

[0082] In an exemplary embodiment, for a transmission channel that only appears in a certain time period, an additional identifier may be added as needed to indicate the start and end of the time period.

[0083] Example Implementation 1

[0084] Figure 4 is a schematic diagram of the structure of a transmission channel according to an example implementation mode 1 of an embodiment of the present invention. The structure of the transmission channel is defined as follows: Figure 4 As shown: Taking N'=16 complex sampling signals as an example, the data required bit width is 14 bits, the lower 2 bits of the 16 bits are fixed bits set as long-term invalid bits, and a transmission channel is composed of a complex sampling data channel I+Q. 1 bit is used to specify the data packet boundary in the transmission channel.

[0085] In an exemplary embodiment, on a transmission channel, the signal to be transmitted is allocated to be transmitted in each data packet. Figure 5 is a schematic diagram of the structure of a data packet in an example implementation mode 1 of an embodiment of the present invention, such as Figure 5 As shown, in an exemplary embodiment, the data packet structure is described as follows:

[0086] In an exemplary embodiment, CS is pulled low to indicate the boundary of a packet of data, where CS stands for chip selection, which means chip selection. In the interface protocol, CS is transmitted from the transmitter to the receiver. When CS is valid (for example, 0), it means that the transmitter informs the receiver that the receiver is selected at this moment, and data can be exchanged between the two. CS can be an independent bit, which can be configured as 0 or 1. Pulling CS low means that from a certain moment, CS changes from 1 to 0. Pulling CS low can indicate the beginning of a data packet. After a period of time, CS changes from 0 to 1 to indicate the end of this packet of data. The period of time when the CS signal is 0 indicates the valid boundary of a packet of data.

[0087] In an exemplary embodiment, each packet of data consists of a header, a payload, and a chk;

[0088] In an exemplary embodiment, the Header is used to indicate the type of the data packet, and the length X can be defined according to requirements;

[0089] In an exemplary embodiment, Payload is used to transmit valid information, such as the control signal mentioned above, and the length Y can be defined according to requirements;

[0090] In an exemplary implementation, Chk is used for checking, which may be a parity check, a CRC check, etc., and the length Z may be defined according to requirements.

[0091] In an exemplary implementation, the header, tail, start, end status, etc. of a data packet may also be used to indicate the boundary of a data packet.

[0092] Example Implementation 2

[0093] Figure 6 is a schematic diagram of the structure of a transmission channel in an example implementation mode 2 according to an embodiment of the present invention. Figure 6 As shown, taking N'=16 multiplexed signals as an example, the data bit width required is 15 bits, the lowest 1 bit in the 16 bits is a long-term valid fixed invalid bit, a transmission channel is composed of a complex sampling data channel I+Q, and the data packet boundary is specified using the status.

[0094] In an exemplary embodiment, on a transmission channel, the signal to be transmitted is allocated in each data packet for transmission. Figure 7 is a schematic diagram of the structure of a data packet in an example implementation mode 2 of an embodiment of the present invention, such as Figure 7 As shown:

[0095] In an exemplary embodiment, the data packet structure is described as follows:

[0096] In an exemplary embodiment, when there is no data packet to be transmitted, the channel is always transmitting in an idle state;

[0097] In an exemplary embodiment, the idle state is represented by a fixed encoding format;

[0098] In an exemplary embodiment, each packet of data consists of a header, a payload, a chk, and a tail;

[0099] In an exemplary embodiment, the Header is used to indicate the type of the data packet, and its definition does not include a fixed code for the idle state, and the length A can be defined according to requirements;

[0100] In an exemplary embodiment, Payload is used to transmit valid information, such as the control signal mentioned above, and the length B can be defined according to requirements;

[0101] In an exemplary embodiment, Chk is used for checking, which may be a parity check, a CRC check, etc., and the length C may be defined according to requirements;

[0102] In an exemplary embodiment, Tail is used to indicate the end of a data packet, and the length D can be defined according to requirements.

[0103] Example Implementation 3

[0104] Figure 8 is a schematic diagram of the structure of the transmission channel in the third exemplary implementation mode according to an embodiment of the present invention. Figure 8 As shown, taking N'=16 single-sample data transmission as an example, under normal circumstances, all 16 bits of data are valid, and user-defined information is not transmitted at this time; but in certain time periods, only 12 bits of data are valid, and at this time, the redundant 4 bits in the 16 bits form a valid transmission channel for a period of time.

[0105] In an exemplary embodiment, during the effective time period of the transmission channel, the signal to be transmitted is allocated to each data packet for transmission. Fig. 9 is a schematic diagram of the structure of a data packet in an example implementation mode 3 of an embodiment of the present invention, such as Fig. 9 As shown:

[0106] In an exemplary implementation, the data packet structure in the exemplary implementation mode 3 is described as follows:

[0107] In an exemplary embodiment, start is used to indicate the start of a user-defined transmission valid time period, start is composed of a group of special codes, and the length X can be defined according to requirements; it should be noted that the transmission valid time period may refer to the valid time period of the remaining invalid bits, because the remaining invalid bits are only valid for a period of time, so some special sequences are required to indicate the start and end of this period, and the above start can be used to indicate the start of the transmission valid time period;

[0108] In an exemplary embodiment, the idel state is represented by a fixed coding format, indicating that no valid data packet is transmitted;

[0109] In an exemplary embodiment, each packet of data consists of a header, a payload, a chk, and a tail;

[0110] In an exemplary embodiment, the Header is used to indicate the type of the data packet, and its definition does not include a fixed code for the idle state, and the length A can be defined according to requirements;

[0111] In an exemplary embodiment, Payload is used to transmit valid information, such as the control signal mentioned above, and the length B can be defined according to requirements;

[0112] In an exemplary embodiment, Chk is used for checking, which may be a parity check, a CRC check, etc., and the length C may be defined according to requirements;

[0113] In an exemplary embodiment, Tail is used to indicate the end of a data packet, and the length D can be defined according to requirements;

[0114] In an exemplary embodiment, end is used to indicate the end of a user-defined transmission valid time period. End consists of a set of special codes, and the length Y can be defined according to requirements, where end corresponds to the above start and is applied to the remaining invalid bits. End can indicate when this period of remaining invalid bits ends (i.e., the end of the transmission valid time period).

[0115] Through the implementation mode of the present invention, an independent transmission channel is formed by utilizing redundant bits that are not used for a long time or a short time or are invalid in the data, into which user-defined signals are integrated, and transmitted at both the receiving and transmitting ends through the SERDES provided by the JESD204 protocol, without the need to use independent IO pins.

[0116] This implementation can be applied to single-board designs that include ASIC and AD / DA devices and use the JESD204 protocol, which can reduce chip IO pins and single-board wiring pressure;

[0117] Take a 32-channel board as an example: Currently, when ASIC is connected to AD / DA devices, in addition to using the JESD204 interface to transmit 32 channels of data, 32 IO pins are usually required to transmit send enable control, 32 IO pins to transmit receive enable control, and 8 pins to transmit feedback enable control.

[0118] Using this solution, these 32+32+8=72 IO pins do not need to be routed on the single board, but can be transmitted along with the data in the JESD204 protocol, reducing the pressure on the single board wiring layout.

[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0120] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0121] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0122] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0123] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0124] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0125] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data transmission method, characterized in that: Applied between chips and analog-to-digital conversion devices, including: First data is transmitted through a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data includes custom data, the second data includes business data, and the first data is transmitted through a first data transmission unit in the first transmission channel, the first data transmission unit includes at least one of the following: a type bit, a payload bit, and a check bit, the type bit is used to indicate a type of the first data transmission unit, the payload bit is used to transmit the first data, and the check bit is used to check the first data transmission unit.

2. The method according to claim 1, characterized in that Before transmitting the first data through the first transmission channel, the method further includes: The invalid bits in the second transmission channel are used to form the first transmission channel, wherein the invalid bits include at least one of the following: a fixed invalid bit in the second transmission channel, wherein the fixed invalid bit is an invalid bit preset in the second transmission channel, and the fixed invalid bit does not carry the second data; The remaining invalid bits in the second transmission channel are invalid bits in the second transmission channel except for the bit width required by the second data.

3. The method according to claim 1, characterized in that The first transmission channel includes one or more invalid bits in the second transmission channel, or the first transmission channel includes one or more invalid bits in a plurality of second transmission channels respectively.

4. The method according to claim 1, characterized in that: The first data transmission unit includes at least one of the following: Start bit, end bit, start bit of transmission effective time, end bit of transmission effective time; Among them, the start bit is used to indicate the start boundary of the first data transmission unit, the end bit is used to indicate the end boundary of the first data transmission unit, the transmission effective time start bit is used to indicate the start of the transmission effective time, and the transmission effective time end bit is used to indicate the end of the transmission effective time.

5. The method according to any one of claims 1 to 2, characterized in that The transmitting the first data through the first transmission channel includes: Transmit the first data through one of the first transmission channels; or, The first data are transmitted through a plurality of the first transmission channels respectively.

6. The method according to any one of claims 1 to 2, characterized in that When the first transmission channel does not transmit the first data, an idle state indication is transmitted in the first transmission channel.

7. The method according to any one of claims 1 to 2, characterized in that A clock of the first transmission channel is the same as a clock of the second transmission channel.

8. The method according to any one of claims 1 to 2, characterized in that The first transmission channel and the second transmission channel are transmission channels connected in parallel between the same chip and the analog-to-digital / digital-to-analog converter.

9. A circuit board, characterized in that: include: Chips, analog-to-digital / digital-to-analog converters; Wherein, first data is transmitted between the chip and the analog-to-digital / digital-to-analog converter via a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data between the chip and the analog-to-digital / digital-to-analog converter, the first data includes custom data, the second data includes business data, and the first data is transmitted in the first transmission channel via a first data transmission unit, the first data transmission unit includes at least one of the following: a type bit, a payload bit, and a check bit, the type bit is used to indicate the type of the first data transmission unit, the payload bit is used to transmit the first data, and the check bit is used to check the first data transmission unit.

10. A data transmission device, characterized in that: include: A transmission module, used to transmit first data through a first transmission channel, wherein the first transmission channel includes an invalid bit in a second transmission channel, the second transmission channel is a transmission channel for transmitting second data, the first data includes custom data, the second data includes business data, and the first data is transmitted in the first transmission channel through a first data transmission unit, the first data transmission unit includes at least one of the following: a type bit, a payload bit, and a check bit, the type bit is used to indicate the type of the first data transmission unit, the payload bit is used to transmit the first data, and the check bit is used to check the first data transmission unit.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 8 when executed.

12. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 8.

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