Silicon optical chip with positioning slot and processing method thereof

Abstract

The application provides a silicon optical chip with a positioning groove and a processing method thereof, and relates to the technical field of semiconductor production. The positioning groove is processed on the side wall to be coupled with the end face of an optical fiber, so that the alignment accuracy can be improved, the utilization rate of the silicon optical chip wafer is improved, and the cost is reduced. The side wall of the silicon optical chip is provided with at least one positioning groove for realizing the coupling of the optical fiber and the end face of a waveguide and having a positioning effect on the optical fiber. The positioning effect is that, in the plane where the silicon optical chip is located, the positioning groove limits the displacement of the optical fiber. When coupling, the silicon optical chip is attached to the upper surface of a PCBA substrate, the optical fiber to be coupled is fixed to the upper surface of a glass substrate with a specific thickness, and the end part of the optical fiber protruding from the glass substrate is inserted into the corresponding positioning groove to realize the coupling. The technical scheme provided by the application is suitable for the process of semiconductor production.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor production, and in particular to a silicon optical chip with positioning grooves and a processing method thereof. BACKGROUND

[0002] In recent years, with the rapid development of Internet of Things and big data applications, global data traffic is growing rapidly, and the demand for transmission is gradually increasing. With the large-scale use of high-speed optical modules in data centers, traditional III-V semiconductor optical chips will face problems such as parallel transmission and high cost of III-V epitaxy. Under this background, silicon photonics technology emerges as the times require and becomes a major alternative to III-V semiconductors. The optical module based on silicon photonics technology is manufactured based on CMOS technology. Large-scale waveguide devices can be quickly processed on a silicon substrate using etching technology. Key devices such as modulators and receivers can be prepared using epitaxial growth and other processing technologies. Ultimately, modulators, receivers, and passive optical devices can be integrated, which has the characteristics of high integration, low cost, and better transmission performance. The key to the practical production of various optical integrated devices from the laboratory is to achieve the coupling of waveguides and optical fibers. However, the original silicon optical chip processed by CMOS technology cannot be directly coupled with the optical fiber at the end face. The main reason is that there is a certain distance between the waveguide region and the edge of the chip, and the excess part of the silicon substrate needs to be removed for use. In order to reduce the distance between the silicon optical chip waveguide and the chip edge and achieve the end face coupling of the waveguide and the optical fiber, the most commonly used method is mechanical grinding and chemical mechanical polishing (CMP). However, there are still many problems, such as high cost, difficulty in mass production, easy penetration of polishing liquid into the chip surface leading to corrosion and pollution, and more prone to waveguide collapse or crack phenomenon. In recent years, with the development of laser technology, laser stealth cutting has gradually become a research hotspot in the field of chip manufacturing. Laser stealth cutting is a non-contact processing process, which not only has high cutting precision and efficiency, but also can avoid damage to the surface of the waveguide device, greatly improving the quality and efficiency of silicon optical chip production and manufacturing.

[0003] The principle diagram of the coupling packaging scheme of the optical fiber array based on IBM is shown in FIG. 1. Figure 1 As shown in FIG. 1, the optical fiber array is connected with the optical fiber joint, and a V-shaped groove array is etched on the upper surface of the silicon optical chip for placing the optical fiber array. Figure 1 The small cuboid above the optical fiber array is a polymer cover. Because the optical fiber array is not convenient to be sucked by the suction head, a polymer cover that is easy to suck is added. After the suction head sucks the polymer cover, it is pressed on the silicon optical chip, so that the optical fiber array falls into the V-shaped groove. The position of each optical fiber can be further finely adjusted, so that the optical fiber completely falls into the V-shaped groove, achieving the optimal coupling efficiency. However, the etching area of the V-shaped groove array often exceeds 20% of the surface area of the silicon optical chip, and the utilization rate of the wafer is low, which is not conducive to cost control and popularization.

[0004] Therefore, it is necessary to study a silicon optical chip with a positioning groove and a processing method thereof to solve or mitigate one or more of the above problems. SUMMARY

[0005] Therefore, the present application provides a silicon optical chip with a positioning groove and a processing method thereof, which can improve the alignment accuracy, increase the utilization rate of silicon optical chip wafer, and reduce the cost by processing a positioning groove on the sidewall to couple with the fiber end face.

[0006] The present application provides a silicon optical chip with a positioning groove, characterized in that the sidewall of the silicon optical chip is provided with at least one positioning groove for realizing the coupling of the optical fiber and the waveguide and having a positioning effect on the optical fiber.

[0007] The positioning effect is specifically that the positioning groove limits the displacement of the optical fiber in the plane where the silicon optical chip is located.

[0008] The distance between the end face of the waveguide and the bottom end face of the positioning groove is not more than 5 μm.

[0009] According to the above-mentioned aspect and any possible implementation manner, further provided is an implementation manner, when the silicon optical chip is viewed from above, the shape of the positioning groove is trapezoidal, V-shaped, U-shaped or rectangular.

[0010] According to the above-mentioned aspect and any possible implementation manner, further provided is an implementation manner, when the number of the positioning grooves is two or more, the shapes of different positioning grooves are the same or different.

[0011] According to the above-mentioned aspect and any possible implementation manner, further provided is an implementation manner, the waveguide region of the silicon optical chip is etched with an alignment mark.

[0012] According to the above-mentioned aspect and any possible implementation manner, further provided is an implementation manner, the alignment mark is any one or more of a "+" type, an L type, a rectangular shape and a circular shape.

[0013] According to the above-mentioned aspect and any possible implementation manner, further provided is an implementation manner, the size of the silicon optical chip is: 5920 μm in length, 4920 μm in width and 220 μm in thickness; and the distance between two adjacent waveguides of the silicon optical chip is 125-500 μm.

[0014] According to the above-mentioned aspect and any possible implementation manner, further provided is an implementation manner, when the positioning groove is a trapezoidal groove:

[0015] The distance between the waveguide end face and the bottom of the trapezoidal groove is 5 μm, and the height of the trapezoidal groove is 40 μm.

[0016] The inner bottom width of the trapezoidal groove is 126 microns, and the outer opening width of the trapezoidal groove is 210 microns.

[0017] The diameter of the optical fiber used is 80-200 microns.

[0018] In another aspect, the present application provides a processing method of a silicon optical chip with a positioning groove, characterized in that the processing method comprises the following steps:

[0019] S1, back-thinning treatment is performed on a silicon optical wafer to obtain a first silicon optical wafer with a suitable back thickness;

[0020] S2, after fixing and aligning the first silicon optical wafer, laser stealth cutting is performed by using a back cutting process;

[0021] S3, a carrier film is attached to the back of the cut silicon optical wafer, and a side wall with a positioning groove is obtained by film expansion treatment.

[0022] As described above, the aspect and any possible implementation manner, further provides an implementation manner, the silicon optical wafer is thinned to 220 microns after being polished by a polishing device.

[0023] As described above, the aspect and any possible implementation manner, further provides an implementation manner, before laser stealth cutting, an alignment mark is etched in the waveguide region of the first silicon optical wafer; during laser stealth cutting, secondary alignment is performed according to the alignment mark to reduce accumulated cutting error.

[0024] As described above, the aspect and any possible implementation manner, further provides an implementation manner, the fixing manner of the first silicon optical wafer in step S2 is specifically that a UV film with a steel ring is cut on the front surface of the first silicon optical wafer, and the first silicon optical wafer is fixed with the front surface facing down on a vacuum chuck.

[0025] As described above, the aspect and any possible implementation manner, further provides an implementation manner, the alignment of the first silicon optical wafer in step S2 is specifically that the first silicon optical wafer is imaged by a penetrating infrared camera, and real-time imaging data is used to realize alignment before cutting.

[0026] Secondary alignment is performed after the infrared camera recognizes the alignment mark of the waveguide region.

[0027] As described above, the aspect and any possible implementation manner, further provides an implementation manner, the method further comprises:

[0028] S4, coupling of a waveguide in the silicon optical chip with an optical fiber is realized through the positioning groove;

[0029] Specifically, the silicon optical chip with the positioning groove is attached to the upper surface of the PCBA substrate, the optical fiber to be coupled is fixed on the upper surface of the glass substrate, and the end of the optical fiber protruding from the glass substrate is inserted into the corresponding positioning groove to achieve coupling.

[0030] According to the aspect and any possible implementation manner described above, further provided is an implementation manner, wherein the length of the optical fiber protruding from the glass substrate is 100-500 mu m, and self-alignment and passive coupling can be achieved.

[0031] According to the aspect and any possible implementation manner described above, further provided is an implementation manner, wherein the positioning of the optical fiber in the direction perpendicular to the silicon optical chip is determined by the thickness of the glass substrate, that is, the glass substrate is attached to the PCBA substrate, the optical fiber is fixed on the upper surface of the glass substrate, and the thickness of the glass substrate determines the distance between the lower section of the optical fiber and the upper surface of the PCBA substrate.

[0032] Compared with the prior art, one of the technical solutions has the following advantages or beneficial effects: the positioning groove is processed on the sidewall of the silicon optical chip, coupling is performed with the end face of the optical fiber, the positioning groove limits the optical fiber in the x-axis and y-axis directions, and high alignment accuracy can be ensured.

[0033] Another of the technical solutions has the following advantages or beneficial effects: the positioning groove is processed on the sidewall of the silicon optical chip, compared with the traditional etching V groove on the upper surface of the silicon optical chip, the utilization rate of the silicon optical wafer is improved, and the cost is reduced.

[0034] Another of the technical solutions has the following advantages or beneficial effects: the positioning groove is processed by laser stealth cutting, the processing efficiency is higher, and the time required for the entire process flow can be shortened.

[0035] Another of the technical solutions has the following advantages or beneficial effects: the alignment mark is processed in the waveguide region of the silicon optical chip, the alignment mark is used for secondary positioning during laser stealth cutting, the cumulative cutting error is reduced, and the cutting accuracy is improved.

[0036] Of course, implementing any product of the present application does not necessarily need to achieve all the technical effects described above. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1is the structural principle diagram of the coupling packaging scheme based on the fiber array provided by the prior art;

[0039] Figure 2 is the design diagram of the positioning groove provided by one embodiment of the present application;

[0040] Figure 3 is the design diagram of the alignment mark provided by one embodiment of the present application;

[0041] Figure 4 is the schematic diagram of the laser stealth cutting of the silicon optical chip with the positioning groove provided by one embodiment of the present application;

[0042] Figure 5 is the end face coupling diagram of the silicon optical chip with the positioning groove and the fiber array provided by one embodiment of the present application;

[0043] Figure 6 is the local schematic diagram of the waveguide and fiber coupling provided by one embodiment of the present application.

[0044] In the figure:

[0045] 1, silicon optical chip; 2, PCBA; 3, waveguide; 4, glass substrate; 5, optical fiber; 6, alignment mark; 7, cutting path; 8, positioning groove. DETAILED DESCRIPTION

[0046] In order to better understand the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0047] It should be clear that the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0048] In view of the deficiencies of the prior art, the present application provides a silicon optical chip with a positioning groove, which is used for end face coupling with a fiber array. The positioning groove is processed on the side wall of the silicon optical chip. When coupling, the movement of the optical fiber in the x-axis and y-axis directions is limited by the positioning groove, which reduces the volume of the silicon optical chip and the cost while meeting the coupling precision.

[0049] The positioning groove of the present application is processed by laser stealth cutting technology, which has higher processing efficiency and can shorten the time required for the entire process flow. Specifically:

[0050] As a specific embodiment, after the silicon light wafer is thinned on the back by a grinding device, a UV film is attached to the front and attached to a steel ring. The wafer with the UV film is placed on the vacuum chuck with the front down, and the entire silicon light wafer is cut by back cutting process. The infrared camera attached to the laser stealth cutting machine can penetrate the silicon substrate to form an image, thereby helping to realize alignment processing. After alignment, the laser cutting machine cuts the silicon light chip along the designed laser cutting path. The infrared alignment can penetrate the silicon material and achieve an alignment accuracy of within 2 um, so when the infrared camera identifies the alignment mark of the waveguide area and determines that the condition is met, the laser performs secondary positioning to reduce the cumulative cutting error. The energy density of the laser in the focal point area is high, forming a multi-photon absorption nonlinear absorption effect, so that the silicon substrate is modified to form a crack. Each laser pulse acts equally to form an equal distance damage, which can form a modified layer inside the silicon substrate. The molecular bonds of the silicon substrate at the modified layer position are destroyed, and the intermolecular connection becomes weak and easy to separate. The wafer after cutting is attached to the back of the bearing film, and the UV operation is performed to tear off the UV film attached to the front. By stretching the bearing film through the film stretching machine (i.e. film stretching treatment), the silicon light chips are fully separated, and gaps are generated between the chips, which is convenient for the next die bonding, coupling and other processing technologies.

[0051] In this embodiment, the positioning groove can define the position of the optical fiber, and the distance between the waveguide end face and the bottom of the positioning groove is small enough to reduce the coupling loss.

[0052] Specifically, the positioning groove can be trapezoidal, V-shaped, U-shaped, rectangular, etc. The waveguide region of the silicon light wafer is etched with an alignment mark for secondary positioning during laser stealth cutting. The alignment mark can be "+" shaped, L-shaped, rectangular, circular, etc.

[0053] Example 1:

[0054] The silicon light chip structure with a positioning groove and the processing method provided in this embodiment are applied to a 400G high-speed optical module. Through the trapezoidal positioning groove, the optical fiber array and the waveguide are end-coupled.

[0055] The silicon light chip size used in this embodiment is 5920 um long, 4920 um wide, and 220 um thick. As shown in Figure 2 , we design the size of the trapezoidal positioning groove. The center distance L between the two waveguides of the silicon light chip is 250 um, the distance d between the waveguide and the upper bottom of the trapezoidal groove is 5 um, the height h of the trapezoidal groove is 40 um, the width of the upper bottom of the trapezoidal groove (i.e. the inner bottom width of the trapezoidal groove) c is 126 um, and the lower bottom of the trapezoidal groove (i.e. the slot width of the trapezoidal groove) w is 210 um. The optical fiber array core diameter used is 130 um, and the trapezoidal groove can limit the position of the x-axis and y-axis of the optical fiber.

[0056] As shown in Figure 3As shown in the figure, the L-shaped alignment marks on both sides of the silicon photonics chip waveguide are designed. The distance x from the alignment mark to the waveguide center is 30 μm, and the distance y from the waveguide end face is 30 μm. The side lengths b and f of the alignment mark are 18 μm and 50 μm, respectively. The alignment marks are etched on the silicon photonics wafer through photolithography, development, and etching.

[0057] like Figure 4 As shown, after the back of the silicon photonics wafer is thinned to 220μm by a grinding machine, a UV film is applied to the front and attached to a steel ring. The UV-filmed wafer is placed face-down on a vacuum chuck, and the entire silicon photonics wafer is cut using a back-cutting process. The infrared camera of the invisible laser cutting machine can penetrate the silicon substrate for imaging. The aligned laser cutting machine cuts the silicon photonics chip along the designed laser cutting path. When the infrared camera recognizes the L-shaped alignment mark in the waveguide area, the laser performs secondary positioning to reduce accumulated cutting errors. The laser has a high energy density in the focal area, which creates a multi-photon absorption nonlinear absorption effect, causing the silicon substrate to be modified and cracked.

[0058] A carrier film is applied to the back of the cut silicon photonics wafer, and UV treatment is performed, and the UV film on the front is removed. A film expander stretches the carrier film to fully separate the silicon photonics chips and create gaps between them, facilitating subsequent processes such as die bonding and coupling.

[0059] like Figure 5 As shown in the figure, the silicon photonic chip is mounted on the PCBA substrate and end-face coupled with the optical fiber array, wherein the fiber array core is fixed on the glass substrate, and the core protrudes 500μm from the glass substrate to facilitate positioning in the x-axis and y-axis directions through the trapezoidal grooves. The z-axis direction (i.e., the direction perpendicular to the silicon photonic chip) is positioned by the height of the glass substrate, thereby determining the spatial position of the optical fiber array (the glass substrate is fixed on the PCBA substrate). Figure 6 As shown in FIG, a partial schematic diagram of the coupling between a silicon optical waveguide with a trapezoidal groove and an optical fiber array is shown. It can be seen from the figure that the alignment accuracy is high and the coupling efficiency is high.

[0060] The above describes in detail a silicon photonic chip with positioning grooves and its processing method provided in the embodiments of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concepts of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

[0061] The term used in the embodiments of the present application is only for the purpose of describing particular embodiments and is not intended to limit the present application. The singular forms "a," "an," and "the" used in the embodiments of the present application and the appended claims are intended to include plural forms as well, unless the context clearly indicates otherwise. In this application, the terms "upper," "lower," "left," "right," "inner," "outer," "middle," "horizontal," "vertical," and the like, refer to the orientation or position as shown in the drawings. The above terms are used only to describe the orientation or position relationship based on the drawings. In addition to the orientation or position relationship, the above terms can also be used to represent other meanings, for example, the term "upper" can also be used to represent a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in this application can be understood according to the specific circumstances. The term "and / or" used in this application is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this application generally represents an "or" relationship between the front and rear associated objects.

[0062] As some terms are used in the description and claims, those skilled in the art can understand that hardware manufacturers may use different names to refer to the same component. The description and claims of the present application do not distinguish components by name differences, but by functional differences. As mentioned throughout the description and claims, "including" and "comprising" are open terms, which should be interpreted as "including / comprising but not limited to". "Approximately" means within an acceptable error range, and those skilled in the art can solve the technical problems within a certain error range and basically achieve the technical effects. The subsequent description in the specification is a preferred embodiment for implementing the present application, and the description is for the purpose of illustrating the general principles of the present application, and is not intended to limit the scope of the present application. The scope of protection of the present application is defined by the appended claims.

Claims

1. A silicon photonic chip with a positioning groove, characterized in that: The side wall of the silicon photonic chip is provided with at least one positioning groove for achieving coupling between the optical fiber and the waveguide and having a positioning effect on the optical fiber; The positioning function is specifically as follows: the positioning groove limits the displacement of the optical fiber in the plane where the silicon photonic chip is located; the positioning groove limits the movement of the optical fiber in the x-axis and y-axis directions; wherein, the bottom end surface of the positioning groove is in contact with the end surface of the optical fiber, thereby limiting the movement of the optical fiber in the y-axis direction; the x-axis and y-axis directions are both parallel to the surface of the silicon photonic chip on which the waveguide is provided; The distance between the end face of the waveguide and the bottom end face of the positioning groove does not exceed 5 μm; The positioning groove passes through the side wall of the silicon photonic chip.

2. The silicon photonic chip with positioning grooves according to claim 1, characterized in that: When looking down at the silicon photonic chip, the positioning groove has a shape of a trapezoid, a V-shaped, a U-shaped or a rectangle.

3. The silicon photonic chip with positioning grooves according to claim 1, wherein: When the number of the positioning grooves is more than two, the shapes of different positioning grooves are the same or different.

4. The silicon photonic chip with positioning grooves according to claim 1, wherein: An alignment mark is etched on the waveguide region of the silicon photonic chip.

5. The silicon photonic chip with positioning grooves according to claim 4, characterized in that: The alignment mark is any one or more of a "+" shape, an L shape, a rectangle and a circle.

6. A method for processing a silicon photonic chip having a positioning groove, characterized in that: The processing method comprises the following steps: S1. Performing backside thinning on the silicon photonic wafer to obtain a first silicon photonic wafer with an appropriate backside thickness; S2. After fixing and aligning the first silicon photonic wafer, perform invisible laser cutting using a back-cutting process; S3. A carrier film is attached to the back of the cut silicon photonic wafer, and a silicon photonic chip with a positioning groove running through its side wall is obtained through film expansion processing, so as to limit the movement of the optical fiber in the x-axis and y-axis directions through the positioning groove; wherein, the bottom end face of the positioning groove is bonded to the end face of the optical fiber to limit the movement of the optical fiber in the y-axis direction; the x-axis and y-axis directions are both parallel to the surface of the silicon photonic chip on which the waveguide is set.

7. The method for processing a silicon photonic chip with positioning grooves according to claim 6, wherein: Before the laser stealth cutting, an alignment mark is etched on the waveguide area of ​​the first silicon photonic wafer; during the laser stealth cutting process, a secondary alignment is performed according to the alignment mark to reduce the accumulated cutting error.

8. The method for processing a silicon photonic chip with positioning grooves according to claim 6, wherein: In step S2, the first silicon photonic wafer is fixed as follows: a UV film with a steel ring is attached to the front surface of the first silicon photonic wafer, and the wafer is placed face down on a vacuum suction cup for fixing.

9. The method for processing a silicon photonic chip with positioning grooves according to claim 7, wherein: The alignment of the first silicon photonic wafer in step S2 is specifically as follows: performing penetrating imaging of the first silicon photonic wafer by an infrared camera, and achieving alignment before cutting based on real-time imaging data; Secondary alignment is performed after the infrared camera recognizes the alignment mark of the waveguide area.

10. The method for processing a silicon photonic chip with positioning grooves according to claim 6, wherein: The method further comprises: S4, achieving coupling between the waveguide in the silicon photonic chip and the optical fiber through the positioning groove; Specifically, the silicon photonic chip with the positioning groove is mounted on the upper surface of the PCBA substrate, the optical fiber to be coupled is fixed on the upper surface of the glass substrate, and the end of the optical fiber protruding from the glass substrate is inserted into the corresponding positioning groove to achieve coupling.

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