Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a second region; forming a plurality of source-drain doped layers, a plurality of gate structures, and an initial first dielectric layer in the substrate in the first region and the second region, respectively; forming a first mask layer on the surface of the initial first dielectric layer, the first mask layer on the first region and the second region respectively having a plurality of first openings, the first openings being located on the source-drain doped layers, and the first opening density on the first region is different from the first opening density on the second region; forming a plurality of second openings in the first mask layer in the first region and the second region, the second openings being located on the gate structures. Thus, the performance and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the chip integration of ultra-large-scale integrated circuits (ULSI) has reached the scale of hundreds of millions or even billions of devices, and multi-level metal interconnect technology has been widely used.

[0003] However, as device density increases, short circuits are more likely to occur between interconnect structures. The continued reduction in the critical dimensions of interconnect structures can also easily lead to short circuits between interconnect structures and devices, thereby affecting the performance and reliability of semiconductor devices. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance and reliability of semiconductor devices.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a plurality of source-drain doped layers, a plurality of gate structures located between adjacent source-drain doped layers in the first region and the second region, and an initial first dielectric layer located on the surface of the substrate and the gate structure in the substrate in the first region and the second region respectively; forming a first mask layer on the surface of the initial first dielectric layer, the first mask layer on the first region and the second region respectively having a plurality of first openings, the first openings being located on the source-drain doped layers, and the first opening density on the first region is different from the first opening density on the second region; forming a plurality of second openings in the first mask layer in the first region and the second region, the second openings being located on the gate structure.

[0006] Optionally, the method for forming the second opening includes: after forming the first mask layer, forming a second opening patterned layer on the surface of the first mask layer, the second opening patterned layer exposing part or all of the surface of the first mask layer on the gate structure of the first area and the second area; using the second opening patterned layer as a mask, etching the first mask layer until the initial first dielectric layer is exposed.

[0007] Optionally, there is a first distance between a top surface of the source / drain doping layer and a top surface of the initial first dielectric layer, and a thickness of the first mask layer is smaller than the first distance.

[0008] Optionally, the thickness of the first mask layer ranges from 100 angstroms to 700 angstroms.

[0009] Optionally, the method for forming the second opening further includes: before forming the second opening patterning layer, forming first sidewalls on sidewall surfaces of the first opening in the first region and the second region respectively.

[0010] Optionally, the method for forming the first sidewall spacer includes: forming a sidewall material layer on the surface of the first mask layer and the surface of the initial first dielectric layer; and etching back the sidewall material layer until the surface of the first mask layer and the surface of the initial first dielectric layer are exposed.

[0011] Optionally, the method for forming the first mask layer also includes: before forming the second opening, forming a first mask material layer on the surface of the initial first dielectric layer; forming a first opening patterned layer on the surface of the first mask material layer, the first opening patterned layer exposing the surface of the first mask material layer on at least part of the source-drain doped layer of the first region and the second region; using the first opening patterned layer as a mask, etching the first mask material layer until the initial first dielectric layer is exposed.

[0012] Optionally, it also includes: after forming the second opening, etching the initial first dielectric layer using the first mask layer as a mask until the gate structure and the surface of the source and drain doped layers in the first and second regions are exposed to form a first dielectric layer, and the first dielectric layer on the first and second regions has a plurality of first interconnect openings and a plurality of second interconnect openings, respectively, the first interconnect openings expose at least a portion of the surface of the source and drain doped layers in the first and second regions, and the second interconnect openings expose at least a portion of the surface of the gate structure in the first and second regions.

[0013] Optionally, the method further includes: before forming the first mask layer, forming a first stop layer on the surface of the initial first dielectric layer.

[0014] Optionally, it also includes: after forming the second opening, etching the first stop layer with the first mask layer as a mask until the surface of the initial first dielectric layer is exposed to form a second mask layer; etching the initial first dielectric layer with the second mask layer as a mask until the gate structure and the surface of the source-drain doped layer of the first region and the second region are exposed to form a first dielectric layer, and the first dielectric layer on the first region and the second region respectively has a plurality of first interconnect openings and a plurality of second interconnect openings, the first interconnect openings expose at least a portion of the surface of the source-drain doped layer of the first region and the second region, and the second interconnect openings expose at least a portion of the surface of the gate structure of the first region and the second region.

[0015] Optionally, the method further includes: after forming the first dielectric layer, removing the second mask layer.

[0016] Optionally, the method for removing the second mask layer includes: forming a first protective film on the sidewalls and bottom surfaces of the first interconnect opening and the second interconnect opening; and after forming the first protective film, removing the second mask layer using a first etching process.

[0017] Optionally, the method for forming the first protective film includes: forming an initial first protective film on the surface of the first dielectric layer, the gate structure, the source and drain doping layer and the second mask layer; after forming the initial first protective film, forming a barrier layer in the first interconnect opening and the second interconnect opening, the top surface of the barrier layer is lower than or flush with the bottom surface of the second mask layer; after forming the barrier layer, removing the initial first protective film on the surface of the second mask layer.

[0018] Optionally, the method further includes: while removing the second mask layer, using the first etching process to remove the barrier layer.

[0019] Optionally, the material of the second mask layer includes titanium nitride, the material of the barrier layer includes a carbon-containing organic material, the first etching process is a wet etching process, and the etching solution used in the first etching process includes sulfuric acid.

[0020] Optionally, the method further includes: after removing the second mask layer, etching back the first protection film until the source / drain doping layer and the top surface of the gate structure are exposed.

[0021] Optionally, the method further includes: forming a first interconnect structure in the first interconnect opening; and forming a second interconnect structure in second interconnect openings in the first region and the second region.

[0022] Optionally, the substrate also includes a third region, the plurality of source-drain doped layers are also located in the substrate of the third region, the gate structure is also located between adjacent source-drain doped layers in the third region, the first dielectric layer is also located on the substrate and gate structure surfaces of the third region, and at least one connected first interconnect opening and second interconnect opening are in the first dielectric layer of the third region.

[0023] Optionally, the substrate includes a base and a plurality of fins located on the base in the first region and the second region and separated from each other, and the gate structure spans across the fins.

[0024] Optionally, the initial first dielectric layer includes a lower initial first dielectric layer located between the gate structures, and an upper initial first dielectric layer located on surfaces of the gate structure and the lower initial first dielectric layer.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure of the technical solution of the present invention, the first opening is used to subsequently form an interconnection structure electrically interconnected with the source and drain doping layers, and the second opening is used to subsequently form an interconnection structure electrically interconnected with the gate structure. On the one hand, since the surface of the initial first dielectric layer is relatively flat, and the first mask layer is formed on the surface of the initial first dielectric layer, the pattern accuracy of the first mask layer and the pattern accuracy of the second opening can be improved, thereby reducing the risk of short circuits and open circuits between the subsequently formed interconnection structures and between the interconnection structures and the devices, so as to improve the performance and reliability of the semiconductor structure. On the other hand, since the first mask layer has a plurality of first openings, and after the first mask layer is formed, a plurality of second openings are formed in the first mask layer, the first mask layer can be used as a transfer mask layer for transferring the patterns of the first openings and the second openings, so that the initial first dielectric layer can be subsequently etched only once, and the patterns of the first openings and the second openings are transferred to the initial first dielectric layer together, thereby reducing the influence of the different first opening density on the first region and the first opening density on the second region on the accuracy of the second opening pattern transferred to the initial first dielectric layer, and not only improving the pattern accuracy of the first opening and the second opening transferred to the initial first dielectric layer, so as to reduce the short circuit risk between the interconnection structure electrically interconnected with the gate structure and the interconnection structure electrically interconnected with the source and drain doping layer, and the open circuit risk between the gate structure and the interconnection structure electrically interconnected with the gate structure, so as to improve the performance and reliability of the semiconductor structure; and reducing the number of etching times when forming the interconnection opening (the pattern transferred to the initial first dielectric layer through the first opening) that exposes the surface of the source and drain doping layer, thereby reducing the damage to the surface of the source and drain doping layer during multiple etching processes, so as to improve the performance of the semiconductor structure.

[0027] Furthermore, since the thickness of the first mask layer is less than the first spacing, the depth of the first opening can be reduced, thereby reducing the height difference of the surface of the second opening patterning layer in the first area and the second area during the formation of the second opening, which is more conducive to improving the pattern accuracy of the second opening in the first area and the second area. Since the pattern accuracy of the second opening in the first area and the second area is improved, the pattern accuracy of the interconnection structure electrically interconnected with the gate structure can be improved, thereby reducing the risk of short circuit between the interconnection structure electrically interconnected with the gate structure and the interconnection structure electrically interconnected with the source and drain doping layer, and also reducing the risk of open circuit between the gate structure and the interconnection structure electrically interconnected with the gate structure, thereby improving the performance and reliability of the semiconductor structure.

[0028] Furthermore, since the first sidewalls are formed on the sidewalls of the first openings before the second opening patterning layer is formed, on the one hand, the first sidewalls can better ensure that the first mask layer between the first opening and the second opening is not etched through, thereby helping to reduce the risk of short circuits between the interconnection structure electrically interconnected with the gate structure and the interconnection structure electrically interconnected with the source and drain doping layer, so as to improve the performance and reliability of the semiconductor structure. On the other hand, in the process of forming the second opening, the pattern of the second opening can be self-aligned through the first sidewalls, which is conducive to improving the pattern accuracy of the second opening, thereby improving the performance and reliability of the semiconductor structure.

[0029] Furthermore, since the first stop layer is formed, on the one hand, it is beneficial to reduce the damage to the initial first dielectric layer caused by the etching process in the process of forming the first mask layer, thereby facilitating the improvement of the graphic accuracy of the first opening and the second opening transferred to the initial first dielectric layer, so as to improve the performance and reliability of the semiconductor structure; on the other hand, in the process of transferring the graphic of the first mask layer to the initial first dielectric layer, a hard mask layer can be formed through the first stop layer, thereby facilitating the improvement of the graphic accuracy of the first opening and the second opening transferred to the initial first dielectric layer, so as to improve the performance and reliability of the semiconductor structure.

[0030] Furthermore, since a first protective film is formed on the sidewalls and bottom surfaces of the first interconnect opening and the second interconnect opening before removing the second mask layer, the first protective film can reduce damage to the surface of the source and drain doping layer and the surface of the gate structure caused by the etching process for removing the second mask layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 to Figure 2 It is a structural schematic diagram of each step of the formation process of a semiconductor structure;

[0032] Figures 3 to 14 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, since the formed interconnect structures are prone to short circuits, or the formed interconnect structures and devices are prone to open circuits, the performance and reliability of semiconductor devices are affected.

[0034] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0035] Figure 1 to Figure 2 It is a structural schematic diagram of the various steps in the formation process of a semiconductor structure.

[0036] Please refer to Figure 1 , providing a substrate, the substrate comprising a first region I and a second region II, the substrate further comprising a base 100 and a plurality of mutually discrete fins (not shown) located on the surface of the base 100, and a plurality of source-drain doped layers 101 are provided between adjacent fins; forming a plurality of gate structures 110 spanning the fins; forming a first dielectric layer 120 on the surface of the substrate and the gate structure 110; forming a first opening 121 in the first dielectric layer 120 between some adjacent gate structures 110, the first opening 121 providing space and limitation for a first interconnection structure (not shown) electrically interconnected with the source-drain doped layer 101 formed subsequently, the first opening 121 exposing the surface of the source-drain doped layer 101, and the spacing between the first openings 121 in the first region I is greater than the spacing between the first openings 121 in the second region II.

[0037] Please refer to Figure 2 , forming a second dielectric layer 130 in the first opening 121 of the first region I and the second region II and on the surface of the first dielectric layer 120; forming a second opening patterned layer (not shown) on the surface of the second dielectric layer 130; using the second opening patterned layer as a mask, etching the second dielectric layer 130 and the first dielectric layer 120 until the top surface of the gate structure 110 of the first region I and the second region II is exposed to form a second opening 131, the second opening 131 provides space and positioning for the subsequent formation of a second interconnection structure (not shown) electrically interconnected with the gate structure 110; after forming the second opening 131, removing the second opening patterned layer and the second dielectric layer 130.

[0038] However, in the above scheme, since the spacing between the first openings 121 in the first region I is greater than the spacing between the first openings 121 in the second region II, the thickness of the second dielectric layer 130 formed after filling the first openings 121 in the first region I is less than the thickness in the second region II. Therefore, when etching the second dielectric layer 130 to form the second openings 131, in order to make the second openings 131 reach the surface of the gate structure 110 in the second region II, the etching process is likely to cause over-etching of the second openings 131 in the first region I, that is, the line width of the second openings 131 is likely to increase, so that the first dielectric layer 120 between the first openings 121 and the second openings 131 is likely to be etched through, resulting in a short circuit between the first interconnection structure and the second interconnection structure in the first region I; and in order to reduce the risk of a short circuit between the first interconnection structure and the second interconnection structure in the first region I, it is likely to cause the second openings 131 in the second region II to fail to expose the surface of the gate structure 110 in the second region II, resulting in a disconnection between the second interconnection structure in the second region II and the gate structure 110. As a result, the performance and reliability of the semiconductor device are affected, causing the performance and reliability of the semiconductor device to deteriorate.

[0039] In order to solve the technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, by forming a first mask layer on the surface of the initial first dielectric layer, the first mask layer having a plurality of first openings located on the source and drain doping layers, and a plurality of second openings located on the gate structure, thereby improving the performance and reliability of the semiconductor device.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 14 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0042] Please refer to Figure 3 , providing a substrate 200, the substrate 200 including a first region I, a second region II and a third region III; forming a plurality of source-drain doped layers 201 in the substrate of the first region I, the second region II and the third region III, respectively, a plurality of gate structures 210 located between adjacent source-drain doped layers 201 in the first region I, the second region II and the third region III, and an initial first dielectric layer 220 located on the surfaces of the substrate 200 and the gate structures 210 in the first region I, the second region II and the third region III.

[0043] In other embodiments, the substrate does not include the third region.

[0044] In this embodiment, the substrate 200 includes a base (not shown) and a plurality of fins (not shown) located on the base in the first region I and the second region II and separated from each other, and the gate structure 210 spans across the fins.

[0045] In other embodiments, the substrate does not include fins.

[0046] The material of the substrate is semiconductor material.

[0047] In this embodiment, the material of the substrate is silicon.

[0048] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0049] In this embodiment, the initial first dielectric layer 220 includes: a lower initial first dielectric layer 221 located between the gate structures 210 , and an upper initial first dielectric layer 222 located on the surfaces of the gate structures 210 and the lower initial first dielectric layer 221 .

[0050] In this embodiment, the material of the initial first dielectric layer 220 includes silicon oxide.

[0051] In this embodiment, the method for forming the source-drain doped layer 201 includes: forming a plurality of dummy gate structures (not shown) on the surface of the substrate 200 and gate sidewalls 211 located on the sidewalls of the dummy gate structure, the dummy gate structure spanning the fin, the gate sidewalls 221 being used to provide space for forming the gate structure 210, and being used to define the position for forming the source-drain doped layer 201; forming a plurality of source-drain doped layers 201 in the substrate 200 between adjacent gate sidewalls 211 in the first region I, the second region II and the third region III.

[0052] In this embodiment, the process of forming the source-drain doping layer 201 includes an ion doping process.

[0053] In other embodiments, the method for forming the source-drain doped layer further includes: after forming the gate sidewalls, forming a plurality of source-drain openings, the source-drain openings being located in the substrate between adjacent gate sidewalls in the first region, the second region, and the third region; and forming the source-drain doped layer in the source-drain openings. The process for forming the source-drain doped layer includes a deposition process or an epitaxial growth process.

[0054] In this embodiment, before forming the lower initial first dielectric layer 221 , a second protection film 231 is formed on the surface of the source / drain doping layer 201 and the sidewall surface of the gate structure 210 .

[0055] The material of the second protection film 231 includes silicon nitride.

[0056] Specifically, the method for forming the lower initial first dielectric layer 221 and the second protective film 231 includes: after forming the source-drain doping layer 201, forming an initial second protective film (not shown) on the surface of the source-drain doping layer 201 and the surface of the pseudo gate structure; forming a lower initial first dielectric material layer (not shown) on the surface of the second protective film; etching back the lower initial first dielectric material layer until the surface of the initial second protective film is exposed to form the lower initial first dielectric layer 221; after forming the lower initial first dielectric layer 221, continuing to etch back the initial second protective film until the surface of the pseudo gate structure is exposed to form the second protective film 231.

[0057] The second protection film 231 is used to protect the surface of the source-drain doped layer 201 during subsequent deposition, etching and other processes.

[0058] In other embodiments, the second protective film is not formed.

[0059] In this embodiment, the process of forming the lower initial first dielectric material layer includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0060] In this embodiment, the process of planarizing the lower initial first dielectric material layer includes a chemical mechanical polishing process.

[0061] In this embodiment, the method of forming the gate structure 210 includes: after forming the second protection film 231 , removing the dummy gate structure to form a gate opening (not shown) between adjacent gate spacers 211 ; and forming the gate structure 210 in the gate opening.

[0062] In this embodiment, the gate structure 210 includes: a gate dielectric layer (not shown) located on the surface of the fin; a work function layer (not shown) located on the surface of the gate dielectric layer; and a gate electrode layer (not shown) located on the surface of the work function layer.

[0063] In this embodiment, after the gate structure 210 is formed, a third protection film 232 is formed on the surface of the gate structure 210 and the surface of the underlying initial first dielectric layer 221 .

[0064] The material of the third protection film 232 includes silicon nitride.

[0065] The third protection film 232 is used to protect the surface of the gate structure during subsequent deposition, etching and other processes.

[0066] In other embodiments, the third protective film is not formed.

[0067] In this embodiment, after the third protection film 232 is formed, an upper initial first dielectric layer 222 is formed on the surface of the third protection film 232 .

[0068] The method for forming the upper initial first dielectric layer 222 includes: forming an upper initial first dielectric material layer (not shown) on the surface of the third protection film 232 ; and planarizing the upper initial first dielectric material layer to form the upper initial first dielectric layer 222 .

[0069] In this embodiment, the process of forming the upper initial first dielectric material layer includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0070] In this embodiment, the process of planarizing the upper initial first dielectric material layer includes a chemical mechanical polishing process.

[0071] In this embodiment, there is a first distance K1 between the top surface of the source / drain doped layer 201 and the top surface of the initial first dielectric layer 220 .

[0072] Subsequently, a first mask layer is formed on the surface of the initial first dielectric layer 220. The first mask layer on the first region I and the first mask layer on the second region II respectively have a plurality of first openings. The first openings are located on the source-drain doped layer 201, and the first opening density on the first region I is different from the first opening density on the second region II. For the specific process of forming the first mask layer, please refer to Figures 4 to 5 .

[0073] Please refer to Figure 4 , forming a first mask material layer 250 on the surface of the initial first dielectric layer 220; forming a first opening patterned layer 251 on the surface of the first mask material layer 250, the first opening patterned layer 251 exposing the surface of the first mask material layer 250 on at least part of the source-drain doped layer 201 of the first region I and the second region II.

[0074] The process of forming the first mask material layer 250 includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0075] In this embodiment, the process of forming the first mask material layer 250 is a chemical vapor deposition process.

[0076] In this embodiment, before forming the first mask material layer 250 , a first stop layer 240 is formed on the surface of the initial first dielectric layer 220 .

[0077] Since the first stop layer 240 is formed, on the one hand, it is beneficial to reduce the damage of the initial first dielectric layer 220 caused by the etching process in the subsequent formation of the first mask layer and the second opening, thereby facilitating the improvement of the pattern accuracy of the first opening and the second opening transferred to the initial first dielectric layer 220, so as to improve the performance and reliability of the semiconductor structure; on the other hand, in the process of transferring the pattern of the first mask layer to the initial first dielectric layer 220, a hard mask layer (i.e., the second mask layer formed subsequently) can be formed through the first stop layer 240, thereby facilitating the improvement of the pattern accuracy of the first opening and the second opening transferred to the initial first dielectric layer 220, so as to improve the performance and reliability of the semiconductor structure.

[0078] The process of forming the first stop layer 240 includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0079] In this embodiment, the process of forming the first stop layer 240 is a chemical vapor deposition process.

[0080] The material of the first stop layer 240 is different from that of the first mask layer, so that the first stop layer 240 can function as a stop layer during the etching process of forming the first mask layer.

[0081] The first stop layer 240 provides material for the subsequent formation of the second mask layer. The material of the first stop layer 240 is different from the material of the initial first dielectric layer 220. Therefore, when the initial first dielectric layer 220 is subsequently etched using the second mask layer as a mask, the etchant used in the etching process can have a higher etching selectivity ratio for the initial first dielectric layer 220 and the second mask layer, thereby facilitating improving the graphic accuracy of the first opening and the second opening transferred to the initial first dielectric layer 220.

[0082] In this embodiment, the material of the first stop layer 240 includes titanium nitride, and correspondingly, the material of the second mask layer includes titanium nitride.

[0083] In this embodiment, the thickness K3 of the first stop layer 240 ranges from 100 angstroms to 700 angstroms.

[0084] If the thickness K3 of the first stop layer 240 is too large, the first mask layer is easily consumed before the second mask layer is formed, which is not conducive to transferring the pattern of the first mask layer to the second mask layer, resulting in poor pattern accuracy of the semiconductor structure; if the thickness K3 of the first stop layer 240 is too small, the second mask layer is easily consumed before the pattern of the second mask layer is completely transferred to the initial first dielectric layer 220, which is not conducive to transferring the pattern of the second mask layer to the initial first dielectric layer 220, resulting in poor pattern accuracy of the semiconductor structure. Therefore, a suitable range of the thickness K3 of the first stop layer 240 is selected, that is, when the thickness K3 of the first stop layer 240 ranges from 100 angstroms to 700 angstroms, it is conducive to transferring the pattern of the first mask layer to the second mask layer, and at the same time, it is conducive to transferring the pattern of the second mask layer to the initial first dielectric layer 220.

[0085] Please refer to Figure 5 , using the first opening patterning layer 251 as a mask, etching the first mask material layer 250 until the first stop layer 240 is exposed to form a first mask layer 252 .

[0086] In this embodiment, a plurality of first openings 261 are respectively provided in the first mask layer 252 on the first region I, the second region II and the third region III. The first openings 261 are located on the source-drain doped layer 201, and the density of the first openings 261 on the first region I is different from the density of the first openings 261 on the second region II.

[0087] It should be noted that the density of the first openings 261 refers to the ratio of the projected area of ​​all the first openings 261 per unit area on the surface of the substrate 200 to the unit area in a direction perpendicular to the surface of the substrate 200 .

[0088] In this embodiment, the thickness K2 of the first mask layer 252 is smaller than the first distance K1.

[0089] Subsequently, a second opening patterning layer is formed on the surface of the first mask layer 252, and the first mask layer 252 is etched using the second opening patterning layer as a mask to form a second opening. Since the thickness K2 of the first mask layer 252 is less than the first spacing K1, the depth of the first opening 261 can be reduced, so that in the process of forming the second opening, the height difference of the surface of the second opening patterning layer in the first area I, the second area II and the third area III is reduced, which is more conducive to improving the pattern accuracy of the second opening in the first area I, the second area II and the third area III. Since the graphic accuracy of the second openings in the first region I, the second region II and the third region III is improved, the graphic accuracy of the interconnection structure electrically interconnected with the gate structure 210 (that is, in the present embodiment, the second interconnection structure formed subsequently) can be improved, thereby reducing the risk of short circuit between the interconnection structure electrically interconnected with the gate structure 210 and the interconnection structure electrically interconnected with the source-drain doping layer 201 (that is, in the present embodiment, the first interconnection structure formed subsequently), and also reducing the risk of open circuit between the gate structure 210 and the interconnection structure electrically interconnected with the gate structure 210, thereby improving the performance and reliability of the semiconductor structure.

[0090] In this embodiment, the thickness K2 of the first mask layer 252 ranges from 100 angstroms to 700 angstroms.

[0091] If the thickness K2 of the first mask layer 252 is too large, it is not conducive to reducing the height difference of the surface of the second opening patterning layer in the first area I, the second area II and the third area III, and thus, it is not conducive to improving the pattern accuracy of the second opening in the first area I, the second area II and the third area III. If the thickness K2 of the first mask layer 252 is too small, it is easy to consume the first mask layer 252 before forming the second mask layer, which is not conducive to transferring the pattern of the first mask layer 252 to the second mask layer, resulting in poor pattern accuracy of the semiconductor structure. Therefore, when a suitable thickness K2 of the first mask layer 252 is selected, that is, when the thickness K2 of the first mask layer 252 ranges from 100 angstroms to 700 angstroms, it is conducive to reducing the height difference of the surface of the second opening patterning layer in the first area I, the second area II and the third area III, so as to improve the pattern accuracy of the second opening in the first area I, the second area II and the third area III, and at the same time, it is also conducive to transferring the pattern of the first mask layer 252 to the second mask layer, so as to improve the pattern accuracy of the semiconductor structure.

[0092] In this embodiment, the process of etching the first mask material layer 250 includes a dry etching process or a wet etching process.

[0093] In other embodiments, the first stop layer is not formed, and therefore, the first mask material layer is etched using the first opening patterning layer as a mask until the initial first dielectric layer is exposed to form a first mask layer.

[0094] In this embodiment, the material of the first mask layer 252 includes silicon oxide.

[0095] In this embodiment, the first opening patterning layer 251 is removed after the first mask layer 252 is formed.

[0096] Subsequently, a plurality of second openings are formed in the first mask layer 252 on part or all of the gate structure 210 in the first region I, the second region II and the third region III. At least one first opening 261 in the third region III is connected to the second opening.

[0097] On the one hand, since the surface of the initial first dielectric layer 220 is relatively flat and the first mask layer 252 is formed on the initial first dielectric layer 220, the graphic accuracy of the first mask layer 252 and the graphic accuracy of the second opening can be improved, thereby reducing the risks of short circuits and open circuits between subsequently formed interconnect structures and between interconnect structures and devices, thereby improving the performance and reliability of the semiconductor structure.

[0098] On the other hand, since the first mask layer 252 has a plurality of first openings 261, and after the first mask layer 252 is formed, a plurality of second openings are formed in the first mask layer 252, the first mask layer 252 can serve as a transit mask layer for transferring the patterns of the first openings 261 and the second openings, so that the initial first dielectric layer 220 can be subsequently etched only once to transfer the patterns of the first openings 261 and the second openings to the initial first dielectric layer 220 together.

[0099] Since the first mask layer 252 can be used as a transfer mask layer for transferring the first opening 261 and the second opening pattern, the first opening 261 density on the first region I, the first opening 261 density on the second region II, and the first opening 261 density on the third region III are different, which not only reduces the influence on the second opening pattern accuracy transferred to the initial first dielectric layer 220, but also improves the pattern accuracy of the first opening 261 and the second opening transferred to the initial first dielectric layer 220, so as to reduce the short circuit risk between the interconnection structure electrically interconnected with the gate structure 210 and the interconnection structure electrically interconnected with the source-drain doping layer 201, and the short circuit risk between the gate structure 210 and the interconnection structure electrically interconnected with the gate structure 210, so as to improve the performance and reliability of the semiconductor structure. In addition, the number of etching times when forming the interconnection opening (the pattern transferred to the initial first dielectric layer 220 through the first opening 261) that exposes the surface of the source-drain doping layer 201 is reduced, so as to reduce the damage of the etching process to the surface of the source-drain doping layer during multiple etching processes, so as to improve the performance of the semiconductor structure. Meanwhile, for the third region III, over-etching caused by the connected first opening 261 and the second opening, ie, a larger opening, during the pattern transfer process is reduced, thereby improving the performance of the semiconductor structure.

[0100] For details on the process of forming the second opening, please refer to Figure 6 to Figure 7 .

[0101] Please refer to Figure 6 , first spacers 253 are formed on the sidewall surfaces of the first openings 261 in the first region I, the second region II, and the third region III, respectively.

[0102] Since the first sidewalls 253 are formed on the sidewalls of the first openings 261 before the second opening patterning layer is subsequently formed, on the one hand, the first sidewalls 253 can better ensure that the first mask layer 252 between the first opening 261 and the second opening is not etched through, thereby helping to reduce the risk of short circuits between the interconnection structure electrically interconnected with the gate structure 210 and the interconnection structure electrically interconnected with the source-drain doping layer 201, so as to improve the performance and reliability of the semiconductor structure. On the other hand, in the process of forming the second opening, the pattern of the second opening can be self-aligned through the first sidewalls 253, which is conducive to improving the pattern accuracy of the second opening, thereby improving the performance and reliability of the semiconductor structure.

[0103] In this embodiment, the method for forming the first side wall 253 includes: forming a side wall material layer (not shown) on the surface of the first mask layer 252 and the surface of the first stop layer 240; and etching back the side wall material layer until the surface of the first mask layer 252 and the surface of the first stop layer 240 are exposed.

[0104] In other embodiments, since the first stop layer is not formed, the method for forming the first side wall includes: forming a side wall material layer on the surface of the first mask layer and the surface of the initial first dielectric layer; and etching back the side wall material layer until the surface of the first mask layer and the surface of the initial first dielectric layer are exposed.

[0105] In this embodiment, the process of forming the spacer material layer includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0106] In this embodiment, the process of etching back the spacer material layer includes an anisotropic etching process.

[0107] In this embodiment, the material of the first spacer 253 includes silicon nitride.

[0108] In other embodiments, the first sidewall spacer is not formed.

[0109] Please refer to Figure 7 After forming the first sidewall 253, a second opening patterned layer 270 is formed on the surface of the first mask layer 252, the first sidewall 253 and the first stop layer 240, and the second opening patterned layer 270 exposes part or all of the surface of the first mask layer 252 on the gate structure 210 of the first region I, the second region II and the third region III; using the second opening patterned layer 270 as a mask, the first mask layer 252 is etched until the first stop layer 240 is exposed to form a plurality of second openings 262.

[0110] In other embodiments, since the first stop layer is not formed, after the first side wall is formed, a second opening patterned layer is formed on the surface of the first mask layer, the first side wall and the initial first dielectric layer, and the second opening patterned layer exposes part or all of the surface of the first mask layer on the gate structure of the first region, the second region and the third region; using the second opening patterned layer as a mask, the first mask layer is etched until the initial first dielectric layer is exposed to form a plurality of second openings.

[0111] In this embodiment, the method for forming a second opening patterned layer 270 includes: forming a second opening patterned material layer (not shown) on the surfaces of the first mask layer 252, the first side wall 253 and the first stop layer 240; forming an anti-reflection layer (not shown) on the surface of the second opening patterned material layer; forming a second opening photoresist layer (not shown) on the surface of the anti-reflection layer; and etching the second opening patterned material layer using the second opening photoresist layer as a mask until the surface of the first stop layer 240 is exposed.

[0112] In this embodiment, after the second opening patterning layer 270 is formed, the second opening photoresist layer is removed.

[0113] In this embodiment, the anti-reflection layer includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0114] In other embodiments, no anti-reflective layer is formed.

[0115] In this embodiment, the process of forming the second opening patterning material layer includes a spin coating process or a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0116] In this embodiment, the material of the second opening patterning layer 270 includes a carbon-containing organic material.

[0117] In this embodiment, at least one first opening 261 on the third region III is connected to the second opening 262 .

[0118] In this embodiment, the process of etching the first mask layer 252 includes a dry etching process or a wet etching process.

[0119] In this embodiment, after the second opening 262 is formed, the second opening patterning layer 270 is removed.

[0120] The process of removing the second opening patterning layer 270 includes a dry etching process or a wet etching process.

[0121] In this embodiment, the process of removing the second opening patterned layer 270 is a wet etching process.

[0122] Please refer to Figure 8 After forming the second opening 262 , the first stop layer 240 is etched using the first mask layer 252 as a mask until the surface of the initial first dielectric layer 220 is exposed to form a second mask layer 241 .

[0123] In this embodiment, the process of etching the first stop layer 240 includes a dry etching process or a wet etching process.

[0124] In this embodiment, after the second mask layer 241 is formed, the first mask layer 252 is removed.

[0125] Please refer to Fig. 9 , using the second mask 241 as a mask, etching the initial first dielectric layer 220 until the gate structure 210 of the first region I, the second region II and the third region III and the surface of the source-drain doped layer 201 are exposed to form a first dielectric layer 280 .

[0126] The first dielectric layer 280 on the first region I, the second region II and the third region III respectively has a plurality of first interconnect openings 281 and a plurality of second interconnect openings 282, wherein the first interconnect openings 281 expose at least a portion of the surface of the source-drain doped layer 201 of the first region I, the second region II and the third region III, and the second interconnect openings 282 expose at least a portion of the surface of the gate structure 210 of the first region I, the second region II and the third region III.

[0127] In the third region III, since at least one first opening 261 is connected to the second opening 262 , at least one connected first interconnection opening 281 and second interconnection opening 282 is within the first dielectric layer of the third region III.

[0128] In other embodiments, since the first stop layer is not formed, after forming the second opening, the initial first dielectric layer is etched using the first mask layer as a mask until the gate structure of the first and second regions and the surface of the source and drain doping layer are exposed to form a first dielectric layer.

[0129] In this embodiment, the process of etching the initial first dielectric layer 220 includes a dry etching process or a wet etching process.

[0130] In this embodiment, after forming the first dielectric layer 280, the second mask layer 241 is removed. For the specific process of removing the second mask layer 241, please refer to Figures 10 to 12 .

[0131] Please refer to Fig.10 An initial first protective film 290 is formed on the surfaces of the first dielectric layer 280, the gate structure 210, the source-drain doping layer 201 and the second mask layer 241; after the initial first protective film 290 is formed, a barrier layer 291 is formed in the first interconnect opening 281 and the second interconnect opening 282, and the top surface of the barrier layer 291 is lower than or flush with the bottom surface of the second mask layer 241.

[0132] In this embodiment, the initial first protection film 290 provides material for subsequently forming a first protection film.

[0133] The material of the initial first protection film 290 is different from that of the barrier layer 291 .

[0134] In this embodiment, the material of the initial first protection film 290 includes silicon nitride or silicon oxide.

[0135] The process of forming the initial first protection film 290 includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0136] In this embodiment, the process for forming the initial first protective film 290 is an atomic layer deposition process, so that a denser and thinner initial first protective film 290 can be formed, so that a dense and thinner first protective film can be formed later. On the one hand, the dense first protective film is conducive to protecting the sidewalls and bottom surfaces of the first interconnect opening 281 and the second interconnect opening 282 during the process of removing the second mask layer 241, reducing the damage to the sidewalls and bottom surfaces of the first interconnect opening 281 and the second interconnect opening 282 caused by the etching process of removing the second mask layer 241; on the other hand, after removing the second mask layer 241, the thinner first protective film is easy to be removed, reducing the process difficulty of the etching process of removing the first protective film.

[0137] In this embodiment, the material of the barrier layer 291 includes a carbon-containing organic material.

[0138] In this embodiment, the method for forming the barrier layer 291 includes: forming an initial barrier layer (not shown) in the first interconnect opening 281, in the second interconnect opening 282, and on the surface of the second mask layer 241; and etching back the initial barrier layer until the top surface of the initial barrier layer is lower than or flush with the bottom surface of the second mask layer 241.

[0139] The process of etching back the initial barrier layer includes a dry etching process or a wet etching process.

[0140] Please refer to Fig.11After forming the barrier layer 291 , the initial first protection film 290 on the surface of the second mask layer 241 is removed to form a first protection film 292 on the sidewalls and bottom surfaces of the first interconnection opening 281 and the second interconnection opening 282 .

[0141] Because the first protective film 292 is formed on the sidewalls and bottom surfaces of the first interconnect opening 281 and the second interconnect opening 282 before removing the second mask layer 241, the first protective film 292 can reduce the damage to the surface of the source-drain doped layer 201 and the surface of the gate structure 210 caused by the etching process for removing the second mask layer 241, thereby improving the performance of the semiconductor structure.

[0142] In this embodiment, the method for removing the initial first protective film 290 on the surface of the second mask layer 241 includes: using the barrier layer 291 as a mask, etching the initial first protective film 290 until the top surface of the initial first protective film 290 is lower than or flush with the bottom surface of the second mask layer 241 .

[0143] The process of etching the initial first protection film 290 includes a dry etching process or a wet etching process.

[0144] Please refer to Fig.12 After forming the first protection film 292 , the second mask layer 241 is removed by a first etching process.

[0145] In this embodiment, the first etching process is used to remove the blocking layer 291 while removing the second mask layer 241 .

[0146] In other embodiments, after removing the second mask layer, the blocking layer is removed.

[0147] In this embodiment, the first etching process is a wet etching process, and an etching solution used in the first etching process includes sulfuric acid.

[0148] Please refer to Fig.13 After removing the second mask layer 241 , the first protection film 292 is etched back until the source / drain doping layer 201 and the top surface of the gate structure 210 are exposed.

[0149] In this embodiment, the process of etching back the first protection film 292 includes: an anisotropic dry etching process or an anisotropic wet etching process.

[0150] Please refer to Fig.14After etching back the first protective film 292, a first interconnect structure 310 is formed in the first interconnect openings 281 of the first region I, the second region II and the third region III, and a second interconnect structure 320 is formed in the second interconnect openings 282 of the first region I, the second region II and the third region III.

[0151] In this embodiment, in the third region III, since at least one first interconnection opening 281 is connected to the second interconnection opening 282 , the first interconnection structure 310 and the second interconnection structure 320 formed in the connected first interconnection opening 281 and the second interconnection opening 282 are connected.

[0152] In this embodiment, the method for forming the first interconnect structure 310 and the second interconnect structure 320 includes: forming an interconnect structure material layer (not shown) in the first interconnect opening 281, in the second interconnect opening 282, and on the top surface of the first dielectric layer 280; and planarizing the interconnect structure material layer until the top surface of the first dielectric layer 280 is exposed.

[0153] In this embodiment, the process of planarizing the interconnect structure material layer includes a chemical mechanical polishing process.

[0154] In this embodiment, the material of the first interconnect structure 310 includes a conductive material, and the conductive material includes a metal material, such as copper, tungsten or aluminum.

[0155] In this embodiment, the material of the second interconnect structure 320 includes a conductive material, and the conductive material includes a metal material, such as copper, tungsten or aluminum.

[0156] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; Forming a plurality of source-drain doped layers, a plurality of gate structures located between adjacent source-drain doped layers in the first and second regions, and an initial first dielectric layer located on the surface of the substrate and the gate structures in the substrate in the first and second regions respectively; A first mask layer is formed on the surface of the initial first dielectric layer, wherein the first mask layer on the first region and the first mask layer on the second region respectively have a plurality of first openings, wherein the first openings are located on the source-drain doped layer, and the first opening density on the first region is different from the first opening density on the second region, and the first openings are used for subsequently forming an interconnection structure electrically interconnected with the source-drain doped layer; Forming a first sidewall on the sidewall surface of the first opening in the first area and the second area; After forming the first sidewall spacer, a plurality of second openings are formed in the first mask layer in the first region and the second region. The second openings are located on the gate structure and are used for subsequently forming an interconnection structure electrically interconnected with the gate structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second opening includes: after forming the first mask layer, forming a second opening patterned layer on the surface of the first mask layer, the second opening patterned layer exposing the surface of the first mask layer on part or all of the gate structure of the first area and the second area; using the second opening patterned layer as a mask, etching the first mask layer until the initial first dielectric layer is exposed.

3. The method for forming a semiconductor structure according to claim 2, wherein: There is a first distance between the top surface of the source / drain doping layer and the top surface of the initial first dielectric layer, and the thickness of the first mask layer is smaller than the first distance.

4. The method for forming a semiconductor structure according to claim 3, wherein: The thickness of the first mask layer ranges from 100 angstroms to 700 angstroms.

5. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the second opening further includes: before forming the second opening patterning layer, forming first sidewalls on the sidewall surfaces of the first opening in the first region and the second region respectively.

6. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the first sidewall spacer includes: forming a sidewall material layer on the surface of the first mask layer and the surface of the initial first dielectric layer; and etching back the sidewall material layer until the surface of the first mask layer and the surface of the initial first dielectric layer are exposed.

7. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first mask layer also includes: before forming the second opening, forming a first mask material layer on the surface of the initial first dielectric layer; forming a first opening patterned layer on the surface of the first mask material layer, the first opening patterned layer exposing the surface of the first mask material layer on at least part of the source-drain doped layer in the first region and the second region; using the first opening patterned layer as a mask, etching the first mask material layer until the initial first dielectric layer is exposed.

8. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the second opening, the initial first dielectric layer is etched using the first mask layer as a mask until the gate structure and the surface of the source-drain doped layer in the first region and the second region are exposed to form a first dielectric layer, and the first dielectric layer on the first region and the second region respectively has a plurality of first interconnect openings and a plurality of second interconnect openings, the first interconnect openings expose at least a portion of the surface of the source-drain doped layer in the first region and the second region, and the second interconnect openings expose at least a portion of the surface of the gate structure in the first region and the second region.

9. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the first mask layer, a first stop layer is formed on the surface of the initial first dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: After forming the second opening, etching the first stop layer using the first mask layer as a mask until the surface of the initial first dielectric layer is exposed to form a second mask layer; The initial first dielectric layer is etched using the second mask layer as a mask until the gate structure and the surface of the source-drain doped layer in the first region and the second region are exposed to form a first dielectric layer, and the first dielectric layer on the first region and the second region respectively has a plurality of first interconnect openings and a plurality of second interconnect openings, the first interconnect openings expose at least a portion of the surface of the source-drain doped layer in the first region and the second region, and the second interconnect openings expose at least a portion of the surface of the gate structure in the first region and the second region.

11. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: After forming the first dielectric layer, removing the second mask layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for removing the second mask layer includes: forming a first protective film on the sidewalls and bottom surfaces of the first interconnect opening and the second interconnect opening; after forming the first protective film, removing the second mask layer using a first etching process.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the first protective film includes: forming an initial first protective film on the surface of the first dielectric layer, the gate structure, the source-drain doping layer and the second mask layer; after forming the initial first protective film, forming a barrier layer in the first interconnect opening and the second interconnect opening, wherein the top surface of the barrier layer is lower than or flush with the bottom surface of the second mask layer; after forming the barrier layer, removing the initial first protective film on the surface of the second mask layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: The blocking layer is removed by using the first etching process while removing the second mask layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the second mask layer includes titanium nitride, the material of the barrier layer includes a carbon-containing organic material, the first etching process is a wet etching process, and the etching solution used in the first etching process includes sulfuric acid.

16. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: After removing the second mask layer, the first protection film is etched back until the source and drain doping layers and the top surface of the gate structure are exposed.

17. The method for forming a semiconductor structure according to claim 8 or 10, characterized in that: Also includes: A first interconnect structure is formed in the first interconnect opening; and a second interconnect structure is formed in the second interconnect openings of the first region and the second region.

18. The method for forming a semiconductor structure according to claim 17, wherein: The substrate also includes a third region, the plurality of source-drain doped layers are also located in the substrate of the third region, the gate structure is also located between adjacent source-drain doped layers in the third region, the first dielectric layer is also located on the substrate and gate structure surfaces of the third region, and at least one connected first interconnect opening and second interconnect opening are in the first dielectric layer of the third region.

19. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes a base and a plurality of fins located on the base in the first region and the second region and separated from each other, and the gate structure crosses the fins.

20. The method for forming a semiconductor structure according to claim 1, wherein: The initial first dielectric layer includes a lower initial first dielectric layer located between the gate structures, and an upper initial first dielectric layer located on the surface of the gate structure and the lower initial first dielectric layer.

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