Light receiving element and electronic device

Abstract

Embodiments of the present technology include an avalanche photodiode including a substrate including a first side having a first surface and a second side having a second surface opposite to the first surface. The second surface is a light incident surface of the substrate. The avalanche photodiode includes: an anode region, which is disposed in the substrate on the first side of the substrate; an anode electrode, which is connected to the anode region; a cathode region, which is disposed in the substrate on the first side of the substrate; a cathode electrode, which is connected to the cathode region; and an insulating layer, which is disposed in the substrate on the first side of the substrate. The anode electrode or the cathode electrode passes through the insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a light receiving element and an electronic device. Background Art

[0002] As one of the distance measurement schemes for measuring the distance to a measurement object using light, a distance measurement technology called a direct ToF (time-of-flight) scheme is known. In this direct ToF scheme, a light receiving element receives reflected light obtained by reflecting light emitted from a light source on a measurement object, and measures the distance to the object based on the time from when the light is emitted to when the light is received as reflected light (for example, see Patent Document 1).

[0003] [Citation list]

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] JP 2004-319576 A Summary of the invention

[0007] [Technical issues]

[0008] The present disclosure proposes a light receiving element and an electronic device capable of achieving relaxation of an electric field between a cathode contact region and an anode contact region while preventing an area of ​​the light receiving element from being enlarged.

[0009] [Technical solution to the problem]

[0010] An embodiment of the present technology includes a light receiving element including a single photon avalanche diode (SPAD) element formed in a semiconductor layer and arranged for each pixel arranged in an array. The light receiving element includes: a cathode electrode and an anode electrode, which are at least partially formed in a wiring layer adjacent to the semiconductor layer and are configured to apply a reverse bias to the SPAD element; an N-type cathode contact region formed in the semiconductor layer and directly connected to the cathode electrode; a P-type anode contact region formed in the semiconductor layer and directly connected to the anode electrode; and an insulating buried layer located between any one of the cathode contact region and the anode contact region of the semiconductor layer and the surface on the opposite side of the light incident side. The light receiving element includes a surface pinning layer formed in the surface on the opposite side of the light incident side of the semiconductor layer and connected to the ground potential. The light receiving element includes an N-type diffusion layer, which contacts the cathode contact region in the semiconductor layer. A gap between the N-type diffusion layer of the semiconductor layer and the surface on the side opposite to the light incident side is covered with the buried layer.

[0011] An embodiment of the present technology has an electronic device including a light receiving element. The light receiving element includes: a single photon avalanche diode (SPAD) element formed in a semiconductor layer and provided for each pixel arranged in an array; a cathode electrode and an anode electrode, which are at least partially formed in a wiring layer adjacent to the semiconductor layer and are configured to apply a reverse bias to the SPAD element; an N-type cathode contact region formed in the semiconductor layer and directly connected to the cathode electrode; a P-type anode contact region formed in the semiconductor layer and directly connected to the anode electrode; and an insulating buried layer located between any one of the cathode contact region and the anode contact region of the semiconductor layer and the surface on the opposite side of the light incident side. The light receiving element also includes a surface pinning layer formed in the surface on the opposite side of the light incident side of the semiconductor layer and connected to a ground potential. The light receiving element also includes an N-type diffusion layer, which contacts the cathode contact region in the semiconductor layer, and the gap between the N-type diffusion layer of the semiconductor layer and the surface on the opposite side of the light incident side is covered by the buried layer.

[0012] Embodiments of the present technology include an avalanche photodiode including a substrate including a first side having a first surface and a second side having a second surface opposite to the first surface. The second surface is a light incident surface of the substrate. The avalanche photodiode includes: an anode region, which is arranged on the first side of the substrate in the substrate; an anode electrode, which is connected to the anode region; a cathode region, which is arranged on the first side of the substrate in the substrate; a cathode electrode, which is connected to the cathode region; and an insulating layer, which is arranged on the first side of the substrate in the substrate. The anode electrode or the cathode electrode passes through the insulating layer. In a plan view, the cathode electrode is arranged closer to the center of the avalanche photodiode than the anode electrode. In a plan view, the cathode electrode surrounds the center of the avalanche photodiode. In a plan view, the cathode electrode is spaced apart from the center of the avalanche photodiode and surrounds the center of the avalanche photodiode. In a plan view, the cathode electrode is continuous. All sides of the cathode electrode are spaced the same distance from the center of the avalanche photodiode. In a plan view, the cathode electrode includes a plurality of cathode portions spaced apart from each other by an insulating layer. Each cathode portion is spaced the same distance from the center of the avalanche photodiode. In a plan view, the insulating layer extends between the two sides of the cathode electrode. The surface of the insulating layer is coplanar with the first surface of the substrate. The insulating layer extends deeper into the substrate than the anode contact region. The avalanche photodiode includes a doped region extending between two sides of the insulating layer. The avalanche photodiode includes a contact electrode connected to the doped region and connected to a node receiving a potential. The potential may be a ground potential.

[0013] According to an embodiment of the present technology, a light detecting device includes a first substrate including a first side having a first surface and a second side having a second surface opposite to the first surface. The second surface is a light incident surface of the first substrate. The light detecting device includes an avalanche photodiode, which includes: an anode region, which is arranged on the first side of the first substrate in the first substrate; an anode electrode, which is connected to the anode region; a cathode region, which is arranged on the first side of the first substrate in the first substrate; an insulating layer, which is arranged on the first side of the first substrate in the first substrate; and a cathode electrode, which is connected to the cathode region. The cathode electrode or the anode electrode passes through the insulating layer. The light detecting device includes a first wiring layer, which is on the first surface of the first substrate and includes: an anode wiring connected to the anode electrode; a cathode wiring connected to the cathode electrode; and a plurality of first bonding pads. The light detecting device includes a second substrate, which includes a second wiring layer and a circuit for processing a signal output from the avalanche photodiode. The second wiring layer includes a plurality of second bonding pads bonded to the plurality of first bonding pads. The plurality of first bonding pads and the plurality of second bonding pads respectively include bonding pads electrically connected to the anode wiring and bonding pads electrically connected to the cathode wiring. In a plan view, the cathode electrode is arranged closer to the center of the avalanche photodiode than the anode electrode. In a plan view, the cathode electrode surrounds the center of the avalanche photodiode. In a plan view, the cathode electrode is spaced apart from the center of the avalanche photodiode and surrounds the center of the avalanche photodiode.

[0014] An embodiment of the present technology is directed to an electronic device including: a light source that emits modulated light toward an object; and an avalanche photodiode that senses the modulated light reflected from the object.

[0015] The avalanche photodiode includes a substrate including a first side having a first surface and a second side having a second surface opposite to the first surface. The second surface is a light incident surface of the substrate. The avalanche photodiode includes: an anode region, which is arranged in the substrate on the first side of the substrate; an anode electrode, which is connected to the anode region; a cathode region, which is arranged in the substrate on the first side of the substrate; an insulating layer, which is arranged in the substrate on the first side of the substrate; and a cathode electrode, which is connected to the cathode region. The cathode electrode or the anode electrode passes through the insulating layer.

[0016] [Beneficial effects of the present invention]

[0017] The present disclosure can achieve relaxation of the electric field between the cathode contact region and the anode contact region while preventing the area of ​​the light receiving element from being enlarged. Note that the effects described here are not limitative, and may be any effect described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] [Figure 1 ] Figure 1 is a diagram schematically showing ranging through a direct ToF solution applicable to an embodiment of the present disclosure.

[0019] [ Figure 2 ] Figure 2 : is a diagram showing one example of a histogram based on the time when the light receiving chip applicable to the embodiment of the present disclosure receives light.

[0020] [ Figure 3 ] Figure 3 is a block diagram showing a configuration example of a light receiving chip according to an embodiment of the present disclosure.

[0021] [ Figure 4 ] Figure 4 is a cross-sectional view showing a configuration example of a pixel array section according to an embodiment of the present disclosure.

[0022] [ Figure 5 ] Figure 5 It shows that Figure 4 A diagram showing an example of a planar configuration at a depth D1 is shown.

[0023] [ Figure 6 ] Figure 6 It shows that Figure 4 A diagram of another example of a planar configuration at a depth D1 is shown.

[0024] [ Figure 7 ] Figure 7 is a cross-sectional view schematically showing a manufacturing process of a pixel array unit according to an embodiment of the present disclosure.

[0025] [ Figure 8 ] Figure 8 is a cross-sectional view schematically showing a manufacturing process of a pixel array unit according to an embodiment of the present disclosure.

[0026] [ Fig. 9 ] Fig. 9 is a cross-sectional view schematically showing a manufacturing process of a pixel array unit according to an embodiment of the present disclosure.

[0027] [ Fig.10 ] Fig.10 is a cross-sectional view schematically showing a manufacturing process of a pixel array unit according to an embodiment of the present disclosure.

[0028] [ Fig.11 ] Fig.11 is a cross-sectional view schematically showing a manufacturing process of a pixel array unit according to an embodiment of the present disclosure.

[0029] [ Fig.12 ] Fig.12is a cross-sectional view schematically showing a manufacturing process of a pixel array unit according to an embodiment of the present disclosure.

[0030] [ Fig.13 ] Fig.13 is a cross-sectional view showing a configuration example of a pixel array section according to a first modification of the embodiment of the present disclosure.

[0031] [ Fig.14 ] Fig.14 is a cross-sectional view showing a configuration example of a pixel array section according to a second modification of the embodiment of the present disclosure.

[0032] [ Fig.15 ] Fig.15 is a cross-sectional view showing a configuration example of a pixel array section according to a third modification of the embodiment of the present disclosure.

[0033] [ Fig.16 ] Fig.16 is a block diagram showing one example of a schematic configuration of an electronic device.

[0034] [ Fig.17 ] Fig.17 is a block diagram showing one example of a schematic configuration of a vehicle control system.

[0035] [ Fig.18 ] Fig.18 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0036] Now, various embodiments of the present disclosure will be described in detail based on the drawings. Note that in each of the following embodiments, the same parts are represented by the same numerals, and thus redundant descriptions are omitted.

[0037] As one of the distance measurement schemes for measuring the distance to a measurement object using light, a distance measurement technology called a direct ToF (time-of-flight) scheme is known. In this direct ToF scheme, a light receiving element receives reflected light obtained by reflecting light emitted from a light source on a measurement object, and measures the distance to the object based on the time from when the light is emitted to when the light is received as reflected light.

[0038] This distance measurement technology uses a light receiving element including a single photon avalanche diode (SPAD) element. This SPAD element applies a large reverse bias voltage (e.g., about -20V) between the anode and cathode that causes avalanche multiplication, thereby generating avalanche multiplication internally caused by electrons generated in response to the incidence of one photon. Therefore, the incidence of one photon contained in the reflected light can be detected with high sensitivity.

[0039] However, on the back side of the semiconductor layer where the SPAD element is formed, a large reverse bias is applied between the cathode contact region and the anode contact region adjacent to each other. This generates an electric field concentrated between the cathode contact region and the anode contact region, and may cause problems such as poor dark current characteristics.

[0040] On the contrary, as described in the related art, by forming STI (shallow trench isolation) between the cathode contact region and the anode contact region, there is a problem that the area of ​​the light receiving element increases by the amount of such STI.

[0041] It is desirable to realize a light receiving element and an electronic device that can realize electric field relaxation between a cathode contact region and an anode contact region while overcoming the above-mentioned problems and preventing the area of ​​the light receiving element from being enlarged.

[0042] Methods of measuring distance

[0043] The present disclosure relates to a technology for measuring distance using light. Figure 1 and Figure 2 A distance measurement method applicable to the embodiment will be described.

[0044] Figure 1 Schematically shows the distance measurement by the direct ToF scheme applicable to the embodiment of the present disclosure. For this embodiment, the direct ToF scheme is applied as the distance measurement scheme.

[0045] This direct ToF scheme is a scheme in which the light receiving chip 3 receives reflected light L2 after the light L1 emitted from the light source 2 is reflected on the measuring object 100, and performs distance measurement based on the time difference between the time when the light is emitted and the time when the light is received.

[0046] The distance measuring device 1 includes a light source 2 and a light receiving chip 3. For example, the light source 2 is a laser diode, and is driven in a pulsed manner to emit laser light.

[0047] The emitted light L1 from the light source 2 is reflected on the measurement object 100 and received by the photoreception chip 3 as the reflected light L2. The photoreception chip 3 converts the light into an electrical signal through photoelectric conversion and outputs a signal corresponding to the received light.

[0048] Here, the time t0 refers to the time when the light source 2 emits light (emission time), the time t1 refers to the time when the photoreception chip 3 receives the reflected light L2 (light reception time), and the reflected light L2 is the reflection of the emitted light L1 from the light source 2 on the measurement object 100.

[0049] Assuming that the speed of light (2.9979×10 8 [m / sec]) is a constant c, the distance D between the distance measuring device 1 and the measurement object 100 can be calculated using the following expression (1).

[0050] D = (c / 2) × (t1 - t0)...(1)

[0051] More specifically, the distance measuring device 1 classifies the time t from the emission time t0 to the light reception time t of the photoreception chip 3 receiving light based on ranks (bins), and generates a histogram. m (Hereinafter also referred to as "light reception time t m ").

[0052] Figure 2 is a diagram showing an example of a histogram based on the time when the photoreception chip 3 applicable to the embodiment of the present disclosure receives light. In Figure 2 , the horizontal axis represents bins, and the vertical axis represents the frequency of each bin. These bins are such that the light reception time t m is classified every predetermined unit time d.

[0053] Specifically, bin #0 is 0 ≦ t m < d, bin #1 is d ≦ t m < 2×d, bin #2 is 2×d ≦ t m < 3×d,..., and bin #(N - 2) is (N - 2)×d ≦ t m < (N - 1)×d. Assuming that the exposure time of the photoreception chip 3 is the time t ep , then t ep = N×d.

[0054] The distance measuring device 1 counts the number of times of obtaining the light reception time t m based on bins to determine the frequency 300 of each bin and generate a histogram. Here, the photoreception chip 3 also receives light other than the reflected light L2, and the reflected light L2 is the reflection of the emitted light L1 from the light source 2.

[0055] For example, examples of light other than the targeted reflected light L2 include ambient light around the distance measuring device 1. This ambient light is light randomly incident on the light receiving chip 3, and an ambient light component 301 of the ambient light in the histogram is noise on the targeted reflected light L2.

[0056] In contrast, the reflected light L2 as a target is light received corresponding to a specific distance and appears in the histogram as an active light component 302. The bar corresponding to the peak frequency in the active light component 302 is a bar corresponding to the distance D of the measuring object 100.

[0057] The distance measuring device 1 obtains the representative time of the bar (for example, the center time of the bar) as the above t1, and can therefore calculate the distance D to the measuring object 100 according to the above expression (1). In this way, using a plurality of light reception results, it is possible to perform distance measurement suitable for random noise.

[0058] Structure of the optical receiver chip

[0059] Next, we will refer to Figure 3 The configuration of the light receiving chip 3 according to the embodiment is described. Figure 3 1 is a block diagram showing a configuration example of the light receiving chip 3 according to an embodiment of the present disclosure. Figure 3 As shown, the light receiving chip 3 according to the embodiment includes a pixel array section 11 and a bias applying section 12. The pixel array section 11 is an example of a light receiving element or a light detecting device.

[0060] The pixel array section 11 has a light receiving surface for receiving light emitted by, for example, an on-chip lens 35 (see FIG. Figure 4 ) and other optical systems converge the reflected light L2 (see Figure 4 ), a plurality of pixels 21 of the pixel array section 11 are arranged in an array. The configuration of such a pixel array section 11 will be described below.

[0061] For example, Figure 3 As shown on the right side of FIG. 2 , the pixel 21 includes a SPAD element (or avalanche photodiode) 22 , a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) 23 , and a CMOS inverter 24 .

[0062] By applying a large negative voltage V between the anode and cathode BD (eg, approximately -20 V), the SPAD element 22 can form an avalanche multiplication region and multiply the electron avalanche generated when one photon is incident.

[0063] When the voltage generated by the avalanche multiplication of electrons in the SPAD element 22 reaches the negative voltage VBD , the P-type MOSFET 23 releases the electrons multiplied by the SPAD element 22, and is quenched to return to its initial voltage.

[0064] The CMOS inverter 24 shapes the voltage generated by the electrons multiplied by the SPAD element 22, thereby outputting a light receiving signal (APD OUT) in which a pulse waveform appears assuming the arrival time of one photon as an initial point.

[0065] The bias applying section 12 applies a reverse bias to each pixel 21 provided in the pixel array section 11 .

[0066] From the light receiving chip 3 thus constructed, each pixel 21 outputs a light receiving signal, and the light receiving signal is provided to a subsequent operation processing section (not shown). For example, such an operation processing section performs operation processing based on the time when a pulse indicating the arrival time of one photon is generated in each light receiving signal to determine the distance D to the measuring object 100, and determines the distance D for each pixel 21.

[0067] Based on the determined distance D, a distance image is generated in which the distances D to the measuring object 100 detected by the respective pixels 21 are arranged in a planar manner.

[0068] Structure of pixel array section

[0069] Next, we will refer to Figures 4 to 6 The configuration of the pixel array section 11 according to the embodiment will be described. Figure 4 is a cross-sectional view showing a configuration example of the pixel array section 11 according to an embodiment of the present disclosure.

[0070] like Figure 4 As shown, the pixel array unit 11 according to the embodiment includes a semiconductor layer (or substrate) 31, a sensor side wiring layer 32, a logic side wiring layer 33, a planarization layer 34, and an on-chip lens 35. Although not explicitly shown, a color filter (e.g., a red, green, or blue filter) may be placed between the planarization layer 34 and the on-chip lens 35 to achieve color imaging. The sensor side wiring layer 32 is an example of a wiring layer.

[0071] The on-chip lens 35 , the planarization layer 34 , the semiconductor layer 31 , the sensor-side wiring layer 32 , and the logic-side wiring layer 33 are stacked in order from the side where the reflected light L2 is incident, thereby constituting the pixel array section 11 .

[0072] Furthermore, a logic-side substrate (not shown) is stacked on the logic-side wiring layer 33. This logic-side substrate has, for example, Figure 3The bias applying section 12, the P-type MOSFET 23 and the CMOS inverter 24 are shown. The logic-side substrate may include a circuit for processing a signal from the pixel array section 11 (eg, a signal processing circuit and / or a logic circuit).

[0073] For example, the sensor side wiring layer 32 is formed on the semiconductor layer 31, and the logic side wiring layer 33 is formed on the logic circuit board. Figure 4 The pixel array unit 11 is manufactured by a manufacturing method using a surface (shown by a dotted line) bonded to the surface.

[0074] For example, a technique for bonding the sensor-side wiring layer 32 and the logic-side wiring layer 33 can include so-called “Cu-Cu bonding” in which Cu pads are exposed at two bonding interfaces respectively and conductivity is also ensured by directly bonding two such Cu pads.

[0075] The semiconductor layer 31 is a layer obtained by thinly grinding a semiconductor substrate such as single crystal silicon, for example, in which the P-type or N-type impurity concentration of the semiconductor layer 31 is controlled, and the SPAD element 22 is formed for each pixel 21 .

[0076] Figure 4 The upper surface of the semiconductor layer 31 in FIG. 1 is regarded as an incident surface 31 a to which the reflected light L2 is incident, and the sensor-side wiring layer 32 is stacked on an opposite surface 31 b which is the opposite side of the incident surface 31 a .

[0077] The sensor-side wiring layer 32 and the logic-side wiring layer 33 have wiring for supplying a voltage applied to the SPAD element 22 , wiring for taking out electrons generated by the SPAD element 22 from the semiconductor layer 31 , and other wirings.

[0078] The SPAD element 22 is configured with a P well 41, a P type diffusion layer 42, an N type diffusion layer 43, a cathode contact region (or cathode region) 44, a hole accumulation layer 45, a pinning layer (or doping region) 46, and an anode contact region (or anode region) 47 formed in the semiconductor layer 31. Figure 4-Figure 6 Various shapes of the cathode region 44 and the anode region 47 are shown, but it should be understood that other configurations are possible. For example, the anode region 47 and / or the cathode region 44 may be regions that appear only once in the cross-sectional view. In the SPAD element 22, the avalanche multiplication region is composed of a depletion layer formed in the junction region between the P-type diffusion layer 42 and the N-type diffusion layer 43.

[0079] Such an avalanche multiplication region is a high electric field region formed in the boundary surface between the P-type diffusion layer 42 and the N-type diffusion layer 43 by applying a large negative voltage to the N-type diffusion layer 43 , and multiplies electrons generated when one photon is incident on the SPAD element 22 .

[0080] The P well 41 is formed by controlling the impurity concentration of the semiconductor layer 31 to be P type, and forms an electric field for transferring electrons generated by photoelectric conversion in the SPAD element 22 to the avalanche multiplication region. Note that the impurity concentration of the semiconductor layer 31 may be controlled to be N type so that an N well is formed instead of the P well 41.

[0081] The P-type diffusion layer 42 is formed near the opposite surface 31b of the semiconductor layer 31 and on the incident surface 31a side relative to the N-type diffusion layer 43 ( Figure 4 A high-concentration P-type diffusion layer (P+) is formed on the upper side of the SPAD element 22, and the P-type diffusion layer 42 is formed on almost the entire SPAD element 22.

[0082] The N-type diffusion layer 43 is formed near the opposite surface 31b of the semiconductor layer 31 and on the opposite surface 31b side relative to the P-type diffusion layer 42 ( Figure 4 An N-type diffusion layer (N) is formed on the lower side of the SPAD element 22, and the N-type diffusion layer 43 is formed on almost the entire SPAD element 22.

[0083] The cathode contact region 44 is located on the opposite surface 31b side of the N-type diffusion layer 43 ( Figure 4 Such a cathode contact region 44 is directly connected to a cathode electrode 61 for supplying a voltage to form an avalanche multiplication region in the N-type diffusion layer 43.

[0084] The hole accumulation layer 45 is a P-type diffusion layer (P) formed to surround the side surface of the P well 41 and the surface on the light incident side thereof, and accumulates holes. The hole accumulation layer 45 is electrically connected to the anode of the SPAD element 22 and has the ability to adjust the bias voltage.

[0085] This increases the hole concentration of the hole accumulation layer 45, thereby being able to strengthen the pinning including the pinning layer 46. Therefore, this embodiment can reduce the occurrence of dark current.

[0086] The pinning layer 46 is a high-concentration P-type diffusion layer (P+) formed on the surface outside the hole accumulation layer 45 (the side in contact with the incident surface 31a of the semiconductor layer 31 and the inter-pixel separation portion 51), and is similar to the hole accumulation layer 45, for example, reducing the occurrence of dark current.

[0087] The anode contact region 47 is a high concentration P-type diffusion layer (P+) formed in such a manner as to contact the pinning layer 46 near the opposite surface 31b of the semiconductor layer 31. Such an anode contact region 47 is directly connected to an anode electrode 62 for supplying a voltage to form an avalanche multiplication region in the P-type diffusion layer 42 via the pinning layer 46, the hole accumulation layer 45, and the P well 41.

[0088] Here, in the embodiment, an insulating buried layer (or insulating layer) 48 is provided between any one of the cathode contact region 44 and the anode contact region 47 of the semiconductor layer 31 and the opposite surface 31b. Figure 4 In the example of FIG. 4 , the buried layer 48 is disposed between the cathode contact region 44 and the opposite surface 31 b of the semiconductor layer 31. In a plan view, the cathode electrode 61 is disposed closer to the center of the avalanche photodiode 22 than the anode electrode 62. The center of the avalanche photodiode 22 may coincide with the optical axis of the on-chip lens 35. Figure 4 As shown, the surface of the insulating layer 48 is coplanar with the first surface of the substrate 31. The insulating layer 48 may extend deeper into the substrate 31 than the anode contact region 47. The cathode electrode 61 or the anode electrode 62 may pass through the insulating layer 48. Figure 4 In the example of , the cathode electrode 61 passes through the insulating layer 48. However, it should be understood that the roles of certain elements of the avalanche photodiode 22 can be reversed, which may result in a change in design. For example, those skilled in the art will understand that certain n-type regions can be exchanged for p-type regions, and certain p-type regions can be exchanged for n-type regions. In this case, the anode electrode 62 can pass through the insulating layer 48.

[0089] For example, the buried layer 48 is configured with an insulator such as silicon oxide (SiO 2 ). The cathode electrode 61 formed in the sensor-side wiring layer 32 passes through such a buried layer 48 , and is directly connected to the cathode contact region 44 .

[0090] By providing the buried layer 48 in this manner, the gap between the anode contact region 47 and the cathode contact region 44 to which a large reverse bias is applied can be insulated and separated in a manner of being spaced apart in the horizontal direction and the vertical direction.

[0091] That is, when the distance between cathode contact region 44 and anode contact region 47 is maintained in the horizontal direction, cathode contact region 44 and anode contact region 47 can be spaced apart by a certain distance at which relaxation of the electric field between cathode contact region 44 and anode contact region 47 can be fully achieved.

[0092] Therefore, this embodiment can achieve relaxation of the electric field between the cathode contact region 44 and the anode contact region 47 while preventing the area of ​​the pixel array section 11 from being enlarged.

[0093] The other parts in the pixel array section 11 are described below. The surface pinning layer 49 is a high-concentration P-type diffusion layer (P+) formed in a place other than the anode contact region 47, the buried layer 48, and the inter-pixel separation portion 51 in the opposite surface 31b of the semiconductor layer 31. The surface pinning layer 49 is connected to the ground potential through the contact electrode 63. In other words, the doped region 49 extends between both sides of the insulating layer 48, and the contact electrode 63 is connected to the doped region 49 and connected to a node receiving a potential (e.g., a ground potential).

[0094] By providing such a surface pinning layer 49 , the interface energy level of the opposite surface 31 b can be lowered, and the dark state characteristics of the pixel array section 11 can be improved.

[0095] Figure 5 It shows that Figure 4 FIG. 1 is a diagram showing an example of a planar structure at a depth D1 as shown. Figure 5 As shown, in the pixel array section 11 , the inter-pixel separator 51 is provided between the SPAD elements 22 adjacent to each other, so that the SPAD elements 22 are electrically and optically separated.

[0096] In the embodiment, for example, in a plan view, a buried layer 48 having a frame shape is formed in a manner surrounding a surface pinning layer 49, and an anode contact region 47 having a frame shape is formed in a manner surrounding such a buried layer 48. In the buried layer 48, a plurality of cathode electrodes 61 (eight in the figure) are uniformly arranged in the peripheral direction.

[0097] Note that the arrangement of the cathode electrode 61 in the buried layer 48 is not limited to Figure 5 For example, Figure 6 As shown, a cathode electrode 61 having a frame shape in a plan view may also be provided along the buried layer 48 . Figure 6 It shows that Figure 4 FIG. 1 is another example of a planar structure at a depth D1 as shown. Figure 5 and Figure 6 As shown, in the plan view, the cathode electrode 61 surrounds the center of the avalanche photodiode 22. Still referring to Figure 5 and Figure 6 , the cathode electrode 61 is spaced apart from the center of the avalanche photodiode 22 and surrounds the center of the avalanche photodiode 22. For example, all sides of the cathode electrode 61 are spaced apart from the center of the avalanche photodiode by the same distance. Figure 6 In the plan view, the cathode electrode 61 is continuous. Figure 5 In the plan view, the cathode electrode 61 includes a plurality of cathode portions spaced apart from each other by the insulating layer 48. For example, the respective cathode portions are spaced apart from the center of the avalanche photodiode 22 by the same distance.

[0098] return Figure 4 Description. Figure 4 As shown, for example, the pixel separation portion 51 is formed to penetrate from the incident surface 31a to the opposite surface 31b of the semiconductor layer 31. For example, the pixel separation portion 51 has a triple structure in which a metal film 52, an insulating film 53, and a fixed charge film 54 are sequentially arranged from the inside.

[0099] For example, the metal film 52 is configured with a reflective metal (for example, tungsten). For example, the insulating film 53 is composed of an insulator such as silicon oxide (SiO2).

[0100] The fixed charge film 54 is formed using a high dielectric having a negative fixed charge, so that a positive charge (hole) accumulation region is formed in the interface portion with the pinning layer 46 to reduce the occurrence of dark current. The fixed charge film 54 is formed to have a negative fixed charge, so that an electric field is applied to the interface with the pinning layer 46 by the negative fixed charge, and a positive charge (hole) accumulation region is formed.

[0101] For example, the fixed charge film 54 can be composed of a hafnium oxide film (HfO2 film). In addition, for example, the fixed charge film 54 can be formed to include at least one of the following oxides: such as hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, and lanthanide elements.

[0102] The sensor-side wiring layer 32 has a cathode electrode 61, an anode electrode 62, a contact electrode 63, a metal wiring 64, a contact electrode 65, and a metal pad (or land) 66. Note that in the sensor-side wiring layer 32, an interlayer insulating film is formed at places other than these portions.

[0103] The cathode electrode 61 , the anode electrode 62 , and the contact electrode 63 are electrically connected to corresponding metal pads 66 via metal wirings 64 and contact electrodes 65 , respectively.

[0104] The logic-side wiring layer 33 has a metal pad (or land) 71, a contact electrode 72, an electrode pad 73, and an insulating layer 74. Note that in the logic-side wiring layer 33, an interlayer insulating film is formed at places other than these portions.

[0105] The metal pads 66 corresponding to the cathode electrode 61, the anode electrode 62 and the contact electrode 63, respectively, are electrically connected to the corresponding electrode pads 73 through the metal pads 71 ​​and the contact electrode 72. The insulating layer 74 insulates the electrode pads 73 from the adjacent electrode pads 73.

[0106] That is, the cathode contact region 44 , the anode contact region 47 , and the surface pinning layer 49 are electrically connected to the corresponding electrode pads 73 through various wirings formed in the sensor-side wiring layer 32 and the logic-side wiring layer 33 .

[0107] The planarization layer 34 is formed in close contact with the entire incident surface 31a of the semiconductor layer 31, and serves to planarize the incident surface 31a of the semiconductor layer 31. The planarization layer 34 is configured with a material (for example, a transparent resin material) that allows the reflected light L2 to pass through.

[0108] For example, the on-chip lens 35 is formed for each pixel 21, and the on-chip lens 35 condenses the reflected light L2 incident on the corresponding pixel 21. Note that, for example, the on-chip lens 35 may be formed for a plurality of pixels 21 adjacent to each other, and is not limited to being formed for each pixel 21.

[0109] Manufacturing process of pixel array unit

[0110] Next, we will refer to Figures 7 to 12 The manufacturing process of the pixel array section 11 according to the present embodiment, particularly the process of forming the buried layer 48 , will be described. Figures 7 to 12 is a cross-sectional view schematically showing a manufacturing process of the pixel array section 11 according to the embodiment of the present disclosure.

[0111] like Figure 7 As shown, by a known technique, a P-type diffusion layer 42, an N-type diffusion layer 43, a cathode contact region 44, and a P-type diffusion layer 101 are formed near the opposite surface 31b of the semiconductor layer 31, and the impurity concentration of the semiconductor layer 31 is controlled to be P-type (i.e., a P well 41 is provided). The P-type diffusion layer 101 as a high-concentration P-type diffusion layer (P+) is formed on the entire surface of the opposite surface 31b.

[0112] Note that Figure 7 In the state, the incident surface 31a side of the semiconductor layer 31 is not polished, so Figure 7 The semiconductor layer 31 is in a state of Figure 4 The semiconductor layer 31 is shown in a thick state.

[0113] In addition, since the hole accumulation layer 45, the pinning layer 46, the pixel separation portion 51, the planarization layer 34, the on-chip lens 35, and other portions are formed after the semiconductor layer 31 is ground to a predetermined thickness, Figure 7 These parts are not formed in the state.

[0114] like Figure 8 As shown, in the surface of the opposite face 31b, a hole portion 102 is formed by a known technique so that at least the cathode contact region 44 is exposed in the bottom surface of the hole portion 102. Such a hole portion 102 is formed at a position corresponding to the buried layer 48.

[0115] like Fig. 9As shown, a known technique is used to form a buried layer 48 by burying an insulator inside the hole 102. Note that by forming such a buried layer 48, the P-type diffusion layer 101 is divided into an anode contact region 47 and a surface pinning layer 49.

[0116] like Fig.10 As shown, then, an insulating layer 103 having a predetermined thickness is formed on the surface of the opposite face 31b by a well-known technique. Note that such an insulating layer 103 is a portion corresponding to a portion of the interlayer insulating film of the sensor-side wiring layer 32.

[0117] like Fig.11 As shown, a hole 104 is then formed in the surface of the insulating layer 103 by a known technique so that at least the cathode contact region 44 is exposed in the bottom surface of the hole 104. The hole 104 is formed at a position corresponding to the cathode electrode 61.

[0118] Furthermore, in the surface of the insulating layer 103, a hole portion 105 is formed by a well-known technique so that at least the anode contact region 47 is exposed in the bottom surface of the hole portion 105. Such a hole portion 105 is formed at a position corresponding to the anode electrode 62.

[0119] Furthermore, then, in the surface of the insulating layer 103, a hole portion 106 is formed by a well-known technique so that at least the surface pinning layer 49 is exposed in the bottom surface of the hole portion 106. Such a hole portion 106 is formed at a position corresponding to the contact electrode 63.

[0120] Then, if Fig.12 As shown, cathode electrode 61 , anode electrode 62 , and contact electrode 63 are formed by embedding metal inside hole portions 104 to 106 using a known technique.

[0121] In the following process, the desired sensor side wiring layer 32 is formed by a known technique, and at the same time, the logic side wiring layer 33 is formed on the logic side substrate by a known technique. Thereafter, the sensor side wiring layer 32 is bonded to the logic side wiring layer 33 using a technique such as Cu-Cu bonding.

[0122] Then, the surface of the semiconductor layer 31 on the side opposite to the sensor-side wiring layer 32 is ground to a predetermined thickness by a known technique, and the incident surface 31a is formed. Thereafter, starting from the incident surface 31a side of the semiconductor layer 31, the hole accumulation layer 45, the pinning layer 46, the pixel separation portion 51, and other portions are formed by a known technique.

[0123] Finally, the planarization layer 34 and the on-chip lens 35 are formed on the incident surface 31 a side of the semiconductor layer 31 , and the pixel array section 11 according to the embodiment is completed.

[0124] Note that the manufacturing process of the pixel array section 11 according to the embodiment is not limited to the above process. For example, in the case where the buried layer 48 and the insulating layer 103 can be made of the same material, the buried layer 48 and the insulating layer 103 can be formed in the same process.

[0125] according to Fig. 9 In the state shown, the insulating layer 103 may be formed after a portion of the cathode electrode 61 is formed in the buried layer 48 .

[0126] Various deformations

[0127] Next, we will refer to Figures 13 to 15 Various modifications of the embodiments will be described. Fig.13 : is a cross-sectional view showing a configuration example of a pixel array section 11 according to a first modification of the embodiment of the present disclosure.

[0128] In the above embodiment, an example is shown in which the buried layer 48 is provided between the cathode contact region 44 and the opposite face 31 b of the semiconductor layer 31 , but the buried layer 48 may be provided between the anode contact region 47 and the opposite face 31 b of the semiconductor layer 31 .

[0129] For example, Fig.13 As shown, the buried layer 48 is disposed between the anode contact region 47 and the opposite face 31 b of the semiconductor layer 31 , while the cathode contact region 44 is disposed in contact with the opposite face 31 b of the semiconductor layer 31 .

[0130] In this configuration as well, the gap between the cathode contact region 44 and the anode contact region 47 can be insulated and separated both horizontally and vertically. This can achieve relaxation of the electric field between the cathode contact region 44 and the anode contact region 47 while preventing the area of ​​the pixel array section 11 from being enlarged.

[0131] Fig.14 2 is a cross-sectional view showing a configuration example of a pixel array section 11 according to a second modification of the embodiment of the present disclosure. Fig.14 As shown, the pixel array section 11 according to the second modification is an example in which the surface pinning layer 49 is not provided on the opposite surface 31 b side of the semiconductor layer 31 .

[0132] In this second modification, since the surface pinning layer 49 is not provided in the semiconductor layer 31, various wirings for connecting such surface pinning layer 49 to the ground potential are not required. In the second modification, the configurations of the sensor side wiring layer 32 and the logic side wiring layer 33 can therefore be simplified, thereby reducing the manufacturing cost of the pixel array section 11.

[0133] Fig.152 is a cross-sectional view showing a configuration example of a pixel array section 11 according to a third modification of the embodiment of the present disclosure. Fig.15 As shown, the pixel array section 11 according to the third modification is an example in which the gap between the N-type diffusion layer 43 and the opposite surface 31b of the semiconductor layer 31 is completely covered by the buried layer 48. That is, in a plan view, the insulating layer 48 extends between both sides (e.g., the inner side) of the cathode electrode 61.

[0134] Also in this third modification, similar to the above-described second modification, the surface pinning layer 49 is not provided in the semiconductor layer 31, and therefore various wirings for connecting such surface pinning layer 49 to the ground potential are not required. In the third modification, the configurations of the sensor side wiring layer 32 and the logic side wiring layer 33 can therefore be simplified, thereby enabling the manufacturing cost of the pixel array section 11 to be reduced.

[0135] Effect

[0136] The light receiving element (pixel array unit 11) according to the embodiment includes a SPAD element 22, a cathode electrode 61 and an anode electrode 62, a cathode contact region 44, an anode contact region 47, and a buried layer 48. The SPAD element 22 is formed in the semiconductor layer 31 and is provided for each of the pixels 21 arranged in an array form. The cathode electrode 61 and the anode electrode 62 are at least partially formed in a wiring layer (sensor side wiring layer 32) adjacent to the semiconductor layer 31, and a reverse bias is applied to the SPAD element 22. The N-type cathode contact region 44 is formed in the semiconductor layer 31 and is directly connected to the cathode electrode 61. The P-type anode contact region 47 is formed in the semiconductor layer 31 and is directly connected to the anode electrode 62. The insulating buried layer 48 is located between any one of the cathode contact region 44 and the anode contact region 47 of the semiconductor layer 31 and the surface (opposite surface 31b) on the opposite side of the light incident side.

[0137] This enables relaxation of the electric field between the cathode contact region 44 and the anode contact region 47 while preventing the area of ​​the pixel array section 11 from being enlarged.

[0138] The light receiving element (pixel array section 11 ) according to the embodiment is formed in the surface (opposite face 31 b ) on the opposite side to the light incident side of the semiconductor layer 31 , and further includes a surface pinning layer 49 connected to a ground potential.

[0139] This can improve the dark state characteristics of the pixel array section 11 .

[0140] The light receiving element (pixel array section 11) according to the embodiment further includes an N-type diffusion layer 43 in contact with the cathode contact region 44 in the semiconductor layer 31. The gap between the N-type diffusion layer 43 of the semiconductor layer 31 and the surface (opposite face 31b) on the opposite side to the light incident side is covered with a buried layer 48.

[0141] This can reduce the manufacturing cost of the pixel array section 11 .

[0142] Electronic devices

[0143] Fig.16 is a block diagram showing a configuration example of a distance image sensor as an electronic device using the light receiving chip 3 .

[0144] like Fig.16 As shown, the distance image sensor 201 includes an optical system 202, a light receiving chip 203, an image processing circuit 204, a monitor 205, and a memory 206. The distance image sensor 201 receives light (modulated light or pulsed light) projected from a light source device 211 toward an object and reflected on the surface of the object, thereby being able to acquire a distance image corresponding to the distance to the object.

[0145] The optical system 202 has one or more lenses, and guides image light (incident light) from an object to the light receiving chip 203 so that the pixel array section 11 of the light receiving chip 203 forms an image.

[0146] The light receiving chip 3 of each of the above-described embodiments is applied to the light receiving chip 203 , and a distance signal indicating a distance determined from a light receiving signal (APD OUT) output from the light receiving chip 203 is supplied to the image processing circuit 204 .

[0147] The image processing circuit 204 performs image processing and forms a distance image based on the distance signal supplied from the light receiving chip 203. The distance image (image data) obtained by the image processing in the image processing circuit 204 is supplied to the monitor 205 and displayed, or supplied to the memory 206 and stored (recorded).

[0148] The distance image sensor 201 configured in this manner to which the above-described light receiving chip 3 is applied can use the light receiving chip 3 that achieves relaxation of the electric field between the cathode contact region 44 and the anode contact region 47 while preventing the area of ​​the pixel array section 11 from being enlarged.

[0149] Mobile Applications

[0150] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as: a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0151] Fig.17: is a block diagram showing a schematic configuration example of a vehicle control system as one example of a moving body control system to which the technology according to the present disclosure can be applied.

[0152] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.17 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. As the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: Interface) 12053 are shown.

[0153] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various computer programs. For example, the drive system control unit 12010 functions as a controller of the following devices: a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, etc.; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; a braking device for generating the braking force of the vehicle; and other devices.

[0154] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various computer programs. For example, the body system control unit 12020 functions as a controller of the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as a headlight, a rear light, a brake light, a turn signal light, or a fog light. In this case, a radio wave sent from a portable machine instead of a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals, and controls the door lock device, the power window device, the light, or other devices of the vehicle.

[0155] The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing on pedestrians, vehicles, obstacles, traffic signs, or text on the road surface and other objects.

[0156] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or may be non-visible light such as infrared rays.

[0157] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for photographing the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information outside or inside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing the functions of the advanced driver assistance system (ADAS), such as collision avoidance or impact reduction of the vehicle, following driving based on the vehicle-to-vehicle distance, speed maintenance driving, collision warning of the vehicle or lane departure warning of the vehicle, etc.

[0159] In addition, the microcomputer 12051 is capable of controlling the driving force generating device, steering mechanism, braking device or other devices based on the information about the vehicle surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control for automatic operations such as achieving autonomous driving without the need for driver operation.

[0160] Based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and perform cooperative control aimed at achieving glare protection, such as switching from high beam to low beam.

[0161] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify passengers on the vehicle or the outside of the vehicle of information. Fig.17 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are exemplified. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0162] Fig.18 This is a diagram showing an example of the installation position of the camera unit 12031.

[0163] exist Fig.18 In the figure, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are provided.

[0164] Camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the following positions: for example, the front nose, rearview mirror, rear bumper and trunk door of the vehicle 12100 and the upper part of the windshield in the vehicle. The camera unit 12101 arranged on the front nose and the camera unit 12105 arranged on the upper part of the windshield in the vehicle mainly obtain the front image of the vehicle 12100. The camera units 12102 and 12103 arranged on the rearview mirror mainly obtain the side image of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or the trunk door mainly obtains the rear image of the vehicle 12100. The camera unit 12105 arranged on the upper part of the windshield in the vehicle is mainly used to detect, for example, the vehicle in front, or pedestrians, obstacles, signaling devices, traffic signs or traffic lanes.

[0165] Notice, Fig.18 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 disposed on the front nose; the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 disposed on the rearview mirror; and the imaging range 12114 indicates the imaging range of the imaging unit 12104 disposed on the rear bumper or the trunk door. For example, by superimposing the pieces of image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above is generated.

[0166] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0167] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can determine the distances to each three-dimensional object within the camera ranges 12111 to 12114 and the changes in these distances over time (relative speed relative to the vehicle 12100), thereby extracting the three-dimensional object that is closest to the vehicle 12100 on the road and traveling at a predetermined speed (for example, greater than or equal to 0 km / h) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can set the inter-vehicle distance to be maintained in front of the leading vehicle in advance, and can perform, for example, automatic braking control (also including follow-up stop control) and automatic acceleration control (also including follow-up start control). In this way, it is possible to perform cooperative control of automatic operations, such as for autonomous driving without the need for driver operation.

[0168] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into bicycles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects, and extract the classified data, and use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult for the driver to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and in the case where the collision risk is higher than or equal to the set value and therefore there is a possibility of collision, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 and the display unit 12062, or perform forced deceleration and evasive steering through the drive system control unit 12010, thereby performing operation assistance for avoiding collision.

[0169] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether there are pedestrians in the images captured by the camera units 12101 to 12104. For example, such pedestrian recognition is performed by the following process: a process of extracting feature points in the images captured by the camera units 12101 to 12104 as infrared cameras; and a process of determining whether the object is a pedestrian by pattern matching a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the images captured by the camera units 12101 to 12104 and identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a rectangular contour line for emphasis is superimposed on the identified pedestrian and displayed. In addition, the sound / image output unit 12052 can also control the display unit 12062 so that an icon for representing a pedestrian, for example, is displayed at a desired position.

[0170] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the camera unit 12031 in the above-mentioned configuration. Specifically, Figure 1 The distance measuring device 1 in the embodiment can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, it is possible to use the light receiving chip 3 that realizes electric field relaxation between the cathode contact region 44 and the anode contact region 47 while preventing the area of ​​the pixel array section 11 from being enlarged.

[0171] Although the embodiments of the present disclosure have been described, the technical scope of the present disclosure is not limited to the above-described embodiments, and various changes can be made without departing from the subject matter of the present disclosure. In addition, components in different embodiments and modifications can be combined as needed.

[0172] For example, in the element structure of the pixel array section 11 shown in the above-described embodiment, as an embodiment, an element structure in which the P-type conductivity type and the N-type conductivity type are interchanged may be adopted.

[0173] The effects described in the specification are merely exemplary and not restrictive, and other effects may exist.

[0174] Note that the present technology can also have the following configurations.

[0175] (1) A light receiving element comprising:

[0176] A single photon avalanche diode (SPAD) element formed in a semiconductor layer and provided for each pixel arranged in an array;

[0177] a cathode electrode and an anode electrode which are at least partially formed in a wiring layer adjacent to the semiconductor layer and are configured to apply a reverse bias to the SPAD element;

[0178] an N-type cathode contact region formed in the semiconductor layer and directly connected to the cathode electrode;

[0179] a P-type anode contact region formed in the semiconductor layer and directly connected to the anode electrode; and

[0180] The insulating buried layer is located between the cathode contact region and the anode contact region of the semiconductor layer and the surface on the side opposite to the light incident side.

[0181] (2) The light receiving element according to (1), further including a surface pinning layer formed in a surface on the opposite side of the light incident side of the semiconductor layer and connected to a ground potential.

[0182] (3) The light receiving element according to one or more of (1) to (2), further comprising an N-type diffusion layer in contact with the cathode contact region in the semiconductor layer, wherein

[0183] A gap between the N-type diffusion layer of the semiconductor layer and the surface on the side opposite to the light incident side is covered with the buried layer.

[0184] (4) An electronic device comprising a light receiving element, the light receiving element comprising:

[0185] A single photon avalanche diode (SPAD) element formed in a semiconductor layer and provided for each pixel arranged in an array;

[0186] a cathode electrode and an anode electrode which are at least partially formed in a wiring layer adjacent to the semiconductor layer and are configured to apply a reverse bias to the SPAD element;

[0187] an N-type cathode contact region formed in the semiconductor layer and directly connected to the cathode electrode;

[0188] a P-type anode contact region formed in the semiconductor layer and directly connected to the anode electrode; and

[0189] The insulating buried layer is located between the cathode contact region and the anode contact region of the semiconductor layer and the surface on the side opposite to the light incident side.

[0190] (5) The electronic device according to (4), wherein:

[0191] The light receiving element further includes a surface pinning layer which is formed in a surface on the opposite side of the light incident side of the semiconductor layer and is connected to a ground potential.

[0192] (6) The electronic device according to one or more of (4) to (5), wherein:

[0193] The light receiving element further includes an N-type diffusion layer which contacts the cathode contact region in the semiconductor layer, and

[0194] A gap between the N-type diffusion layer of the semiconductor layer and the surface on the side opposite to the light incident side is covered with the buried layer.

[0195] (7) An avalanche photodiode, comprising:

[0196] a substrate including a first side having a first surface and a second side having a second surface opposite to the first surface, the second surface being a light incident surface of the substrate;

[0197] an anode region disposed in the substrate on a first side of the substrate;

[0198] an anode electrode connected to the anode region;

[0199] a cathode region disposed in the substrate on a first side of the substrate; and

[0200] a cathode electrode connected to the cathode region;

[0201] An insulating layer is disposed on a first side of the substrate in the substrate, wherein the anode electrode or the cathode electrode passes through the insulating layer.

[0202] (8) The avalanche photodiode according to (7), wherein the cathode electrode is provided closer to the center of the avalanche photodiode than the anode electrode in a plan view.

[0203] (9) The avalanche photodiode according to one or more of (7) to (8), wherein the cathode electrode surrounds the center of the avalanche photodiode in a plan view.

[0204] (10) The avalanche photodiode according to one or more of (7) to (9), wherein the cathode electrode is spaced apart from the center of the avalanche photodiode and surrounds the center of the avalanche photodiode in a plan view.

[0205] (11) The avalanche photodiode according to one or more of (7) to (10), wherein the cathode electrode is continuous in a plan view.

[0206] (12) The avalanche photodiode according to one or more of (7) to (11), wherein all sides of the cathode electrode are spaced the same distance from the center of the avalanche photodiode.

[0207] (13) The avalanche photodiode according to one or more of (7) to (12), wherein, in a plan view, the cathode electrode includes a plurality of cathode portions spaced apart from each other by an insulating layer.

[0208] (14) An avalanche photodiode according to one or more of (7) to (13), wherein each cathode portion is spaced the same distance from the center of the avalanche photodiode.

[0209] (15) The avalanche photodiode according to one or more of (7) to (14), wherein the insulating layer extends between both sides of the cathode electrode in a plan view.

[0210] (16) The avalanche photodiode according to one or more of (7) to (15), wherein a surface of the insulating layer is coplanar with the first surface of the substrate.

[0211] (17) An avalanche photodiode according to one or more of (7) to (16), wherein the insulating layer extends deeper into the substrate than the anode contact region.

[0212] (18) The avalanche photodiode according to one or more of (7) to (17), further comprising:

[0213] A doped region extends between two sides of the insulating layer.

[0214] (19) The avalanche photodiode according to one or more of (7) to (18), further comprising:

[0215] A contact electrode is connected to the doped region and to a node that receives a potential.

[0216] (20) The avalanche photodiode according to one or more of (7) to (19), wherein the potential is ground potential.

[0217] (21) A light detection device comprising:

[0218] a first substrate including a first side having a first surface and a second side having a second surface opposite to the first surface, the second surface being a light incident surface of the first substrate;

[0219] An avalanche photodiode, the avalanche photodiode comprising:

[0220] an anode region disposed in the first substrate on a first side of the first substrate;

[0221] an anode electrode connected to the anode region;

[0222] a cathode region disposed in the first substrate on a first side of the first substrate;

[0223] an insulating layer disposed in the first substrate on a first side of the first substrate;

[0224] a cathode electrode connected to the cathode region, wherein the cathode electrode or the anode electrode passes through the insulating layer;

[0225] a first wiring layer on the first surface of the first substrate, the first wiring layer including an anode wiring connected to the anode electrode, a cathode wiring connected to the cathode electrode, and a plurality of first bonding pads; and

[0226] A second substrate includes a second wiring layer and a circuit for processing a signal output from the avalanche photodiode, the second wiring layer including a plurality of second bonding pads bonded to the plurality of first bonding pads.

[0227] (22) The light detection device according to (21), wherein the plurality of first bonding pads and the plurality of second bonding pads include bonding pads electrically connected to the anode wiring and bonding pads electrically connected to the cathode wiring, respectively.

[0228] (23) The photodetection device according to one or more of (21) to (22), wherein, in a plan view, the cathode electrode is disposed closer to the center of the avalanche photodiode than the anode electrode.

[0229] (24) The photodetection device according to one or more of (21) to (23), wherein the cathode electrode surrounds the center of the avalanche photodiode in a plan view.

[0230] (25) The photodetection device according to one or more of (21) to (24), wherein, in a plan view, the cathode electrode is spaced apart from the center of the avalanche photodiode and surrounds the center of the avalanche photodiode.

[0231] (26) An electronic device comprising:

[0232] a light source that emits modulated light toward the object; and

[0233] An avalanche photodiode that senses modulated light reflected from an object, the avalanche photodiode comprising:

[0234] a substrate including a first side having a first surface and a second side having a second surface opposite to the first surface, the second surface being a light incident surface of the substrate;

[0235] an anode region disposed in the substrate on a first side of the substrate;

[0236] an anode electrode connected to the anode region;

[0237] a cathode region disposed in the substrate on a first side of the substrate;

[0238] an insulating layer disposed in the substrate on a first side of the substrate; and

[0239] A cathode electrode is connected to the cathode region, wherein the cathode electrode or the anode electrode passes through the insulating layer.

[0240] [reference numerals list]

[0241] 1 Distance measuring device

[0242] 3. Optical receiving chip

[0243] 11 Pixel array section (an example of a light receiving element)

[0244] 21 pixels

[0245] 22 SPAD element

[0246] 31 Semiconductor layer

[0247] 31a Incident surface

[0248] 31b Opposite side

[0249] 32 Sensor side wiring layer (an example of a wiring layer)

[0250] 43 N-type diffusion layer

[0251] 44 Cathode contact area

[0252] 47 Anode contact area

[0253] 48 buried layer

[0254] 49 Surface pinning layer

[0255] 61 cathode electrode

[0256] 62 Anode electrode

Claims

1. An avalanche photodiode, comprising: a substrate, the substrate comprising a first side having a first surface and a second side having a second surface opposite to the first surface, the second surface being a light incident surface of the substrate; an anode region, the anode region being disposed in the substrate on the first side of the substrate; an anode electrode connected to the anode region; a cathode region, the cathode region being disposed in the substrate on the first side of the substrate; a cathode electrode connected to the cathode region; and an insulating layer, the insulating layer being disposed in the substrate on the first side of the substrate, wherein the anode electrode or the cathode electrode passes through the insulating layer, wherein, in a plan view, the anode electrode is located in a peripheral portion of the avalanche photodiode, Wherein, in the plan view, the cathode electrode is arranged closer to the center of the avalanche photodiode than the anode electrode.

2. The avalanche photodiode according to claim 1, wherein: The cathode electrode surrounds the center of the avalanche photodiode in a plan view.

3. The avalanche photodiode according to claim 2, wherein: The cathode electrode is spaced apart from the center of the avalanche photodiode and surrounds the center of the avalanche photodiode in a plan view.

4. The avalanche photodiode according to claim 3, wherein: In plan view, the cathode electrode is continuous.

5. The avalanche photodiode according to claim 4, wherein: All sides of the cathode electrode are spaced the same distance from the center of the avalanche photodiode.

6. The avalanche photodiode according to claim 2, wherein: In a plan view, the cathode electrode includes a plurality of cathode portions spaced apart from each other by the insulating layer.

7. The avalanche photodiode according to claim 6, wherein: Each cathode portion is spaced the same distance from the center of the avalanche photodiode.

8. The avalanche photodiode according to claim 2, wherein: In a plan view, the insulating layer extends between both sides of the cathode electrode.

9. The avalanche photodiode according to any one of claims 1 to 8, wherein: A surface of the insulating layer is coplanar with the first surface of the substrate.

10. The avalanche photodiode according to claim 9, wherein: The insulating layer extends deeper into the substrate than the anode region.

11. The avalanche photodiode according to claim 2, further comprising: A doped region extends between two sides of the insulating layer as a surface pinning layer.

12. The avalanche photodiode according to claim 11, further comprising: A contact electrode is connected to the doped region and to a node receiving a potential.

13. The avalanche photodiode according to claim 12, wherein: The potential is ground potential.

14. A light detection device, comprising: a first substrate, the first substrate including a first side having a first surface and a second side having a second surface opposite to the first surface, the second surface being a light incident surface of the first substrate; An avalanche photodiode, the avalanche photodiode comprising: an anode region disposed in the first substrate on the first side of the first substrate; an anode electrode connected to the anode region; a cathode region disposed in the first substrate on the first side of the first substrate; an insulating layer disposed on the first side of the first substrate in the first substrate; a cathode electrode connected to the cathode region, wherein the cathode electrode or the anode electrode passes through the insulating layer; a first wiring layer on the first surface of the first substrate, the first wiring layer including an anode wiring connected to the anode electrode, a cathode wiring connected to the cathode electrode, and a plurality of first bonding pads; and a second substrate including a second wiring layer and a circuit for processing a signal output from the avalanche photodiode, the second wiring layer including a plurality of second bonding pads bonded to the plurality of first bonding pads, wherein, in a plan view, the anode electrode is located in a peripheral portion of the avalanche photodiode, Wherein, in the plan view, the cathode electrode is arranged closer to the center of the avalanche photodiode than the anode electrode.

15. The light detection device according to claim 14, wherein: The plurality of first bonding pads and the plurality of second bonding pads respectively include a bonding pad electrically connected to the anode wiring and a bonding pad electrically connected to the cathode wiring.

16. The light detection device according to claim 14, wherein: The cathode electrode surrounds the center of the avalanche photodiode in a plan view.

17. The light detection device according to claim 16, wherein: The cathode electrode is spaced apart from the center of the avalanche photodiode and surrounds the center of the avalanche photodiode in a plan view.

18. An electronic device, comprising: a light source that emits modulated light toward the object; and An avalanche photodiode that senses the modulated light reflected from the object, the avalanche photodiode being the avalanche photodiode according to any one of claims 1 to 13.

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