A high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU

Abstract

The present invention proposes a high-precision IRIG‑B (AC) time code demodulation method based on FPGA+MCU; the method is a B (AC) code decoding design based on the combination of FPGA+MCU and analog-to-digital conversion chip, and adopts a demodulation circuit with a digital circuit as the core. The method realizes the functions of some analog circuits in the analog method through digital circuits, thereby solving the problems in the prior art that time information is prone to bit errors and the demodulated second signal has large jitter.

Description

Technical Field

[0001] The invention belongs to the technical field of time unification, and in particular relates to a high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU. Background Art

[0002] At present, IRIG-B (AC) code demodulation equipment generally uses analog demodulation, and its circuit includes filter circuit, power detection circuit, voltage comparator and zero-crossing comparator to achieve demodulation. However, after passing through the op amp and comparator, the B (AC) code is easily affected by temperature and external interference to produce jitter and zero drift, resulting in the demodulated time information being prone to bit errors. At the same time, the demodulated second signal has a large jitter, and the second pulse error synchronized with the satellite is greater than 10us; the principle of analog demodulation is as follows Figure 1 shown. Summary of the invention

[0003] In view of the above-mentioned defects and needs of the prior art, the present invention proposes a high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU; the present invention proposes a B (AC) code decoding design based on the combination of FPGA+MCU and analog-to-digital conversion chip, and adopts a demodulation circuit with digital circuit as the core. This method realizes the functions of some analog circuits in the analog method through digital circuits, thereby solving the problems in the prior art that time information is prone to bit errors and the demodulated second signal has large jitter.

[0004] The specific implementation contents of the present invention are as follows:

[0005] The present invention proposes a high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU, and digitally demodulates the IRIG-B (AC) code based on an IRIG-B (AC) code digital demodulation circuit to obtain an IRIG-B (DC) code; the IRIG-B (AC) code digital demodulation circuit includes a filter circuit, an ADC acquisition unit, an FPGA processing unit, and an MCU processing unit;

[0006] The filtering circuit, the ADC acquisition unit, the FPGA processing unit, and the MCU processing unit are connected in sequence; the MCU processing unit is also connected to the ADC acquisition unit;

[0007] The specific steps of the demodulation method are:

[0008] Step 1: Use a filter circuit to receive the IRIG-B (AC) code signal and filter the IRIG-B (AC) code signal;

[0009] Step 2: Send the IRIG-B (AC) code signal after filtering by the filtering circuit to the ADC acquisition unit for processing to obtain the peak voltage signal and the valley voltage signal of the IRIG-B (AC) code signal;

[0010] Step 3: Send the peak voltage signal and the valley voltage signal obtained by the ADC acquisition unit to the FPGA processing unit in parallel for processing to obtain a binary time signal; the binary time signal is a pulse signal with a small wave having a long low level and a large wave having a period of 1ms;

[0011] Step 4: Use the FPGA processing unit to obtain the rising edge of the pulse of the binary time signal. When the rising edge arrives, use the FPGA processing unit to set the binary time signal high, and use the counter to delay for 1ms before pulling it down; when the next pulse rising edge is collected, clear the counter and repeat this operation; obtain the processed FPGA demodulation signal, which is the IRIG-B (DC) code signal.

[0012] In order to better implement the present invention, further, after performing step 4, the following step 5 is also performed:

[0013] Step 5: Use the FPGA processing unit to output the demodulated IRIG-B (DC) code signal to the MCU processing unit, and then use the MCU processing unit to decode the P code time of the IRIG-B (DC) code signal according to the time code protocol; at the same time, output the timing signal to the FPGA processing unit through the TIM pin of the MCU processing unit; then use the FPGA processing unit to perform logical "AND" processing on the IRIG-B (DC) code signal and the timing signal sent by the TIM pin to demodulate the second time of the IRIG-B code signal.

[0014] In order to better implement the present invention, further, an ADC acquisition chip ADS8365 is used as an ADC acquisition unit.

[0015] In order to better implement the present invention, further, in step 4, the clock frequency used for the rising edge is selected to be greater than 100 MHz.

[0016] In order to better implement the present invention, further, in step 4, after obtaining the FPGA demodulation signal, it is necessary to filter the FPGA demodulation signal, and obtain the IRIG-B (DC) code signal after eliminating the burrs through filtering.

[0017] In order to better implement the present invention, further, the MCU processing unit adopts an STM32 series chip or a GD32 series chip.

[0018] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0019] (1) This solution uses digital demodulation, which has strong adaptability to high and low temperatures and external environments and is basically not affected by environmental interference;

[0020] (2) This scheme can demodulate time information without errors;

[0021] (3) This solution has high demodulation second accuracy and small jitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of a B (AC) analog demodulation circuit in the prior art;

[0023] Figure 2 It is a module schematic diagram of the IRIG-B (AC) code digital demodulation circuit of the present invention;

[0024] Figure 3 Schematic diagram of B(AC) digital demodulation to obtain a binary time signal;

[0025] Figure 4 This is a schematic diagram of FPGA demodulation signal;

[0026] Figure 5 Schematic diagram of obtaining timing for demodulating seconds. DETAILED DESCRIPTION

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, and therefore should not be regarded as limiting the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technical personnel in this field without making creative work are within the scope of protection of the present invention.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0029] Embodiment 1:

[0030] This embodiment proposes a high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU, which digitally demodulates the IRIG-B (AC) code based on the IRIG-B (AC) code digital demodulation circuit to obtain the IRIG-B (DC) code; Figure 2 As shown, the IRIG-B (AC) code digital demodulation circuit includes a filter circuit, an ADC acquisition unit, an FPGA processing unit, and an MCU processing unit;

[0031] The filtering circuit, the ADC acquisition unit, the FPGA processing unit, and the MCU processing unit are connected in sequence; the MCU processing unit is also connected to the ADC acquisition unit;

[0032] like Figure 3 , Figure 4 As shown, the specific steps of the demodulation method are:

[0033] Step 1: Use a filter circuit to receive the IRIG-B (AC) code signal and filter the IRIG-B (AC) code signal;

[0034] Step 2: Send the IRIG-B (AC) code signal after filtering by the filtering circuit to the ADC acquisition unit for processing to obtain the peak voltage signal and the valley voltage signal of the IRIG-B (AC) code signal;

[0035] Step 3: Send the peak voltage signal and the valley voltage signal obtained by the ADC acquisition unit to the FPGA processing unit in parallel for processing to obtain a binary time signal; the binary time signal is a pulse signal with a small wave having a long low level and a large wave having a period of 1ms;

[0036] Step 4: Use the FPGA processing unit to obtain the rising edge of the pulse of the binary time signal. When the rising edge arrives, use the FPGA processing unit to set the binary time signal high, and use the counter to delay for 1ms before pulling it down; when the next pulse rising edge is collected, clear the counter and repeat this operation; obtain the processed FPGA demodulation signal, which is the IRIG-B (DC) code signal.

[0037] Working principle: At present, IRIG-B (AC) code demodulation equipment generally adopts analog demodulation, and its circuit includes filter circuit, power detection circuit, voltage comparator and zero-crossing comparator to realize demodulation. However, after passing through the op amp and comparator, the B (AC) code is easily affected by temperature and external interference to produce jitter and zero drift, which makes the demodulated time information prone to bit errors. At the same time, the demodulated second signal has large jitter, and the second pulse error synchronized with the satellite is greater than 10us. The analog demodulation principle of the existing technology is as follows: Figure 1As shown. In order to ensure the accuracy of B(AC) code demodulation time information and high demodulation second precision, the present invention proposes a B(AC) code decoding design based on the combination of FPGA+MCU and analog-to-digital conversion chip. FPGA can choose multiple Xilinx models and domestic FPGA models, MCU adopts the current mainstream STM32 or domestic GD32 series models, and the analog-to-digital conversion chip adopts ADS8365 or other similar ADC chips.

[0038] The purpose of the present invention is to provide a digital demodulation of IRIG-B (AC) code, which solves the problem in the prior art that time information is prone to bit errors and the demodulated second signal has large jitter.

[0039] The present invention adopts a demodulation circuit with a digital circuit as the core. In this method, the functions of part of the analog circuit in the analog method are realized by the digital circuit.

[0040] like Figure 2 As shown, the present invention obtains the peak voltage and valley voltage of the B(AC) signal after B(AC) passes through the filtering circuit and enters the ADC acquisition chip ADS8365, and sends the peak value and the estimated voltage parallel data to the FPGA to process the digital signal to obtain binary time information.

[0041] The signals before and after processing are as follows Figure 3 As shown in the figure, the processed digital signal wavelet is a long low level, and the large wavelet is a pulse signal with a period of 1ms. FPGA takes the rising edge of the pulse signal. When the rising edge arrives, the FPGA demodulation signal is set high, and the counter is used to delay for 1ms before pulling it low. When the next pulse rising edge is collected, the counter is cleared and the above operation is repeated. The processed FPGA demodulation signal is as follows Figure 4 shown.

[0042] Embodiment 2:

[0043] This embodiment is based on the above embodiment 1, in order to better implement the present invention, further, as follows Figure 5 As shown, after performing step 4, the following step 5 is also performed:

[0044] Step 5: Use the FPGA processing unit to output the demodulated IRIG-B (DC) code signal to the MCU processing unit, and then use the MCU processing unit to decode the P code time of the IRIG-B (DC) code signal according to the time code protocol; at the same time, output the timing signal to the FPGA processing unit through the TIM pin of the MCU processing unit; then use the FPGA processing unit to perform logical "AND" processing on the IRIG-B (DC) code signal and the timing signal sent by the TIM pin to demodulate the second time of the IRIG-B code signal.

[0045] Working principle: FPGA outputs the demodulated B(DC) time code to MCU. MCU decodes the P code moment of B(DC) code according to the time code protocol and outputs the timing signal to FPGA through TIM pin. FPGA performs “AND” operation on B(DC) and TIM timing signals and then demodulates the accurate second moment of B code. The corresponding timing is as follows: Figure 5 shown.

[0046] The time interval between the demodulated B (AC) code second pulse and the second pulse output by the satellite synchronization clock is measured using Agilent's 53132A counter and is about 440ns, which is much higher than the analog demodulation second accuracy. The demodulation second error measurement is shown in Table 1 below:

[0047] Table 1 Demodulation seconds error measurement

[0048]

[0049] The other parts of this embodiment are the same as those of the above-mentioned embodiment 1, and thus will not be described in detail.

[0050] Embodiment 3:

[0051] This embodiment is based on any one of the above embodiments 1-2, and in order to better implement the present invention, further adopts ADC acquisition chip ADS8365 as the ADC acquisition unit.

[0052] The other parts of this embodiment are the same as any of the above embodiments 1-2, so they are not repeated here.

[0053] Embodiment 4:

[0054] In this embodiment, based on any one of the above embodiments 1-3, in order to better implement the present invention, further, in step 4, the clock frequency used for the rising edge is selected to be greater than 100 MHz.

[0055] In order to better implement the present invention, further, in step 4, after obtaining the FPGA demodulation signal, it is necessary to filter the FPGA demodulation signal, and obtain the IRIG-B (DC) code signal after eliminating the burrs through filtering.

[0056] Working principle: In order to ensure the accuracy of the demodulated signal, the rising edge sampling clock frequency is selected to be greater than 100MHz, and the error can be controlled within 10ns. At the same time, due to the large wave interval of 1ms, there will be deviations. When the deviation is greater than 10ns, FPGA demodulated signals will have glitches, so the demodulated signal needs to be filtered to filter out the glitches; the demodulated signal obtained at this time is the standard IRIG-B (DC) time code signal.

[0057] The other parts of this embodiment are the same as any one of the above embodiments 1-3, so they are not repeated here.

[0058] Embodiment 5:

[0059] In this embodiment, based on any one of the above embodiments 1-4, in order to better realize the present invention, the MCU processing unit further adopts an STM32 series chip or a GD32 series chip.

[0060] The other parts of this embodiment are the same as any one of the above embodiments 1-4, so they are not repeated here.

[0061] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent change made to the above embodiment based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU, which digitally demodulates the IRIG-B (AC) code based on the IRIG-B (AC) code digital demodulation circuit to obtain the IRIG-B (DC) code; characterized in that: The IRIG-B (AC) code digital demodulation circuit includes a filter circuit, an ADC acquisition unit, an FPGA processing unit, and an MCU processing unit; The filtering circuit, the ADC acquisition unit, the FPGA processing unit, and the MCU processing unit are connected in sequence; the MCU processing unit is also connected to the ADC acquisition unit; The specific steps of the demodulation method are: Step 1: Use a filter circuit to receive the IRIG-B (AC) code signal and filter the IRIG-B (AC) code signal; Step 2: Send the IRIG-B (AC) code signal after filtering by the filtering circuit to the ADC acquisition unit for processing to obtain the peak voltage signal and the valley voltage signal of the IRIG-B (AC) code signal; Step 3: Send the peak voltage signal and the valley voltage signal obtained by the ADC acquisition unit to the FPGA processing unit in parallel for processing to obtain a binary time signal; the binary time signal is a pulse signal with a small wave having a long low level and a large wave having a period of 1ms; Step 4: Use the FPGA processing unit to obtain the rising edge of the pulse of the binary time signal. When the rising edge arrives, use the FPGA processing unit to set the binary time signal high, and use the counter to delay for 1ms and then pull it low; when the next pulse rising edge is collected, clear the counter and repeat this operation; obtain the processed FPGA demodulation signal, which is the IRIG-B (DC) code signal; After performing step 4, perform the following step 5: Step 5: Use the FPGA processing unit to output the demodulated IRIG-B (DC) code signal to the MCU processing unit, and then use the MCU processing unit to decode the P code time of the IRIG-B (DC) code signal according to the time code protocol; at the same time, the timing signal is output to the FPGA processing unit through the TIM pin of the MCU processing unit; then the FPGA processing unit performs a logical "AND" process on the IRIG-B (DC) code signal and the timing signal sent by the TIM pin to demodulate the second time of the IRIG-B code signal.

2. A high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU as claimed in claim 1, characterized in that: The ADC acquisition chip ADS8365 is used as the ADC acquisition unit.

3. A high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU as claimed in claim 1, characterized in that: In step 4, the clock frequency used for the rising edge is selected to be greater than 100 MHz.

4. A high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU as claimed in claim 3, characterized in that: In step 4, after obtaining the FPGA demodulation signal, it is necessary to filter the FPGA demodulation signal to eliminate burrs through filtering to obtain the IRIG-B (DC) code signal.

5. A high-precision IRIG-B (AC) time code demodulation method based on FPGA+MCU as claimed in claim 1, characterized in that: The MCU processing unit adopts an STM32 series chip or a GD32 series chip.

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