Microsystem module chip embedded packaging structure and packaging method

Abstract

The invention provides a microsystem module chip embedded packaging structure and packaging method. The invention adopts a method for reshaping photoresist around a chip to be packaged by performing a rewiring process from top to bottom. First, a rewiring structure is made on a temporary supporting substrate. Then, a side of the chip to be packaged with a chip pad and an electrical interconnection pad on the rewiring structure are reflowed. Then, the outer layer of the chip to be packaged is reshaped by using a thick film photoresist. Finally, the reshaped chip to be packaged with the rewiring structure is buckled into a groove of a semiconductor substrate. The remaining width around a silicon cavity after the chip is embedded is greatly reduced, and the suspended wiring structure is eliminated to improve the reliability of the module as a whole. The electrical interconnection failure caused by the deviation of the wiring and the interconnection PAD on the chip is avoided, and the surface of the chip to be packaged is repeatedly subjected to processes with relatively high intensity and the structure on the upper surface of the chip to be packaged is damaged.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a microsystem module chip embedded packaging structure and a packaging method. Background Art

[0002] With the development of silicon-based microelectromechanical systems (MEMS) and radio frequency through silicon via (RF TSV) process technology, three-dimensional heterogeneous integrated microsystem technology has become an important direction for the development of the next generation of military high-integration electronic system technology. Three-dimensional heterogeneous integration is an integration method that embeds chips of different sizes and textures into silicon cavities on a silicon-based substrate, fanning them out through post-wiring technology, and then uses through silicon vias to achieve high-density integration.

[0003] However, such a bottom-up process flow of embedding first and then wiring has many problems. For example, first: the error of the back-end chip cutting is larger and the accuracy is smaller than that of the front-end etching process. Therefore, in order to avoid the problem that the chip size cannot be embedded due to the increase in cutting when the chip is embedded, the width of the etched cavity is usually increased during cavity etching. However, the introduction of this excess width will cause the problem of dangling wires when the chip is embedded and then wired. This dangling wire will greatly reduce the overall reliability of the module. Second: The chip embedding process involves using the back-end process to cut the chip from the wafer, and then use a chip mounter to stick it to the bottom of the embedded silicon cavity for reflow, and then use the front-end process of photolithography and electroplating to rewire and fan out from the bottom to the top. The bottom-up layout can be: after the chip is embedded in the cavity, the lower layer of metal and dielectric are grown on the chip PAD and the cavity surface, and then the upper layer of metal and dielectric are grown. For example, Fig.26 As shown, after the chip 401 is buried in the cavity of the silicon substrate 400, the lower metal 402 and the lower dielectric 403 are grown on the PAD of the chip 401 and the cavity surface, and then the upper metal 404 is grown. Due to the different process precisions of the front and back processes, it is easy to cause the chip to deviate from the originally set standard position during the reflow process, and the fan-out process such as photolithography and electroplating in the next step uses the originally set standard position as the reference position, which causes the fan-out metal routing to deviate from the interconnection PAD on the chip and cause the problem of electrical interconnection failure. Third: Many embedded functional chips have environmental requirements for the upper surface of the chip. Generally, the upper surface is required to be exposed to the air, and there must be no silicon dioxide dielectric layer or PI glue dielectric layer covering it. In this way, the exposed upper surface of the chip will be subjected to a series of high-intensity processes such as glue coating, development, PVD sputtering, and wet etching to remove the seed layer over and over again. The repeated execution of these processes can easily cause the structure on the upper surface of the chip to be damaged and affect the chip performance.

[0004] Therefore, it is necessary to provide a microsystem module chip embedded packaging structure and packaging method to solve the above problems in the prior art. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a microsystem module chip embedded packaging structure and packaging method, which are used to solve the problems of module reliability, electrical interconnection failure caused by pad deviation, and chip surface damage affecting performance caused by the embedded packaging of the microsystem module chip in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a microsystem module chip embedded packaging method, the packaging method comprising the following steps:

[0007] Providing a temporary bearing base;

[0008] forming a rewiring structure on the temporary carrier substrate, wherein an electrical interconnection pad is formed on the surface of the rewiring structure;

[0009] Providing a chip to be packaged having a front side and a back side opposite to each other, wherein a chip bonding pad is formed on the front side;

[0010] The chip to be packaged is flipped on the rewiring structure, and the chip pad is connected to the electrical interconnection pad;

[0011] Forming a reformed photoresist layer on the rewiring structure, wherein the reformed photoresist layer surrounds the chip to be packaged, and the upper surface of the reformed photoresist layer is flush with the back surface of the chip to be packaged, to obtain a reconstructed connection structure;

[0012] Providing a semiconductor substrate, in which a cavity to be embedded is formed, and the outer edge size of the reformed photoresist layer is the same as the size of the cavity to be embedded;

[0013] Loading the reconstructed connection structure on the semiconductor substrate, wherein the chip to be packaged and the reformed photoresist layer are buried in the cavity to be embedded; and

[0014] The temporary supporting substrate is removed to obtain a chip embedded module structure.

[0015] Optionally, the step of forming the rewiring structure includes:

[0016] forming a temporary bonding layer on the temporary supporting substrate;

[0017] forming a rewiring layer on the temporary bonding layer, wherein the rewiring layer comprises at least one metal wire layer and at least one dielectric layer, wherein the metal wire layer is located in the dielectric layer to form a metal interconnect structure;

[0018] The electrical interconnect pad electrically connected to the metal interconnect structure is formed on the rewiring layer.

[0019] Optionally, the temporary bonding layer includes any one of thermally degradable glue, ultraviolet light degradable glue and temporary bonding glue.

[0020] Optionally, the step of forming the rewiring layer and the electrical interconnection pad comprises:

[0021] forming a first patterned dielectric layer on the temporary bonding layer, wherein a plurality of first openings exposing the temporary bonding layer are formed on the first patterned dielectric layer;

[0022] forming a continuous first seed layer on the surface of the first patterned dielectric layer and the exposed temporary bonding layer;

[0023] forming a first sacrificial dielectric layer on the first seed layer, wherein a plurality of first auxiliary openings for exposing the first seed layer are formed on the first sacrificial dielectric layer, and the first auxiliary openings correspond to the first openings in a vertical direction;

[0024] forming a first metal wiring layer on the first seed layer corresponding to the first auxiliary opening, and removing the first sacrificial dielectric layer and the first seed layer corresponding thereto to expose the first patterned dielectric layer at the corresponding position;

[0025] forming a pad patterned dielectric layer on the first patterned dielectric layer and the first metal wiring layer, wherein a plurality of pad openings exposing the first metal wiring layer are formed on the pad patterned dielectric layer;

[0026] forming a continuous second seed layer on the surface of the pad patterned dielectric layer and the exposed first metal wiring layer;

[0027] forming a second sacrificial dielectric layer on the second seed layer, wherein a plurality of second auxiliary openings for exposing the second seed layer are formed on the second sacrificial dielectric layer, and the second auxiliary openings correspond to the pad openings in a vertical direction;

[0028] The electrical interconnect pad is formed on the second seed layer corresponding to the second auxiliary opening, and the second sacrificial dielectric layer and the second seed layer corresponding thereto are removed to expose the second patterned dielectric layer at the corresponding position.

[0029] Optionally, before forming the pad patterned dielectric layer, the method further includes forming an Nth patterned dielectric layer and an Nth metal wiring layer, wherein the uppermost metal wiring layer is electrically connected to the electrical interconnection pad.

[0030] Optionally, the first patterned dielectric layer includes a photoresist layer, and the thickness of the first patterned dielectric layer is between 5-10μm; the first seed layer includes at least one of a titanium layer, a copper layer, a nickel layer, a palladium layer, a gold layer, a tin layer and a silver layer, and the thickness of the first seed layer is between 0.5-1.5μm; the thickness of the first metal wiring layer is between 5-10μm; the pad patterned dielectric layer includes a photoresist layer, and the thickness of the pad patterned dielectric layer is between 5-10μm; the second seed layer includes at least one of a titanium layer, a copper layer, a nickel layer, a palladium layer, a gold layer, a tin layer and a silver layer, and the thickness of the second seed layer is between 0.5-1.5μm; the thickness of the electrical interconnect pad is between 8-15μm.

[0031] Optionally, one side of the rewiring structure formed with the electrical interconnection pad is also formed with a first metal bonding layer having a spacing with the electrical interconnection pad, and the reformed photoresist layer is formed between the chip to be packaged and the first metal bonding layer.

[0032] Optionally, before loading the reconstructed connection structure onto the semiconductor substrate, the step further includes: forming a second bonding metal layer on the surface of the semiconductor substrate around the cavity to be embedded and forming solder at the bottom of the cavity to be embedded, wherein the first metal bonding layer is bonded to the second bonding metal layer.

[0033] Optionally, before loading the reconstructed connection structure onto the semiconductor substrate, the step of forming an adhesive layer on the surface of the semiconductor substrate around the cavity to be embedded and forming solder at the bottom of the cavity to be embedded, wherein the rewiring structure around the reformed photoresist layer is bonded to the adhesive layer.

[0034] Optionally, the reformed photoresist layer covers the side of the chip to be packaged and fills the gap between the chip to be packaged and the rewiring structure, and the thickness of the reformed photoresist layer is between 100-200 μm.

[0035] Optionally, an air bridge is formed on the chip to be packaged, and the air bridge is located on a side of the chip to be packaged close to the chip pad.

[0036] The present invention further provides a microsystem module chip embedded packaging structure, wherein the packaging structure is preferably packaged by the packaging method of the present invention, and of course, other packaging methods may also be used. The packaging structure includes:

[0037] a semiconductor substrate having a cavity to be embedded formed therein;

[0038] The chip to be packaged has a front side and a back side opposite to each other, the back side of the chip to be packaged is formed at the bottom of the cavity to be embedded, and a chip pad is formed on the front side of the chip to be packaged;

[0039] A rewiring structure having a first surface and a second surface opposite to each other, wherein the first surface is close to the chip to be packaged and an electrical interconnection pad is formed on the first surface, and the electrical interconnection pad is connected to the chip pad;

[0040] A reformed photoresist layer is formed on the periphery of the chip to be packaged, the outer edge size of the reformed photoresist layer is the same as the size of the cavity to be embedded, and fills the gap between the chip to be packaged and the side wall of the cavity to be embedded.

[0041] Optionally, the rewiring structure includes a rewiring layer, wherein the rewiring layer includes at least one metal wire layer and at least one dielectric layer, the metal wire layer is located in the dielectric layer to form a metal interconnection structure, and the electrical interconnection pad is formed on the rewiring layer and electrically connected to the metal interconnection structure.

[0042] Optionally, a bonding layer is formed between the semiconductor substrate around the cavity to be embedded and the rewiring structure around the reformatted photoresist layer, wherein the bonding layer includes any one of a metal bonding layer and an adhesive layer.

[0043] Optionally, the reformed photoresist layer covers the side of the chip to be packaged and fills the gap between the chip to be packaged and the rewiring structure, and the thickness of the reformed photoresist layer is between 100-200 μm.

[0044] Optionally, an air bridge is provided on the chip to be packaged, and the air bridge is located on a side of the chip to be packaged close to the chip pad.

[0045] As described above, the present invention provides a microsystem module chip embedded packaging structure and packaging method. By reshaping the photoresist around the chip to be packaged in a rewiring process from top to bottom, a rewiring structure is first made on a temporary carrier substrate, and then the side of the chip to be packaged with the chip pad and the electrical interconnection pad on the rewiring structure are reflowed, and then the outer layer of the chip to be packaged is reshaped with a thick film photoresist, and finally the reshaped chip to be packaged with the rewiring structure is buckled into the groove of the semiconductor substrate. The use of thick film photoresist to reshape the outer layer of the chip can reduce the back-end cutting error and the front-end cutting error. The matching of etching errors is converted into matching of the errors of the front-end photolithography and the errors of the front-end etching, thereby greatly reducing the remaining width around the silicon cavity after the chip is embedded, thereby eliminating the suspended wiring structure and improving the overall reliability of the module; firstly interconnect the chip pads of the chip to be packaged with the rewiring structure, and then embed the chip, thereby avoiding the problem of electrical interconnection failure caused by deviation between the wiring and the interconnection PAD on the chip; first make the rewiring structure and then connect the rewiring structure to the chip to be packaged, thereby avoiding the surface of the chip to be packaged from being subjected to high-intensity processes again and again, and avoiding damage to the structure on the surface of the chip to be packaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Shown is a flow chart of the microsystem module chip embedded packaging method of the present invention.

[0047] Figure 2 Shown is a schematic structural diagram of providing a temporary bonding substrate in an example of the present invention.

[0048] Figure 3 Shown is a schematic structural diagram of forming a temporary bonding layer in an example of the present invention.

[0049] Figure 4 It is a schematic structural diagram of forming a first patterned dielectric layer in one example of the present invention.

[0050] Figure 5 It is a schematic diagram showing the structure of forming a first seed layer in an example of the present invention.

[0051] Figure 6 It is a schematic diagram showing a structure of forming a first sacrificial dielectric layer in an example of the present invention.

[0052] Figure 7 It is a schematic diagram showing the structure of forming the first metal wiring layer in one example of the present invention.

[0053] Figure 8 It is a schematic diagram showing a structure in which the first sacrificial dielectric layer and a portion of the first seed layer are removed in an example of the present invention.

[0054] Fig. 9It is a schematic diagram showing the structure of forming a pad patterned dielectric layer in one example of the present invention.

[0055] Fig.10 It is a schematic diagram showing a structure of forming a second seed layer in an example of the present invention.

[0056] Fig.11 It is a schematic diagram showing a structure of forming a second sacrificial dielectric layer in an example of the present invention.

[0057] Fig.12 It is a schematic diagram showing a structure for forming an electrical interconnection pad in an example of the present invention.

[0058] Fig.13 It is a schematic diagram showing a structure in which the second sacrificial dielectric layer and a portion of the second seed layer are removed in an example of the present invention.

[0059] Fig.14 Shown is a schematic structural diagram of the second sacrificial dielectric layer in another example of the present invention.

[0060] Fig.15 Shown as the present invention Fig.14 Schematic diagram of the structure of depositing material layers to form electrical interconnect pads in an example.

[0061] Fig.16 Shown as the present invention Fig.14 Schematic diagram of the structure of forming electrical interconnect pads and a first metal bonding layer in an example.

[0062] Fig.17 It is a schematic diagram showing the structure of a chip to be packaged in one example of the present invention.

[0063] Fig.18 It is a schematic diagram showing a structure of forming a photoresist layer in an example of the present invention.

[0064] Fig.19 It is a schematic diagram showing a structure of forming a reformed photoresist layer in one example of the present invention.

[0065] Fig. 20 Shown as the present invention Fig.14 A schematic diagram of the structure for forming a reformed photoresist layer in the example shown.

[0066] Fig.21 Shown is a schematic structural diagram of a semiconductor substrate provided in an example of the present invention.

[0067] Fig. 22 It is a schematic diagram showing the structure of forming a bonding layer and solder in one example of the present invention.

[0068] Fig.23 It is a schematic diagram showing the structure of burying the chip to be packaged into the cavity to be embedded in one example of the present invention.

[0069] Fig.24 Shown as the present invention Fig.14 The schematic diagram of the structure of burying the chip to be packaged into the cavity to be embedded is shown.

[0070] Fig.25 It is a schematic structural diagram of peeling off a temporary carrier substrate to form a chip embedded module structure in one example of the present invention.

[0071] Fig.26 Shown is the bottom-up embedded chip interconnect process for a traditional silicon interposer.

[0072] Component number description

[0073] 100 Temporary bearing base

[0074] 101 Temporary bonding layer

[0075] 102 first patterned dielectric layer

[0076] 102a First opening

[0077] 103 First seed layer

[0078] 104 first sacrificial dielectric layer

[0079] 104a First auxiliary opening

[0080] 105 First metal wiring layer

[0081] 106 Pad patterning dielectric layer

[0082] 106a Pad opening

[0083] 107 Second seed layer

[0084] 108 second sacrificial dielectric layer

[0085] 108a Second auxiliary opening

[0086] 109 Electrical interconnect pads

[0087] 110 Rewiring Structure

[0088] 111 First metal bonding layer

[0089] 200 Chips to be packaged

[0090] 201 Air Bridge

[0091] 202 photoresist layer

[0092] 203 Reshaping the photoresist layer

[0093] 300 Semiconductor Substrate

[0094] 301 Cavity to be embedded

[0095] 302 Bonding layer

[0096] 303 solder

[0097] Steps S1 to S7 DETAILED DESCRIPTION

[0098] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0099] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0100] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0101] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0102] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0103] like Figure 1 As shown, the present invention provides a microsystem module chip embedded packaging method, the packaging method comprising the following steps:

[0104] S1: Provide a temporary bearing base;

[0105] S2: forming a rewiring structure on the temporary carrier substrate, wherein an electrical interconnection pad is formed on the surface of the rewiring structure;

[0106] S3: providing a chip to be packaged having a front side and a back side opposite to each other, wherein a chip pad is formed on the front side, and the chip to be packaged is flipped on the rewiring structure, wherein the chip pad is connected to the electrical interconnection pad;

[0107] S4: forming a reformed photoresist layer on the rewiring structure, wherein the reformed photoresist layer surrounds the chip to be packaged, and the upper surface of the reformed photoresist layer is flush with the back surface of the chip to be packaged, thereby obtaining a reconstructed connection structure;

[0108] S5: providing a semiconductor substrate, wherein a cavity to be embedded is formed in the semiconductor substrate, and the outer edge size of the reformed photoresist layer is the same as the size of the cavity to be embedded;

[0109] S6: loading the reconstructed connection structure onto the semiconductor substrate, wherein the chip to be packaged and the reformed photoresist layer are buried in the cavity to be embedded; and

[0110] S7: removing the temporary supporting substrate to obtain a chip embedded module structure.

[0111] The embedded packaging method of the microsystem module chip of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the embedded packaging method of the microsystem module chip of the present invention, and those skilled in the art may change it according to the actual process steps. Figure 1 Only the steps of the microsystem module chip embedded packaging method in one example are shown.

[0112] First, if Figure 1 S1 and Figure 2 As shown, step S1 is performed to provide a temporary carrier substrate 100. The temporary carrier substrate 100 can be a temporary carrier wafer, which can be a high-resistance silicon wafer, a low-resistance silicon wafer, an SOI wafer, a glass carrier, a gallium nitride substrate, and a gallium arsenide substrate, etc., which are peeled off in the subsequent process to obtain a packaging structure.

[0113] Then, if Figure 1 S2 and Figure 3-16 As shown, step S2 is performed to form a rewiring structure 110 on the temporary carrier substrate 100, and an electrical interconnection pad 109 is formed on the surface of the rewiring structure 110. The rewiring structure 110 can realize line layout according to actual needs, and can realize electrical lead-out and electrical connection of the chip according to actual needs.

[0114] As an example, the steps of forming the rewiring structure 110 include:

[0115] First, if Figure 3 As shown, a temporary bonding layer 101 is formed on the temporary carrier substrate 100. In one example, the temporary bonding layer 101 includes any one of a thermally degradable glue (heat-removable glue) and an ultraviolet-light-degradable glue (ultraviolet-light-removable glue). Of course, the temporary bonding layer 101 may also be a temporary bonding glue, wherein the temporary bonding glue is a type of glue commonly used in the semiconductor industry, and is a liquid glue-like glue. In one example, a temporary bonding glue with a thickness ranging from 1 to 100 μm, which may be 10 μm, 20 μm, or 50 μm, may be applied to the temporary carrier substrate 100, and then the glue is cured to obtain the temporary bonding layer 101, which is used for subsequent peeling.

[0116] Then, if Figure 4-11 and Fig.14 As shown, a rewiring layer is formed on the temporary bonding layer, and the rewiring layer includes at least one metal wire layer (such as the first metal wire layer 105) and at least one dielectric layer (such as the first patterned dielectric layer 102). The metal wire layer is located in the dielectric layer to form a metal interconnection structure. The metal interconnection structure may refer to a metal conductive structure formed by electrically connecting metal wire layers of different layers in the rewiring layer through the dielectric layer according to actual needs.

[0117] Finally, if Fig.12 , 13 and Fig.15 , 16 As shown, the electrical interconnect pad 109 electrically connected to the metal interconnect structure is formed on the rewiring layer. The electrical interconnect pad 109 is electrically connected to the metal interconnect structure, so that the connection with the external components can be realized based on the electrical interconnect pad 109, and the required routing arrangement can be realized based on the metal interconnect structure.

[0118] In one example, the steps of forming the rewiring layer and the electrical interconnect pad 109 include:

[0119] First, if Figure 4As shown, a first patterned dielectric layer 102 is formed on the temporary bonding layer 101, and a plurality of first openings 102a are formed on the first patterned dielectric layer 102 to expose the temporary bonding layer 101. The first patterned dielectric layer 102 may be a patterned photoresist layer, and the thickness of the first patterned dielectric layer 102 is between 5-10 μm, and may be 6 μm, 8 μm, or 9 μm, wherein the first openings 102a may be obtained by exposure and development, and may be used to form a pattern of an external interconnection PAD. The number and size of the first openings 102a may be set according to actual needs. In addition, the photoresist may be a positive photoresist or a negative photoresist, and the coating method may be a spin coating method or may be directly pasted with a dry film.

[0120] Then, if Figure 5 As shown, a continuous first seed layer 103 is formed on the surface of the first patterned dielectric layer 102 and the exposed temporary bonding layer 101. As an example, the first seed layer 103 includes at least one of a titanium layer, a copper layer, a nickel layer, a palladium layer, a gold layer, a tin layer and a silver layer, and can be one of them, or a laminated structure composed of the above material layers. The thickness of the first seed layer 103 is between 0.5-1.5μm, and can be 0.8μm, 1μm, 10.μm. In addition, the first seed layer 103 can be formed by evaporation, chemical vapor deposition, physical vapor deposition, etc.

[0121] Then, if Figure 6 As shown, a first sacrificial dielectric layer 104 is formed on the first seed layer 103, and a plurality of first auxiliary openings 104a are formed on the first sacrificial dielectric layer 104 to expose the first seed layer 103. The first auxiliary openings 104a correspond to the first openings 102a in a vertical direction, wherein the vertical correspondence between the two means that there is an intersecting area between the two openings in a vertical direction. In an example, the size of the first auxiliary opening 104a is larger than the size of the first opening 102a, that is, the first auxiliary opening 104a is equivalent to covering the first opening 102a, see Figure 6 The structure is shown. The material of the first sacrificial dielectric layer 104 can be photoresist, which can be positive or negative, and the coating method can be spin coating or direct pasting with dry film, and the first auxiliary opening 104a is formed by exposure and development, and the photoresist pattern of the rewiring RDL is formed to obtain the first sacrificial dielectric layer 104.

[0122] Then, if Figure 7-8As shown, a first metal wiring layer 105 is formed on the first seed layer 103 corresponding to the first auxiliary opening 104a, and the first sacrificial dielectric layer 104 and the first seed layer 103 corresponding thereto are removed, that is, the material of the first sacrificial dielectric layer 104 around the first auxiliary opening 104a and the material of the first seed layer 103 directly below this part of the material are removed to expose the first patterned dielectric layer 102 at the corresponding position. The first metal layer 105 may be formed by electroplating, and the thickness of the first metal wiring layer 105 is between 5-10 μm, and may be 6 μm, 8 μm, or 9 μm. In addition, the removal method of the first seed layer 103 may be dry etching or wet etching.

[0123] Then, if Fig. 9 As shown, a pad patterned dielectric layer 106 is formed on the first patterned dielectric layer 102 and the first metal wiring layer 105, and a plurality of pad openings 106a are formed on the pad patterned dielectric layer 106 to expose the first metal wiring layer 105. The pad patterned dielectric layer 106 can be a patterned photoresist layer, and the thickness of the pad patterned dielectric layer 106 is between 5-10 μm, and can be 6 μm, 8 μm, and 9 μm. The pad openings 106a can be obtained by exposure and development, and can be used to form the pattern of the external interconnection PAD. In addition, the photoresist can be a positive photoresist or a negative photoresist, and the coating method can be a spin coating method or a dry film can be directly pasted.

[0124] Then, if Fig.10 As shown, a continuous second seed layer 107 is formed on the surface of the pad patterned dielectric layer 106 and the exposed first metal wiring layer 105. As an example, the second seed layer 107 includes at least one of a titanium layer, a copper layer, a nickel layer, a palladium layer, a gold layer, a tin layer and a silver layer. It can be one of them or a laminated structure composed of the above material layers. The thickness of the second seed layer 107 is between 0.5-1.5μm, and can be 0.8μm, 1μm, or 1.2μm. In addition, the second seed layer 107 can be formed by evaporation, chemical vapor deposition, physical vapor deposition, etc.

[0125] Then, if Fig.11As shown, a second sacrificial dielectric layer 108 is formed on the second seed layer 107, and a plurality of second auxiliary openings 108a are formed on the second sacrificial dielectric layer 108 to expose the second seed layer 107. The second auxiliary openings 108a correspond to the pad openings 106a in a vertical direction, wherein the vertical correspondence between the two means that there is an intersecting area between the two openings in a vertical direction. In an example, the size of the second auxiliary opening 108a is larger than the size of the pad opening 106a, that is, the second auxiliary opening 108a is equivalent to covering the pad opening 106a, see Fig.11 The structure is shown. The material of the second sacrificial dielectric layer 108 can be photoresist, which can be positive or negative, and the coating method can be spin coating or direct pasting with a dry film, and the second auxiliary opening 108a is formed by exposure and development, and a photoresist pattern of the rewiring RDL is formed to obtain the second auxiliary opening 108a.

[0126] Finally, if Figure 12-13 As shown, the electrical interconnect pad 109 is formed on the second seed layer 107 corresponding to the second auxiliary opening 108a, and the second sacrificial dielectric layer 108 and the corresponding second seed layer 107 thereunder are removed, that is, the material of the second sacrificial dielectric layer 108 around the second auxiliary opening 108a and the material of the second seed layer 107 directly below this part of the material are removed to reveal the second patterned dielectric layer 106 at the corresponding position. The electrical interconnect pad 109 may be formed by electroplating, and the material may be tin-silver. At the same time, those skilled in the art may understand that the material used in this electroplating step may be arbitrarily selected to achieve good coordination with subsequent steps. The thickness of the electrical interconnect pad 109 is between 8-15 μm, and may be 10 μm, 12 μm, or 13 μm. In addition, the removal method corresponding to the second seed layer 107 may be dry etching or wet etching. Thus, a rewiring structure 110 with an electrical interconnect pad is formed.

[0127] As an example, before forming the pad patterned dielectric layer 106, the steps of forming up to the Nth patterned dielectric layer and the Nth metal wiring layer are also included, wherein the uppermost metal wiring layer is electrically connected to the electrical interconnection pad 109. That is to say, after forming the first patterned dielectric layer 102 and the first metal wiring layer 105, the steps of forming the second patterned dielectric layer and the second metal wiring layer thereon are also included, wherein the second metal wiring layer is electrically connected to the first metal wiring layer 105 according to the actual design, and the second metal wiring layer is electrically connected to the electrical interconnection pad 109 according to the actual situation to form a metal interconnection structure. Further, the steps of continuing to form up to the Nth patterned dielectric layer and the Nth metal wiring layer are also included, wherein the steps of forming the second patterned dielectric layer to the Nth patterned dielectric layer can refer to the steps of forming the first patterned dielectric layer 102, and the steps of forming the second metal wiring layer to the Nth metal wiring layer can refer to the steps of forming the first metal wiring layer 106, wherein N is an integer greater than or equal to 2.

[0128] In another example, if Figure 14-16 As shown, one side of the rewiring structure 110 formed with the electrical interconnection pad 109 is also formed with a first metal bonding layer 111 with a spacing from the electrical interconnection pad 109. Fig.16 As shown, an electrical interconnect pad 109 and a first metal bonding layer 111 are formed on the same surface of the rewiring structure 110 with a distance therebetween, wherein the first metal bonding layer 111 can be used for a subsequent bonding process.

[0129] In one example, the step of forming the first metal bonding layer 111 may be:

[0130] like Fig.14 As shown, in the formed second sacrificial dielectric layer 108, not only the second auxiliary opening 108a is formed, but also the bonding layer opening 108b is formed based on the same process; then, as shown in FIG. Fig.15 As described above, while forming the electrical interconnect pad 109, the first metal bonding layer 111 is also formed on the second seed layer 107 corresponding to the bonding layer opening 108b. Finally, as described above, Fig.16 As shown, the material of the second sacrificial dielectric layer 108 around the second auxiliary opening 108 a and the bonding layer opening 108 b and the material of the second seed layer 107 directly below this portion of material are removed.

[0131] Then, if Figure 1 S3 and Fig.17As shown, step S3 is performed, providing a chip 200 to be packaged with a relative front and back, the front side is formed with a chip pad (not shown in the figure), the chip 200 to be packaged is flipped on the rewiring structure 110, and the chip pad is connected to the electrical interconnection pad 109. In this step, the chip 200 to be packaged (such as a bare chip) is reflowed onto the PAD (the electrical interconnection pad 109) on the rewiring layer of the temporary carrier wafer to achieve the PAD connection between the chip PAD and the RDL.

[0132] In one example, an air bridge 201 is formed on the chip to be packaged 200, the air bridge 201 is located on the side of the chip to be packaged 200 close to the chip pad, and the front of the chip to be packaged 200 has an air bridge 201. Through the top-down process structure of the present invention, the shielding of the air bridge 201 caused by the traditional process preparation can be avoided.

[0133] As an example, after the chip pad is connected to the electrical interconnection pad 109, a reflow step is performed. In one example, the connected RDL layer and the bare chip are placed in a reflow furnace for reflow. The reflow process is conducive to the stable electrical interconnection between the chip to be packaged and the circuit. The upper and lower metal layers can be heated to fuse the metals on both sides together, which is conducive to forming a stable mechanical connection and electrical connection. In addition, those skilled in the art can understand that the temperature curve used in this reflow step can be arbitrarily selected to achieve a good interconnection result.

[0134] Then, if Figure 1 S4 and Figure 18-20 As shown, step S4 is performed to form a reformed photoresist layer 203 on the rewiring structure 110, the reformed photoresist layer 203 surrounds the chip to be packaged 200, and the upper surface of the reformed photoresist layer 203 is flush with the back surface of the chip to be packaged 200, and the back surface of the chip is exposed to obtain a reconstructed connection structure. In this step, the chip pad of the chip to be packaged 200 is electrically connected to the electrical interconnection pad 109 of the rewiring structure, and then the photoresist is reshaped. Using thick film photoresist to reshape the outer layer of the chip can convert the matching of the back-end cutting error and the front-end etching error into the matching of the front-end photolithography error and the front-end etching error, thereby greatly reducing the remaining width around the silicon cavity after the embedded chip, thereby eliminating the dangling wiring structure and improving the overall reliability of the module.

[0135] In one example, a photoresist layer 202 may be formed on the rewiring structure on which the chip 200 to be packaged is formed. Fig.18As shown, the glue coating method here can be spin coating or scraping glue; the photoresist can be positive or negative. The upper surface of the photoresist layer 202 is flush with the back surface of the chip to be packaged 200. Optionally, the photoresist layer covers the periphery of the chip to be packaged 200. In one example, the photoresist layer not only surrounds and covers the left and right sides of the chip to be packaged, but also fills the gap between the upper and lower chips to be packaged and the rewiring structure; then, as shown in FIG. Fig.19 As shown, the formed photoresist layer is then exposed and developed to obtain the reformed photoresist layer 203 .

[0136] In one example, the thickness of the reformed photoresist layer 203 is between 100-200 μm, for example, it can be 120 μm or 150 μm. In one example, the minimum width of the reformed photoresist layer 203 is greater than the error value of the chip cutting back process, wherein the minimum width of the reformed photoresist layer 203 is greater than 0, that is, it is ensured that a photoresist layer is formed around the chip, and further greater than the error value of the chip cutting back process, which is conducive to ensuring the stability of the process. The minimum width of the reformed photoresist layer 203 refers to the width value of the position where the photoresist layer corresponds to the smallest width of the chip periphery, that is, the photoresist thickness corresponding to the maximum protrusion position of the chip. For example, in one example, chip cutting uses a rough back-end process, which may cause a size deviation of about plus or minus 50um, while the photoresist exposure process uses a front-end process with a size deviation of about plus or minus 5 microns. When the chip size is 1000*1000um, the cut size varies between 1000*1000 and 1050*1050um. Through the above scheme, by adding a step of photoresist, chips with deviations of 1000*1000 to 1050*1050 can be standardized within a size of, for example, 1100*1100 to 1105*1105 by wrapping a circle of photoresist on the outside, or other sizes greater than or equal to 1050*1050, thereby avoiding the situation of dangling wiring.

[0137] In another example, if Fig. 20 As shown, when the first metal bonding layer 111 is formed, the reformed photoresist layer 203 fills up the gap between the first metal bonding layer 111 and the chip 200 to be packaged.

[0138] Then, if Figure 1 S5 and Fig.21As shown, step S5 is performed to provide a semiconductor substrate 300, wherein the semiconductor substrate 300 can be a silicon adapter plate, a cavity 301 (silicon cavity) to be embedded is formed in the semiconductor substrate 300, and the outer edge size of the reformed photoresist layer 203 is the same as the size of the cavity 301 to be embedded, that is, the reformed photoresist layer 203 can just enter the cavity 301 to be embedded. The chip pad of the chip to be packaged is first interconnected with the rewiring structure and then the chip is embedded, thereby avoiding the problem of electrical interconnection failure caused by the deviation of the interconnection PAD on the routing and the chip. The rewiring structure is first made and then the rewiring structure is connected to the chip to be packaged, thereby avoiding the surface of the chip to be packaged from bearing a high-intensity process again and again, and avoiding damage to the structure on the surface of the chip to be packaged.

[0139] Then, if Figure 1 S6 and Figure 22-23 As shown, step S6 is performed to load the reconstructed connection structure onto the semiconductor substrate, wherein the chip 200 to be packaged and the reformed photoresist layer 203 are buried in the cavity to be embedded.

[0140] As an example, Fig. 22 As shown, before the reconstructed connection structure is loaded on the semiconductor substrate, the steps are also included: forming a bonding layer 302 on the surface of the semiconductor substrate around the cavity 301 to be embedded and forming a solder 303 at the bottom of the cavity 301 to be embedded, wherein the rewiring structure 110 around the reformed photoresist layer is bonded to the bonding layer 302, that is, when the reformed photoresist layer 203 surrounding the chip to be packaged just enters the cavity 301 to be embedded, the surface of the rewiring structure around the reformed photoresist layer 203 is just bonded to the bonding layer 302, so as to achieve wafer-level bonding between the rewiring structure and the semiconductor substrate. The solder 303 applied to the silicon adapter with silicon cavity can be selected according to actual conditions. Those skilled in the art can understand that the adapter with silicon cavity here can include more than one functional structure of silicon cavity, and can also include a series of functional structures such as TSV structure and microchannel structure for conducting signals.

[0141] In one example, two implementations of wafer-level bonding are provided:

[0142] like Fig.23As shown, the first bonding method is wafer-level bonding by bonding. The bonding layer 302 is selected as an adhesive layer, and the adhesive layer can be an adhesive. In one example, a layer of adhesive with a thickness of 9-15 microns is coated on the silicon adapter plate (the semiconductor substrate 300) with a silicon cavity, and then solder 303 is added to the bottom of the silicon cavity (the cavity 301 to be embedded), and then the carrier wafer with RDL and the reshaped bare chip is pressed and cured with the bonding adhesive on the semiconductor substrate 300, and then placed in a reflow furnace for reflow to form the final bonding structure. The coating method of the adhesive here can be spin coating or direct pasting with a dry film; the solder at the bottom of the cavity 301 to be embedded can be solder paste or solder sheet.

[0143] like Fig.24 As shown, another bonding method is to use metal bonding to perform wafer-level bonding. When the first metal bonding layer 111 is formed, the bonding layer 302 is selected as the second bonding metal layer. In one example, a bonding metal layer with a thickness of 8 to 15 microns is formed on a silicon adapter plate with a cavity (the semiconductor substrate 300), and then solder 303 is placed at the bottom of the cavity. Finally, the carrier wafer with the chip RDL and the adapter plate wafer are pressed and reflowed to obtain the final bonding structure. The bonding metal layer material here can be a titanium copper layer, and layers such as nickel, palladium, gold, tin, and silver can also be added.

[0144] Finally, if Figure 1 S7 and Fig.24 As shown, step S7 is performed to remove the temporary carrier substrate 100 to obtain a chip embedded module structure. In one example, a temporary bonding layer 101 is formed on the surface of the temporary carrier substrate 100, and the temporary carrier substrate and the rewiring layer are separated based on the decomposition of the temporary bonding layer 101.

[0145] In addition, the present invention also provides a microsystem module chip embedded packaging structure, wherein the packaging structure is preferably packaged by the packaging method of the present invention, and of course, other methods can also be used for packaging, wherein the features and related descriptions of the packaging structure can refer to the description of the above packaging method, and will not be repeated here. The packaging structure includes:

[0146] A semiconductor substrate 300, wherein a cavity 301 to be embedded is formed in the semiconductor substrate 300;

[0147] The chip to be packaged 200 has a front side and a back side opposite to each other. The back side of the chip to be packaged 200 is formed at the bottom of the cavity to be embedded 301, and a chip pad (not shown in the figure) is formed on the front side of the chip to be packaged 200.

[0148] The rewiring structure 110 has a first surface and a second surface opposite to each other, wherein the first surface is close to the chip 200 to be packaged, and an electrical interconnection pad 109 is formed on the first surface, and the electrical interconnection pad 109 is connected to the chip pad;

[0149] The reformed photoresist layer 203 is formed on the periphery of the chip 200 to be packaged. The outer edge size of the reformed photoresist layer 203 is the same as the size of the cavity 301 to be embedded, and fills the gap between the chip 200 to be packaged and the side wall of the cavity 301 to be embedded.

[0150] As an example, the rewiring structure includes a rewiring layer, wherein the rewiring layer includes at least one metal wire layer and at least one dielectric layer, the metal wire layer is located in the dielectric layer to form a metal interconnection structure, and the electrical interconnection pad 109 is formed on the rewiring layer and electrically connected to the metal interconnection structure.

[0151] As an example, a bonding layer 302 is formed between the surface of the semiconductor substrate 300 around the cavity 301 to be embedded and the rewiring structure around the reformatted photoresist layer 203 , wherein the bonding layer 302 includes any one of a metal bonding layer and a bonding layer.

[0152] As an example, the chip to be packaged 200 has an air bridge 201 , and the air bridge 201 is located on a side of the chip to be packaged 200 close to the chip pad.

[0153] As an example, the reformed photoresist layer 203 covers the side of the chip to be packaged 200 and fills the gap between the chip to be packaged 200 and the rewiring structure 110 . The thickness of the reformed photoresist layer is between 100-200 μm.

[0154] In summary, the present invention provides a microsystem module chip embedded packaging structure and packaging method. The method of reshaping the photoresist around the chip to be packaged by performing a rewiring process from top to bottom, firstly, a rewiring structure is made on a temporary carrier substrate, and then the side of the chip to be packaged with the chip pad and the electrical interconnection pad on the rewiring structure are reflowed, and then the outer layer of the chip to be packaged is reshaped with a thick film photoresist, and finally the reshaped chip to be packaged with the rewiring structure is buckled into the groove of the semiconductor substrate. The use of thick film photoresist to reshape the outer layer of the chip can reduce the back-end cutting error and the front-end cutting error. The matching of etching errors is converted into the matching of the errors of the front-end photolithography and the errors of the front-end etching, thereby greatly reducing the remaining width around the silicon cavity after the embedded chip, thereby eliminating the suspended wiring structure and improving the overall reliability of the module; firstly interconnect the chip pads of the chip to be packaged with the rewiring structure, and then embed the chip, thereby avoiding the problem of electrical interconnection failure caused by the deviation of the interconnection PAD on the wiring and the chip; first make the rewiring structure and then connect the rewiring structure to the chip to be packaged, thereby avoiding the surface of the chip to be packaged from bearing the high-intensity process again and again, and avoiding the damage to the structure on the surface of the chip to be packaged. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0155] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A microsystem module chip embedded packaging method, characterized in that: The packaging method comprises the following steps: Providing a temporary bearing base; forming a rewiring structure on the temporary carrier substrate, wherein an electrical interconnection pad is formed on the surface of the rewiring structure; Providing a chip to be packaged having a front side and a back side opposite to each other, wherein a chip pad is formed on the front side, and the chip to be packaged is flipped on the rewiring structure, wherein the chip pad is connected to the electrical interconnection pad; Forming a reformed photoresist layer on the rewiring structure, wherein the reformed photoresist layer surrounds the chip to be packaged, and the upper surface of the reformed photoresist layer is flush with the back surface of the chip to be packaged, to obtain a reconstructed connection structure; Providing a semiconductor substrate, wherein a cavity to be embedded is formed in the semiconductor substrate, and the outer edge size of the reformed photoresist layer is the same as the size of the cavity to be embedded; Loading the reconstructed connection structure on the semiconductor substrate, wherein the chip to be packaged and the reformed photoresist layer are buried in the cavity to be embedded; as well as The temporary supporting substrate is removed to obtain a chip embedded module structure.

2. The microsystem module chip embedded packaging method according to claim 1, characterized in that: The steps of forming the rewiring structure include: forming a temporary bonding layer on the temporary supporting substrate; forming a rewiring layer on the temporary bonding layer, wherein the rewiring layer comprises at least one metal wire layer and at least one dielectric layer, wherein the metal wire layer is located in the dielectric layer to form a metal interconnect structure; The electrical interconnect pad electrically connected to the metal interconnect structure is formed on the rewiring layer.

3. The microsystem module chip embedded packaging method according to claim 2, characterized in that: The steps of forming the rewiring layer and the electrical interconnect pads include: forming a first patterned dielectric layer on the temporary bonding layer, wherein a plurality of first openings exposing the temporary bonding layer are formed on the first patterned dielectric layer; forming a continuous first seed layer on the surface of the first patterned dielectric layer and the exposed temporary bonding layer; forming a first sacrificial dielectric layer on the first seed layer, wherein a plurality of first auxiliary openings for exposing the first seed layer are formed on the first sacrificial dielectric layer, and the first auxiliary openings correspond to the first openings in a vertical direction; forming a first metal wiring layer on the first seed layer corresponding to the first auxiliary opening, and removing the first sacrificial dielectric layer and the first seed layer corresponding thereto to expose the first patterned dielectric layer at the corresponding position; forming a pad patterned dielectric layer on the first patterned dielectric layer and the first metal wiring layer, wherein a plurality of pad openings exposing the first metal wiring layer are formed on the pad patterned dielectric layer; forming a continuous second seed layer on the surface of the pad patterned dielectric layer and the exposed first metal wiring layer; forming a second sacrificial dielectric layer on the second seed layer, wherein a plurality of second auxiliary openings for exposing the second seed layer are formed on the second sacrificial dielectric layer, and the second auxiliary openings correspond to the pad openings in a vertical direction; The electrical interconnection pad is formed on the second seed layer corresponding to the second auxiliary opening, and the second sacrificial dielectric layer and the corresponding second seed layer thereunder are removed to expose the pad patterned dielectric layer at the corresponding position.

4. The microsystem module chip embedded packaging method according to claim 3, characterized in that: Before forming the pad patterned dielectric layer, the method further includes forming an Nth patterned dielectric layer and an Nth metal wiring layer, wherein the uppermost metal wiring layer is electrically connected to the electrical interconnection pad.

5. The microsystem module chip embedded packaging method according to claim 3, characterized in that: The first patterned dielectric layer includes a photoresist layer, and the thickness of the first patterned dielectric layer is between 5-10μm; the first seed layer includes at least one of a titanium layer, a copper layer, a nickel layer, a palladium layer, a gold layer, a tin layer and a silver layer, and the thickness of the first seed layer is between 0.5-1.5μm; the thickness of the first metal wiring layer is between 5-10μm; the pad patterned dielectric layer includes a photoresist layer, and the thickness of the pad patterned dielectric layer is between 5-10μm; the second seed layer includes at least one of a titanium layer, a copper layer, a nickel layer, a palladium layer, a gold layer, a tin layer and a silver layer, and the thickness of the second seed layer is between 0.5-1.5μm; the thickness of the electrical interconnect pad is between 8-15μm.

6. The microsystem module chip embedded packaging method according to claim 1, characterized in that: A first metal bonding layer having a spacing with the electrical interconnection pad is also formed on one side of the rewiring structure having the electrical interconnection pad, and the reformed photoresist layer is formed between the chip to be packaged and the first metal bonding layer.

7. The embedded packaging method of microsystem module chip according to claim 6, characterized in that: Before loading the reconstructed connection structure onto the semiconductor substrate, the steps also include: forming a second bonding metal layer on the surface of the semiconductor substrate around the cavity to be embedded and forming solder at the bottom of the cavity to be embedded, wherein the first metal bonding layer is bonded to the second bonding metal layer.

8. The microsystem module chip embedded packaging method according to claim 1, characterized in that: Before loading the reconstructed connection structure onto the semiconductor substrate, the steps also include: forming an adhesive layer on the surface of the semiconductor substrate around the cavity to be embedded and forming solder at the bottom of the cavity to be embedded, wherein the rewiring structure around the reformed photoresist layer is bonded to the adhesive layer.

9. The microsystem module chip embedded packaging method according to claim 1, characterized in that: The reformed photoresist layer covers the side of the chip to be packaged and fills the gap between the chip to be packaged and the rewiring structure. The thickness of the reformed photoresist layer is between 100-200 μm.

10. The microsystem module chip embedded packaging method according to claim 1, characterized in that: An air bridge is formed on the chip to be packaged, and the air bridge is located on a side of the chip to be packaged close to the chip pad.

11. A microsystem module chip embedded packaging structure, characterized in that: The packaging structure comprises: a semiconductor substrate having a cavity to be embedded formed therein; The chip to be packaged has a front side and a back side opposite to each other, the back side of the chip to be packaged is formed at the bottom of the cavity to be embedded, and a chip pad is formed on the front side of the chip to be packaged; A rewiring structure having a first surface and a second surface opposite to each other, wherein the first surface is close to the chip to be packaged and an electrical interconnection pad is formed on the first surface, and the electrical interconnection pad is connected to the chip pad; A reformed photoresist layer is formed on the periphery of the chip to be packaged, wherein the outer edge size of the reformed photoresist layer is the same as the size of the cavity to be embedded, and the reformed photoresist layer fills the gap between the chip to be packaged and the side wall of the cavity to be embedded; The packaging structure is formed by adopting the microsystem module chip embedded packaging method as described in any one of claims 1-10.

12. The microsystem module chip embedded packaging structure according to claim 11, characterized in that: The rewiring structure includes a rewiring layer, wherein the rewiring layer includes at least one metal wire layer and at least one dielectric layer, the metal wire layer is located in the dielectric layer to form a metal interconnection structure, and the electrical interconnection pad is formed on the rewiring layer and electrically connected to the metal interconnection structure.

13. The microsystem module chip embedded packaging structure according to claim 11, characterized in that: A bonding layer is formed between the semiconductor substrate around the cavity to be embedded and the rewiring structure around the reformed photoresist layer, wherein the bonding layer includes any one of a metal bonding layer and an adhesive layer.

14. The microsystem module chip embedded packaging structure according to claim 11, characterized in that: The reformed photoresist layer covers the side of the chip to be packaged and fills the gap between the chip to be packaged and the rewiring structure. The thickness of the reformed photoresist layer is between 100-200 μm.

15. The microsystem module chip embedded packaging structure according to claim 11, characterized in that: The chip to be packaged is provided with an air bridge, and the air bridge is located on a side of the chip to be packaged close to the chip pad.

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