Pixelated optoelectronic devices

Abstract

A method for forming a pixelated optoelectronic stack is disclosed, the method comprising obtaining a stacked layer structure comprising a bottom electrode layer, a optoelectronic layer above the bottom electrode layer, and a patterned hard mask comprising a pattern above the optoelectronic layer; replicating the pattern into the optoelectronic layer and the bottom electrode layer to thereby obtain a first intermediate pixelated stack comprising at least two stacked islands separated from each other by non-stacked areas; providing an electrically insulating layer on the first intermediate pixelated stack; removing the top of the electrically insulating layer and removing any remaining hard mask so that the top surface of the electrically insulating layer is coplanar with the exposed top surface of the first intermediate pixelated stack; producing a second intermediate pixelated stack; and forming a top transparent electrode layer above the second intermediate pixelated stack.

Description

Technical Field

[0001] The present invention relates to an optoelectronic device and more particularly to a method for producing a pixelated optoelectronic device and a pixelated optoelectronic device that can be produced by the method. Background Art

[0002] In optoelectronic devices comprising thin film optoelectronic (TFO) layers (i.e., TFO devices), a layer stack is typically used, comprising a bottom electrode, an optoelectronic stack above the bottom electrode, and a top transparent electrode above the optoelectronic stack. The optoelectronic stack typically consists of three basic functional layers, namely an electron transport layer (ETL), an active layer, and a hole transport layer (HTL). The TFO device can be a sensing device comprising a photodiode (PD) layer, such as a thin film photodiode (TFPD) device: in this case, photons are injected into the active (here photosensitive) layer via the top transparent electrode, thereby generating electron and hole pairs in the photosensitive layer, which are extracted to the electrodes as output signals. The TFO device can be a light emitting diode (LED) instead: in this case, electrons and holes are injected into the ETL and HTL, respectively, via the electrodes, and then move into the light emitting layer, where the electrons and holes form photons, which can pass through the top transparent electrode. Although the following discussion focuses on PD devices, similar issues arise for LEDs.

[0003] A PD device may include a plurality of pixels forming a pixel array. Generally speaking, for a PD device including a pixel array, a top transparent electrode is used as a common connection for all pixels in the array. On the other hand, the bottom electrode is pixelated. Each bottom electrode pixel can generate an output signal, wherein the output signal is in principle related to the intensity of light incident on the photosensitive layer above the electrode pixel. By combining the output signals of all bottom electrode pixels, an output image can be generated, wherein the electrical signal from each pixelated bottom electrode corresponds to a pixel in the output image.

[0004] Currently, a common practice for manufacturing PD devices is to first fabricate the bottom electrode by patterning. Afterwards, a photoelectric stack is formed on the pixelated bottom electrode by spin coating, evaporation, sputtering or other deposition techniques. Typically, the bottom electrodes are electrically isolated from each other, while the photoelectric stack is continuous. For this configuration, one of the sources of noise in the pixel array is crosstalk between adjacent pixels: photocarriers generated in one pixel may diffuse horizontally into adjacent pixels through functional layers (e.g., ETL, HTL or photosensitive layer) and trigger unexpected readout signals (noise). As the pixel size decreases, the distance / gap between adjacent bottom electrodes approaches the diffusion length of the photocarriers generated in the photosensitive layer, and the crosstalk noise will increase dramatically as the pixel size decreases.

[0005] In order to prevent this crosstalk noise, a common practice is to pixelate the optoelectronic stack into the pixel so that the crosstalk between pixels can be significantly reduced. In the prior art, the bottom electrode is first pixelated by selective etching to form a bottom electrode island, and, for example, a dielectric material is selectively deposited in the electrode-free space between the islands. Thereafter, the optoelectronic stack is deposited on top of the pixelated bottom electrode. Furthermore, the optoelectronic stack can then be pixelated, for example, via etching. For example, in order to manufacture an LED array, in CN108987425, a plurality of electrode structures, which are equivalent to pixelated bottom electrodes, are first created by a process including etching. A continuous LED functional structure is generated at the top, and the structure is subsequently etched to form a plurality of LED functional structures and a first opening that penetrates the LED functional layer and is located between two adjacent LED functional structures. Then, an isolation structure is formed in the first opening. Finally, a continuous electrode connecting all pixels is deposited on top of the isolation structure.

[0006] However, the step of etching the bottom electrode, which is performed before depositing the optoelectronic stack on the (pixelated) bottom electrode, introduces defects on the top surface of the bottom electrode, which may be detrimental to the electrical contact between the bottom electrode and the optoelectronic stack. In addition, the top surface of the bottom electrode is roughened due to etching, thereby reducing its reflectivity. However, it is desirable that the top surface of the bottom electrode has a high reflectivity so that, for example, light that passes through the optoelectronic stack in the first pass without being absorbed in a PD device used as a sensor is reflected back into the optoelectronic stack by the bottom electrode so that this light may be absorbed in the second pass. Similarly, in an LED array, light emitted towards the bottom electrode is reflected back by the bottom electrode and emitted outside the top transparent electrode. In addition, in particular, the adhesion between the organic / organic-inorganic optoelectronic stack and the dielectric material deposited between the electrode islands is poor, which may lead to delamination. Finally, there is also a need in the art for a good method to improve the pixelation process of organic / organic-inorganic thin film optoelectronic devices in CMOS manufacturing, where there is little experience with such organic materials. In particular, such materials are susceptible to degradation during the pixelation process, for example due to moisture absorption or oxidation, for example immediately after the pixelation process due to exposure to the environment. Summary of the Invention

[0007] It is an object of the present invention to provide an elegant method for forming pixelated optoelectronic devices.

[0008] The above objects are achieved by the method and device according to the present invention.

[0009] An advantage of embodiments of the present invention is that the pixelation process can be easily scaled up. Another advantage of embodiments of the present invention is that the method is compatible with CMOS manufacturing. Yet another advantage of embodiments of the present invention is that the process flow is short and has a very limited number of steps, especially the pixelation step. In this way, the total thermal treatment time of the thin film stack is minimized during the process flow.

[0010] An advantage of embodiments of the present invention is that crosstalk between different pixels is prevented by pixelating the optoelectronic stack. An advantage of embodiments of the present invention is that crosstalk between different pixels is minimized by preventing direct electrical contact between adjacent pixels of the optoelectronic stack. Another advantage of embodiments of the present invention is that the pixels are isolated from the atmosphere, thereby preventing moisture absorption and oxidation of the optoelectronic stack. Another advantage of embodiments of the present invention is that no device degradation is expected during the patterning process and during ambient storage after the pixelation process.

[0011] An advantage of embodiments of the present invention is that because the optoelectronic stack is first formed on the bottom electrode and only thereafter the optoelectronic stack and the bottom electrode are pixelated via etching in a single step, the defect rate of the top surface of the bottom electrode is not affected by the process. Another advantage of embodiments of the present invention is that this series of steps thereby results in good adhesion between the bottom electrode and the optoelectronic stack. Yet another advantage of embodiments of the present invention is that the smoothness of the top surface of the bottom electrode is not affected, and therefore its reflectivity is also not affected, resulting in an improved external quantum efficiency (EQE) of the optoelectronic device comprising the optoelectronic stack formed according to an embodiment of the method of the present invention. If the optoelectronic device is a photodiode array, this translates into better sensitivity.

[0012] An advantage of embodiments of the present invention is that the photovoltaic stack is only deposited on the bottom electrode: the adhesion between the photovoltaic stack and the bottom electrode is generally strong and, for example, not prone to delamination.

[0013] An advantage of embodiments of the present invention is that the optoelectronic array has a flat top surface, which facilitates the formation of post-processing modules, such as color filters or microlenses, formed over individual pixels.

[0014] According to a first aspect, the present invention relates to a method for forming a pixelated optoelectronic stack above a substrate, the method comprising:

[0015] (i) obtaining a stacked layer structure on a substrate, the stacked layer structure comprising: (a) a bottom electrode layer, (b) a photovoltaic layer above the bottom electrode layer, and (c) a patterned hard mask above the photovoltaic layer and comprising a pattern, the pattern comprising at least two hard mask islands separated by a hard mask-free region,

[0016] (ii) replicating the pattern into the photovoltaic layer and the bottom electrode layer by etching selectively with respect to the hard mask, thereby obtaining a first intermediate pixelated stack above the substrate, the first intermediate pixelated stack comprising at least two stacking islands separated from each other by a non-stacked area,

[0017] (iii) providing an electrically insulating layer on the first intermediate pixelated stack to fill the stack-free area and cover the at least two stacking islands,

[0018] (iv) removing the top of the electrically insulating layer and removing any remaining hard mask so that the top surface of the electrically insulating layer is coplanar with the exposed top surface of the first intermediate pixelated stack to produce a second intermediate pixelated stack above the substrate, and

[0019] (v) forming a top transparent electrode layer over the second intermediate pixelated stack.

[0020] According to a second aspect, the present invention relates to a method for forming an intermediate structure in a pixelated optoelectronic device, comprising:

[0021] A stacked layer structure on a substrate, the stacked layer structure comprising:

[0022] Continuous bottom electrode layer,

[0023] a photovoltaic layer above the bottom electrode layer, and

[0024] A patterned hard mask is over the photovoltaic layer and includes a pattern comprising at least two hard mask islands separated by a non-hard mask region, wherein a vertical projection of each hard mask island onto the top surface of the continuous bottom electrode layer is included therein.

[0025] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate, and not merely as explicitly set out in a claim.

[0026] While devices in the art are constantly improving, changing, and evolving, the present inventive concepts are believed to represent a substantially new and inventive advancement involving a departure from prior practice, thereby providing a more efficient, stable, and reliable device of this nature.

[0027] The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention by way of example. This description is given for illustrative purposes only and does not limit the scope of the invention. The reference figures cited below are referenced to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 9 Shown are schematic representations of vertical cross-sections of an intermediate structure obtained after different steps of a method according to an embodiment of the invention.

[0029] The same reference numbers in different drawings refer to the same or similar elements. DETAILED DESCRIPTION

[0030] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are merely schematic and non-limiting. In the drawings, the dimensions of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. Dimensions and relative dimensions do not correspond to actual reductions to the practice of the invention.

[0031] In addition, the terms first, second, and third, etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a sequence in time, space, arrangement, or any other manner. It should be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in a different sequence than described or illustrated herein.

[0032] Furthermore, the terms top, bottom, over, under, etc., in the specification and claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in orientations other than those described or illustrated herein.

[0033] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Therefore, the term "comprising" covers the case where only the stated features are present as well as the case where these features and one or more other features are present. The word "comprising" according to the present invention therefore also includes an embodiment in which the other components are absent. Therefore, the scope of the expression "a device comprising means A and B" should not be interpreted as being limited to a device consisting only of components A and B. This means that for the present invention, the only relevant components of the device are A and B.

[0034] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0035] Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, inventive aspects reside in fewer features than all of the features of a single preceding disclosed embodiment. Accordingly, the claims appended following the detailed description are hereby expressly incorporated into this detailed description, with each claim itself representing a separate embodiment of the invention.

[0036] Furthermore, although some embodiments described herein include some features included in other embodiments but do not include other features included in other embodiments, as will be understood by those skilled in the art, combinations of features from different embodiments are intended to fall within the scope of the present invention and to form different embodiments. For example, in the appended claims, any of the claimed embodiments can be used in any combination.

[0037] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques are not shown in detail to avoid obscuring understanding of this description.

[0038] In the description provided herein, reference is made to selective etching. In various embodiments, selectively etching a first region relative to a second region includes etching the material included in the first region at a higher etch rate (such as twice as fast, such as ten times as fast, such as one hundred times as fast) than the material included in the second region. In some embodiments, selective etching includes substantially not etching the material included in the second region and etching substantially only the material included in the first region.

[0039] In a first aspect, the present invention relates to a method for forming a pixelated optoelectronic stack above a substrate, the method comprising:

[0040] (i) obtaining a stacked layer structure on a substrate, the stacked layer structure comprising:

[0041] (a) bottom electrode layer,

[0042] (b) a photovoltaic layer above the bottom electrode layer, and

[0043] (c) a patterned hard mask over the photovoltaic layer and comprising a pattern comprising at least two hard mask islands separated by a hard mask free region,

[0044] (ii) replicating the pattern into the photovoltaic layer and the bottom electrode layer by etching selectively with respect to the hard mask, thereby obtaining a first intermediate pixelated stack above the substrate, the first intermediate pixelated stack comprising at least two stacking islands separated from each other by a non-stacked area,

[0045] (iii) providing an electrically insulating layer on the first intermediate pixelated stack to fill the stack-free area and cover the at least two stacking islands.

[0046] (iv) removing the top of the electrically insulating layer and removing any remaining hard mask so that the top surface of the electrically insulating layer is coplanar with the exposed top surface of the first intermediate pixelated stack to produce a second intermediate pixelated stack above the substrate, and

[0047] (v) forming a top transparent electrode layer over the second intermediate pixelated stack.

[0048] In various embodiments, the bottom electrode layer has not been etched before step (ii). In other words, the bottom electrode layer has not been etched after it has been formed. In other words, the bottom electrode layer can be a continuous non-patterned layer. This is preferred because: first, in this case, the defect rate of the top surface of the bottom electrode layer is still the defect rate of the bottom electrode layer when it is formed. For example, it can be defect-free or have relatively few defects. This is beneficial for the physical and electrical contact between the bottom electrode layer and any layer deposited on the bottom electrode layer; second, the smoothness of the top surface is still the smoothness of the bottom electrode layer when it is formed. For example, it can be smooth, which is beneficial for light reflection. In various embodiments, the surface roughness has a value equal to or less than (such as from 2 to ) of the root mean square value of . In various embodiments, the contact area between the bottom electrode layer and the photovoltaic layer may be defect-free. In various embodiments, the bottom electrode layer may be made of a conductive material that reflects at least 80% (such as at least 90%) of light at the maximum light absorption wavelength of the photovoltaic active layer included in the photovoltaic layer. The wavelength may be, for example, in the visible, near-infrared or mid-infrared wavelength range. Examples of typical materials suitable for the bottom electrode are metals such as aluminum, copper, tantalum nitride and titanium nitride, in particular copper and titanium nitride. These materials are advantageous because they are highly reflective over a large wavelength range. The bottom electrode can be deposited, for example, via chemical vapor deposition, physical vapor deposition, sputtering, pulsed laser deposition, atomic layer deposition, evaporation. The preferred thickness range is 50nm–300nm.

[0049] The photovoltaic layer is above the bottom electrode layer. In various embodiments, it is on the photovoltaic layer. The photovoltaic layer includes a photovoltaic active layer. For example, if the method is intended to form an intermediate to a photodiode pixel array, the photovoltaic active layer can be a photosensitive layer, while if the method is intended to form an intermediate to a light-emitting diode pixel array, the photovoltaic active layer can be a light-emitting layer.

[0050] In various embodiments, the optoelectronic layer is a light emitting diode stack, so that devices formed by embodiments according to the first aspect of the present invention can be used in light emitting devices.

[0051] The photovoltaic layer may be a photovoltaically active layer, but it is more typically a multilayer comprising the photovoltaically active layer.

[0052] In various embodiments, the photovoltaic layer may include a first charge transport layer for transporting charges of a first polarity above (e.g., above) the bottom electrode, an active photovoltaic layer above (e.g., above) the first charge transport layer, and a second charge transport layer for transporting charges of a second polarity above (e.g., above) the photovoltaic layer. In various embodiments, the charges of the first polarity may be negative charges, i.e., charges carried by electrons, and the charges of the second polarity may be positive charges, i.e., charges carried by holes. In these embodiments, the first charge transport layer may include titanium oxide, and the second charge transport layer may include nickel oxide. In various embodiments, the charges of the first polarity may be positive charges, i.e., charges carried by holes, and the charges of the second polarity may be negative charges, i.e., charges carried by electrons. In these embodiments, the first charge transport layer may include nickel oxide, and the second charge transport layer may include titanium oxide. In various embodiments, the active photovoltaic layer includes or is composed of an organic material, or includes quantum dots.

[0053] In a preferred embodiment, the optoelectronic layer is a photodiode stack, so that devices formed according to embodiments of the first aspect of the present invention can be used in sensor devices. In a preferred embodiment in which the optoelectronic layer is a photodiode stack, the layer that transports electrons selected from the first and second charge transport layers may include titanium oxide. In a preferred embodiment in which the optoelectronic layer is a photodiode stack, the layer that transports holes selected from the first and second charge transport layers may include nickel oxide. In an embodiment in which the optoelectronic layer is a photodiode stack, the active optoelectronic layer may include quantum dots, such as PbS quantum dots, CdS quantum dots, InGaAs quantum dots, or an organic photodiode material.

[0054] The patterned hard mask can be obtained by first depositing a hard mask layer on the photovoltaic layer and then patterning the hard mask layer. The hard mask layer can be patterned by, for example, photolithography (such as deep ultraviolet lithography, preferably at a laser wavelength of 248 nm) and dry etching methods (such as reactive ion etching). The patterned hard mask can include or consist of one of the following materials: silicon oxide, silicon nitride, titanium nitride, tantalum nitride, ruthenium, and aluminum oxide.

[0055] In step (ii), the photovoltaic layer and the bottom electrode layer are patterned (i.e., pixelated) in a single step, i.e., by etching, including, for example, ion beam milling or reactive ion etching selectively through the photovoltaic layer and the bottom electrode layer relative to a hard mask to produce a first intermediate pixelated stack above the substrate. In preferred embodiments, the stacked layer structure further comprises an additional transparent electrode layer above (and preferably on) the photovoltaic layer. In these embodiments, step (ii) comprises etching selectively through the additional transparent electrode layer, the photovoltaic layer, and the bottom electrode layer relative to a hard mask to replicate the pattern into the additional transparent electrode layer, the photovoltaic layer, and the bottom electrode layer. The additional transparent electrode layer advantageously protects the layers included below the additional transparent electrode layer, such as the second charge transport layer, the active photovoltaic layer, or the first charge transport layer.

[0056] In various embodiments, the additional transparent electrode layer is transparent to light at least at the wavelength of maximum light absorption of the photovoltaic active layer included in the photovoltaic layer. Preferably, the additional transparent electrode layer is transparent to light with a wavelength from 200 nm to 2000 nm. Furthermore, the additional transparent electrode layer should be electrically conductive. In various embodiments, the additional transparent electrode layer comprises indium tin oxide.

[0057] In a preferred embodiment, the stacked layer structure further includes an additional thin hard mask layer, i.e., an unpatterned hard mask layer, above (such as on) the photovoltaic layer. Advantageously, the additional thin hard mask layer protects the layer, i.e., the material below the additional thin hard mask layer, from environmental and moisture corrosion. In embodiments where the stacked layer structure includes an additional transparent electrode layer, the additional thin hard mask layer is above (such as on) the additional transparent electrode layer in various embodiments. The patterned hard mask is above (such as on) the additional thin hard mask layer in various embodiments. In embodiments where the stacked layer structure includes the additional thin hard mask layer, step (ii) includes replicating the pattern into the additional thin hard mask layer, the photovoltaic layer, and the bottom electrode layer by etching through the additional thin hard mask layer, the photovoltaic layer, and the bottom electrode layer selectively relative to the patterned hard mask (in embodiments where a transparent electrode layer is present, the transparent electrode layer is also etched and the pattern is replicated into the transparent electrode layer). Because the additional thin hard mask layer is thin, it is etched away relatively quickly. In these embodiments, the etching of step (ii) necessarily includes an etch in which the hard mask material (i.e., the hard mask material of the patterned hard mask islands or the additional thin hard mask layer) is also etched. However, in these embodiments, the etching rate for the other materials included in the stacked layer structure is higher than the etching rate for the hard mask material. The pattern is preferably replicated in the photovoltaic layer and the bottom electrode layer, and in embodiments in which a transparent electrode layer is present, the transparent electrode layer is completely etched away before the hard mask islands. In various embodiments, the additional thin hard mask layer comprises the same material as the hard mask islands. In various embodiments, the hard mask layer and the additional thin hard mask layer are deposited simultaneously, and the hard mask layer is patterned after deposition.

[0058] In various embodiments, the thickness of the patterned hard mask, and in various embodiments, the additional thin hard mask layer, can be such that some hard mask (i.e., from the patterned hard mask and possibly from the additional thin hard mask layer) remains above the photovoltaic layer after step (ii). The thickness of the remaining hard mask can be 50-100 nm. The remaining hard mask protects the photovoltaic stack below and acts as a buffer, i.e., a buffer for the etching of step (ii). In some embodiments, the hard mask can be a double layer hard mask comprising a top layer and a bottom layer, wherein the top layer of the hard mask is removed in step (ii) and the bottom layer is the hard mask that remains above the photovoltaic layer after step (ii). In various embodiments, the top layer and the bottom layer of the double layer hard mask comprise the same material, while in other embodiments, the top layer and the bottom layer of the double layer hard mask comprise different materials.

[0059] The first intermediate pixelated stack comprises at least two (i.e., multiple) stacked islands separated from each other by no stacking area at the end of step (ii). In various embodiments, the lateral dimension of the stacked island is at least 100 nm, such as from 100 nm to 10 μm. Each stacked island comprises a bottom electrode layer and a photovoltaic layer. In various embodiments, the stacked island comprises an additional transparent electrode layer. In various embodiments, the top of the stacked island comprises a hard mask layer or at least a portion of the hard mask layer that is not etched during the etching of step (ii), wherein the hard mask layer that is not etched may have a thickness of from 20 nm to 200 nm in various embodiments. The stacked islands may form a one-dimensional array or alternatively a two-dimensional array.

[0060] The advantage of the electrically insulating layer formed on the non-stacked area and covering at least two stacked islands in step (iii) is that it protects the material of the stacked island from moisture and oxidation in the atmospheric environment. Therefore, preferably, step (iii) is performed substantially immediately after etching step (ii). In addition, by covering the non-stacked area with an electrically insulating layer, adjacent stacked islands are electrically insulated from each other, thereby preventing charge from moving between adjacent islands. The electrically insulating layer may include a dielectric material, such as silicon oxide or silicon nitride. In various embodiments, the dielectric material may have a dielectric constant lower than that of silicon oxide.

[0061] In various embodiments, the step (iii) of forming an electrically insulating layer on the first intermediate pixelated stack comprises forming a first conformal electrically insulating layer above the first intermediate pixelated stack and providing a second electrically insulating layer on the first conformal electrically insulating layer to fill the non-stacked area and cover at least two stacked islands. Advantageously, the first conformal electrically insulating layer can be deposited substantially in the same device (i.e., the initial device) immediately after the etching of step (ii). The second electrically insulating layer can be deposited in a separate device. The first conformal electrically insulating layer in this case protects the material of the stacked islands from atmospheric corrosion (such as moisture), for example when the first intermediate pixelated stack (i.e., the first intermediate pixelated stack above the substrate) is transported from the initial device to the separate device.

[0062] In various embodiments, the first conformal electrically insulating layer comprises a dielectric material such as silicon oxide or silicon nitride. In various embodiments, the dielectric material may have a lower dielectric constant than silicon oxide. In various embodiments, the second electrically insulating layer comprises a dielectric material such as silicon oxide or silicon nitride. In various embodiments, the dielectric material may have a lower dielectric constant than silicon oxide. In a preferred embodiment, the first conformal electrically insulating layer comprises SiN, and the second electrically insulating layer comprises a dielectric selected from silicon nitride and silicon oxide. In various embodiments, the second electrically insulating layer further comprises a metal such as copper and / or cobalt. Copper and / or cobalt can be easily deposited in the non-stacked area.

[0063] Removing the top portion of the electrically insulating layer and removing any remaining hard mask in step (iv) is typically performed by a chemical mechanical planarization process.

[0064] The second intermediate pixelated stack includes the first intermediate pixelated stack, i.e., at least two stacked islands, wherein the stacked islands are separated from each other by an electrically insulating layer, and wherein top surfaces of the stacked islands are coplanar with a top surface of the electrically insulating layer. In various embodiments, the electrically insulating layer includes a first conformal electrically insulating layer and a second electrically insulating layer.

[0065] The top transparent electrode layer provided in step (v) should be transparent to light at least at the wavelength of maximum light absorption of the photovoltaic active layer included in the photovoltaic layer and should be electrically conductive. The top transparent electrode layer conducts charge of the second polarity. In embodiments where the stacked layers include an additional transparent electrode layer, the top transparent electrode layer may include the same material as the additional transparent electrode layer. In various embodiments, the top transparent electrode layer includes indium tin oxide. The top transparent electrode layer is a common electrode layer that electrically connects each stacked island.

[0066] In each embodiment, the method further includes a step (v') of forming a transparent cover layer above the top transparent electrode layer after step (v). In each embodiment, the transparent cover layer electrically and / or physically isolates the top transparent electrode layer from external materials. In addition, in each embodiment, the transparent cover layer prevents potential moisture absorption or oxidation of the top transparent electrode layer. The transparent cover layer is preferably transparent at least to light at the maximum light absorption wavelength of the photoelectric active layer included in the photoelectric layer. Preferably, the transparent cover layer is transparent to light at a wavelength from 200nm to 2000nm. The transparent cover layer can be formed, for example, by physical vapor deposition, atomic layer deposition, evaporation and spin coating. The transparent cover layer may include one of the following materials: indium tin oxide, silicon oxide, silicon nitride and a transparent organic material. Preferably, the transparent cover layer has a thickness of from 50nm to 500nm.

[0067] In various embodiments, the substrate includes a connection layer above the integrated circuit layer, the connection layer including conductive elements isolated from each other by a dielectric and connecting the integrated circuit layer to the bottom electrode layer. In various embodiments, the conductive elements may be metal pillars. In various embodiments, each stacked island is connected to the integrated circuit layer via a conductive element.

[0068] For example, in the case where the optoelectronic stack is a photodiode stack, the integrated circuit layer can be an active CMOS device, such as a CMOS readout integrated circuit (ROIC). The CMOS ROIC is adapted to read out the photocurrent generated in each pixel in the array of the photodiode device formed by the method of the first aspect, wherein the pixel includes a stacked island. Since the movement of charge of the first polarity is prohibited between adjacent pixels, the charge read out by the integrated circuit layer for a pixel has already been generated in the pixel. In an embodiment where the charge of the first polarity is negative, the CMOS ROIC reads the negative charge. In an embodiment where the charge of the first polarity is positive, the CMOS ROIC reads the positive charge.

[0069] This readout can be accomplished, for example, by accumulating the charge of the first polarity generated in each pixel over a time interval and then detecting, for each pixel, how much charge of the first polarity has accumulated over the duration of the time interval. Dividing the detected accumulated charge by the length of the time interval yields a measure of the average light intensity incident on each pixel over the duration of the time interval.

[0070] As another example, where the optoelectronic stack is a light-emitting diode stack, the integrated circuit layer can be a CMOS driver integrated circuit. The CMOS driver integrated circuit is adapted to drive current individually to each pixel in an array of a light-emitting device formed by the method of the first aspect, where the pixel comprises a stacked island. The light intensity generated in the pixel depends on the drive current passing through the pixel.

[0071] In various embodiments, the method may further comprise a step (iv') of exposing the conductive elements of the connecting layer between step (iv) and step (v). Exposing the conductive elements may be performed by etching, such as dry etching, such as etching through a patterned photoresist, wherein the patterned photoresist is formed above or on the second intermediate pixelated stack and comprises a pattern for exposing the conductive elements. The etching may be performed by etching through all layers included in the second intermediate pixelated stack selectively relative to the photoresist, thereby copying the pattern of the patterned photoresist into the second intermediate pixelated stack. Thus, the second intermediate pixelated stack comprises a pattern for exposing the conductive elements. Preferably, etching through all layers included in the second intermediate pixelated stack comprises etching through an electrically insulating layer, i.e., an electrically insulating layer between the stacked islands. The etching preferably has an etching rate for the conductive elements and for the dielectric of the connecting layer surrounding the conductive elements that is lower than the etching rate for the second intermediate pixelated stack (such as for the electrically insulating layer). Subsequently, the patterned photoresist is removed.

[0072] By exposing the conductive element, the top transparent electrode layer deposited on the second intermediate pixelated stack in step (v) can be in electrical contact with the conductive element and the integrated circuit layer. As a result, the charge of the second polarity generated in the device produced by this method is conducted to the integrated circuit layer through the top transparent electrode layer and the conductive element, thereby forming a closed circuit.

[0073] In various embodiments, the connecting layer may further include a probe pad on the integrated circuit layer, and the method may further include a step (vi) of exposing the probe pad. Exposing the probe pad may be performed by etching, such as dry etching, such as etching through a patterned photoresist, wherein the patterned photoresist includes a pattern for exposing the probe pad and is formed above or on the transparent electrode. In embodiments in which the method includes step (v'), step (vi) is performed after step (v') in various embodiments, and the patterned photoresist is formed above or on the transparent cover layer. Etching can be performed by selectively etching through all layers above the substrate relative to the photoresist, thereby copying the pattern of the patterned photoresist to the layers above the substrate. Thus, all layers above the substrate include a pattern for exposing the probe pad. Subsequently, the patterned photoresist is removed.

[0074] The detection pad can be used to transmit power and signals between the pixelated optoelectronic stack on the substrate and one or more external devices. For example, if the optoelectronic stack is a photodiode stack, then, for example, a signal (i.e., a photocurrent collected by a pixel of the pixelated optoelectronic stack) can be transmitted to the external device via the detection pad. In another example, if the optoelectronic stack is a light-emitting diode stack, power can be transmitted from the external device to the pixel of the pixelated optoelectronic stack via the detection pad so that the pixel can emit light.

[0075] In a preferred embodiment, each stacked island has a lateral dimension of from 10 μm to 100 μm. However, the lateral dimension is not limited thereto and can be smaller or larger. In various embodiments, each stacked island corresponds to a pixel of a pixelated optoelectronic stack. Therefore, in various embodiments, the pixel size of an optoelectronic device including a pixelated optoelectronic stack has the same size as the stacked island.

[0076] In various embodiments, the distance between two adjacent stacked islands is from 50 nm to 5 μm. However, the distance is not limited thereto, and may be smaller or larger.

[0077] In various embodiments, the optoelectronic layer comprises an organic semiconductor material. Preferably, the active optoelectronic layer comprises or consists of an organic material, or comprises quantum dots.

[0078] In various embodiments, the pixelated optoelectronic stack includes a second intermediate pixelated stack above the substrate and a top transparent electrode layer above or on the second intermediate pixelated stack. In various embodiments, the pixelated optoelectronic stack further includes a transparent cover layer above or on the transparent electrode material. In some embodiments where the substrate includes a conductive element and an integrated circuit layer, the second intermediate pixelated stack may include a pattern for exposing the conductive element, and the top transparent electrode layer of the pixelated optoelectronic stack may be in electrical contact with the conductive element and the integrated circuit layer. In embodiments where the connecting layer of the pixelated optoelectronic stack includes a detection pad, all layers above the substrate may include a pattern for exposing the detection pad.

[0079] In a second aspect, the present invention relates to a method for forming an intermediate structure in a pixelated optoelectronic device, comprising:

[0080] a. A stacked layer structure on a substrate, the stacked layer structure comprising:

[0081] i. a continuous bottom electrode layer,

[0082] ii. a photovoltaic layer above the bottom electrode layer, and

[0083] iii. A patterned hard mask over the photovoltaic layer and comprising a pattern comprising at least two hard mask islands separated by a hard mask free region, wherein a vertical projection of each hard mask island onto the top surface of the continuous bottom electrode layer is included therein.

[0084] Any features of the second aspect may be as correspondingly described in the first aspect.

[0085] The present invention will now be described in detail by describing several embodiments of the present invention. Obviously, other embodiments of the present invention can be configured according to the knowledge of those skilled in the art without departing from the technical teachings of the present invention, and the present invention is only limited by the terms of the appended claims.

[0086] In various embodiments, the layer stack may include an additional thin hard mask layer between the photovoltaic layer and the patterned hard mask layer.

[0087] Example

[0088] In this example, an embodiment of a method for forming a pixelated optoelectronic stack over a substrate according to the first aspect of the invention is shown.

[0089] Reference Figure 1 In this example, the substrate 1 includes an integrated circuit layer 11 and a connection layer 12 on the integrated circuit layer 11. The connection layer 12 includes conductive elements 121 isolated from each other by a dielectric 122. In addition, in this embodiment, the connection layer 12 includes a detection pad 123.

[0090] Now refer to Figure 2 . The stacked layer 2 is deposited on the substrate 1. The stacked layer 2 includes a bottom electrode layer 21, a photovoltaic layer 22 above the bottom electrode layer 21, an additional transparent electrode layer 25 above the photovoltaic layer 22, an additional thin hard mask layer 262 above the additional transparent electrode layer 25, and a hard mask layer 26 above the additional thin hard mask layer 262. The hard mask layer 26 and the additional thin hard mask layer 262 may include the same material and be formed in the same step. The photovoltaic layer 22 includes a first charge transport layer 221, an active photovoltaic layer 222, and a second charge transport layer 223. Advantageously, the bottom electrode layer 21 is not patterned so that the top surface of the bottom electrode layer 21 (i.e., the first charge transport layer 221) is smooth and defect-free. As a result, the contact between the bottom electrode layer 21 and the photovoltaic layer 22 is good.

[0091] Now refer to Figure 3 The hard mask layer is patterned, for example using deep ultraviolet lithography, to produce a patterned hard mask 261 over the additional thin hard mask layer 262 .

[0092] Now refer to Figure 4 . The pattern of the hard mask layer is replicated in the layers above the substrate 1 by etching selectively with respect to the hard mask through all layers above the substrate 1. The etching is selective with respect to the hard mask, which in this embodiment means that the etching rate for the hard mask is much slower than the etching rate for the other layers above the substrate. The patterned hard mask 261 is thick enough so that some of the patterned hard mask 261 is retained after this step. The etching produces a first intermediate pixelated stack above the substrate 1, which first intermediate pixelated stack comprises at least two stacking islands 3 separated from each other by no stacking areas 31. Immediately after this etching step, a first conformal electrically insulating layer 41 is deposited above the first intermediate pixelated stack, thereby protecting the stacking islands 3, for example, from moisture or atmospheric corrosion.

[0093] Now refer to Figure 5 The second electrically insulating layer 42 is formed over the first conformal electrically insulating layer 41 . As a result, the electrically insulating layer 4 (ie, including the first conformal electrically insulating layer 41 and the second insulating layer 42 ) fills the stacking-free area 31 and covers the stacking island 3 .

[0094] Now refer to Figure 6. First, the top of the electrically insulating layer 4 and any remaining hard mask is removed so that the top surface of the electrically insulating layer 43 is coplanar with the exposed top surface of the first intermediate pixelated stack 31. This produces a second intermediate pixelated stack 5 above the substrate 1. Secondly, a pair of conductive elements 121 ' included on the substrate 1 is exposed, for example by etching through the layers above the substrate 1 selectively with respect to a patterned photoresist (not shown) (i.e. comprising a pattern) deposited above the second intermediate pixelated stack 5. Thereby, the second intermediate pixelated stack 5 includes the pattern of the patterned photoresist.

[0095] Now refer to Figure 7 . A top transparent electrode layer 6 is formed above the second intermediate pixelated stack. The top transparent electrode layer 6 is thereby in electrical contact with the stacked island 3. Since the conductive elements 121' are exposed, they are also electrically contacted by the top transparent electrode layer 6. Thus, charges of the second polarity are able to flow between the second charge transport layer 223 (i.e. above and in electrical contact with the active photoelectric layer 222) and the integrated circuit layer 11, i.e. through the additional transparent electrode layer 25 and through the top transparent electrode layer 6 and through the conductive elements 121' in contact with the top transparent electrode layer 6. Charges of the first polarity are able to flow between the first charge transport layer 221 (i.e. below and in electrical contact with the active photoelectric layer 222) and the integrated circuit layer 11, i.e. through the bottom electrode layer 21 and the conductive elements 121" in contact with the bottom electrode layer 21.

[0096] Now refer to Figure 8 A portion of the top transparent electrode layer 6 is removed, thereby limiting the size of the stacked island array, i.e. the number of pixels in contact with the top transparent electrode layer 6. Another reason will be Figure 9 It is obvious.

[0097] Now refer to Figure 9 . A transparent cover layer 7 is deposited above the top transparent electrode layer 6. In an embodiment in which a portion of the top transparent electrode layer 6 has been removed, the transparent cover layer 7 is also deposited above the area in which the top transparent electrode layer 6 has been removed. The transparent cover layer 7 prevents electrical contact (e.g., with external materials) of the top transparent electrode layer 6 or contact of the transparent electrode layer 6 with the environment. Next, the probe pads 123 are exposed by selectively etching through the layers above the probe pads 123 relative to a patterned photoresist (not shown) (i.e., including a pattern) deposited above the transparent cover layer 7. Thus, the layers above the probe pads 123 include the pattern of the patterned photoresist. Since a portion of the top transparent electrode layer 6 has been removed and is then covered by the transparent cover layer 7, the wires (not shown) can contact the probe pads 123 without electrically contacting the top transparent electrode layer 6. Thus, a pixelated optoelectronic stack 8 on the substrate 1 is obtained.

[0098] It will be understood that although preferred embodiments, specific structures and configurations, and materials have been discussed herein for apparatus according to the present invention, various changes or modifications in form and detail may be made without departing from the scope of the present invention. For example, any formulas given above are merely representative of steps that may be used. Functions may be added or deleted from the block diagrams, and operations may be interchanged between functional blocks. Steps may be added or deleted from the method within the scope of the present invention.

Claims

1. A method for forming a pixelated optoelectronic stack on a substrate, the method comprising: i. obtaining a stacked layer structure on a substrate, the stacked layer structure comprising a bottom electrode layer, a photovoltaic layer above the bottom electrode layer, and a patterned hard mask above the photovoltaic layer and comprising a pattern, the pattern comprising at least two hard mask islands separated by a hard mask-free area, ii. replicating the pattern into the photovoltaic layer and the bottom electrode layer by etching selectively with respect to the hard mask, thereby obtaining a first intermediate pixelated stack above the substrate, the first intermediate pixelated stack comprising at least two stacking islands separated from each other by a non-stacked area, iii. providing an electrically insulating layer on the first intermediate pixelated stack to fill the stack-free area and cover the at least two stacked islands, iv. removing the top of the electrically insulating layer and removing any remaining hard mask so that the top surface of the electrically insulating layer is coplanar with the exposed top surface of the first intermediate pixelated stack to produce a second intermediate pixelated stack above the substrate, and v. Forming a top transparent electrode layer over the second intermediate pixelated stack.

2. The method of claim 1, wherein the photovoltaic layer comprises: a first charge transport layer on the bottom electrode for transporting charges of a first polarity, an active photovoltaic layer above the first charge transport layer, and A second charge transport layer is provided on the photovoltaic layer and is used for transporting charges of a second polarity.

3. A method as claimed in claim 1 or claim 2, wherein the stacked layer structure further includes an additional transparent electrode layer above the photovoltaic layer, and wherein step ii includes replicating the pattern into the additional transparent electrode layer, the photovoltaic layer and the bottom electrode layer by selectively etching through the additional transparent electrode layer, the photovoltaic layer and the bottom electrode layer relative to the hard mask, thereby obtaining the first intermediate pixelated stack above the substrate, the first intermediate pixelated stack including at least two stacked islands separated from each other by non-stacked areas. 4 . The method of claim 1 , comprising a step v′ of forming a transparent cover layer over the top transparent electrode layer after step v. The method of claim 1 , wherein the photovoltaic layer is a photodiode stack.

6. The method of claim 1 , wherein step iii of forming the electrical insulating layer on the first intermediate pixelated stack includes forming a first conformal electrical insulating layer above the first intermediate pixelated stack and providing a second electrical insulating layer on the first conformal electrical insulating layer to fill the non-stacked area and cover the at least two stacked islands.

7. The method of claim 6, wherein the first conformal electrically insulating layer comprises SiN, and wherein the second electrically insulating layer comprises a dielectric selected from the group consisting of silicon nitride and silicon oxide.

8. The method of claim 1, wherein the substrate comprises a connection layer over an integrated circuit layer, the connection layer comprising conductive elements isolated from each other by a dielectric and connecting the integrated circuit layer to the bottom electrode layer.

9. The method of claim 8, further comprising a step iv' between step iv and step v of exposing the conductive element of the connection layer.

10. The method of claim 8 or claim 9, wherein the connection layer further comprises probe pads on the integrated circuit layer, and wherein the method further comprises the step vi of exposing the probe pads. The method of claim 1 , wherein each stacked island has a lateral dimension from 10 μm to 100 μm.

12. The method of claim 1, wherein a distance between two adjacent stacked islands is from 50 nm to 5 μm.

13. The method of claim 1, wherein the photovoltaic layer comprises an organic semiconductor material.

14. The method of claim 1, wherein the thickness of the patterned hard mask is such that some hard mask remains over the photovoltaic layer after step ii.

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